TW202404147A - Electronic device - Google Patents

Abstract

The disclosure provides an electronic device which includes a substrate, a data line disposed on the substrate, a drain disposed on the substrate, and a semiconductor layer disposed on the substrate. The semiconductor layer includes a first portion connected to the data line, a second portion connected to the drain, and a third portion connected between the first portion and the second portion. Wherein, at least a part of the third portion includes at least one of Group IIIA elements and Group VA elements, and the doping concentration of the at least one of Group IIIA elements and Group VA elements is greater than 0 and less than or equal to 10<SP>16</SP> atoms/cubic cm.

Description

electronic device

The present disclosure relates to an electronic device, and in particular, to an electronic device including a semiconductor layer.

With the advancement of technology, electronic devices have become indispensable items in modern people's lives. Electronic devices usually include driving elements and/or switching elements, and the semiconductor layers in the driving elements and switching elements may reduce the process space due to the increase in resolution, resulting in variations in the width of the semiconductor layer and affecting its performance.

On the other hand, as the resolution of electronic devices increases, the distance between components will shrink, so that the contact hole design of the existing technology may cause unexpected conductive layers to be exposed during the manufacturing process, causing short circuits between components. .

Therefore, electronic device manufacturers need to provide better component configuration designs to improve existing technology defects such as insufficient aperture ratio and short circuits caused by component size reduction and process factors.

Some embodiments of the present disclosure provide an electronic device, which includes a substrate, a data line disposed on the substrate, a drain disposed on the substrate, and a semiconductor layer disposed on the substrate. The semiconductor layer includes a first part connected to the data line, a second part connected to the drain, and a third part connected between the first part and the second part. Wherein, at least part of the third part includes at least one of Group IIIA elements and Group VA elements, and the doping concentration of at least one of Group IIIA elements and Group VA elements is greater than 0 and less than or equal to 10^16 ( 10 ¹⁶ ) atoms/cubic centimeter.

Some embodiments of the present disclosure provide an electronic device, which includes a substrate, a data line disposed on the substrate, a drain disposed on the substrate, a scan line disposed on the substrate, and a semiconductor layer disposed on the substrate. The data lines extend along a first direction, and the scan lines extend along a second direction, where the second direction is different from the first direction. The semiconductor layer includes a first part connected to the data line, a second part connected to the drain, and a third part connected between the first part and the second part, and the third part overlaps the scan line. Wherein, at least part of the third part includes at least one of Group IIIA elements and Group VA elements, and the doping concentration of at least one of Group IIIA elements and Group VA elements is greater than 0 and less than or equal to 10^16 ( 10 ¹⁶ ) atoms/cubic centimeter.

The content of the present disclosure is described in detail below with reference to specific embodiments and drawings. It should be noted that, in order to make the readers easy to understand and the drawings to be concise, many of the drawings in the present disclosure only depict a part of the device or structure. And certain elements in the drawings are not drawn to actual scale. In addition, the number and size of components in the figures are only for illustration and are not intended to limit the scope of the present disclosure.

Certain words are used throughout this disclosure and in the appended claims to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may refer to the same component by different names. This article is not intended to differentiate between components that have the same function but have different names.

In the following description and patent application, the words "include", "have" and "include" are open-ended words, so they should be interpreted to mean "including but not limited to...". When the terms "comprising", "including" and/or "having" are used in this specification, they specify the presence of the stated features, regions, steps, operations and/or elements but do not exclude one or more other The presence or addition of features, regions, steps, operations, elements and/or combinations thereof.

The ordinal numbers used in the specification and claims, such as "first", "second", etc., are used to modify the elements of the claim. They themselves do not imply or represent that the claimed element has any previous ordinal number, nor do they Represents the order between a certain required component and another required component, or the order in the manufacturing method. The use of the ordinal number is only used to make it clear that a required component with a certain name can be compared with another required component with the same name. Distinguish.

Directional terms mentioned in the following embodiments, such as "up", "down", "left", "right", "front" or "back", etc., are only for reference to the directions of the drawings. Accordingly, the directional terms used are intended to illustrate and not to limit the disclosure. It must be understood that the elements described or illustrated may exist in a variety of forms known to those skilled in the art.

In addition, when an element or layer is referred to as being on another element or layer, or is referred to as being connected to another element or layer, it should be understood that the element or layer is Directly on another element or another film layer, or directly connected to another element or another film layer, or there can be other elements or film layers between the two (indirectly). In contrast, when an element or layer is referred to as being "directly on" or "directly connected to" another element or layer, this should be understood as meaning that the element or layer is "directly on" or "directly connected to" another element or layer. There are no intervening components or layers between them. If a first device on a circuit is described as electrically connected to a second device, it means that the first device can be directly electrically connected to the second device, or the first device can be indirectly electrically connected to the second device. When describing a first device that is directly electrically connected to a second device, the first device and the second device are only connected through wires or passive components (such as resistors, capacitors, etc.), and no other electronic components are connected between the first device and the second device. between.

In this disclosure, the thickness, length, and width can be measured using an optical microscope (optical microscopy, OM), and the thickness or length can be measured using a cross-sectional image using a scanning electron microscope (scanning electron microscope, SEM). Measured, but not limited to this. The impurity doping concentration can be measured using SEM, transmission electron microscope (TEM), X-ray photoelectron spectroscopy (XPS), or X-ray energy dispersive spectrometer (Energy-dispersive). Measured by X-ray spectroscopy (EDS) or secondary ion mass spectrometer (SIMS), but not limited to this. In addition, any two values or directions used for comparison may have certain errors.

In this context, the terms "about", "substantially" and "approximately" usually mean within 10%, or within 5%, or within 3%, or within 2%, or within 1% of a given value or range. Within %, or within 0.5%. The quantities given here are approximate quantities, that is, without specifically stating "about", "substantially" and "approximately", the terms "approximately", "substantially" and "approximately" can still be implied. meaning.

The electronic device described in the present disclosure may include a display device, a light emitting device, a backlight device, a virtual reality (VR) device, an antenna device, a sensing device or a splicing device, but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The display device may be a non-self-luminous display device or a self-luminous display device. The antenna device may be a liquid crystal type antenna device or a non-liquid crystal type antenna device, and the sensing device may be a sensing device that senses capacitance, light, heat energy or ultrasonic waves, but is not limited thereto. The electronic device may include, for example, passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. Diodes may include light emitting diodes or photodiodes. The light emitting diode may include, for example, an inorganic light emitting diode, an organic light emitting diode (OLED), a sub-millimeter light emitting diode (mini LED), a micro light emitting diode (micro LED) or a quantum dot. Light emitting diode (quantum dot LED), but not limited to this. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device can be any combination of the above, but is not limited thereto. In addition, the shape of the electronic device may be a rectangular shape, a circular shape, a polygonal shape, a shape with curved edges, or other suitable shapes. Electronic devices may have peripheral systems such as driving systems, control systems, and light source systems to support display devices, antenna devices, wearable devices (for example, including augmented reality or virtual reality), vehicle-mounted devices (for example, including car windshields), or splicing devices .

It should be noted that in the following embodiments, the technical features in several different embodiments can be disassembled, replaced, reorganized, and mixed without departing from the spirit of the present disclosure to complete other embodiments.

Please refer to FIGS. 1A and 2 . FIG. 1A is a partial top view of the first embodiment of the disclosed electronic device, and FIG. 2 is a partial cross-sectional schematic view of the disclosed electronic device along the section line A-A’ in FIG. 1A . In this embodiment, examples of the electronic device ED of the present disclosure include (but are not limited to) the display panel 100 for displaying images or pictures. In other embodiments, the electronic device ED of the present disclosure can be any device with driving components, switches, etc. components or thin film transistor devices. The electronic device ED includes a substrate SB1, at least one data line DL, at least one drain DE and a semiconductor layer SC, wherein the data line DL, the drain DE and the semiconductor layer SL are disposed on the substrate SB1. The electronic device ED may further include a scan line GL provided on the substrate SB1. The scan line GL may extend along the first direction X and overlap with at least a portion of the semiconductor layer SC, and the data line DL may extend along the second direction Y, where the first direction Taking the first direction X perpendicular to the second direction Y as an example, but not limited to this. In some embodiments, a plurality of data lines DL and a plurality of scan lines GL can be formed on the substrate SB1, which intersect with each other to define a plurality of pixel areas PX (or sub-pixel areas) arranged in an array. Only two are marked in Figure 1A PX representation of the complete pixel area.

In some embodiments, each pixel area PX may correspond to and include a driving element DV. The driving element DV is, for example, a thin film transistor. In some embodiments, the driving element DV can be replaced by a switching element. The driving element DV includes a source SE, a drain DE, a gate GE and a semiconductor layer SC. The source SE may be part of the data line DL, and the gate GE may be part of the scan line GL. The semiconductor layer SC may have a U-shaped pattern and include a first part S1 connected to the data line DL (ie, the source electrode SE), a second part S2 connected to the drain electrode DE, and a third part connected between the first part S1 and the second part S2. Three parts S3. In detail, the extension direction of the pattern of the first part S1 and the second part S2 of the semiconductor layer SC may be substantially parallel to the extension direction of the data line DL (ie, the second direction Y), and the extension direction of the pattern of the third part S3 may be Approximately parallel to the extension direction of the scan line GL (ie, the first direction X). In FIG. 1A , the third part S3 extends to the left and right directions along the first direction X to the lower sides of the first part S1 and the second part S2 so as to be connected to the lower ends of the first part S1 and the second part S2. In other words, in a simpler definition, the lower part of the U-shaped pattern of the semiconductor layer SC that extends laterally along the first direction The longitudinally extending portions are regarded as the first portion S1 and the second portion S2, and their lower portions are connected to the upper sides of the left and right ends of the third portion S3. Please refer to the partially enlarged schematic diagram of the semiconductor layer SC and the scan line GL on the right side of FIG. 1A. When the patterned semiconductor layer SC is fabricated using a photolithography etching process, the pattern of the semiconductor layer SC actually formed may have non-linear edges, or may have rounded and curved edges. According to the embodiment shown in FIG. 1A , a more specific definition of the third part S3 of the present disclosure may be, for example: the farthest point from the scan line GL of the inner edge SC1 of the semiconductor layer SC near the turning point of the U-shaped pattern is defined as The saddle point P1, and a reference line CSL extending along the first direction X and passing through the saddle point P1 can be defined, and the portion of the semiconductor layer SC below the reference line CSL is defined as the third portion S3 of the semiconductor layer SC of the present disclosure. , the left part of the semiconductor layer SC above the reference line CSL (i.e., the part electrically connected to the data line DL) is defined as the first part S1 of the semiconductor layer SC, and the right part of the semiconductor layer SC above the reference line CSL (i.e., the part electrically connected to the drain DE part) is defined as the second part S1 of the semiconductor layer SC. In the top view of the present disclosure, the "upper side" refers to the side facing the second direction Y, the "lower side" refers to the side opposite to the second direction Y, and the "right side" refers to the side facing the first direction Y. The "left" side of the direction X refers to the side opposite to the first direction X. This is the same for other subsequent embodiments and will not be repeated.

As shown in FIG. 2 , the semiconductor layer SC can be divided into an undoped region SCC, a lightly doped region SCL and a heavily doped region SCD according to the doping concentration. The undoped region SCC can be used as the channel region of the driving element DV, which roughly corresponds to the gate GE. That is, the portion of the semiconductor layer SC corresponding to the scan line GL is the undoped region SCC. The lightly doped region SCL can also be called the lightly doped drain (LDD). Its doping concentration is greater than 0 and less than or equal to 10^16 atoms/cubic centimeter (atom/cm ³ ), or doped The concentration can be 10^10~10^16, but is not limited to this. For example, the lightly doped region SCL may be doped with at least one of group IIIA elements and group VA elements, such as boron (B), aluminum (Al), gallium (Ga), indium (In), phosphorus (P), arsenic At least one of (As), antimony (Sb), etc., but not limited to the above. The doping concentration of the heavily doped region SCD is greater than 10^16 atoms/cubic centimeter, and can be doped with at least one of group IIIA elements and group VA elements. Examples of doped impurities are as above and will not be described again. The impurity doping concentration can be obtained by component analysis or measurement using SEM, TEM, XPS, EDS, SIMS and other instruments. Please refer to FIG. 2 and FIG. 1A at the same time. The heavily doped region SCD electrically connected to the source SE can be used as the source region in the semiconductor layer SC, which is located at the upper left side of the U-shaped semiconductor layer SC, but is not limited to this. A lightly doped region SCL may be provided between the heavily doped region SCD as the source region and the undoped region SCC as the channel region. Furthermore, the heavily doped region SCD electrically connected to the drain DE can be used as the drain region in the semiconductor layer SC, which is located on the upper right side of the U-shaped semiconductor layer SC, but is not limited to this. A lightly doped region SCL may be provided between the heavily doped region SCD as the drain region and the undoped region SCC as the channel region. Providing a lightly doped region SCL with a transition effect between the heavily doped region SCD and the undoped region SCC can reduce damage to the semiconductor layer SCC.

According to the present disclosure, the third portion S3 of the semiconductor layer SC is located between the gates GE, and at least a portion of the third portion S3 is the lightly doped region SCL. Specifically, when manufacturing the semiconductor layer SC, an area is set on the substrate SB1 according to a predetermined doping concentration, and a doping process is performed on the semiconductor layer SC according to the set area. The above-mentioned set region includes, for example, a lightly doped predetermined region RL1, a lightly doped predetermined region RL2, a heavily doped predetermined region RD1, and a heavily doped predetermined region RD2. These regions can extend across multiple driving elements along the first direction X. DV, that is, can extend parallel to the scan line GL. As shown in FIG. 1A , one driving element DV can correspond to two lightly doped predetermined regions RL1 and RL2 and two heavily doped predetermined regions RD1 and RD2. The lightly doped predetermined region RL1 corresponds to the lower part of the driving element DV. In the embodiment shown in FIG. 1A , the upper boundary of the lightly doped predetermined region RL1 can be substantially aligned with the lower edge of the scan line GL, and the lightly doped predetermined region The lower boundary of RL1 may be located between the inner edge SC1 and the outer edge SC2 of the third portion S3 of the semiconductor layer SC (in the second direction Y). The portion of the semiconductor layer SC corresponding to the lightly doped predetermined region RL1 may define a lightly doped region SCL located between two undoped regions SCC. The upper boundary of the heavily doped predetermined region RD1 overlaps the lower boundary of the lightly doped predetermined region RL1, and its lower boundary may be flush with the outer edge SC2 of the third part S3 of the semiconductor layer SC, but is not limited thereto. The portion of the semiconductor layer SC corresponding to the heavily doped predetermined region RD1 may define a heavily doped region SCD located between the two undoped regions SCC. Therefore, the upper part of the third part S3 of the semiconductor layer SC includes the lightly doped region SCL, and the lower part of the third part S3 includes the heavily doped region SCD. In other words, at least part of the third part S3 is the lightly doped region SCL, that is, It includes at least one of Group IIIA elements and Group VA elements, and the doping concentration of at least one of Group IIIA elements and Group VA elements is greater than 0 and less than or equal to 10^16 atoms/cubic centimeter.

Furthermore, the heavily doped predetermined region RD2 corresponds to the upper part of the driving element DV. In the structural top view of the embodiment shown in FIG. 1A , that is, in the top view direction of the substrate SB1 (ie, the normal direction Z of the substrate), the heavily doped region RD2 corresponds to the upper part of the driving element DV. The upper boundary of the impurity predetermined region RD2 is, for example (but not limited to) aligned with the upper edge of the semiconductor layer SC, the lower boundary is, for example (but not limited to) located on the lower edge of the drain electrode DE or the upper side of the upper edge of the scan line GL, and the semiconductor The portion of the layer SC corresponding to the heavily doped predetermined region RD2 may define a heavily doped region SCD serving as the source region and the drain region respectively. The lightly doped predetermined region RL2 is located between the heavily doped predetermined region RD2 and the scan line GL. The upper boundary of the lightly doped predetermined region RL2 may overlap with the lower boundary of the heavily doped predetermined region RD2. The lower boundary of the lightly doped predetermined region RL2 The boundary may overlap with the upper edge of the scan line GL, and the portion of the semiconductor layer SC corresponding to the lightly doped predetermined region RL2 may define a lightly doped region SCL between the undoped region SCC and the heavily doped region SCD.

In the embodiment shown in FIG. 1A , the third portion S3 of the semiconductor layer SC has an inner edge SC1 closer to the scan line GL, and the maximum distance between the inner edge SC1 and the scan line GL ranges from greater than 0 microns to less than or is equal to 5 microns. The above-mentioned maximum distance is represented by distance d1 in Figure 1A (that is, 0 μm < d1 ≦5 μm). The maximum distance can refer to the distance between the saddle point P1 and the lower edge of the scan line GL perpendicular to the scan line GL. The distance in the second direction Y of the extension direction. Since the saddle point P1 is the farthest point between the inner edge SC1 of the third part S3 and the lower edge of the scan line GL, the distance d1 between the inner edge SC1 of the third part S3 and the lower edge of the scan line GL is less than or equal to the above The range of the maximum distance is, for example, 1 micron, 2 microns, 3 microns, 4 microns or 5 microns, but the actual value is not limited to the above example. According to the present disclosure, when the distance between the third part S3 and the scan line GL is within the above range (for example, less than or equal to 5 microns), it means that the turning point of the semiconductor layer SC with the U-shaped pattern (ie, the third part S3 ) is closer The scan line GL makes the distance d2 of the semiconductor layer SC between different adjacent pixels PX on the upper and lower sides larger. This design can increase the aperture ratio of the pixel PX and increase the ratio of the light-emitting area/display area to the area of the pixel PX. For example, when the display device ED is used in high-resolution products, its pixel PX size is small (for example, the distance between adjacent scan lines GL is less than 30 micrometers (μm)), and when the semiconductor layer SC adopts carrier migration When using materials with higher rates (such as low temperature polysilicon (LTPS) materials), the aperture ratio of the pixel PX can be improved by including the lightly doped region SCL in the third part S3 (or the corner of the semiconductor layer SC). , and will not have a significant impact on the charging performance of Pixel PX.

Please refer to FIG. 2 , the following further introduces the configuration of various components of the electronic device ED of the present disclosure. The patterned light-shielding layer M0, the insulating layer 102, the patterned semiconductor layer SC, the insulating layer GI, the patterned first conductive layer M1, the insulating layer 104, and the patterned second conductive layer M2 can be disposed in sequence on the substrate SB1. , the insulating layer 106, the patterned third conductive layer I1, the insulating layer 108 and the fourth conductive layer I2. The substrate SB1 may include a hard substrate or a flexible substrate, but is not limited thereto. The material of the substrate SB1 includes, for example, glass, quartz, sapphire, ceramic, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), and other suitable materials. materials or a combination of the above materials. The light-shielding layer M0 may, for example, include a metal layer or any material with a light-shielding function, and its pattern may at least correspond to the pattern of the gate GE to form a plurality of light-shielding elements LS. For example, the width of the light-shielding element LS may be slightly larger than the width of the gate GE. , but not limited to this. The semiconductor layer SC may include any suitable semiconductor material, such as silicon or metal oxide, such as low-temperature polycrystalline silicon semiconductor or amorphous silicon (a-Si) semiconductor, indium gallium zinc oxide (IGZO) Semiconductor or other suitable semiconductor, but not limited to this. The semiconductor layer SC in this embodiment includes low-temperature polycrystalline silicon semiconductor material as an example. The patterned first conductive layer M1 may constitute the gate GE and the scan line GL. The patterned second conductive layer M2 can form the source electrode SE, the data line DL and the drain electrode DE, wherein the source electrode SE can contact and be electrically connected through the contact hole V1 of the insulating layer 104 and the insulating layer GI as the core of the source region. The doped region SCD and the drain DE can contact and electrically connect to the heavily doped region SCD serving as the drain region through the contact hole V2 between the insulating layer 104 and the gate dielectric layer GI. The insulating layer 106 is disposed on the data line DL and includes a contact hole V3, which exposes part of the drain electrode DE, and the third conductive layer I1 constitutes a transparent electrode PE (for example, as a pixel electrode), which can be exposed through the contact hole V3. Contact and electrically connected to the drain DE. In the normal direction Z, the contact hole V3 may or may not overlap the light shielding layer M0. The insulating layer 108 and a portion of the fourth conductive layer I2 may be disposed in the contact hole V3, and the insulating layer 108 is located between the fourth conductive layer I2 and the third conductive layer I1, so that the fourth conductive layer I2 in the contact hole V3 and the transparent electrode PE are insulated from each other. In this embodiment, the portion of the fourth conductive layer I2 disposed on the upper side of the transparent electrode PE can be used as the common electrode CE, but is not limited to this. The first conductive layer M1 and the second conductive layer M2 may include metal materials, where the metal materials include, for example, aluminum, molybdenum, copper, titanium, other suitable materials, or a combination of at least two of the above, but are not limited thereto. The insulating layer 102, the insulating layer GI, the insulating layer 104, the insulating layer 106 and the insulating layer 108 may include inorganic or organic insulating materials. The inorganic material may include, for example, silicon oxide (SiOx), silicon nitride (SiN), silicon oxynitride (SiOxNy) or other suitable materials or combinations of the above materials, but is not limited thereto. For example, the insulating layer 106 may include organic materials and may serve as a planar layer. The insulating layer 108 may include inorganic materials and serve as a passivation layer, but is not limited to the above.

Furthermore, when the electronic device ED is applied as a display device and includes the display panel 100, the display panel 100 may further include another substrate SB2 and a display medium layer LC, where the display medium layer LC is located between the substrate SB2 and the substrate SB1. The display medium layer LC includes, for example, a liquid crystal layer, but is not limited thereto. The surface of the substrate SB2 may be additionally provided with a patterned light shielding layer, a color filter layer and/or an optical conversion layer (not shown), but is not limited to the above. In addition, polarizers (not shown) can also be provided on the surfaces of the substrate SB2 and the substrate SB1, and spacers (not shown) can also be provided between the substrate SB2 and the substrate SB1, but are not limited to the above.

Please refer to FIG. 1B , which is a partial top view of a variation of the first embodiment of the electronic device of the present disclosure. The difference between the electronic device ED shown in FIG. 1B and FIG. 1A is that the lower side of the scan line GL may not have a heavily doped predetermined region RD1, and the lightly doped predetermined region RL1 may have a larger width W1, so that the third part S3 It is completely located in the lightly doped predetermined region RL1. In other words, the third part S3 is all lightly doped region SCL, and the semiconductor layer SC is in the part between the two undoped regions SCC (or between the two gates GE part) does not have a heavily doped region SCD. The relative positions of the undoped region SCC, the heavily doped region SCD and the lightly doped region SCL in the semiconductor layer SC corresponding to the cross-section line A-A' in FIG. 1B can be referred to FIG. 2 and will not be described again. Furthermore, in the embodiment shown in FIG. 1B , the lower edge of the drain DE and the upper edge of the scan line GL may optionally have a distance d3, that is, the drain DE may not overlap the scan line GL. In the modified embodiment of FIG. 1B , there is still a distance d1 between the inner edge SC1 of the third part S3 and the lower edge of the scan line GL, and the maximum value thereof may range from greater than 0 microns to less than or equal to 5 microns.

The electronic device of the present disclosure is not limited to the above embodiments. Other embodiments or variations of the present disclosure will continue to be disclosed below. However, in order to simplify the description and highlight the differences between the various embodiments or variations, the same elements will be labeled with the same numbers in the following, and the repeated parts will not be described again. In addition, the film layer materials and process step conditions (such as impurity doping concentration) in subsequent embodiments of the present disclosure can refer to the first embodiment, and therefore will not be described again.

Please refer to FIG. 3A , which is a partial top view of an electronic device according to a second embodiment of the present disclosure. The difference between the electronic device ED shown in FIG. 3A and FIG. 1A is that the inner edge SC1 of the third part S3 close to the corresponding scan line GL is aligned with the lower side of the scan line GL, that is, between the inner edge SC1 and the scan line GL. The distance d1 between them is 0 microns. In some embodiments, the distance d1 between the saddle point P1 of the inner edge SC1 and the scan line GL is 0 μm, but the disclosure is not limited thereto. Under this design, the third part S3 of the semiconductor layer SC is disposed close to the lower edge of the scan line GL, thus adding the lower edge of the semiconductor layer SC in the pixel PX and the semiconductor layer SC of another pixel PX below the pixel PX. The advantages of the distance d2 include improving the aperture ratio of the pixel PX. Similar to the embodiment shown in FIG. 1A , a part of the third part S3 (the part closer to the scan line GL in the second direction Y) is the lightly doped region SCL, which corresponds to the lightly doped predetermined region RL1 , and the third part S3 is a lightly doped region SCL. Another part of the part S3 (the part farther away from the scan line GL in the second direction Y) is the heavily doped region SCD. The cross-sectional structure of the electronic device ED corresponding to the cross-section line A-A' in Figure 3A can be referred to Figure 2 and will not be described again.

Please refer to FIG. 3B , which is a partial top view of a variation of the second embodiment of the electronic device of the present disclosure. The difference between the modified embodiment shown in FIG. 3B and FIG. 3A is that the electronic device ED may not have the heavily doped predetermined region RD1, and the lightly doped predetermined region RL1 may have a larger width W1, so that the third part S3 is completely located in the lightly doped region. The doped predetermined region RL1, that is, the third part S3, is a lightly doped region SCL. The semiconductor layer SC does not have a heavily doped region SCD in the part between the two undoped regions SCC (or gate GE). . The cross-sectional structure of the electronic device ED corresponding to the cross-section line A-A' in Figure 3A can be referred to Figure 2 and will not be described again.

Please refer to FIGS. 4A and 4B . FIG. 4A is a partial top view of the electronic device according to the third embodiment of the present disclosure. FIG. 4B is a partial cross-sectional view of the electronic device shown in FIG. 4A along the sectional line BB′. FIG. 4A The cross-sectional structure of the electronic device ED corresponding to the cross-section line AA' can be referred to FIG. 2 . The difference between the embodiment shown in FIG. 4A and FIG. 1A is that the third part S3 of the electronic device ED is close to the inner edge SC1 of the corresponding scan line GL and overlaps the scan line GL and is located between the upper edge and the lower edge of the scan line GL. , that is, a part of the third part S3 overlaps the scan line GL. The part of the third part S3 that overlaps the scan line GL is the undoped region SCC, and the part of the third part S3 that does not overlap the scan line GL is the lightly doped region SCL and corresponds to the lightly doped predetermined region RL1, and the third part S3 does not overlap the scan line GL. Part S3 does not have the heavily doped region SCD. In the embodiment shown in FIG. 4A , the design in which the third part S3 partially overlaps the scan line GL can increase the distance d2 between the semiconductor layers SC in adjacent pixels PX, thereby improving the aperture ratio and process feasibility of the pixel PX.

Please refer to FIG. 5. FIG. 5 is a partial top view of the fourth embodiment of the electronic device of the present disclosure. The partial cross-sectional structure of the electronic device shown in FIG. 5 along the tangent line B-B' can be referred to FIG. 4B. The difference between the electronic device ED shown in Figure 5 and Figure 4A is that the third part S3 is completely covered by the scan line GL, that is, the third part S3 completely overlaps the scan line GL, so the third part S3 is all undoped area SCC. , and does not have the lightly doped region SCL and the heavily doped region SCD. The above design can further increase the distance d2 between the semiconductor layers SC in adjacent pixels PX, thereby improving the aperture ratio and process feasibility of the pixels PX. Alternatively, when the overall size of the pixel PX is reduced, the above design can try to maintain a large aperture ratio of the pixel PX.

Please refer to FIGS. 6A and 6B . FIG. 6A is a partial top view of a fifth embodiment of the electronic device of the present disclosure. FIG. 6B is a partial cross-sectional view of the electronic device shown in FIG. 6A along the section line A-A’. In the partial top view schematic view of FIG. 6A , a top view pattern of the light shielding layer M0 and the contact hole RV of the electronic device ED is shown. The electronic device ED includes a contact hole RV. The contact hole V1 and the contact hole V2 are part of the contact hole RV. The contact hole RV can be formed by etching the insulating layer 104 and the insulating layer GI and exposing the semiconductor layer SC, so that the source The pole SE and the drain DE can be electrically connected to the heavily doped region SCD of the semiconductor layer SC through the contact hole RV. In the embodiment shown in FIG. 6A , the contact hole RV is a laterally extending area, but this design is only an example. In some embodiments, the contact hole RV can be a plurality of mutually separated areas, corresponding to each drain DE. and the predetermined area of source SE. The light-shielding layer M0 includes a light-shielding element LS. The light-shielding element LS may have a rectangular pattern or a laterally extending strip pattern in the normal direction Z of the electronic device ED. For example, the light-shielding element LS may roughly correspond to the scan line GL but may be larger than the scan line GL. Have a larger width, but not limited to this. As shown in FIG. 6A , the width W2 of the scan line GL in the second direction Y may be approximately smaller than the width W3 of the light shielding element LS in the second direction Y. The light-shielding element LS at least partially overlaps the semiconductor layer SC. For example, the light-shielding element LS at least overlaps with the portion of the semiconductor layer SC corresponding to the scan line GL, but is not limited to this. The light-shielding element LS includes a first edge M01 and a second edge M02. The upper edge and the lower edge of the scan line GL are respectively defined as a third edge GL1 and a fourth edge GL2. The first edge M01 of the light-shielding element LS is adjacent to the third edge GL2. The edge GL1 has a first distance D1 from the third edge GL1, the second edge M02 is adjacent to the fourth edge GL2 and has a second distance D2 from the fourth edge GL2, and the first distance D1 is different from the second edge GL2. Distance D2. As shown in FIG. 6A , compared to the third edge GL1 , the fourth edge GL2 of the scan line GL is closer to the inner edge SC1 of the third portion S3 of the semiconductor layer SC, and the first distance D1 is smaller than the second distance D2, also That is to say, the distance between the first edge M01 of the light-shielding element LS and the scanning line GL is smaller than the distance between the second edge M02 and the scanning line GL. The upper and lower edges of the light-shielding element LS have an asymmetric distance relative to the scanning line GL. . Since the first edge M01 of the light-shielding element LS is closer to the scan line GL and has a distance d4 between it and the contact hole RV (as shown in FIG. 6B ), that is, the first edge M01 is located on the scan line GL1 in the second direction Y. between the upper edge (that is, the third edge GL1) and the lower boundary of the contact hole RV, therefore the contact hole RV does not overlap the light-shielding layer M0, that is, the contact hole V2 may not overlap the light-shielding layer M0 or the light-shielding element LS. When the size of the pixel PX is smaller, such as when applied to a high-resolution device (such as a VR device), the contact hole RV will be closer to the scan line GL. In this embodiment, when the first distance D1 is smaller than the second distance D2, the risk of short circuit caused by the electrical connection between the second conductive layer M2 and the light-shielding layer M0 can be reduced. In addition, as shown in FIGS. 6A and 6B , there is a distance d5 between the lower boundary of the contact hole RV and the third edge GL1 of the scan line GL, that is, the contact hole RV may not overlap the scan line GL. The above design of preventing the contact hole RV from overlapping the light shielding layer M0 and the scan line GL can be applied to other embodiments or modified embodiments of the present disclosure, and will not be described again.

According to the present disclosure, the semiconductor layer will be close to the scan line or partially overlap the scan line at the turning point (ie, the third part of the semiconductor layer), so at least a part of the third part is a lightly doped region, or when the turning point of the semiconductor layer When the third part of the semiconductor layer is completely covered or overlapped by the scan line, the third part of the semiconductor layer may be completely an undoped region without a lightly doped region and a heavily doped region. Under the above design, the distance between the semiconductor layers of adjacent pixels can be increased and the pixel aperture ratio can be improved. Even when the pixel size is small, it can still achieve good performance. On the other hand, the design disclosed in the present disclosure prevents the light-shielding layer from overlapping the contact hole, which can improve the problem of component short circuit caused by exposure of the light-shielding layer by the contact hole, and improve product yield.

The above descriptions are only embodiments of the disclosure and are not intended to limit the disclosure. For those skilled in the art, the disclosure may have various modifications and changes. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this disclosure shall be included in the protection scope of this disclosure.

100:Display panel 102,104,106,108,GI:insulation layer CSL: reference line D1: first distance d1,d2,d3: distance D2: second distance d4: interval DE: drain DL: data line DV: driving element ED: electronic device GE: gate GL: scan line GL1: Third Edge GL2: Fourth Edge I1: The third conductive layer I2: The fourth conductive layer LC: display medium layer LS: light shielding element M0: light shielding layer M01: First edge M02:Second edge M1: first conductive layer M2: Second conductive layer P1: saddle point PE: transparent electrode PX: pixel area RD1, RD2: heavily doped predetermined area RL1, RL2: Lightly doped predetermined area S1:Part One S2:Part Two S3:Part Three SB1,SB2:Substrate SC: semiconductor layer SC1: inner edge SC2: outer edge SCC: undoped area SCD: heavily doped region SCL: lightly doped region SE: source RV,V1,V2,V3: contact holes W1,W2,W3: Width X: first direction Y: second direction Z: normal direction

FIG. 1A is a partial top view of the electronic device according to the first embodiment of the present disclosure. FIG. 1B is a partial top view of a variation of the first embodiment of the electronic device of the present disclosure. FIG. 2 is a partial cross-sectional view of the electronic device of the present disclosure along the cross-sectional line A-A’ of FIG. 1A. FIG. 3A is a partial top view of the electronic device according to the second embodiment of the present disclosure. FIG. 3B is a partial top view of a variation of the second embodiment of the electronic device of the present disclosure. FIG. 4A is a partial top view of an electronic device according to a third embodiment of the present disclosure. FIG. 4B is a partial cross-sectional view of the electronic device of the present disclosure along the section line B-B' of FIG. 4A. FIG. 5 is a partial top view of an electronic device according to a fourth embodiment of the present disclosure. FIG. 6A is a partial top view of an electronic device according to a fifth embodiment of the present disclosure. FIG. 6B is a partial cross-sectional view of the electronic device of the present disclosure along the cross-sectional line A-A' of FIG. 6A.

CSL: reference line

d1,d2: distance

DE: drain

DL: data line

DV: driving element

ED: electronic device

GL: scan line

M1: first conductive layer

M2: Second conductive layer

P1: saddle point

PX: pixel area

RD1, RD2: heavily doped predetermined area

RL1, RL2: Lightly doped predetermined area

S1:Part One

S2:Part Two

S3:Part Three

SC: semiconductor layer

SC1: inner edge

SC2: outer edge

SCC: undoped area

SCD: heavily doped region

SCL: lightly doped region

X: first direction

Y: second direction

Z: normal direction

Claims (10)

An electronic device including: a substrate; A data line is provided on the substrate; a drain disposed on the substrate; and A semiconductor layer is provided on the substrate, the semiconductor layer includes a first part connected to the data line, a second part connected to the drain, and a third part connected between the first part and the second part; At least part of the third part includes at least one of Group IIIA elements and Group VA elements, and the doping concentration of at least one of Group IIIA elements and Group VA elements is greater than 0 and less than or equal to 10^16 atoms. /cubic centimeter. The electronic device of claim 1, further comprising a scan line disposed on the substrate, the scan line extending in one direction and at least partially overlapping the semiconductor layer, the third portion having an inner portion close to the scan line. The range of the maximum distance between the edge and the inner edge and the scan line is greater than 0 microns and less than or equal to 5 microns. The electronic device of claim 1, further comprising a scan line disposed on the substrate, the scan line extending in one direction and at least partially overlapping the semiconductor layer, the third portion having an inner portion close to the scan line. edge, and the distance between the inner edge and the scan line is 0 microns. The electronic device of claim 1, further comprising a scan line disposed on the substrate, the scan line extending in one direction and at least partially overlapping the semiconductor layer, the third portion having an inner portion close to the scan line. edge, and the inner edge overlaps the scan line. The electronic device as described in claim 1 further includes: A scan line is disposed on the substrate, the scan line extends along a direction and at least partially overlaps the semiconductor layer, wherein the third portion has an inner edge close to the scan line; and A light-shielding layer is disposed between the substrate and the semiconductor layer, and the light-shielding layer at least partially overlaps the semiconductor layer; The light shielding layer includes a first edge and a second edge, the scan line includes a third edge and a fourth edge, the first edge is adjacent to the third edge and has a first edge between the first edge and the third edge. distance, the second edge is adjacent to the fourth edge and has a second distance from the fourth edge, and the first distance is different from the second distance. The electronic device of claim 5, wherein the fourth edge is adjacent to the inner edge, and the first distance is smaller than the second distance. The electronic device as described in claim 5 further includes: An insulating layer is disposed on the semiconductor layer, wherein the insulating layer includes a contact hole; and A transparent electrode is electrically connected to the semiconductor layer through the contact hole, wherein the contact hole does not overlap the light-shielding layer. The electronic device according to claim 1, wherein the doping concentration range of the at least one of the IIIA group elements and the VA group elements in the at least part of the third part is 10^10 to 10^16 atoms/cubic centimeter. . An electronic device, characterized by including: a substrate; A data line is provided on the substrate and extends along a first direction; a drain, disposed on the substrate; A scan line is provided on the substrate and extends along a second direction, wherein the second direction is different from the first direction; and A semiconductor layer is provided on the substrate, the semiconductor layer includes a first part connected to the data line, a second part connected to the drain, and a third part connected between the first part and the second part, and The third part overlaps the scan line GL; At least part of the third part includes at least one of Group IIIA elements and Group VA elements, and the doping concentration of at least one of Group IIIA elements and Group VA elements is greater than 0 and less than or equal to 10^16 atoms. /cubic centimeter. The electronic device according to claim 9, wherein the doping concentration of the at least one of the Group IIIA elements and the Group VA elements in the at least part of the third part ranges from 10 ¹⁰ to 10 ¹⁶ atoms/cubic centimeter.

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