TW202349743A - Current spreading layer structures for light-emitting diode chips - Google Patents
Current spreading layer structures for light-emitting diode chips Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
- H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
- H01L33/405—Reflective materials
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Abstract
Description
本發明係關於包含發光二極體之固態發光裝置，且更特定言之係關於用於發光二極體晶片之電流分散層結構。The present invention relates to solid state light emitting devices including light emitting diodes, and more particularly to current dispersion layer structures for light emitting diode wafers.
諸如發光二極體(light-emitting diode；LED)之固態發光裝置愈來愈用於消費者及商業應用兩者中。發光二極體技術中之進步已產生具有長使用壽命之高效且機械強健的光源。因此，現代發光二極體已啟用各種新顯示器應用，且愈來愈多用於概括照明應用，通常替代白熾及螢光光源。Solid-state light-emitting devices such as light-emitting diodes (LEDs) are increasingly used in both consumer and commercial applications. Advances in light-emitting diode technology have resulted in efficient and mechanically robust light sources with long service life. As a result, modern light-emitting diodes have enabled a variety of new display applications and are increasingly used in general lighting applications, often replacing incandescent and fluorescent light sources.
發光二極體為將電能轉換成光之固態裝置，且通常包含配置於相反摻雜之n型層與p型層之間的半導體材料之一或多個主動層(或主動區)。當跨摻雜層施加偏壓時，電洞及電子注入至一或多個主動層中，其中電洞及電子復合以產生發射，諸如可見光或紫外線發射。可由例如碳化矽、氮化鎵、磷化鎵、氮化鋁及/或砷化鎵基材料及/或由有機半導體材料製成主動區。由主動區產生之光子在所有方向被激發。Light-emitting diodes are solid-state devices that convert electrical energy into light, and typically include one or more active layers (or active regions) of semiconductor material disposed between oppositely doped n-type and p-type layers. When a bias is applied across the doped layer, holes and electrons are injected into one or more active layers, where they recombine to produce emission, such as visible or ultraviolet emission. The active region may be made of, for example, silicon carbide, gallium nitride, gallium phosphide, aluminum nitride and/or gallium arsenide based materials and/or made of organic semiconductor materials. Photons generated by the active region are excited in all directions.
典型地，期望以最高光發射效率操作發光二極體，最高光發射效率能藉由相對於輸出功率(例如，以流明/瓦特為單位)之發射強度來量測。增強發射效率之實際目標為最大化在所要光透射之方向由主動區發射之光的萃取。發光二極體之光萃取及外部量子效率能受包含內部反射之多個因子限制。若以重複方式內部反射光子，則此類光子最終被吸收且從不提供從發光二極體出射之可見光。為增加光子從發光二極體出射之機會，已發現圖案化、粗糙化或以其他方式紋理化發光二極體表面與周圍環境之間的介面，以提供增加折射超過內部反射之機率，且因此增強光萃取的變化表面係有用的。亦可提供反射性表面以反射所產生光以使得此光可促成自發光二極體晶片之可用發射。發光二極體已開發具有用以反射所產生光之內部反射表面或層。Typically, it is desirable to operate a light emitting diode with maximum light emission efficiency, which can be measured by emission intensity relative to output power (eg, in lumens/watt). The actual goal of enhancing emission efficiency is to maximize the extraction of light emitted by the active region in the direction of desired light transmission. The light extraction and external quantum efficiency of light-emitting diodes can be limited by multiple factors including internal reflection. If photons are internally reflected in a repeated pattern, such photons are eventually absorbed and never provide visible light emitted from the light-emitting diode. To increase the chance of photons emerging from a light-emitting diode, it has been found to pattern, roughen, or otherwise texture the interface between the light-emitting diode surface and the surrounding environment to provide increased opportunities for refraction over internal reflection, and thus Varying surface systems are useful to enhance light extraction. Reflective surfaces may also be provided to reflect the light generated so that this light contributes to usable emission from the self-luminescent diode wafer. Light emitting diodes have been developed with internal reflective surfaces or layers to reflect the light generated.
發光二極體之量子效率亦能藉由其他因子(諸如電流能夠在發光二極體內分散的程度如何)限制。為增加發光二極體(且特定言之較大區域發光二極體)之電流分散，已發現在發光二極體之一或多個磊晶層之上添加高電導率層係有用的。另外，用於發光二極體之電極能具有較大表面區域且可包含布置以跨越發光二極體路由且更均勻分配電流的各種電極延伸部或指。The quantum efficiency of an LED can also be limited by other factors, such as how well the current can be dispersed within the LED. To increase the current dispersion of a light emitting diode (and in particular a larger area light emitting diode), it has been found useful to add a high conductivity layer on top of one or more epitaxial layers of the light emitting diode. Additionally, electrodes for light-emitting diodes can have larger surface areas and may include various electrode extensions or fingers arranged to route and more evenly distribute current across the light-emitting diodes.
隨著現代發光二極體技術發展的進步，此項技術持續尋求具有能夠克服與習知發光裝置相關聯之挑戰的所需照明特性的改良發光二極體及固態發光裝置。As modern light-emitting diode technology advances, the technology continues to seek improved light-emitting diodes and solid-state light-emitting devices with desirable lighting characteristics that overcome the challenges associated with conventional light-emitting devices.
本發明係關於包含發光二極體之固態發光裝置，且更特定言之係關於用於發光二極體晶片之電流分散層結構。發光二極體晶片包含主動發光二極體結構，所述主動發光二極體結構具有提供到達所述主動發光二極體結構中之高效電流注入，同時亦提供改良之光萃取的相對於反射結構之電流分散層配置。電流分散層包含允許介電反射器層之部分形成與鄰近電流分散層之主動發光二極體結構的介面的開口。金屬反射器層提供於介電反射器層上，且形成穿過介電反射器層以接觸電流分散層之部分的反射層互連件。The present invention relates to solid state light emitting devices including light emitting diodes, and more particularly to current dispersion layer structures for light emitting diode wafers. A light-emitting diode chip including an active light-emitting diode structure having a structure that provides efficient current injection into the active light-emitting diode structure while also providing improved light extraction relative to a reflective structure The current dispersion layer configuration. The current spreading layer includes openings that allow portions of the dielectric reflector layer to interface with the active light emitting diode structure adjacent the current spreading layer. A metallic reflector layer is provided on the dielectric reflector layer and a reflective layer interconnect is formed through the dielectric reflector layer to contact portions of the current dispersion layer.
在一態樣中，發光二極體晶片包括：主動發光二極體結構，其包括n型層、p型層及介於該n型層與該p型層之間的主動層；電流分散層，其在該主動發光二極體結構上；及介電反射器層，其在該電流分散層上，該電流分散層形成複數個開口，且該介電反射器層之部分延伸穿過該複數個開口。在某些實施例中，電流分散層包括氧化銦錫。在某些實施例中，介電反射器層包括二氧化矽。發光二極體晶片可進一步包括在介電反射器層上的金屬反射器層及自該金屬反射器層且穿過該介電反射器層而延伸的複數個反射層互連件。在某些實施例中，複數個反射層互連件接觸電流分散層之部分。在某些實施例中，複數個電流分散層開口界定電流分散層之複數個不連續區。在某些實施例中，複數個反射層互連件接觸複數個電流分散層不連續區。在某些實施例中，複數個電流分散層開口界定藉由電流分散層之延伸部連接的複數個電流分散層區。In one aspect, the light-emitting diode chip includes: an active light-emitting diode structure including an n-type layer, a p-type layer and an active layer between the n-type layer and the p-type layer; a current dispersion layer , which is on the active light emitting diode structure; and a dielectric reflector layer, which is on the current dispersion layer, the current dispersion layer forms a plurality of openings, and a portion of the dielectric reflector layer extends through the plurality of openings. an opening. In certain embodiments, the current dispersion layer includes indium tin oxide. In certain embodiments, the dielectric reflector layer includes silicon dioxide. The light emitting diode wafer may further include a metal reflector layer on the dielectric reflector layer and a plurality of reflective layer interconnects extending from the metal reflector layer and through the dielectric reflector layer. In some embodiments, a plurality of reflective layer interconnects contact portions of the current spreading layer. In certain embodiments, a plurality of current dispersion layer openings define a plurality of discontinuous regions of the current dispersion layer. In certain embodiments, a plurality of reflective layer interconnects contact a plurality of current dispersion layer discontinuities. In some embodiments, a plurality of current spreading layer openings define a plurality of current spreading layer regions connected by extensions of the current spreading layer.
在某些實施例中，發光二極體晶片進一步包括配置以延伸穿過電流分散層、p型層及主動層以接觸n型層之一部分的n接觸互連件，其中電流分散層之邊緣與n接觸互連件側向間隔開。在某些實施例中，電流分散層之邊緣形成圍繞n接觸互連件之周邊的非圓形形狀。In certain embodiments, the light emitting diode wafer further includes an n-contact interconnect configured to extend through the current spreading layer, the p-type layer, and the active layer to contact a portion of the n-type layer, wherein an edge of the current spreading layer is The n-contact interconnects are laterally spaced apart. In certain embodiments, the edges of the current spreading layer form a non-circular shape around the perimeter of the n-contact interconnect.
在另一態樣中，發光二極體晶片包括：主動發光二極體結構，其包括n型層、p型層及介於該n型層與該p型層之間的主動層；複數個電流分散區，其在該主動發光二極體結構上，複數個電流分散區中之各電流分散區與複數個電流分散區中之其他電流分散區不連續；介電反射器層，其在複數個電流分散區上；及金屬反射器層，其在該介電反射器層上，且藉由自金屬反射器層及穿過該介電反射器層延伸的複數個反射層互連件而電耦接至複數個電流分散區。在某些實施例中，複數個電流分散區中之各電流分散區藉由複數個反射性層互連件中之單一反射性層互連件電耦接至金屬反射器層。在某些實施例中，反射層互連件包括與金屬反射器層相同之材料。在某些實施例中，介電反射器層之部分在複數個電流分散區之鄰近電流分散區之間延伸。在某些實施例中，介電反射器層之部分接觸複數個電流分散區之鄰近電流分散區之間的主動發光二極體結構。在某些實施例中，複數個電流分散區中之各電流分散區形成圓形形狀。在某些實施例中，各圓形形狀之直徑大於複數個反射層互連件中之各反射層互連件的直徑。在某些實施例中，複數個電流分散區中之各電流分散區形成正方形、矩形、橢圓形、六邊形或八邊形之形狀。在某些實施例中，複數個反射層互連件中之個別反射性層互連件的直徑跨越主動發光二極體結構而變化。In another aspect, a light-emitting diode chip includes: an active light-emitting diode structure including an n-type layer, a p-type layer, and an active layer between the n-type layer and the p-type layer; a plurality of A current dispersion region, on the active light emitting diode structure, each current dispersion region in the plurality of current dispersion regions is discontinuous with other current dispersion regions in the plurality of current dispersion regions; a dielectric reflector layer, which is in the plurality of current dispersion regions. on a current dispersion region; and a metal reflector layer on the dielectric reflector layer and electrically electrically connected by a plurality of reflective layer interconnects extending from the metal reflector layer and through the dielectric reflector layer. Coupled to a plurality of current dispersion regions. In certain embodiments, each current spreading region of the plurality of current spreading regions is electrically coupled to the metal reflector layer by a single reflective layer interconnect of the plurality of reflective layer interconnects. In some embodiments, the reflective layer interconnects include the same material as the metal reflector layer. In certain embodiments, portions of the dielectric reflector layer extend between adjacent current spreading regions of the plurality of current spreading regions. In some embodiments, a portion of the dielectric reflector layer contacts the active light emitting diode structure between adjacent current spreading regions of the plurality of current spreading regions. In some embodiments, each of the plurality of current dispersion regions forms a circular shape. In some embodiments, the diameter of each circular shape is greater than the diameter of each reflective layer interconnect of the plurality of reflective layer interconnects. In some embodiments, each of the plurality of current dispersion regions forms a square, rectangular, elliptical, hexagonal or octagonal shape. In certain embodiments, the diameter of individual reflective layer interconnects in the plurality of reflective layer interconnects varies across the active light emitting diode structure.
發光二極體晶片可進一步包括配置以延伸穿過複數個電流分散區、p型層及主動層以與n型層電耦接的n接觸互連件，其中：複數個反射層互連件包括第一反射層互連件及第二反射層互連件；該第一反射層互連件比該第二反射層互連件更接近於n接觸互連件而定位，且該第一反射層互連件之直徑大於該第二反射層互連件之直徑。發光二極體晶片可進一步包括配置以延伸穿過複數個電流分散區、p型層及主動層以與n型層電耦接的n接觸互連件，其中：複數個電流分散區包括第一電流分散區及第二電流分散區，使得該第一電流分散區比該第二電流分散區更接近於n接觸互連件；且該第一電流分散區之直徑大於該第二電流分散區之直徑。The light emitting diode wafer may further include n-contact interconnects configured to extend through the plurality of current dispersion regions, the p-type layer, and the active layer to electrically couple with the n-type layer, wherein: the plurality of reflective layer interconnects include a first reflective layer interconnect and a second reflective layer interconnect; the first reflective layer interconnect is positioned closer to the n-contact interconnect than the second reflective layer interconnect, and the first reflective layer The diameter of the interconnect is larger than the diameter of the second reflective layer interconnect. The light emitting diode chip may further include an n-contact interconnect configured to extend through the plurality of current spreading regions, the p-type layer, and the active layer to electrically couple with the n-type layer, wherein: the plurality of current spreading regions include a first The current dispersion region and the second current dispersion region are such that the first current dispersion region is closer to the n-contact interconnect than the second current dispersion region; and the diameter of the first current dispersion region is larger than that of the second current dispersion region. diameter.
在另一態樣中，如本文所述的任一前述態樣、及/或各種獨立態樣及特徵可個別或一起組合以得到額外優點。如本文所揭示的各種特徵及元件之任一者可與所揭示之一或多種其他特徵及元件組合，除非本文中有相反繪示。In another aspect, any of the foregoing aspects, and/or various independent aspects and features as described herein, can be combined individually or together to obtain additional advantages. Any of the various features and elements as disclosed herein may be combined with one or more other features and elements disclosed, unless indicated to the contrary herein.
所屬技術領域中具有通常知識者將瞭解本發明之範疇，且在閱讀與隨附圖式結合的以下較佳實施例之詳細描述之後認識到本發明之額外態樣。Those of ordinary skill in the art will understand the scope of the invention and recognize additional aspects of the invention upon reading the following detailed description of the preferred embodiments taken in conjunction with the accompanying drawings.
下文所闡述之實施例表示使所屬技術領域中具有通常知識者能夠實踐實施例所必需的資訊，且繪示實踐實施例之最佳方式。所屬技術領域中具有通常知識者結合附圖閱讀以下繪示後，將瞭解本發明之概念且將認識本文中未具體提出的所述概念之應用。應理解的是，所述概念及應用屬於本發明及隨附申請專利範圍之範疇內。The embodiments described below represent the information necessary to enable a person of ordinary skill in the art to practice the embodiments and illustrate the best way of practicing the embodiments. A person of ordinary skill in the art will understand the concepts of the present invention after reading the following illustrations in conjunction with the accompanying drawings and will recognize applications of the concepts not specifically proposed herein. It is understood that the concepts and applications described are within the scope of this invention and the accompanying patent applications.
應理解的是，儘管術語第一、第二等可在本文中用以描述各種元件，但所述元件不應受所述術語限制。所述術語僅用於將一個元件與另一個元件區分開來。舉例而言，在不脫離本發明之範疇的情況下，可將第一元件稱為第二元件，且類似地，可將第二元件稱為第一元件。如本文中所用，術語「及/或」包含相關聯的所列項目中之一或多者的任何及所有組合。It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, the elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element, without departing from the scope of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
應理解的是，當諸如層、區或基板的元件稱作在另一元件「上」或延伸至另一元件「上」時，其能直接在另一元件上或直接延伸至另一元件上，或亦可存在介入元件。相比之下，當一元件稱作「直接位於另一元件上」或「直接延伸至另一元件上」時，不存在介入元件。同樣，應瞭解的是，當諸如層、區或基板之元件稱作「位於另一元件上方」或「在另一元件上方」延伸時，其能直接位於另一元件上方或直接在另一元件上方延伸，或亦可存在介入元件。相比之下，當一元件稱作「直接位於另一元件上方」或「直接在另一元件上方延伸」時，不存在介入元件。亦應理解的是，當一元件稱作「連接」或「耦接」至另一元件時，其能直接連接或耦接至另一元件，或可存在介入元件。相比之下，當元件稱作「直接連接」或「直接耦接」至另一元件時，不存在介入元件。It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "on" another element, it can be directly on or extending directly to the other element , or intervening components may also be present. In contrast, when an element is referred to as being "directly on" or "directly extending directly onto" another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" or "extending over" another element, it can be directly on the other element or directly on the other element. Extend above, or there may also be intervening elements. In contrast, when an element is referred to as being "directly on" or "extending directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening components present.
諸如「下方」或「之上」、或「上部」或「下部」、或者「水平」或「垂直」的相對術語可在本文中用於描述如諸圖中所繪示的一個元件、層或區與另一元件、層或區的關係。應瞭解的是，所述術語及上文所論述之術語意欲涵蓋除諸圖中所描繪之定向之外的不同裝置定向。Relative terms such as “below” or “above,” or “upper” or “lower,” or “horizontal” or “vertical” may be used herein to describe an element, layer, or element as depicted in the Figures. A zone's relationship to another component, layer, or zone. It will be understood that the terms described and discussed above are intended to cover different orientations of the device in addition to those depicted in the figures.
本文中使用之術語僅用於描述特定實施例之目的，且並不意欲限制本發明。如本文中所使用，除非上下文另外清楚地指示，否則單數形式「一」及「該」亦意欲包含複數形式。應進一步理解，術語「包括」及/或「包含」在本文中使用時指定所陳述之特徵、整體、步驟、操作、元件及/或組件的存在，但不排除一或多個其他特徵、整體、步驟、操作、元件、組件及/或其群組的存在或添加。The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "includes" when used herein designate the presence of stated features, integers, steps, operations, elements and/or components but do not exclude one or more other features, integers , the existence or addition of steps, operations, elements, components and/or groups thereof.
除非另外定義，否則本文使用的全部術語(包含技術及科學術語)的含義與一般熟習本發明所屬的技術者通常理解的含義相同。應進一步瞭解，本文所用的術語應解釋為具有符合其在本說明書上下文中及相關技術中之含義的含義，且不應在理想化或過度正式的意義上解釋，除非本文中明確如此定義。Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It is further understood that terms used herein are to be construed to have meanings consistent with their meaning in the context of this specification and in the related art, and are not to be construed in an idealized or overly formal sense unless expressly so defined herein.
本文中參考本發明之實施例之示意性繪示來描述實施例。因此，層及元件之實際尺寸能不同，且預期到由於(例如)製造技術及/或公差引起的繪示之形狀的變化。舉例而言，繪示或描述為正方形或矩形之區能具有圓形或彎曲特徵，且展示為直線之區可具有某一不規則性。因此，諸圖中所繪示之區為示意性的，且其形狀並不意欲繪示裝置之區的精確形狀，且並不意欲限制本發明之範疇。另外，出於繪示性目的，結構或區之尺寸可相對於其他結構或區放大，且因此經提供以繪示本發明主題之通用結構且可或可不按比例繪製。諸圖之間的共同元件可在本文中展示為具有共同元件符號，且可隨後不進行重複描述。Embodiments are described herein with reference to schematic illustrations of embodiments of the invention. Accordingly, actual dimensions of layers and elements can vary, and variations in depicted shapes due, for example, to manufacturing techniques and/or tolerances are anticipated. For example, areas shown or described as squares or rectangles can have rounded or curved features, and areas shown as straight lines can have certain irregularities. Accordingly, the regions depicted in the figures are schematic and their shapes are not intended to depict the precise shapes of regions of the device and are not intended to limit the scope of the invention. Additionally, for illustrative purposes, the dimensions of structures or regions may be exaggerated relative to other structures or regions, and thus are provided to illustrate general structures of the present subject matter and may or may not be drawn to scale. Common elements between the figures may be shown herein with common element symbols and may not be described again subsequently.
本發明係關於包含發光二極體之固態發光裝置，且更特定言之係關於用於發光二極體晶片之電流分散層結構。發光二極體晶片包含主動發光二極體結構，所述主動發光二極體結構具有提供到達所述主動發光二極體結構中之高效電流注入同時亦提供改良之光萃取的相對反射性結構之電流分散層配置。電流分散層包含允許介電反射器層之部分形成與鄰近電流分散層之主動發光二極體結構的介面的開口。金屬反射器層提供於介電反射器層上，且形成穿過介電反射器層以接觸電流分散層之部分的反射層互連件。The present invention relates to solid state light emitting devices including light emitting diodes, and more particularly to current dispersion layer structures for light emitting diode wafers. A light emitting diode chip includes an active light emitting diode structure having a relatively reflective structure that provides efficient current injection into the active light emitting diode structure while also providing improved light extraction. Current dispersion layer configuration. The current spreading layer includes openings that allow portions of the dielectric reflector layer to interface with the active light emitting diode structure adjacent the current spreading layer. A metallic reflector layer is provided on the dielectric reflector layer and a reflective layer interconnect is formed through the dielectric reflector layer to contact portions of the current dispersion layer.
發光二極體晶片典型包括能具有以不同方式配置之許多不同半導體層的主動發光二極體結構或區。發光二極體及其主動結構之製造及操作通常為在所屬領域中已知，且本文中僅簡要地論述。主動發光二極體結構之層能使用具有使用金屬有機化學氣相沉積製造合適處理之已知製程製造。主動發光二極體結構之層能包括許多不同層，且通常包括夾在n型與p型相反摻雜磊晶層之間的主動層，其皆連續形成於生長基板上。應理解的是，額外層及元件亦能包含於主動發光二極體結構中，包含(但不限於)緩衝層、成核層、超晶格結構、未摻雜層、包覆層、接觸層、以及電流分散層及光萃取層及元件。主動層能包括單量子井、多量子井、雙異質結構或超晶格結構。Light emitting diode wafers typically include active light emitting diode structures or regions that can have many different semiconductor layers configured in different ways. The fabrication and operation of light emitting diodes and their active structures are generally known in the art and are only briefly discussed herein. The layers of the active light emitting diode structure can be fabricated using known processes with suitable processes using metal organic chemical vapor deposition. The layers of an active light emitting diode structure can include many different layers, and typically include an active layer sandwiched between n-type and p-type oppositely doped epitaxial layers, both formed continuously on a growth substrate. It should be understood that additional layers and components can also be included in the active light emitting diode structure, including (but not limited to) buffer layers, nucleation layers, superlattice structures, undoped layers, cladding layers, and contact layers. , as well as current dispersion layer and light extraction layer and components. Active layers can include single quantum wells, multiple quantum wells, double heterostructures or superlattice structures.
主動發光二極體結構能由不同材料系統製造，其中一些材料系統為基於III族氮化物之材料系統。III族氮化物指形成於氮(N)與週期表III族元素之間的彼等半導體化合物，通常為鋁(Al)、鎵(Ga)及銦(In)。氮化鎵(Gallium nitride；GaN)為常見二元化合物。III族氮化物亦指三元及四元化合物，諸如氮化鋁鎵(aluminum gallium nitride；AlGaN)、氮化銦鎵(indium gallium nitride；InGaN)及氮化鋁銦鎵(aluminum indium gallium nitride；AlInGaN)。對於III族氮化物，矽(Si)為常見n型摻雜劑，且鎂(Mg)為常見p型摻雜劑。因此，對於基於III族氮化物之材料系統，主動層、n型層及p型層可包含GaN、AlGaN、InGaN以及AlInGaN之一或多個層，所述層為未經摻雜或摻雜有Si或Mg。其他材料系統包含碳化矽(silicon carbide；SiC)、有機半導體材料及諸如磷化鎵(gallium phosphide；GaP)、砷化鎵(gallium arsenide；GaAs)之其他III至V族系統及相關化合物。Active light-emitting diode structures can be fabricated from different material systems, some of which are Group III nitride-based material systems. Group III nitrides refer to those semiconductor compounds formed between nitrogen (N) and Group III elements of the periodic table, typically aluminum (Al), gallium (Ga), and indium (In). Gallium nitride (GaN) is a common binary compound. Group III nitrides also refer to ternary and quaternary compounds, such as aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN) and aluminum indium gallium nitride (AlInGaN). ). For Group III nitrides, silicon (Si) is a common n-type dopant, and magnesium (Mg) is a common p-type dopant. Therefore, for III-nitride based material systems, the active layer, the n-type layer, and the p-type layer may include one or more layers of GaN, AlGaN, InGaN, and AlInGaN, either undoped or doped with Si or Mg. Other material systems include silicon carbide (SiC), organic semiconductor materials, and other Group III to V systems such as gallium phosphide (GaP), gallium arsenide (GaAs) and related compounds.
主動發光二極體結構可生長於生長基板上，生長基板能包含許多材料，諸如藍寶石、SiC、氮化鋁(aluminum nitride；AlN)、GaN，其中合適的基板是SiC的4H多型體(polytype)，但亦能使用其他SiC多型體，包含3C、6H及15R的多型體。SiC具有某些優點，諸如相比於其他基板更接近III族氮化物之晶格匹配且產生高品質III族氮化物膜。SiC亦具有極高導熱性，使得SiC上之III族氮化物裝置之總輸出功率不受基板熱耗散限制。藍寶石為用於III族氮化物之另一常見基板且亦具有某些優點，包含較低成本、具有成熟製造製程及具有良好的透光光學性質。The active light-emitting diode structure can be grown on a growth substrate. The growth substrate can contain many materials, such as sapphire, SiC, aluminum nitride (AlN), GaN. A suitable substrate is the 4H polytype of SiC. ), but other SiC polytypes can also be used, including those of 3C, 6H and 15R. SiC has certain advantages, such as a closer lattice match to III-nitride than other substrates and producing high-quality III-nitride films. SiC also has extremely high thermal conductivity, so that the total output power of III-nitride devices on SiC is not limited by substrate heat dissipation. Sapphire is another common substrate for Group III nitrides and also offers certain advantages, including lower cost, mature manufacturing processes, and good light-transmitting optical properties.
主動發光二極體結構之不同實施例能取決於主動層、以及n型及p型層之組成而發射不同波長之光。在某些實施例中，主動發光二極體結構可發射峰值波長範圍為大約430奈米(nm)至480 nm之藍光。在其他實施例中，主動發光二極體結構可發射峰值波長範圍為500 nm至570 nm之綠光。在其他實施例中，主動發光二極體結構可發射峰值波長範圍為600 nm至650 nm之紅光。在某些實施例中，主動發光二極體結構可發射峰值波長在任何可見光譜區域中之光，例如峰值波長主要在400 nm至700 nm範圍中。Different embodiments of active light emitting diode structures can emit light at different wavelengths depending on the composition of the active layer, and n-type and p-type layers. In some embodiments, the active light emitting diode structure can emit blue light with a peak wavelength ranging from approximately 430 nanometers (nm) to 480 nm. In other embodiments, the active light-emitting diode structure can emit green light with a peak wavelength ranging from 500 nm to 570 nm. In other embodiments, the active light emitting diode structure can emit red light with a peak wavelength ranging from 600 nm to 650 nm. In some embodiments, the active light emitting diode structure can emit light with a peak wavelength in any visible spectrum region, for example, a peak wavelength primarily in the range of 400 nm to 700 nm.
在某些實施例中，主動發光二極體結構可布置以發射可見光譜之外的光，包含紫外(ultraviolet；UV)光譜、紅外(infrared；IR)或近IR光譜之一或多個部分。UV光譜通常劃分成用字母A、B及C表示之三個波長範圍類別。以此方式，UV-A光典型定義為315 nm至400 nm之範圍中的峰值波長，UV-B典型定義為280 nm至315 nm之範圍中的峰值波長，且UV-C典型定義為100 nm至280 nm之範圍中的峰值波長。UV發光二極體特別適用於與空氣、水及表面中之微生物消毒相關的應用以及其他應用。在其他應用中，UV發光二極體亦可具備一或多種發光磷光材料，以為發光二極體封裝提供具有用於可見光應用之寬廣光譜及經改良色彩品質的密集發射。用於本發明之發光二極體結構的近IR及/或IR波長可具有高於700 nm(諸如在750 nm至1100 nm或多於1100 nm之範圍中)之波長。In certain embodiments, the active light emitting diode structure may be arranged to emit light outside the visible spectrum, including one or more portions of the ultraviolet (UV) spectrum, the infrared (IR) or the near-IR spectrum. The UV spectrum is usually divided into three wavelength range categories represented by the letters A, B and C. In this way, UV-A light is typically defined as having a peak wavelength in the range of 315 nm to 400 nm, UV-B is typically defined as having a peak wavelength in the range of 280 nm to 315 nm, and UV-C is typically defined as 100 nm to a peak wavelength in the range of 280 nm. UV light-emitting diodes are particularly suitable for applications related to the disinfection of microorganisms in air, water and surfaces, among other applications. In other applications, UV light emitting diodes may also be provided with one or more luminescent phosphorescent materials to provide the light emitting diode package with dense emission with a broad spectrum and improved color quality for visible light applications. The near IR and/or IR wavelengths used in the light emitting diode structures of the present invention may have wavelengths above 700 nm, such as in the range of 750 nm to 1100 nm or more than 1100 nm.
發光二極體晶片亦能覆蓋有一或多種發光磷光或其他轉換材料(諸如磷光體)，使得來自發光二極體晶片之光中之至少一些由一或多種磷光體吸收且根據來自一或多種磷光體之特性轉換成一或多個不同波長光譜。在一些實施例中，發光二極體晶片與一或多個磷光體之組合發射通常白色之光組合。一或多種磷光體可包含發射黃色(例如YAG:Ce)、綠色(例如LuAg:Ce)及紅色(例如Ca i-x-ySr xEu yAlSiN 3)之磷光體及其組合。如本文中所描述之發光磷光材料可為或可包含磷光體、閃爍體、發光磷光墨水、量子點材料、日光帶及類似者中之一或多者。可藉由任何適合手段提供發光磷光材料，例如直接塗佈於發光二極體之一或多個表面上、分散於經布置以覆蓋一或多個發光二極體之囊封材料中、及/或塗佈於一或多個光學或支撐元件上(例如藉由粉末塗佈、噴墨印刷或其類似方式)。在某些實施例中，發光磷光材料可降頻轉換或升頻轉換，且可提供降頻轉換及升頻轉換材料兩者之組合。在某些實施例中，布置以產生不同峰值波長之多個不同(例如組成不同)發光磷光材料可布置以自一或多個發光二極體晶片接收發射。在一些實施例中，一或多種磷光體可包含黃色磷光體(例如，YAG:Ce)、綠色磷光體(例如，LuAg:Ce)、及紅色磷光體(例如，Ca i-x-ySr xEu yAlSiN 3)、以及以上各者之組合。一或多種發光磷光材料可以各種布置提供於發光二極體晶片及/或子安裝件之一或多個部分上。在某些實施例中，發光二極體晶片之一或多個表面可以一或多種發光材料保形塗佈，而此類發光二極體晶片及/或相關聯子安裝件之其他表面可不含發光磷光材料。在某些實施例中，發光二極體晶片之頂表面可包含發光磷光材料，而發光二極體晶片之一或多個側表面可不含發光磷光材料。在某些實施例中，發光二極體晶片之全部或實質全部外表面(例如，除接觸界定或安裝表面外)可用一或多種發光磷光材料塗佈或以其他方式覆蓋。在某些實施例中，一或多種發光磷光材料可以實質均勻之方式布置於發光二極體晶片之一或多個表面上或上方。在其他實施例中，一或多種發光磷光材料可以相對於材料組分、濃度及厚度之一或多者之非均勻方式配置於發光二極體晶片之一或多個表面上或上方。在某些實施例中，一或多種發光磷光材料之填料百分比可在發光二極體晶片之一或多個外部表面上或當中變化。在某些實施例中，一或多種發光磷光材料可在發光二極體晶片之一或多個表面之部分上圖案化以包含一或多個條、點、曲線或多邊形形狀。在某些實施例中，多種發光磷光材料可布置於發光二極體晶片上或上方之不同離散區或離散層中。 The light-emitting diode wafer can also be coated with one or more luminescent phosphorescent or other conversion materials (such as phosphors) such that at least some of the light from the light-emitting diode wafer is absorbed by the one or more phosphors and is based on the light emitting diode wafer from the one or more phosphors. The characteristics of the body are converted into one or more different wavelength spectra. In some embodiments, a combination of a light emitting diode chip and one or more phosphors emits a generally white light combination. The one or more phosphors may include yellow (eg, YAG:Ce), green (eg, LuAg :Ce), and red (eg, CaixySrxEuyAlSiN3 ) emitting phosphors and combinations thereof . Luminescent phosphorescent materials as described herein may be or may include one or more of phosphors, scintillators, luminescent phosphorescent inks, quantum dot materials, daylight strips, and the like. The luminescent phosphorescent material may be provided by any suitable means, such as coating directly on one or more surfaces of the light emitting diodes, being dispersed in an encapsulating material arranged to cover the one or more light emitting diodes, and/ or coated on one or more optical or supporting elements (eg by powder coating, inkjet printing or the like). In certain embodiments, the luminescent phosphorescent material can be down-converting or up-converting, and a combination of both down-converting and up-converting materials can be provided. In certain embodiments, multiple different (eg, compositionally different) luminescent phosphorescent materials arranged to produce different peak wavelengths may be arranged to receive emissions from one or more light emitting diode wafers. In some embodiments, the one or more phosphors may include a yellow phosphor (eg, YAG:Ce), a green phosphor (eg, LuAg:Ce), and a red phosphor (eg, Ca ixy Sr x Eu y AlSiN 3 ), and combinations of the above. One or more luminescent phosphorescent materials may be provided on one or more portions of the light emitting diode die and/or submount in various arrangements. In certain embodiments, one or more surfaces of an LED chip may be conformally coated with one or more luminescent materials, while other surfaces of such LED chips and/or associated submounts may be free of Luminous phosphorescent materials. In certain embodiments, the top surface of the LED wafer may include a luminescent phosphorescent material, while one or more side surfaces of the LED wafer may not contain a luminescent phosphorescent material. In certain embodiments, all or substantially all of the outer surface of a light-emitting diode die (eg, except for contact defining or mounting surfaces) may be coated or otherwise covered with one or more light-emitting phosphorescent materials. In certain embodiments, one or more luminescent phosphorescent materials may be disposed in a substantially uniform manner on or over one or more surfaces of the light emitting diode wafer. In other embodiments, one or more luminescent phosphorescent materials may be disposed on or over one or more surfaces of the light emitting diode wafer in a non-uniform manner with respect to one or more of material composition, concentration, and thickness. In certain embodiments, the filler percentage of one or more luminescent phosphorescent materials may vary on or among one or more exterior surfaces of the light-emitting diode wafer. In certain embodiments, one or more luminescent phosphorescent materials may be patterned on portions of one or more surfaces of the light emitting diode wafer to include one or more stripes, dots, curves, or polygonal shapes. In certain embodiments, multiple luminescent phosphorescent materials may be disposed in different discrete regions or layers on or over a light emitting diode wafer.
藉由發光二極體晶片之主動層或區發射的光典型在多個方向激發。對於方向性應用，內部鏡或外部反射表面可用以將儘可能多的光朝向所要發射方向重新導向。內部鏡可包含單個或多個層。一些多層鏡面包含金屬反射層及介電反射層，其中介電反射層配置於金屬反射層與複數個半導體層之間。鈍化層配置於該金屬反射層與第一及第二電接觸之間，其中該第一電接觸與第一半導體層導電連通地配置，且第二電接觸與第二半導體層導電連通地配置。對於包含呈現小於100%反射率之表面的單一或多層鏡面，某光可由鏡面吸收。另外，透過主動發光二極體結構重新導向的光可由發光二極體晶片內之其他層或元件吸收。Light emitted by active layers or regions of a light-emitting diode chip is typically excited in multiple directions. For directional applications, internal mirrors or external reflective surfaces can be used to redirect as much light as possible toward the desired emission direction. Internal mirrors can contain single or multiple layers. Some multi-layer mirrors include a metal reflective layer and a dielectric reflective layer, where the dielectric reflective layer is disposed between the metal reflective layer and a plurality of semiconductor layers. The passivation layer is disposed between the metal reflective layer and the first and second electrical contacts, wherein the first electrical contact is disposed in conductive communication with the first semiconductor layer, and the second electrical contact is disposed in conductive communication with the second semiconductor layer. For single or multi-layer mirrors that contain surfaces that exhibit less than 100% reflectivity, some light can be absorbed by the mirror. Additionally, light redirected through the active LED structure may be absorbed by other layers or components within the LED chip.
如本文中所使用，當照射於發光裝置之層或區上的所發射輻射之至少80%穿過該層或區出射時，可將該層或區視為「透明的」。此外，如本文所用，當照射於發光二極體之一層或區上的發射輻射之至少80%被反射時，將該層或區視為「反射」或體現為「鏡面」或「反射器」。在一些實施例中，發射輻射包括可見光，諸如具有或不具有發光磷光材料之藍色及/或綠色發光二極體。在其他實施例中，發射輻射可包括非可見光。舉例而言，在基於GaN之藍色及/或綠色發光二極體之上下文中，銀(Ag)可被視為反射材料(例如，至少80%反射性)。在UV發光二極體之狀況下，可選擇適當材料以提供所要反射率(且在一些實施例中，為高反射率)及/或所要吸收率(且在一些實施例中，為低吸收率)。在某些實施例中，「光透射性」材料可布置以透射所要波長之發射輻射之至少50%。As used herein, a layer or region of a light emitting device may be considered "transparent" when at least 80% of the emitted radiation impinging on the layer or region exits through the layer or region. Furthermore, as used herein, a layer or region of a light-emitting diode is considered to be "reflective" or embodied as a "mirror" or "reflector" when at least 80% of the emitted radiation impinging on that layer or region is reflected. . In some embodiments, the emitted radiation includes visible light, such as blue and/or green light emitting diodes with or without emitting phosphorescent materials. In other embodiments, the emitted radiation may include non-visible light. For example, in the context of GaN-based blue and/or green light-emitting diodes, silver (Ag) may be considered a reflective material (eg, at least 80% reflective). In the case of UV light emitting diodes, appropriate materials can be selected to provide the desired reflectivity (and in some embodiments, high reflectivity) and/or the desired absorbance (and in some embodiments, low absorbance ). In certain embodiments, a "light-transmissive" material may be arranged to transmit at least 50% of the emitted radiation at a desired wavelength.
本發明能適用於具有多種幾何形狀(諸如，垂直幾何形狀)之發光二極體晶片。垂直幾何結構發光二極體晶片典型包含發光二極體晶片相對側或面上之陽極及陰極連接件。在某些實施例中，垂直幾何形狀發光二極體晶片亦可包含配置於陽極與陰極連接件之間的生長基板。在某些實施例中，發光二極體晶片結構可包含載體子安裝件，且其中生長基板經移除。在另外其他實施例中，所描述原理中之任一者亦可適用於其中自發光二極體晶片之同一側面獲得陽極及陰極連接件以用於將晶片覆晶安裝至另一表面的覆晶晶片結構。The present invention is applicable to light emitting diode wafers having various geometries, such as vertical geometries. Vertical geometry LED chips typically include anode and cathode connections on opposite sides or faces of the LED chip. In some embodiments, the vertical geometry LED wafer may also include a growth substrate disposed between anode and cathode connections. In certain embodiments, the light emitting diode wafer structure may include a carrier submount with the growth substrate removed. In yet other embodiments, any of the principles described may also be applicable to flip chip wherein anode and cathode connections are obtained from the same side of the light emitting diode die for flip chip mounting of the die to another surface. Wafer structure.
圖1為包含提供穿過介電層14之導電路徑的互連件12或通孔之發光二極體晶片10的一部分之概括截面。舉例而言，互連件12可電耦接至半導體層16及/或介入電流分散層18。在發光二極體晶片結構之內容背景中，半導體層16可體現主動發光二極體結構之n型層或p型層，且電流分散層18可體現一層導電材料，例如諸如氧化銦錫(indium tin oxide；ITO)之透明導電氧化物或諸如鉑(Pt)之金屬，但可使用其他材料。在此配置中，大部分電流20沿著互連件12之邊緣12'射出，其中電流20之較少量相對於互連件12而居中射出。電流分散層18亦用以在電流20注入至半導體層16中之前側向分散電流20，藉此提供增加之電流注入區域。雖然提供此類益處，但電流分散層18有時能影響裝置性能。舉例而言，電流分散層18可吸收某一百分比之藉由主動發光二極體結構產生的光。就此而言，電流分散層18可形成於跨越半導體層16之區段中以使得介電層14之部分在電流分散層18之所述區段之間形成於半導體層16上。在某些實施例中，介電層14之材料可與半導體層16形成階階折射率以使得到達此介面之光可經重新導向或以其他方式反射。如此，介電層14可充當介電反射器。藉由以介電層14之部分在其間的區段形式證明電流分散層18，發光二極體晶片10可顯現充分電流分散同時亦具有增加之光萃取。另外，將電流分散層18分成多個區段而允許跨越發光二極體晶片10微調電流注入。FIG. 1 is a general cross-section of a portion of a light emitting diode die 10 including interconnects 12 or vias that provide conductive paths through dielectric layer 14 . For example, interconnect 12 may be electrically coupled to semiconductor layer 16 and/or intervening current dispersion layer 18 . In the context of light-emitting diode chip structures, semiconductor layer 16 may embody an n-type layer or a p-type layer of an active light-emitting diode structure, and current dispersion layer 18 may embody a layer of conductive material, such as indium tin oxide. tin oxide; ITO) transparent conductive oxide or a metal such as platinum (Pt), but other materials can be used. In this configuration, a majority of the current 20 exits along the edge 12' of the interconnect 12, with a smaller amount of the current 20 exiting centrally relative to the interconnect 12. The current dispersion layer 18 also serves to laterally disperse the current 20 before the current 20 is injected into the semiconductor layer 16, thereby providing an increased current injection area. While providing such benefits, current spreading layer 18 can sometimes affect device performance. For example, current dispersion layer 18 may absorb a certain percentage of the light generated by the active light emitting diode structure. In this regard, current spreading layer 18 may be formed in sections spanning semiconductor layer 16 such that portions of dielectric layer 14 are formed on semiconductor layer 16 between the sections of current spreading layer 18 . In some embodiments, the material of dielectric layer 14 may form a stepped refractive index with semiconductor layer 16 such that light reaching this interface may be redirected or otherwise reflected. As such, dielectric layer 14 may act as a dielectric reflector. By having current dispersion layer 18 in the form of sections of dielectric layer 14 therebetween, light emitting diode chip 10 can exhibit sufficient current dispersion while also having increased light extraction. Additionally, dividing the current dispersion layer 18 into multiple sections allows fine-tuning of current injection across the light emitting diode wafer 10 .
圖2為配置成覆晶布置中的代表性發光二極體晶片22之截面圖，但其他布置係可能的。發光二極體晶片22包含包括有形成於基板32上的p型層26、n型層28及主動層30的主動結構24。在某些實施例中，一或多個緩衝層及/或未摻雜層34可提供於基板32與主動發光二極體結構24之間。基板32可體現圖案化之基板，使得最接近於主動發光二極體結構24的基板32之表面32'經圖案化。在某些實施例中，n型層28介於主動層30與基板32之間。在其他實施例中，摻雜次序可顛倒。基板32能包括諸如碳化矽(SiC)或藍寶石之許多不同材料，且能具有經塑形、紋理化或圖案化以增強光萃取的一或多個表面。在某些實施例中，基板32透光(較佳為透明)，且可包含接近主動發光二極體結構24且包含多個凹陷及/或凸起特徵的圖案化表面32'。Figure 2 is a cross-sectional view of a representative light emitting diode die 22 configured in a flip-chip arrangement, although other arrangements are possible. The light emitting diode chip 22 includes an active structure 24 including a p-type layer 26 , an n-type layer 28 and an active layer 30 formed on the substrate 32 . In some embodiments, one or more buffer layers and/or undoped layers 34 may be provided between substrate 32 and active light emitting diode structure 24 . The substrate 32 may embody a patterned substrate such that the surface 32 ′ of the substrate 32 closest to the active light emitting diode structure 24 is patterned. In some embodiments, n-type layer 28 is interposed between active layer 30 and substrate 32 . In other embodiments, the doping order may be reversed. Substrate 32 can include many different materials, such as silicon carbide (SiC) or sapphire, and can have one or more surfaces that are shaped, textured, or patterned to enhance light extraction. In some embodiments, the substrate 32 is light-transmissive (preferably transparent) and may include a patterned surface 32' proximate the active light-emitting diode structure 24 and including a plurality of recessed and/or raised features.
在圖2中，第一反射層36提供於p型層26之部分上，其中電流分散層18以類似於圖1之方式在其間。就此而言，第一反射層36可以類似於圖1之介電層14的配置而提供。第一反射層36可包括許多不同材料且較佳包括呈現階梯折射率的材料，其中主動發光二極體結構24之材料促進由主動發光二極體結構24產生的光之全內反射(total internal reflection；TIR)。經歷TIR之光在不經歷吸收或損失的情況下重新導向，且能藉此促成適用或所要的發光二極體晶片發射。在某些實施例中，第一反射層36包括具有低於主動發光二極體結構24材料折射率的折射率的材料。第一反射層36可包括許多不同材料，其中一些材料具有小於2.3之折射率，而其他材料能具有小於2.15、小於2.0及小於1.5之折射率。在一些實施例中，第一反射層36包括介電材料，在一些實施例情況下，包括二氧化矽(SiO 2)及/或氮化矽(SiN)。應理解能使用許多介電材料，諸如SiN、SiN x、Si 3N 4、矽(Si)、鍺(Ge)、二氧化矽(SiO 2)、SiOx、二氧化鈦(TiO 2)、五氧化二鉭(Ta 2O 5)、ITO、氧化鎂(MgO x)、氧化鋅(ZnO)及以上各者之組合。在某些實施例中，第一反射層36可包含不同介電材料之多個交替層，例如對稱重複或不對稱配置的SiO 2及SiN之交替層。諸如GaN之一些III族氮化物材料可具有大約2.4之折射率，SiO 2能具有大約1.48之折射率，且SiN可具有大約1.9之折射率。具有包括GaN之主動發光二極體結構24及包括SiO 2之第一反射層36的實施例能形成在二者之間的充分階梯折射率，以允許光之高效TIR。第一反射層36能取決於所使用材料之類型而具有不同厚度，在一些實施例情況下，具有至少0.2微米(μm)之厚度。在此等實施例之一些中，第一反射層36能具有介於0.2 μm至0.7 μm範圍中的厚度，而在一些實施例中厚度能為大約0.5 μm。第一反射層36之部分可沿著主動發光二極體結構24之凸台側壁延伸。 In FIG. 2 , a first reflective layer 36 is provided over part of the p-type layer 26 with the current dispersion layer 18 therebetween in a similar manner to FIG. 1 . In this regard, the first reflective layer 36 may be provided in a configuration similar to the dielectric layer 14 of FIG. 1 . The first reflective layer 36 may include many different materials and preferably includes a material exhibiting a stepped refractive index, wherein the material of the active light-emitting diode structure 24 promotes total internal reflection of light generated by the active light-emitting diode structure 24 reflection; TIR). Light that undergoes TIR is redirected without experiencing absorption or loss, and thereby enables suitable or desired emission from the light emitting diode chip. In some embodiments, first reflective layer 36 includes a material with a refractive index lower than the refractive index of the material of active light emitting diode structure 24 . The first reflective layer 36 can include many different materials, some of which have refractive indexes of less than 2.3, while other materials can have refractive indexes of less than 2.15, less than 2.0, and less than 1.5. In some embodiments, the first reflective layer 36 includes a dielectric material, including, in some embodiments, silicon dioxide (SiO 2 ) and/or silicon nitride (SiN). It will be appreciated that many dielectric materials can be used, such as SiN, SiNx , Si3N4 , silicon (Si), germanium ( Ge), silicon dioxide ( SiO2 ), SiOx, titanium dioxide ( TiO2 ), tantalum pentoxide (Ta 2 O 5 ), ITO, magnesium oxide (MgO x ), zinc oxide (ZnO) and combinations of the above. In some embodiments, first reflective layer 36 may include multiple alternating layers of different dielectric materials, such as alternating layers of SiO 2 and SiN in symmetrical repeating or asymmetric configurations. Some III-nitride materials such as GaN can have a refractive index of about 2.4, SiO2 can have a refractive index of about 1.48, and SiN can have a refractive index of about 1.9. Embodiments having an active light emitting diode structure 24 including GaN and a first reflective layer 36 including SiO2 can create a sufficient step index of refraction between the two to allow for efficient TIR of light. The first reflective layer 36 can have different thicknesses depending on the type of material used, and in some embodiments has a thickness of at least 0.2 micrometers (μm). In some of these embodiments, first reflective layer 36 can have a thickness in the range of 0.2 μm to 0.7 μm, and in some embodiments the thickness can be about 0.5 μm. A portion of the first reflective layer 36 may extend along the sidewalls of the boss of the active light emitting diode structure 24 .
如上文所描述，圖2中之電流分散層18具備上文對於圖1所描述的類似配置。因此，電流分散層18形成有允許第一反射層36之部分36'延伸穿過電流分散層18且接觸p型層26的數個開口或甚至不連續區，而不是連續覆蓋p型層26。以此方式，形成於p型層26與第一反射層36之間的不包含電流分散層18之介面可顯現對藉由主動發光二極體結構24產生之光的增加反射率。即使電流分散層18未連續地覆蓋p型層26，電流分散層18之開口或不連續區可具有足夠小的側向尺寸以仍適當沿著p型層26分散電流。As described above, the current dispersion layer 18 in FIG. 2 has a similar configuration as described above with respect to FIG. 1 . Therefore, current spreading layer 18 is formed with several openings or even discontinuous regions that allow portion 36' of first reflective layer 36 to extend through current spreading layer 18 and contact p-type layer 26, rather than continuously covering p-type layer 26. In this manner, the interface formed between p-type layer 26 and first reflective layer 36 that does not include current dispersion layer 18 may exhibit increased reflectivity for light generated by active light emitting diode structure 24 . Even if current dispersion layer 18 does not continuously cover p-type layer 26 , the openings or discontinuities in current dispersion layer 18 may have lateral dimensions that are small enough to still disperse current appropriately along p-type layer 26 .
發光二極體晶片22可進一步包含在第一反射層36上的第二反射層38，使得第一反射層36配置於主動發光二極體結構24與第二反射層38之間。第二反射層38可包含布置以反射來自主動發光二極體結構24之可傳遞通過第一反射層36之任何光的金屬層。第二反射層38能包括許多不同材料，諸如Ag、金(Au)、Al或以上各者之組合。如所繪示，第二反射層38可包含提供穿過第一反射層36至電流分散層18之導電路徑的一或多個反射層互連件40。在某些實施例中，反射層互連件40包括反射性層通孔。因此，第一反射層36、第二反射層38及反射層互連件40形成發光二極體晶片22之反射結構。在某些實施例中，反射層互連件40包括與第二反射層38相同的材料，且與第二反射層38同時形成。在其他實施例中，反射層互連件40可包括與第二反射層38不同的材料。發光二極體晶片22亦可包括在與第一反射層36相反的第二反層38之側面上的障壁層42以防止第二反射層38材料(諸如Ag)遷移至其他層。防止此遷移有助於發光二極體晶片22維持在其整個使用壽命中的有效操作。障壁層42可包括導電材料，其中合適之材料包含但不限於繼之以蒸鍍Au塊材的濺鍍Ti/Pt、或繼之以蒸鍍Ti/Au塊材的濺鍍Ti/Ni。除可未藉由障壁層42覆蓋的第二反射層38之任何部分以外，鈍化層44包含於障壁層42上。鈍化層44可進一步配置於未由第二反射層38覆蓋的第一反射層36之部分上。鈍化層44保護並提供用於發光二極體晶片22之電絕緣，且能包括許多不同材料，諸如介電材料。在某些實施例中，鈍化層44為單層，且在其他實施例中，鈍化層44包括複數個層。用於鈍化層44之合適材料包含但不限於SiN、SiNx及/或Si 3N 4。在某些實施例中，第一反射層36包括SiO 2且鈍化層44包括SiN、SiN x或Si 3N 4。在其他實施例中，第一反射層36及鈍化層44的至少一部分可各自包括SiO 2。 The light-emitting diode chip 22 may further include a second reflective layer 38 on the first reflective layer 36 such that the first reflective layer 36 is disposed between the active light-emitting diode structure 24 and the second reflective layer 38 . Second reflective layer 38 may include a metal layer arranged to reflect any light from active light emitting diode structure 24 that may be transmitted through first reflective layer 36 . The second reflective layer 38 can include many different materials, such as Ag, gold (Au), Al, or combinations thereof. As shown, second reflective layer 38 may include one or more reflective layer interconnects 40 that provide a conductive path through first reflective layer 36 to current dispersion layer 18 . In some embodiments, reflective layer interconnect 40 includes reflective layer vias. Therefore, the first reflective layer 36 , the second reflective layer 38 and the reflective layer interconnect 40 form the reflective structure of the light emitting diode chip 22 . In some embodiments, reflective layer interconnect 40 includes the same material as second reflective layer 38 and is formed simultaneously with second reflective layer 38 . In other embodiments, reflective layer interconnect 40 may include a different material than second reflective layer 38 . The LED chip 22 may also include a barrier layer 42 on the side of the second reflective layer 38 opposite the first reflective layer 36 to prevent the second reflective layer 38 material (such as Ag) from migrating to other layers. Preventing this migration helps the light emitting diode die 22 maintain efficient operation throughout its useful life. Barrier layer 42 may include a conductive material, where suitable materials include, but are not limited to, sputtered Ti/Pt followed by evaporated Au bulk, or sputtered Ti/Ni followed by evaporated Ti/Au bulk. Passivation layer 44 is included on barrier layer 42 , except for any portion of second reflective layer 38 that may not be covered by barrier layer 42 . The passivation layer 44 may be further disposed on the portion of the first reflective layer 36 that is not covered by the second reflective layer 38 . Passivation layer 44 protects and provides electrical insulation for light emitting diode die 22 and can include many different materials, such as dielectric materials. In some embodiments, passivation layer 44 is a single layer, and in other embodiments, passivation layer 44 includes a plurality of layers. Suitable materials for passivation layer 44 include, but are not limited to, SiN, SiNx, and/or Si 3 N 4 . In certain embodiments, first reflective layer 36 includes SiO 2 and passivation layer 44 includes SiN, SiN x or Si 3 N 4 . In other embodiments, at least a portion of first reflective layer 36 and passivation layer 44 may each include SiO 2 .
在圖2中，發光二極體晶片22包括配置於鈍化層44上且布置以提供與主動發光二極體結構24之電連接的p接點46及n接點48。亦可稱為陽極接觸之p接點46可包括延伸穿過鈍化層44至障壁層42或第二反射層38以提供到達p型層26之電路徑的一或多個p接觸互連件50。在某些實施例中，一或多個p接觸互連件50包括一或多個p接觸通孔。亦可稱為陰極接觸之n接點48可包括延伸穿過鈍化層44、障壁層42、第一反射層36及第二反射層38、p型層26及主動層30以提供剄達n型層28之電路徑的一或多個n接觸互連件52。在某些實施例中，一或多個n接觸互連件52包括一或多個n接觸通孔。在操作中，跨p接點46及n接點48所施加的信號傳導至p型層26及n型層28，從而致使發光二極體晶片22自主動層30發射光。p接點46及n接點48可包括許多不同材料，諸如Au、銅(Cu)、鎳(Ni)、In、Al、Ag、錫(Sn)、Pt或以上各者之組合。在另其他實施例中，p接點46及n接點48能包括導電氧化物及透明導電氧化物，諸如ITO、氧化鎳(NiO)、氧化鋅(ZnO)、氧化鎘錫、氧化銦、氧化錫、氧化鎂、氧化鋅鎵(ZnGa 2O 4)、氧化鋅摻銻(ZnO 2/Sb)、氧化鎵摻錫(Ga 2O3/Sn)、氧化銀銦摻錫(AgInO 2/Sn)、氧化銦摻鋅(In 2O 3/Zn)、氧化鋁銅(CuAlO 2)、LaCuOS、二氧化銅鎵(CuGaO 2)及鍶銅氧化物(SrCu 2O 2)。所使用材料之選擇能取決於接觸之位置及所要電特性，諸如透明度、接面電阻率及片電阻。如上文所描述，發光二極體晶片22配置用於覆晶安裝，且p接點46及n接點48布置以安裝或接合至諸如印刷電路板之表面。雖然在覆晶結構之內容背景中描述圖2，但揭示用於電流分散層18、第一反射層36、第二反射層38及障壁層42之一或多者的原理容易地適用於其他晶片結構。 In FIG. 2 , LED die 22 includes p-contacts 46 and n-contacts 48 disposed on passivation layer 44 and arranged to provide electrical connection to active LED structure 24 . The p-contact 46 , also referred to as the anode contact, may include one or more p-contact interconnects 50 extending through the passivation layer 44 to the barrier layer 42 or the second reflective layer 38 to provide an electrical path to the p-type layer 26 . In certain embodiments, one or more p-contact interconnects 50 include one or more p-contact vias. An n-contact 48, also referred to as a cathode contact, may include an n-contact extending through the passivation layer 44, the barrier layer 42, the first and second reflective layers 36, 38, the p-type layer 26, and the active layer 30 to provide n-type contact. One or more n-contact interconnects 52 for the electrical path of layer 28 . In certain embodiments, one or more n-contact interconnects 52 include one or more n-contact vias. In operation, signals applied across p-contact 46 and n-contact 48 are conducted to p-type layer 26 and n-type layer 28 , causing light-emitting diode die 22 to emit light from active layer 30 . p-contact 46 and n-contact 48 may include many different materials, such as Au, copper (Cu), nickel (Ni), In, Al, Ag, tin (Sn), Pt, or combinations thereof. In still other embodiments, p-contact 46 and n-contact 48 can include conductive oxides and transparent conductive oxides, such as ITO, nickel oxide (NiO), zinc oxide (ZnO), cadmium tin oxide, indium oxide, oxide Tin, magnesium oxide, zinc gallium oxide (ZnGa 2 O 4 ), zinc oxide doped with antimony (ZnO 2 /Sb), gallium oxide doped with tin (Ga 2 O3/Sn), silver indium oxide doped with tin (AgInO 2 /Sn), Indium oxide doped with zinc (In 2 O 3 /Zn), copper aluminum oxide (CuAlO 2 ), LaCuOS, copper gallium dioxide (CuGaO 2 ) and strontium copper oxide (SrCu 2 O 2 ). The choice of materials used can depend on the location of the contacts and the desired electrical properties, such as transparency, junction resistivity and sheet resistance. As described above, the LED chip 22 is configured for flip-chip mounting, and the p-contacts 46 and n-contacts 48 are arranged for mounting or bonding to a surface such as a printed circuit board. Although FIG. 2 is described in the context of a flip-chip structure, the principles disclosed for one or more of current dispersion layer 18, first reflective layer 36, second reflective layer 38, and barrier layer 42 are readily applicable to other wafers. structure.
圖3為在形成電流分散層18之後根據電流分散層18相對於n接觸互連件52之位置的視角的發光二極體晶片54之視圖。雖然圖2之n接觸互連件52的材料在圖3中尚未形成，但出於此論述之目的，其開口或位置係在圖3中指示且將在下文中稱為n接觸互連件52。在某些實施例中，電流分散層18形成自n接觸互連件52拉回或插入的邊緣18'。若電流分散層18將接觸n接觸互連件52，則一些拉回為避免電短路所必需。然而，藉由增加電流分散層18之邊緣18'與n接觸互連件52之間的距離，第一反射層36之更多反射材料可與鄰近n接觸互連件52的圖2之主動發光二極體結構24的部分形成增加之介面。另外，藉由增加邊緣18'之距離，在主動發光二極體結構24之鄰近部分處的減少電流注入可歸因於肖克萊-里德-霍爾(Shockley-Read-Hall)復合而導致沿著靠近n接觸互連件52的主動發光二極體結構24之側壁的減少非輻射性復合。FIG. 3 is a view of the light emitting diode wafer 54 according to the position of the current dispersion layer 18 relative to the n-contact interconnect 52 after the current dispersion layer 18 is formed. Although the material of n-contact interconnect 52 of FIG. 2 has not been formed in FIG. 3, for the purpose of this discussion, its opening or location is indicated in FIG. 3 and will be referred to as n-contact interconnect 52 hereafter. In certain embodiments, current dispersion layer 18 forms an edge 18 ′ that is pulled back or inserted from n-contact interconnect 52 . If current spreading layer 18 were to contact n-contact interconnect 52, some pullback is necessary to avoid electrical shorting. However, by increasing the distance between edge 18' of current dispersion layer 18 and n-contact interconnect 52, more reflective material of first reflective layer 36 can be used to actively illuminate adjacent n-contact interconnect 52 in FIG. 2 Portions of diode structure 24 form an increased interface. Additionally, by increasing the distance of edge 18', reduced current injection at adjacent portions of active light emitting diode structure 24 may be caused by Shockley-Read-Hall recombination. Reduced non-radiative recombination along the sidewalls of active light emitting diode structure 24 proximate n-contact interconnect 52 .
圖4為類似於繪示電流分散層18之不連續區的圖3之發光二極體晶片54的發光二極體晶片56之視圖。以類似於圖3之方式，圖2之n接觸互連件52的材料在圖4中尚未形成，但其對應開口或位置在圖4中指示且將在下文中稱為n接觸互連件52。另外，雖然圖2的反射層互連件40之材料在圖4中亦尚未形成，但其對應開口或位置在圖4中指示且在下文中將稱為反射層互連件40。如所繪示，電流分散層18形成為跨越p型層26的不連續區或島狀物之陣列。在某些實施例中，電流分散層18的區配置有提供跨越p型層26之全部表面區域的合適電流分散的足夠近間隔同時亦留下未藉由電流分散層18覆蓋的p型層26足夠部分。在圖4中的p型層26之此等未覆蓋區與圖2之第一反射層36可在其間無電流分散層18的情況下接觸p型層26，以顯現增加反射率所在的區域對應。FIG. 4 is a view of a light-emitting diode chip 56 similar to the light-emitting diode chip 54 of FIG. 3 illustrating discontinuous regions of the current dispersion layer 18 . In a manner similar to FIG. 3 , the material of n-contact interconnect 52 of FIG. 2 has not yet been formed in FIG. 4 , but its corresponding opening or location is indicated in FIG. 4 and will be referred to as n-contact interconnect 52 hereafter. In addition, although the material of the reflective layer interconnect 40 of FIG. 2 has not yet been formed in FIG. 4 , its corresponding opening or position is indicated in FIG. 4 and will be referred to as the reflective layer interconnect 40 below. As shown, current dispersion layer 18 is formed as an array of discontinuous regions or islands across p-type layer 26 . In some embodiments, the regions of current spreading layer 18 are configured to be sufficiently close together to provide suitable current spreading across the entire surface area of p-type layer 26 while also leaving portions of p-type layer 26 not covered by current spreading layer 18 Enough portion. These uncovered areas of the p-type layer 26 in FIG. 4 correspond to areas where the first reflective layer 36 of FIG. 2 can contact the p-type layer 26 without the current dispersion layer 18 therebetween to exhibit increased reflectivity. .
如在圖4中進一步繪示，反射層互連件40之直徑可形成小於電流分散層18之區的區域。就此而言，對準公差可經改良同時亦提供沿著鄰近反射層互連件40的電流分散層18之部分的第一反射層36之增加涵蓋範圍。電流分散層18及反射層互連件40之結構可提供跨越p型層26精細調諧電流分散的能力。舉例而言，反射層互連件40可具備在最接近n接觸互連件52的位置中之較大直徑及在較遠離n接觸互連件52的位置中之較小直徑。在另外實施例中，電流分散層18的區之尺寸亦可以類似方式縮放。在圖4之實例中，電流分散層18之區係提供作為隨距n接觸互連件52之距離而減少直徑的圓形區。在其他實施例中，電流分散層18之區可體現其他形狀，諸如正方形、橢圓形、矩形、六邊形、八邊形等。As further illustrated in FIG. 4 , the diameter of reflective layer interconnect 40 may form an area that is smaller than the area of current spreading layer 18 . In this regard, alignment tolerances may be improved while also providing increased coverage of first reflective layer 36 along portions of current dispersion layer 18 adjacent reflective layer interconnects 40 . The structure of current spreading layer 18 and reflective layer interconnect 40 provides the ability to finely tune current spreading across p-type layer 26 . For example, reflective layer interconnect 40 may have a larger diameter in a location closest to n-contact interconnect 52 and a smaller diameter in a location farther from n-contact interconnect 52 . In alternative embodiments, the size of the regions of current dispersion layer 18 can be scaled in a similar manner. In the example of FIG. 4 , the regions of current spreading layer 18 are provided as circular regions that decrease in diameter with distance from n-contact interconnect 52 . In other embodiments, the regions of current dispersion layer 18 may embody other shapes, such as square, elliptical, rectangular, hexagonal, octagonal, etc.
圖5A至圖5D繪示根據本發明之原理的電流分散層18之其他配置。圖5A為繪示電流分散層18之各種區18-1、區18-2的圖案之圖4的發光二極體晶片54之視圖。n接觸互連件52之位置展示為不含電流分散層區18-1、區18-2的較大區域。如所繪示，最接近n接觸互連件52的區18-1相比於更遠離n接觸互連件52之區18-2具有更大直徑。以此方式，可沿著靠近n接觸互連件52的圖2之p型層26之邊緣提供增加之電流分散及注入。Figures 5A-5D illustrate other configurations of current dispersion layer 18 in accordance with the principles of the present invention. FIG. 5A is a view of the light emitting diode chip 54 of FIG. 4 illustrating patterns of various regions 18 - 1 , 18 - 2 of the current dispersion layer 18 . The location of n-contact interconnect 52 is shown as a larger area that does not include current spreading layer regions 18-1, 18-2. As shown, the region 18 - 1 closest to the n-contact interconnect 52 has a larger diameter than the region 18 - 2 further away from the n-contact interconnect 52 . In this manner, increased current dispersion and injection may be provided along the edges of p-type layer 26 of FIG. 2 proximate n-contact interconnect 52.
圖5B為對於其中電流分散層18形成更密封之區的實施例的類似於圖5A之發光二極體晶片54的發光二極體晶片56之視圖。在某些實施例中，電流分散層18的區可彼此相切或甚至重疊以提供增加之電流分散。另外，定界n接觸互連件52之位置的電流分散層18之邊緣18'可形成有非圓形形狀，以維持電流分散層18與n接觸互連件52之間的側向間隔，如對於圖3所描述。Figure 5B is a view of a light emitting diode wafer 56 similar to the light emitting diode wafer 54 of Figure 5A for an embodiment in which the current dispersion layer 18 forms a more sealed region. In certain embodiments, regions of current dispersion layer 18 may be tangential to each other or even overlap to provide increased current dispersion. Additionally, the edge 18' of the current spreading layer 18 that defines the location of the n-contact interconnect 52 may be formed with a non-circular shape to maintain lateral spacing between the current spreading layer 18 and the n-contact interconnect 52, such as As described in Figure 3.
圖5C為對於其中電流分散層18之某些區彼此連接的實施例的類似於圖5A之發光二極體晶片54的發光二極體晶片58之視圖。舉例而言，電流分散層18可形成具有諸如圓形之形狀的區之陣列，且電流分散層18之延伸部可將區之鄰近者連接在一起。在圖5C之實例中，列經連接以使得電流分散層18之區的各列為電流分散層18的連續部分之部分。此配置可在圖4的反射層互連件40中之一或多者非故意錯失電流分散層18之目標區的情況下提供備用電流分散層18。FIG. 5C is a view of a light emitting diode wafer 58 similar to the light emitting diode wafer 54 of FIG. 5A for an embodiment in which certain areas of the current dispersion layer 18 are connected to each other. For example, current spreading layer 18 may form an array of regions having a shape such as a circle, and extensions of current spreading layer 18 may connect adjacent regions together. In the example of FIG. 5C , the columns are connected such that each column of the region of current spreading layer 18 is part of a contiguous portion of current spreading layer 18 . This configuration may provide backup current spreading layer 18 in the event that one or more of the reflective layer interconnects 40 of FIG. 4 inadvertently miss the target area of current spreading layer 18.
圖5D為對於其中電流分散層18形成連續結構，且其某些開口界定n接觸互連件52之位置，且電流分散層18其他開口界定第一反射層36可如圖2中所說明接觸p型層26所在的位置之實施例的類似於圖5A之發光二極體晶片54的發光二極體晶片60之視圖。5D is a diagram for a location where current dispersion layer 18 forms a continuous structure with certain openings defining n contact interconnects 52 and other openings in current dispersion layer 18 defining first reflective layer 36 may contact p as illustrated in FIG. 2 A view of a light-emitting diode wafer 60 similar to the light-emitting diode wafer 54 of FIG. 5A in an embodiment where the pattern layer 26 is located.
圖6A為類似於圖5A之發光二極體晶片54的發光二極體晶片62之視圖並說明根據本發明之原理的n接觸互連件52及電流分散層18之區18-1、區18-2的圖案。圖6B為具有反射層互連件40-1、反射層互連件40-2之配置的來自圖6A之電流分散層18的區18-1、區18-2之視圖。在圖6B中，反射層互連件40-1、反射層互連件40-2耦接至電流分散層18之對應區18-1、區18-2，或反射層互連件40-1、反射層互連件40-2之相對尺寸根據電流分散層18之對應區18-1、區18-2的尺寸或面積縮放。舉例而言，反射層互連件40-1及電流分散層18之對應區18-1兩者均按比例大於反射層互連件40-2及對應區18-2。圖6C為具有反射層互連件40-1、反射層互連件40-2之替代性配置的來自圖6A之電流分散層18的區18-1、區18-2之視圖。在圖6C中，反射層互連件40-1、反射層互連件40-2之相對尺寸與電流分散層18之對應區18-1、區18-2之尺寸解耦合。舉例而言，在圖6C中，反射層互連件40-1、反射層互連件40-2中之各者可具有相同尺寸，而不管對應區18-1、區18-2之面積。Figure 6A is a view of a light emitting diode wafer 62 similar to the light emitting diode wafer 54 of Figure 5A and illustrating n-contact interconnect 52 and regions 18-1, 18 of the current dispersion layer 18 in accordance with the principles of the present invention. -2 pattern. Figure 6B is a view of regions 18-1, 18-2 of the current dispersion layer 18 from Figure 6A with a configuration of reflective layer interconnects 40-1, 40-2. In FIG. 6B , reflective layer interconnections 40 - 1 and 40 - 2 are coupled to corresponding regions 18 - 1 and 18 - 2 of the current dispersion layer 18 , or reflective layer interconnections 40 - 1 The relative dimensions of the reflective layer interconnects 40 - 2 are scaled according to the size or area of the corresponding regions 18 - 1 and 18 - 2 of the current dispersion layer 18 . For example, reflective layer interconnect 40-1 and corresponding region 18-1 of current dispersion layer 18 are both proportionally larger than reflective layer interconnect 40-2 and corresponding region 18-2. Figure 6C is a view of regions 18-1, 18-2 of the current spreading layer 18 from Figure 6A with an alternative configuration of reflective layer interconnects 40-1, 40-2. In FIG. 6C , the relative dimensions of reflective layer interconnects 40 - 1 , 40 - 2 are decoupled from the dimensions of corresponding regions 18 - 1 , 18 - 2 of current dispersion layer 18 . For example, in FIG. 6C , each of reflective layer interconnect 40 - 1 , reflective layer interconnect 40 - 2 may have the same size regardless of the area of corresponding region 18 - 1 , region 18 - 2 .
就此而言，圖6A至圖6C之實施例繪示反射層互連件40-1、反射層互連件40-2與電流分散層18之對應區18-1、區18-2之間的某些關係。相對尺寸可共同縮放或彼此獨立。在其他實施例中，反射層互連件40-1、反射層互連件40-2及電流分散層18之對應區18-1、區18-2的尺寸可在彼此之相對方向改變。在另外其他實施例中，反射層互連件40-1、反射層互連件40-2或對應區18-1、區18-2之一者可具有恆定尺寸而另一者具有可變尺寸。在上文所描述之實施例中的任一者中，電流分散層18之某些區18-1、區18-2可如圖5C中所繪示而連接。在另外其他實施例中，此等結構可進一步圖案化成光子晶體空腔以增加在發光二極體外的光總量。In this regard, the embodiment of FIGS. 6A-6C illustrates the reflective layer interconnects 40 - 1 , 40 - 2 and corresponding regions 18 - 1 , 18 - 2 of the current dispersion layer 18 . certain relationships. Relative dimensions can scale together or independently of each other. In other embodiments, the dimensions of corresponding regions 18 - 1 , 18 - 2 of reflective layer interconnect 40 - 1 , reflective layer interconnect 40 - 2 and current dispersion layer 18 may vary relative to each other. In still other embodiments, one of the reflective layer interconnects 40-1, 40-2, or corresponding regions 18-1, 18-2 may have a constant size while the other has a variable size. . In any of the embodiments described above, certain regions 18-1, 18-2 of the current dispersion layer 18 may be connected as shown in Figure 5C. In still other embodiments, these structures can be further patterned into photonic crystal cavities to increase the amount of light outside the light emitting diode.
如本文中所描述，本發明之實施例提供促進具有改良效率之電流注入的發光二極體中之晶片架構。根據原理之電流分散層配置允許電流分散層之周邊接觸區域的控制及相關聯電流分散、注入及光萃取。As described herein, embodiments of the invention provide chip architectures in light emitting diodes that facilitate current injection with improved efficiency. The configuration of the current dispersion layer according to the principle allows the control of the peripheral contact area of the current dispersion layer and the associated current dispersion, injection and light extraction.
預期如本文中所描述，前述態樣中之任一者、及/或各種個別態樣及特徵可加以組合以達到額外優點。除非本文中有相反指出，否則如本文所揭示之各種實施例中之任一者可與一或多個其他所揭示實施例組合。It is contemplated that any of the foregoing aspects, and/or various individual aspects and features, may be combined to achieve additional advantages, as described herein. Unless indicated to the contrary herein, any of the various embodiments as disclosed herein may be combined with one or more other disclosed embodiments.
所屬技術領域中具有通常知識者將認識到對本發明之較佳實施例之改良及修改。所有此類改良及修改皆視為在本文中所揭示之概念及隨附申請專利範圍之範疇內。Those of ordinary skill in the art will recognize improvements and modifications to the preferred embodiments of the invention. All such improvements and modifications are deemed to be within the scope of the concepts disclosed herein and the accompanying patent claims.
10、22、54、56、58、60、62:發光二極體晶片 12:互連件 12',18':邊緣 14:介電層 16:半導體層 18:電流分散層 18-1、18-2:區 20:電流 24:主動結構 26:p型層 28:n型層 30:主動層 32:基板 32':表面 34:未摻雜層 36:第一反射層 36':部分 38:第二反射層 40:反射層互連件 40-1、40-2:反射層互連件 42:障壁層 44:鈍化層 46:p接點 48:n接點 50:p接觸互連件 52:n接觸互連件 10, 22, 54, 56, 58, 60, 62: light emitting diode chip 12:Interconnections 12',18': edge 14: Dielectric layer 16: Semiconductor layer 18:Current dispersion layer 18-1, 18-2: District 20:Current 24:Active structure 26: p-type layer 28: n-type layer 30:Active layer 32:Substrate 32':Surface 34: Undoped layer 36: First reflective layer 36': part 38: Second reflective layer 40: Reflective layer interconnects 40-1, 40-2: Reflective layer interconnects 42: Barrier layer 44: Passivation layer 46: p contact 48:n contact 50:p Contact Interconnects 52:n Contact Interconnect
併入於本說明書中且形成本說明書之一部分的隨附圖式繪示本發明之若干態樣，且與描述一起用於解釋本發明之原理。The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the invention and, together with the description, serve to explain the principles of the invention.
[圖1]為根據本發明之原理的包含提供穿過介電層至電流分散層之導電路徑的互連件的發光二極體晶片的一部分之概括截面。[FIG. 1] is a general cross-section of a portion of a light emitting diode wafer including interconnects that provide a conductive path through a dielectric layer to a current dispersion layer in accordance with the principles of the present invention.
[圖2]為根據本發明之原理的配置成覆晶布置中的代表性發光二極體晶片之截面圖。[Fig. 2] is a cross-sectional view of a representative light emitting diode die configured in a flip-chip arrangement in accordance with the principles of the present invention.
[圖3]為在形成電流分散層之後根據電流分散層相對於n接觸互連件之位置的視角的發光二極體晶片之視圖。[Fig. 3] is a view of the light emitting diode wafer according to the position of the current dispersion layer with respect to the n-contact interconnection after the current dispersion layer is formed.
[圖4]為繪示電流分散層之不連續區的類似於圖3之發光二極體晶片的發光二極體晶片之視圖。[FIG. 4] is a view of a light-emitting diode wafer similar to the light-emitting diode wafer of FIG. 3 illustrating discontinuous regions of the current dispersion layer.
[圖5A]為繪示電流分散層之各種區的圖案之圖4的發光二極體晶片之視圖。[FIG. 5A] is a view of the light emitting diode wafer of FIG. 4 illustrating patterns of various regions of the current dispersion layer.
[圖5B]為對於其中電流分散層形成更密封之區的實施例的類似於圖5A之發光二極體晶片的發光二極體晶片之視圖。[FIG. 5B] is a view of a light-emitting diode wafer similar to the light-emitting diode wafer of FIG. 5A for an embodiment in which the current dispersion layer forms a more sealed region.
[圖5C]為對於其中電流分散層之某些區彼此連接的實施例的類似於圖5A之發光二極體晶片的發光二極體晶片之視圖。[FIG. 5C] is a view of a light-emitting diode wafer similar to the light-emitting diode wafer of FIG. 5A for an embodiment in which certain areas of the current dispersion layer are connected to each other.
[圖5D]為對於其中電流分散層形成連續結構且其某些開口界定n接觸互連件之位置的實施例的類似於圖5A之發光二極體晶片的發光二極體晶片之視圖。[FIG. 5D] is a view of a light-emitting diode wafer similar to that of FIG. 5A for an embodiment in which the current dispersion layer forms a continuous structure and certain openings thereof define the locations of n-contact interconnects.
[圖6A]為類似於圖5A之發光二極體晶片的發光二極體晶片之視圖並繪示根據本發明之原理的n接觸互連件及電流分散層之區的圖案。[FIG. 6A] is a view of a light emitting diode wafer similar to the light emitting diode wafer of FIG. 5A and depicts a pattern of regions of n-contact interconnects and current dispersion layers in accordance with the principles of the present invention.
[圖6B]為具有反射層互連件之配置的來自圖6A之電流分散層的區之視圖。[FIG. 6B] is a view of a region of the current dispersion layer from FIG. 6A with a configuration of reflective layer interconnects.
[圖6C]為具有反射層互連件之替代性配置的來自圖6A之電流分散層的區之視圖。[FIG. 6C] is a view of regions of the current dispersion layer from FIG. 6A with an alternative configuration of reflective layer interconnects.
18:電流分散層 18:Current dispersion layer
22:發光二極體晶片 22: Light emitting diode chip
24:主動結構 24:Active structure
26:p型層 26: p-type layer
28:n型層 28: n-type layer
30:主動層 30:Active layer
32:基板 32:Substrate
32':表面 32':Surface
34:未摻雜層 34: Undoped layer
36:第一反射層 36: First reflective layer
36':部分 36': part
38:第二反射層 38: Second reflective layer
40:反射層互連件 40: Reflective layer interconnects
42:障壁層 42: Barrier layer
44:鈍化層 44: Passivation layer
46:p接點 46: p contact
48:n接點 48:n contact
50:p接觸互連件 50:p Contact Interconnects
52:n接觸互連件 52:n contact interconnect
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| US18/302,149 | 2023-04-18 | ||
| US18/302,149 US20230395747A1 (en) | 2022-06-01 | 2023-04-18 | Current spreading layer structures for light-emitting diode chips |
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| TWI584496B (en) * | 2015-08-13 | 2017-05-21 | 隆達電子股份有限公司 | Semiconductor light emitting structure |
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