TW202349708A - Shield gate mosfet - Google Patents

Abstract

A shield gate MOSFET includes a substrate, a multilayer epitaxial structure, a shield gate, a control gate, an insulating layer between the shield gate and the multilayer epitaxial structure, a gate oxide layer between the control gate and the multilayer epitaxial structure, and an inter-gate oxide layer between the shield gate and the control gate. The shield gate and the control gate are formed in a trench of the multilayer epitaxial structure. In the multilayer epitaxial structure, a first epitaxial layer is disposed at the surface of the multilayer epitaxial structure, a third epitaxial layer is disposed between the bottom of the trench to the substrate, and a second epitaxial layer is sandwiched by the first and the third epitaxial layers. The resistance of the first epitaxial layer is less than that of the third epitaxial layer, and the resistance of the second epitaxial layer is less than that of the first epitaxial layer.

Description

SHIELD GATE MOSFET

The present invention relates to a power semiconductor device, and in particular to a shielded gate metal oxide semi-field effect transistor.

The shielded gate metal oxide semi-field effect transistor is an improved structure of the trench gate metal oxide semiconductor structure. Compared with the traditional metal oxide semiconductor structure, the shielded gate metal oxide semi-field effect transistor can effectively reduce the gate-to-drain capacitance (C _gd ), thereby improving switching losses.

With the advancement of semiconductor products, the application voltage of shielded gate metal oxide semi-field effect transistors has increased significantly to more than 150V. However, in order to meet high voltage requirements, shielded gate MOSFETs need to use thicker epitaxial layers, which in turn causes the on-resistance (Rdson) to become larger and increases switching losses.

The invention provides a shielded gate metal oxygen semi-field effect transistor, which can simultaneously reduce on-resistance and improve breakdown voltage (BVDSS).

The shielded gate MOSFET of the present invention includes a substrate, a multilayer epitaxial structure, a shielded gate, a control gate, an insulating layer, a gate oxide layer and an inter-gate oxide layer. A multi-layer epitaxial structure is formed on the surface of the substrate, and the multi-layer epitaxial structure has a plurality of trenches. The shielding gate is arranged in the trench, and the control gate is arranged in the trench on the shielding gate. The insulating layer is disposed between the shielding gate and the multi-layer epitaxial structure, the gate oxide layer is disposed between the control gate and the multi-layer epitaxial structure, and the inter-gate oxide layer is disposed between the shielding gate and the multi-layer epitaxial structure. between control gates. The multi-layer epitaxial structure includes a continuous first epitaxial layer, a second epitaxial layer and a third epitaxial layer, wherein the first epitaxial layer is arranged on the surface of the multi-layer epitaxial structure, and the third epitaxial layer The second epitaxial layer is disposed between the bottom of the trench and the substrate, the second epitaxial layer is disposed between the first epitaxial layer and the third epitaxial layer, and the resistance of the first epitaxial layer is smaller than the resistance of the third epitaxial layer. value, the resistance value of the second epitaxial layer is smaller than the resistance value of the first epitaxial layer.

In an embodiment of the present invention, the greater the difference between the resistance of the second epitaxial layer and the resistance of the first epitaxial layer, the greater the breakdown voltage of the shielded gate MOSFET.

In an embodiment of the present invention, the smaller the resistance of the third epitaxial layer, the smaller the on-resistance of the shielded gate MOSFET.

In an embodiment of the present invention, the smaller the thickness of the third epitaxial layer, the smaller the on-resistance of the shielded gate MOSFET.

In an embodiment of the present invention, the first epitaxial layer surrounds the control gate.

In an embodiment of the invention, the second epitaxial layer surrounds the shielding gate.

In an embodiment of the present invention, the interface between the first epitaxial layer and the second epitaxial layer is within a range from the inter-gate oxide layer to half the depth of each trench.

In an embodiment of the present invention, the ratio of the thickness of the first epitaxial layer to the thickness of the second epitaxial layer is between 1:4 and 1:1.

In an embodiment of the present invention, the shielded gate MOSFET may further include a source region formed in the first epitaxial layer, wherein the source region and the first epitaxial layer have the same conductivity type.

In an embodiment of the present invention, the above-mentioned shielded gate MOSFET may further include a drain layer disposed on the back side of the substrate, and the back side is opposite to the surface of the substrate.

Based on the above, according to the shielded gate MOSFET of the present invention, three epitaxial layers with different resistance values are used to simultaneously improve the breakdown voltage (BVDSS) and reduce the on-resistance (Rdson). Among them, the second layer with low resistance value is used. The epitaxial layer enhances the electric field to increase BVDSS, and is paired with a third epitaxial layer that is thinner and/or has a lower resistance than the traditional epitaxial layer to reduce Rdson.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings.

Examples are listed below and described in detail with reference to the accompanying drawings. However, the examples provided are not intended to limit the scope of the present invention. To facilitate understanding, the same components will be identified with the same symbols in the following description. In addition, the drawings are for illustrative purposes only and are not drawn to original size. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

The terms "include", "include", "have", etc. used in the article are all open terms, which means "including but not limited to".

FIG. 1 is a schematic cross-sectional view of a shielded gate MOSFET according to an embodiment of the present invention.

Please refer to Figure 1. The shielded gate MOSFET of this embodiment includes a substrate 100, a multi-layer epitaxial structure 102, a shielded gate SG, a control gate CG, an insulating layer 106, a gate oxide layer 108 and an inter-gate oxidation layer. Layer 110. The substrate 100 and the multi-layer epitaxial structure 102 may be silicon or other semiconductor materials. The multilayer epitaxial structure 102 is formed on the surface 100a of the substrate 100, and the multilayer epitaxial structure 102 has a plurality of trenches 104. Each trench 104 extends from the surface 102a of the multilayer epitaxial structure 102 to the substrate 100, and from the top view It appears that the trenches 104 are parallel to each other, but the present invention is not limited to this; in another embodiment, the trenches 104 are not parallel to each other. The shielding gate SG is arranged in the trench 104, and the control gate CG is arranged in the trench 104 on the shielding gate SG. The shielding gate SG and the control gate CG are made of materials such as but not limited to polysilicon. The insulating layer 106 is disposed between the shielded gate SG and the multi-layer epitaxial structure 102, and the thickness of the insulating layer 106 is sufficient to reduce the gate-drain overlap capacitance, thereby reducing the gate charge. The gate oxide layer 108 is disposed between the control gate CG and the multi-layer epitaxial structure 102, and the inter-gate oxide layer 110 is disposed between the shielding gate SG and the control gate CG, wherein the inter-gate oxide layer The position of 110 is also between the insulating layer 106 and the gate oxide layer 108, but the invention is not limited thereto; in another embodiment, due to the manufacturing sequence, the inter-gate oxide layer 110 can be formed on the shielded gate SG. and the control gate CG, and the insulating layer 106 and the gate oxide layer 108 are in direct contact.

Please continue to refer to FIG. 1 . The multi-layer epitaxial structure 102 includes a continuous first epitaxial layer EPI1 , a second epitaxial layer EPI2 and a third epitaxial layer EPI3 . The first epitaxial layer EPI1 is disposed at the end of the multi-layer epitaxial structure 102 . On the surface 102a, the third epitaxial layer EPI3 is disposed between the bottom of the trench 104 and the substrate 100, and the second epitaxial layer EPI2 is disposed between the first epitaxial layer EPI1 and the third epitaxial layer EPI3, and The resistance value of the first epitaxial layer EPI1 is less than the resistance value of the third epitaxial layer EPI3, and the resistance value of the second epitaxial layer EPI2 is less than the resistance value of the first epitaxial layer EPI1. That is to say, there are three epitaxial layers in the multi-layer epitaxial structure 102, and the resistance values of these three epitaxial layers change from the surface 102a of the multi-layer epitaxial structure 102 to the substrate 100, ranging from medium resistance value, low resistance value to High resistance value.

Compared with the traditional high-resistance epitaxial layer, the design of three epitaxial layers with different resistances in this embodiment can use the low-resistance second epitaxial layer EPI2 to enhance the electric field there to improve the collapse. voltage (BVDSS), and is paired with a third epitaxial layer EPI3 that is thinner and/or has a slightly lower resistance than the traditional high resistance to reduce the on-resistance (Rdson). Therefore, the greater the difference between the resistance of the second epitaxial layer EPI2 and the resistance of the first epitaxial layer EPI1, the greater the breakdown voltage of the shielded gate MOSFET. On the one hand, the smaller the resistance of the third epitaxial layer EPI2, the smaller the on-resistance of the shielded gate metal oxide semi-field effect transistor; on the other hand, the smaller the thickness of the third epitaxial layer EPI3, the smaller the shielded gate metal oxide semi-field effect transistor. The on-resistance of the transistor is also smaller.

In Figure 1, the first epitaxial layer EPI1 surrounds the control gate CG, and the second epitaxial layer EPI2 surrounds the shielding gate SG. Therefore, the interface between the first epitaxial layer EPI1 and the second epitaxial layer EPI2 is close to The location of the inter-gate oxide layer 110. However, the present invention is not limited thereto; in FIG. 2 of another embodiment, the interface between the first epitaxial layer EPI1 and the second epitaxial layer EPI2 is close to half the depth of the trench 104 . That is to say, the interface between the first epitaxial layer EPI1 and the second epitaxial layer EPI2 may be within a range from the inter-gate oxide layer 110 to half the depth of each trench 104 . From the perspective of the thickness of the epitaxial layer, the ratio of the thickness t1 of the first epitaxial layer EPI1 to the thickness t2 of the second epitaxial layer EPI2 can be between 1:4 and 1:1.

The aforementioned structural features are mainly due to the fact that in the simulation experiments of the shielded gate MOSFET with a single high-resistance epitaxial layer, the inventors found that the epitaxial layer around the shielded gate SG has a problem of low electric field, resulting in BVDSS decreases and a thicker epitaxial layer needs to be used, but this will increase Rdson. Therefore, the present invention uses multiple epitaxial layers to reduce the resistance of the second epitaxial layer EPI2 surrounding the shielding gate SG. , to enhance the electric field there, and then reduce Rdson by reducing the thickness of the third epitaxial layer EPI3 and/or slightly reducing the resistance of the third epitaxial layer EPI3. Since the third epitaxial layer EPI3 accounts for more than 40% of the entire multi-layer epitaxial structure 102, once the thickness of the third epitaxial layer EPI3 is reduced or the resistance of the third epitaxial layer EPI3 is reduced, Rdson can be significantly reduced.

For example, when a high-voltage 150V shielded gate MOSFET is used for simulation, and all components except the epitaxial layer are the same, the simulation results are shown in Table 1 below.

Table 1 Simulation experiment Comparative example 1 2 3 The first epitaxial layer EPI1 Resistance: 0.35ohm Resistance: 1.50ohm Thickness: 13.0µm Thickness: 3.5µm The second epitaxial layer EPI2 Resistance: 0.30ohm Resistance: 0.20ohm Resistance: 0.18ohm Thickness: 3.5µm The third epitaxial layer EPI3 Resistance: 1.20ohm Thickness: 6.0µm BVDSS(V) 180 194 183 172

It can be seen from Table 1 that when three epitaxial layers are used and the resistance of the second epitaxial layer EPI2 is set to the lowest, the BVDSS of the shielded gate MOSFET can be improved.

In addition, it was found through simulation that if the thickness of the second epitaxial layer EPI2 is set to 0.2µm and the resistance value is used as a variable (other conditions are the same as the simulation experiment), then the resistance value of the second epitaxial layer EPI2 is between 0.20ohm~ BVDSS between 0.25ohm is above 190V. Therefore, according to the concept of the present invention, the resistance and/or thickness of the second epitaxial layer can be adjusted according to different high-voltage applications to improve the BVDSS of the shielded gate MOSFET.

Then, a high-voltage 150V shielded gate metal oxide semi-field effect transistor was also used for simulation. Simulation Experiment 4 adopted the conditions of Simulation Experiment 2 and reduced the resistance of the third epitaxial layer EPI3 to 0.90ohm. The simulation results are shown in Table 2 below. .

Table 2 Simulation experiment 4 Comparative example The first epitaxial layer EPI1 Resistance: 0.35ohm Resistance: 1.50ohm Thickness: 13.0µm Thickness: 3.5µm The second epitaxial layer EPI2 Resistance: 0.20ohm Thickness: 3.5µm The third epitaxial layer EPI3 Resistance: 0.90ohm Thickness: 6.0µm BVDSS(V) 189 172 Rsp (mohm-mm ² ) 83 108

It can be seen from Table 1 that the sheet resistance (Rsp) of simulation experiment 4 is about 24% lower than that of Comparator. Therefore, the smaller thickness of the third epitaxial layer EPI3 of the present invention can further reduce the on-resistance Rdson without affecting BVDSS.

In FIGS. 1 to 2 , the shielded gate MOSFET may also include a source region 112 formed in the first epitaxial layer EPI1 , where the source region 112 and the first epitaxial layer EPI1 have the same conductivity type. . For example, the source region 112 and the first epitaxial layer EPI1 are also N-type, and the doping concentration of the source region 112 is greater than the doping concentration of the first epitaxial layer EPI1. In another embodiment, the source region 112 and the first epitaxial layer EPI1 are P-type. The first epitaxial layer EPI1, the second epitaxial layer EPI2 and the third epitaxial layer EPI3 are usually of the same conductivity type. In addition, the shielded gate MOSFET may further include a drain layer 114 disposed on the backside 100b of the substrate 100, where the backside 100b is opposite to the surface 100a of the substrate 100. For circuit connection, there is a dielectric layer 116 above the multi-layer epitaxial structure 102 and a contact window 118 formed therein and connected to the first epitaxial layer EPI1 through the source region 112, and in order to improve the electrical connection, A heavily doped region (not shown) with a different conductivity type from the first epitaxial layer EPI1 may also be provided at the bottom of the contact window 118 .

As for the shielded gate MOSFET in FIGS. 1 and 2 , the following steps can be used to manufacture the shielded gate MOSFET, but the present invention is not limited thereto. The shielded gate MOSFET of the present invention can also be manufactured in other ways.

Step 1. Sequentially epitaxially grow the first epitaxial layer EPI1, the second epitaxial layer EPI2, and the third epitaxial layer EPI3 on the surface 100a of the substrate 100 to obtain a multi-layer epitaxial structure 102.

Step 2. Use a photolithography etching process to etch from the surface 102a of the multi-layer epitaxial structure 102 toward the substrate 100 to form a plurality of trenches 104. Although the trench 104 in FIGS. 1 and 2 is located above the third epitaxial layer EPI3, the invention is not limited thereto; in another embodiment, the trench 104 can be formed in part of the third epitaxial layer EPI3, so that The bottom of the trench 104 is slightly lower than the interface between the third epitaxial layer EPI3 and the second epitaxial layer EPI2.

Step 3. Form an insulating layer 106 on the inner surface of the trench 104. For example, a thermal oxidation method or chemical vapor deposition (CVD) is used to form a silicon oxide layer as the insulating layer 106.

Step 4. Form the shielding gate SG in the trench 104. For example, first deposit polysilicon to fill the trench 104, and then use methods such as chemical mechanical planarization and etching back to remove excess polysilicon and retain the shielding gate SG in the trench 104. Then, the shielding gate SG can be used as a mask, and the insulating layer 106 above the shielding gate SG can be removed by etching.

Step 5. Form an inter-gate oxide layer 110 on the shielded gate SG. For example, use CVD to form a silicon oxide layer as the inter-gate oxide layer 110.

Step 6. Form a gate oxide layer 108 on the inner surface of the trench 104 above the inter-gate oxide layer 110. For example, use thermal oxidation or chemical vapor deposition (CVD) to form a silicon oxide layer as the gate oxide layer 108.

Step 7. Form the control gate CG in the trench 104 on the shield gate SG.

Step 8. Dope the surface of the first epitaxial layer EPI1 to form a source region 112, and then form a contact window 118.

Step 9. Form a drain layer 114 on the back side 100b of the substrate 100, where the drain layer 114 is, for example, a metal layer.

To sum up, the present invention changes the original one-layer epitaxial layer into three epitaxial layers with different resistance values, so it can reduce the on-resistance of the shielded gate metal oxide semi-field effect transistor while maintaining a high breakdown voltage. , or even improve BVDSS.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

100:Substrate 100a, 102a: surface 100b: back 102:Multilayer epitaxial structure 104:Ditch 106:Insulation layer 108: Gate oxide layer 110: Oxide layer between gates 112: Source region 114: Drain layer 116:Dielectric layer 118:Contact window CG: control gate EPI1: The first epitaxial layer EPI2: The second epitaxial layer EPI3: The third epitaxial layer SG: shielded gate t1, t2: thickness

FIG. 1 is a schematic cross-sectional view of a shielded gate MOSFET according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of a shielded gate MOSFET according to another embodiment of the present invention.

100:Substrate

100a, 102a: surface

100b: back

102:Multilayer epitaxial structure

104:Ditch

106:Insulation layer

108: Gate oxide layer

110: Oxide layer between gates

112: Source region

114: Drain layer

116:Dielectric layer

118:Contact window

CG: control gate

EPI1: The first epitaxial layer

EPI2: The second epitaxial layer

EPI3: The third epitaxial layer

SG: shielded gate

t1, t2: thickness

Claims (10)

A shielded gate metal oxygen semi-field effect transistor, including: substrate; A multilayer epitaxial structure is formed on the surface of the substrate, and the multilayer epitaxial structure has a plurality of trenches; Shielding gates are arranged in the plurality of trenches; A control gate configured in the plurality of trenches on the shielding gate; An insulating layer is arranged between the shielding gate and the multi-layer epitaxial structure; a gate oxide layer disposed between the control gate and the multi-layer epitaxial structure; and An intergate oxide layer is disposed between the shielding gate and the control gate, wherein The multi-layer epitaxial structure includes a continuous first epitaxial layer, a second epitaxial layer and a third epitaxial layer, wherein the first epitaxial layer is disposed on the surface of the multi-layer epitaxial structure, and the third epitaxial layer The epitaxial layer is disposed between the bottom of the trench and the substrate, the second epitaxial layer is disposed between the first epitaxial layer and the third epitaxial layer, and the first epitaxial layer The resistance value of the second epitaxial layer is less than the resistance value of the third epitaxial layer, and the resistance value of the second epitaxial layer is less than the resistance value of the first epitaxial layer. As for the shielded gate MOSFET described in item 1 of the patent application, the greater the difference between the resistance value of the second epitaxial layer and the resistance value of the first epitaxial layer, the greater the difference. The greater the breakdown voltage of the shielded gate MOSFET. As for the shielded gate metal oxide semi-field effect transistor described in item 1 of the patent application, the smaller the resistance value of the third epitaxial layer, the smaller the on-resistance of the shielded gate metal oxide semi-field effect transistor. . For the shielded gate metal oxide semi-field effect transistor described in claim 1, the smaller the thickness of the third epitaxial layer, the smaller the on-resistance of the shielded gate metal oxide semi-field effect transistor. In the shielded gate MOSFET described in claim 1 of the patent application, the first epitaxial layer surrounds the control gate. In the shielded gate MOSFET described in claim 1, the second epitaxial layer surrounds the shielded gate. The shielded gate MOSFET as described in item 1 of the patent application, wherein the interface between the first epitaxial layer and the second epitaxial layer is from the inter-gate oxide layer to each of the within half the depth of the trench. As for the shielded gate MOSFET as described in item 1 of the patent application, the ratio of the thickness of the first epitaxial layer to the thickness of the second epitaxial layer is between 1:4 and 1:1. between. The shielded gate MOSFET as described in item 1 of the patent application further includes a source region formed in the first epitaxial layer, wherein the source region and the first epitaxial layer have the same conductivity type. The shielded gate metal oxide semiconductor field effect transistor described in claim 1 of the patent application further includes a drain layer disposed on the back side of the substrate, and the back side is opposite to the surface of the substrate.