TW202347734A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A semiconductor device includes a circuit board, a bottom plate, a plurality of landing pads, a stack, a plurality of support pillars, and a plurality of memory pillars. The circuit board includes a plurality of circuit structures and a plurality of wires, the circuit structures are electrically connected to the corresponding wires, and the circuit board has a peripheral area, an array area and a staircase area disposed between the peripheral area and the array area. The bottom plate is disposed over the circuit board, and the bottom plate includes a bottom conductive layer. The landing pads are embedded in at least a top portion of the bottom conductive layer and contact the bottom conductive layer in the staircase area. The stack is disposed on the bottom plate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked along a first direction. The support pillars pass through the stack along the first direction in the staircase area and extend to the landing pads. The memory pillars pass through the stack along the first direction in the array area.

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular, to a memory device and a manufacturing method thereof.

Recently, as the demand for better memory devices has gradually increased, various three-dimensional (3D) memory devices have been provided, such as three-dimensional NAND (3D NAND) memory devices having a multi-layer stacked structure. This type of three-dimensional memory device can achieve higher storage capacity and have better electrical properties, such as good data storage reliability and operation speed.

The conventional three-dimensional anti-snap memory device has quite complex manufacturing steps. Therefore, how to simplify the manufacturing process of 3D NAND memory devices is still a focus of current research.

The present invention relates to a semiconductor device and a manufacturing method thereof. In particular, a semiconductor device with a simpler manufacturing process and a manufacturing method thereof are provided.

According to an embodiment of the present invention, a semiconductor device is provided. The semiconductor device includes a circuit board, a base plate, a plurality of landing pads, a stack, a plurality of support columns and a plurality of memory columns. The circuit board includes a plurality of circuit structures and a plurality of wires. The circuit structures are electrically connected to corresponding wires. The circuit board has a peripheral area, an array area, and a step area disposed between the peripheral area and the array area. The base plate is disposed on the circuit board and includes a bottom conductive layer. The landing pad is embedded in at least a top portion of the bottom conductive layer in the step region and contacts the bottom conductive layer. The stack is disposed on the base plate and includes a plurality of conductive layers and a plurality of insulating layers alternately stacked along a first direction. The support posts extend through the stack in a first direction in the step area and to the landing pad. The memory pillars pass through the stack along a first direction in the array area.

According to another embodiment of the present invention, a method of manufacturing a semiconductor device is provided. A method of manufacturing a semiconductor device includes the following steps. First, a circuit board is formed. The circuit board includes a plurality of circuit structures and a plurality of wires. The circuit structures are electrically connected to corresponding wires. The circuit board has a peripheral area, an array area and is disposed between the peripheral area and the array area. a stepped area. Secondly, a base plate is formed, the base plate is arranged on the circuit board, and the base plate includes a bottom conductive layer. A plurality of landing pads are formed, and the landing pads are embedded in at least a top portion of the bottom conductive layer in the step area and contact the bottom conductive layer. A stack is formed, which is disposed on the bottom plate. The stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked along a first direction. A plurality of support columns are formed, and the support columns pass through the stack along the first direction in the step area and extend to the landing pad. Thereafter, a plurality of memory columns are formed, and the memory columns pass through the stack along a first direction in the array area.

In order to have a better understanding of the above and other aspects of the present invention, examples are given below and are described in detail with reference to the accompanying drawings:

In the following detailed description, for convenience of explanation, various specific details are provided to provide an overall understanding of embodiments of the present disclosure. However, it is understood that one or more embodiments may be practiced without these specific details. In other cases, well-known structures and components are represented by schematic diagrams in order to simplify the drawings.

Generally speaking, the manufacturing method of a 3D NAND memory device includes a gate replacement process. Since multiple sacrificial layers are removed during the gate replacement process, support pillars need to be provided in the step area to maintain the stability of the overall structure. In some comparative examples, the support pillars disposed in the step region are formed by a separate process, such as forming oxide pillars passing through the stacked structure. According to an embodiment of the present case, the formation of the support pillars can be integrated with the process of other components (such as the formation of vertical contacts in the peripheral area). Therefore, compared with the comparative example in which the support pillars are formed by an independent process , the manufacturing method of the memory device in this case can save more time and money.

1 to 17B illustrate a manufacturing flow chart of the semiconductor device 10 according to an embodiment of the present invention. Among them, Figures 1 to 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A and 17A correspond to the plane formed by the first direction (such as Z direction) and the second direction (such as X direction) . Figures 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B and 17B correspond to the plane formed by the first direction (eg Z direction) and the third direction (eg Y direction). The first direction, the second direction and the third direction may be different from each other, may be interlaced with each other, for example, may be perpendicular to each other.

Please refer to FIG. 1 , which illustrates a schematic diagram of a circuit board 110 . The steps of forming the circuit board 110 include providing a substrate 112 , forming a plurality of circuit structures 114 and a plurality of conductors 116 on the substrate 112 , and forming an insulating material 118 covering the substrate 112 , the circuit structures 114 and the conductors 116 . The wires 116 are electrically connected to corresponding circuit structures 114 respectively. Circuit structure 114 includes metal oxide semiconductor (CMOS). Insulating material 118 may include oxide. The circuit board 110 corresponds to the peripheral area PA, the step area SA, and the array area AA, and the step area SA is disposed between the peripheral area PA and the array area AA.

Please refer to FIG. 2 , which illustrates a schematic diagram of forming the base plate 120 on the circuit board 110 . For example, the first conductive layer 121, the first insulating layer 123, the second conductive layer 125, the second insulating layer 127 and the third conductive layer can be sequentially formed in the first direction (such as the Z direction) through multiple deposition processes. 129 on the circuit board 110. That is, the base plate 120 may include a first conductive layer 121, a first insulating layer 123, a second conductive layer 125, a second insulating layer 127 and a third conductive layer 129. In this embodiment, the materials of the first conductive layer 121 , the second conductive layer 125 and the third conductive layer 129 may include polycrystalline silicon. The materials of the first insulating layer 123 and the second insulating layer 127 may include oxide. It should be understood that the invention is not limited thereto.

Referring to Figure 3, the first conductive layer 121, the second conductive layer 125 and the third conductive layer 129 at predetermined positions are removed through an etching process to form a plurality of openings, and then the insulating material is filled in the openings and placed on the steps. Area SA forms a plurality of bottom supports 122 . The bottom support 122 may be composed of an insulating material, which may include an oxide. In the step area SA, the bottom support 122 passes through the first conductive layer 121 , the second conductive layer 125 and the third conductive layer 129 in the first direction.

Referring to FIG. 4 , a plurality of top openings 124p are formed in the top portion of the third conductive layer 129 in the step area SA. Each top opening 124p is partially recessed in the third conductive layer 129 without exposing the upper surface of the second insulating layer 127. The top openings 124p are separated from each other. For example, adjacent top openings 124p may be separated from each other by at least a portion of the bottom support member 122.

Referring to FIG. 5 , a conductive layer passing through the first conductive layer 121 , the first insulating layer 123 , the second conductive layer 125 , the second insulating layer 127 and the third conductive layer 129 (that is, passing through the bottom plate 120 ) is formed in the step area SA. A plurality of through openings 126p. Each through opening 126p exposes the upper surface of the corresponding conductor 116. The through openings 126p are separated from each other.

Referring to FIG. 6, conductive material is filled into the top opening 124p and the through opening 126p through at least one deposition process, and a planarization process is performed to form a plurality of landing pads 124 and a plurality of discharge pillars 126 respectively. That is, the landing pads 124 are embedded in at least the top portion of the third conductive layer 129 , and adjacent landing pads 124 are separated from each other by at least a portion of the bottom support member 122 . The top surface of landing pad 124 and the top surface of discharge column 126 are substantially coplanar. The discharge pillar 126 passes through the first conductive layer 121 , the first insulating layer 123 , the second conductive layer 125 , the second insulating layer 127 and the third conductive layer 129 and is in electrical contact with the corresponding wire 116 . The discharge column 126 can be used to remove charges accumulated during the process. The landing pad 124 can provide a better etching selectivity ratio in a subsequent etching process (detailed below).

Please refer to Figures 7A and 7B simultaneously, a stacked structure 130' is formed on the bottom plate 120 (ie, on the third conductive layer 129). The forming step of the stacked structure 130' includes forming a plurality of alternately stacked insulating layers 132 and a plurality of sacrificial layers 135 in a first direction (ie, the Z direction) through a plurality of deposition processes. The bottommost layer of the stacked structure 130' is, for example, an insulating layer 132. The material of the insulating layer 132 may include oxide, and the material of the sacrificial layer 135 may include nitride. After forming the stacked structure 130', a plurality of memory pillars MP are formed in the array area AA through the stacked structure 130' and through the first conductive layer 121 of part of the base plate 120. Each memory pillar MP may include a memory layer 136, a channel layer 138, an insulating pillar 140 and a bonding pad 142. The channel layer 138 surrounds the insulating pillar 140 and covers the bottom surface of the insulating pillar 140 . The memory layer 136 surrounds the channel layer 138 and covers the bottom surface of the channel layer 138 . The bonding pad 142 is disposed on the channel layer 138 and is in electrical contact with the channel layer 138 . After forming the memory pillar MP, a plurality of top spacers SSLC extending along the second direction (eg, X direction) are formed. The top spacer SSLC passes through the top portion of the stacked structure 130' along a first direction (e.g., Z direction). After the top spacer SSLC is formed, the sacrificial layer 135 of the stepped area SA is patterned so that the sacrificial layer 135 of the stepped area SA becomes a stepped structure to expose the predetermined position of the landing area of the word line. Thereafter, the insulating material 144 is covered on the ladder structure formed by the sacrificial layer 135 .

In one embodiment, the material of the memory layer 136 may include a tunneling layer, a charge trapping layer, and a blocking layer. The tunneling layer may include silicon oxide, or a silicon oxide/silicon nitride combination (eg, Oxide/Nitride/Oxide or ONO). The charge trapping layer may include silicon nitride (SiN) or other materials capable of trapping charges. The barrier layer may include silicon oxide, aluminum oxide, and/or combinations of these materials. The material of the channel layer 138 and the bonding pad 142 may include polysilicon. The materials of the insulating pillar 140 and the top spacer SSLC may include oxides.

Please refer to Figures 8A and 8B at the same time. A plurality of first openings 150p and a plurality of second openings 160p passing through the stacked structure 130' along the first direction are formed in the step area SA and the peripheral area PA respectively. In the step area SA, the first opening 150p exposes the corresponding landing pad 124 (at least the top portion of the third conductive layer 129 embedded in the bottom plate 120). In the peripheral area PA, the second opening 160 p exposes the corresponding conductor 116 of the circuit board 110 . The first opening 150p and the second opening 160p are formed, for example, by an etching process (eg, dry etching).

Please refer to Figures 9A and 9B at the same time. The first lining 1521 and the second lining 1621 are formed in the first opening 150p and the second opening 160p respectively. For example, the first lining 1521 and the second lining 1621 disposed on the side walls of the first opening 150p and the second opening 160p can be formed respectively through a deposition process. The materials of the first lining 1521 and the second lining 1621 may include oxide. In one embodiment, oxide can be deposited in the first opening 150p and the second opening 160p first, and then the unnecessary oxide is removed through an etching process, leaving only the sidewalls of the first opening 150p and the second opening 160p. oxide to form the first lining 1521 and the second lining 1621. The corresponding landing pad 124 of the first opening 150p and the corresponding conductor 116 of the circuit board 110 of the second opening 160p are exposed.

Please refer to Figures 10A and 10B at the same time. In an example, the conductive material is filled in the first opening 150p and the second opening 160p respectively (ie, the space surrounded by the first lining 1521 and the second lining 1621). Therefore, the first conductive pillar 1522 and the second conductive pillar 1622 are formed. In this way, the support pillars 152 can be formed in the step area SA and the vertical contacts 162 can be formed in the peripheral area PA through the same process (eg, the same etching process and deposition process). The support pillar 152 includes a first conductive pillar 1522 and a first lining 1521 surrounding the first conductive pillar 1522. The first conductive pillar 1522 of the support pillar 152 contacts the corresponding landing pad 124 embedded in the third conductive layer 129 of the base plate 120 . The vertical contact 162 includes a second conductive pillar 1622 and a second lining 1621 surrounding the second conductive pillar 1622. The vertical contacts 162 are in electrical contact with the corresponding wires 116 of the circuit board 110 .

In another example, the materials filled in the first opening 150p and the second opening 160p (ie, the space surrounded by the first liner 1521 and the second liner 1621) respectively in separate processes may be different. The material filling the first opening 150p may include a dielectric material, such as an oxide or a nitride. Support posts 152 are dielectric posts. The material filled in the second opening 160p may be a conductive material, such as tungsten or polysilicon. The vertical contact 162 includes a second conductive pillar 1622 and a second lining 1621 surrounding the second conductive pillar 1622. The vertical contacts 162 are in electrical contact with the corresponding wires 116 of the circuit board 110 .

Referring to FIGS. 11A and 11B simultaneously, a plurality of trenches LT are formed along the first direction (for example, the Z direction) through the stacked structure 130' and extending along the second direction (for example, the X direction). A plurality of trenches LT stop on the second conductive layer 125 of the base plate 120 . For example, the trench LT may be formed by an etching process (eg, dry etching).

Please refer to Figures 12A and 12B at the same time. The second conductive layer 125 in the base plate 120 is removed through the trench LT through the etching process, and the first insulating layer 121 and the second insulating layer 127 are removed. In this step, a portion of the bottom plate 120 is removed to form an opening between the first conductive layer 123 and the third conductive layer 129 , so the bottom support 122 is required to maintain the stability of the structure. In some embodiments, a portion of the memory layer 136 of the corresponding memory pillar MP between the first conductive layer 123 and the third conductive layer 129 is removed. A portion of the channel layer 138 of the corresponding memory pillar MP is exposed to the opening.

Please refer to Figures 13A and 13B at the same time. The conductive material is filled in the removed positions of the second conductive layer 125, the first insulating layer 121 and the second insulating layer 127 through a deposition process. The conductive material is, for example, polysilicon. In this way, the conductive material connects the first conductive layer 121 and the third conductive layer 129 to each other, and the conductive material, the first conductive layer 121 and the third conductive layer 129 together form a bottom conductive layer CSL (which can be used as a common source line) . An interface may exist between the first conductive layer 121 and the conductive material. Likewise, an interface may exist between the third conductive layer 129 and the conductive material. A portion of the channel layer 138 of the corresponding memory pillar MP contacts the bottom conductive layer CSL. The channel layer 138 covering the bottom surface of the insulating pillar 140 of the memory pillar MP is embedded in the bottom conductive layer CSL. The memory layer 136 covering the bottom surface of the channel layer 138 of the memory pillar MP is embedded in the bottom conductive layer CSL. The discharge pillar 126 passes through the first conductive layer 121 , the first insulating layer 123 , the second conductive layer 125 , the second insulating layer 127 and the third conductive layer 129 and is electrically connected to the corresponding wire 116 . In the process of Figures 13A and 13B, the conductive material can be first filled in the second conductive layer 125, the locations where the first insulating layer 123 and the second insulating layer 127 are removed, and the trench LT, and then etched back The process removes the conductive material in the trench LT and exposes the trench LT again.

Please refer to FIGS. 14A and 14B at the same time. The sacrificial layer 135 in the array area AA and the step area SA is removed through the trench LT through an etching process. In this step, since the present case has support pillars 152, the support pillars 152 can provide sufficient supporting force. Even if the sacrificial layer 135 is removed, the support pillars 152 can still maintain the stability of the entire structure and prevent it from easily collapsing.

Please refer to Figures 15A and 15B at the same time to fill the position where the sacrificial layer 135 was removed with conductive material. Therefore, in the array area AA and the step area SA, a stack 130 in which the conductive layers 134 and the insulating layers 132 are alternately stacked is formed. In one embodiment, the conductive material of conductive layer 134 may include tungsten. In the peripheral area PA, the alternately stacked sacrificial layer 135 and the insulating layer 132 in the stacked structure 130' remain, that is, the sacrificial layer 135 in the peripheral area PA has not been removed. The steps shown in Figures 14A~15B can also be called the gate replacement process.

Please refer to Figures 16A and 16B at the same time, slightly expand the trench LT, and fill the trench LT with insulating material and conductive material in sequence. The filled trench LT includes insulating sidewalls L3 on the sidewalls of the trench LT. The filled trench LT includes a first conductive layer L1 and a second conductive layer L2 surrounded by insulating sidewalls L3. The first conductive layer L1 and the second conductive layer L2 filled in the trench LT are electrically in contact with the bottom conductive layer CSL (serving as a common source line). The materials of the first conductive layer L1 and the second conductive layer L2 may be different from each other. For example, the first conductive layer L1 may be polycrystalline silicon, the material of the second conductive layer L2 may be a metal, such as tungsten, and the material of the insulating sidewall L3 may include an oxide. , however, the present invention is not limited to this.

Please refer to Figures 17A and 17B at the same time to form and dispose a plurality of extended contacts 174 on the landing area of the step area SA. A plurality of extended contacts 174 are in contact with corresponding conductive layers 134 . A back end of line (BEOL) process is performed to form interconnects 172 and extended contacts 174 in contact with the bonding pads 142 . A plurality of connectors 176 are formed to connect corresponding vertical contacts 162 in the peripheral area PA. In the back end of line (BEOL) process, the support pillar 152 is not connected to any interconnect line 172 . It should be understood that the back-end process also includes the formation steps of more wires/conductive layers/plugs (not shown). The interconnections 172, extended contacts 174 and connectors 176 can be formed by more wires/conductors. The layers/plugs are electrically connected to other circuits (not shown). Those with ordinary knowledge in the art can make them in a conventional manner, which will not be described again.

Through the above steps, a semiconductor device 10 according to an embodiment of the present invention is formed, as shown in Figures 17A-17B. The semiconductor device 10 includes a circuit board 110, a backplane 120, a stacked structure 130', a stack 130, a memory pillar MP, a support pillar 152, and a vertical contact 162. The base plate 120 is disposed on the circuit board 110 . The laminated structure 130' and the stack 130 are arranged side by side on the base plate 120, and the laminated structure 130' and the stack 130 are adjacent to each other. The support pillars 152 and the vertical contacts 162 pass through the stack 130 and the stacked structure 130' respectively along the first direction (such as the Z direction). The memory pillar MP passes through the stack 130 along a first direction, such as the Z direction.

Please refer to Figures 17A-17B again. The circuit board 110 includes a substrate 112, a plurality of circuit structures 114, a plurality of wires 116 and an insulating material 118. The circuit structure 114 is disposed on the substrate 112, and the wires 116 are electrically connected to the corresponding circuit structures 114 respectively. Insulating material 118 covers substrate 112, circuit structure 114 and conductors 116. The circuit board 110 corresponds to the peripheral area PA, the step area SA, and the array area AA. The step area SA is provided between the peripheral area PA and the array area AA. The plurality of memory pillars MP pass through the stack 130 along the first direction in the array area AA.

The base plate 120 may include a bottom conductive layer CSL (for example, in the step area SA and the array area AA). The bottom conductive layer CSL may serve as a common source line in the semiconductor device 10 . The semiconductor device 10 further includes a plurality of landing pads 124 , a plurality of discharge columns 126 and a plurality of bottom supports 122 . The landing pad 124 is embedded in at least a top portion of the bottom conductive layer CSL in the step area SA, and is in direct contact (physical contact and electrical contact) with the bottom conductive layer CSL. The discharge pillar 126 passes through the bottom conductive layer CSL along the first direction (eg, Z direction) and is in electrical contact with the bottom conductive layer CSL and the corresponding conductor 116 . During the process of manufacturing the semiconductor device 10, a lot of charges may be accumulated. The discharge column 126 can discharge the accumulated charges downward to avoid excessive voltage difference between the upper and lower conductors. The bottom support 122 is disposed in the step area SA and passes through the bottom conductive layer CSL along the first direction (eg, Z direction). The bottom support members 122 are separated from each other to maintain structural stability during the process of forming the bottom conductive layer CSL, such as providing supporting force during the steps shown in FIGS. 12A and 12B . In this embodiment, the discharge pillar 126 includes a conductive material, and the landing pad 124 includes a conductive material. The discharge pillar 126 and the landing pad 124 can be formed under the same process (such as etching and deposition processes, as shown in Figures 5-6 (shown), the conductive material of the discharge column 126 may be the same as the conductive material of the landing pad 124, but the present invention is not limited thereto.

In the array area AA and the step area SA, the stack 130 includes a plurality of conductive layers 134 and a plurality of insulating layers 132 alternately stacked along the first direction. The stacked structure 130' includes a plurality of sacrificial layers 135 and a plurality of insulating layers 132 alternately stacked along a first direction. The insulating layer 132 of the stack 130 and the insulating layer 132 of the stacked structure 130' are connected to each other. The conductive layer 134 of the stack 130 and the sacrificial layer 135 of the stacked structure 130' are connected to each other in the step area SA or the peripheral area PA. Conductive layer 134 may include one or more series select lines for a top portion of stack 130 , a plurality of word lines for a middle portion of stack 130 , and one or more ground select lines for a bottom portion of stack 130 .

The support posts 152 and the vertical contacts 162 pass through the stack 130 and the stacked structure 130' along a first direction (eg, Z direction). In more detail, the support pillars 152 extend through the stack 130 and through the bottommost conductive layer 134 (ie, the bottommost ground select line) in the stack 130 to the landing pads 124 on the bottom conductive layer CSL. The support column 152 may directly contact (physically and electrically) the landing pad 124 . In other words, there is a landing pad 124 between the bottom conductive layer CSL and the support pillar 152 . The bottom surface of the landing pad 124 in the stepped area SA is lower than the top surface of the bottom conductive layer CSL in the array area AA, that is, the distance in the first direction between the bottom surface of the landing pad 124 in the stepped area SA and the bottom surface of the bottom conductive layer CSL DA is less than the distance DB in the first direction between the top surface of the bottom conductive layer CSL and the bottom surface of the bottom conductive layer CSL in the array area AA. In the first direction (eg, Z direction), the support pillar 152 and the landing pad 124 overlap each other in the step area SA. In one embodiment, support posts 152 may include conductive material. Furthermore, the support pillar 152 includes a first conductive pillar 1522 and a first lining 1521 surrounding the first conductive pillar 1522. In this embodiment, the first conductive pillar 1522 is in direct contact with the landing pad 124. The material of the first conductive pillar 1522 can be the same as the material of the landing pad 124 (such as tungsten). However, the invention is not limited thereto. In other embodiments, , the material of the first conductive pillar 1522 may be different from the material of the landing pad 124 . In another embodiment, support posts 152 are dielectric posts. Since there is a landing pad 124 under the support pillar 152, during the formation of the support pillar 152, the landing pad 124 can provide a good etching option when an opening (such as the first opening 150 shown in FIG. 8A) is formed in the etching process. Compared with the comparative example without a landing pad, the etching depth in this case can be better controlled, and the formation of the etching opening can appropriately stop on the landing pad 124 .

The vertical contacts 162 pass through the stacked structure 130' and the bottom plate 120 (ie, through the bottom conductive layer CSL) along the first direction (for example, the Z direction) to the corresponding conductive wires 116. The vertical contact 162 includes a second conductive pillar 1622 and a second lining 1621 surrounding the second conductive pillar 1622. In this embodiment, the material of the second conductive pillar 1622 may be the same as the material of the first conductive pillar 1522 (such as tungsten), and the material of the second lining 1621 may be the same as the material of the first lining 1521 (such as oxide). , however, the present invention is not limited to this. The support pillars 152 and the vertical contacts 162 can be formed in the same process (as shown in FIGS. 8A to 10A ). That is, the formation of the support pillars 152 and the vertical contacts 162 can be integrated in the same deep etching process. There is no need to manufacture the supporting pillars 152 through additional processes.

In the stack 130 corresponding to the array area AA, each conductive layer 134 intersects the memory layer 136 and the channel layer 138 to form a series of memory cells extending along a first direction (eg, Z direction). The channel layer 138 is in electrical contact with the bottom conductive layer CSL. Each memory column MP includes a series of memory cells connected in NAND type, but the invention is not limited thereto. Furthermore, the trench LT and the top spacer SSLC extend along the first direction (such as the Z direction) and the second direction (such as the X direction), dividing the stack 130 into a predetermined number of blocks and sub-blocks (not shown) . Each trench LT includes a first conductive layer L1 (such as polysilicon), a second conductive layer L2 (such as tungsten), and an insulating sidewall L3 (such as an oxide). The insulating sidewall L3 makes the first conductive layer L1 and the second conductive layer L2 It may be isolated from adjacent layers (such as conductive layer 134). The first conductive layer L1 is in electrical contact with the underlying bottom conductive layer CSL. The top spacer SSLC (eg, oxide) passes through the conductive layer 134 corresponding to the top portion of the stack 130 along a first direction (eg, the Z direction) to define a series select line.

In the stepped area SA of the stack 130 , the conductive layer 134 has a stepped structure to provide a landing area connected to the extended contact 174 so that the extended contact 174 is in electrical contact with the corresponding conductive layer 134 . Extended contacts 174 may include word line contacts.

Figures 18A to 18F illustrate a manufacturing flow chart of the semiconductor device 20 according to another embodiment of the present invention. Among them, Figures 18A to 18F correspond to the plane formed by the second direction (for example, the X direction) and the third direction (for example, the Y direction).

The semiconductor device 20 has the same and similar process and structure as the semiconductor device 10 , except that the semiconductor device 20 further includes a vertical support member 180 in the step area SA.

Referring to FIG. 18A, after the base plate 120 is formed on the circuit board 110, the first conductive layer 121, the second conductive layer 125 and the third conductive layer 129 at predetermined positions are removed to form a plurality of openings, and then the insulating material is filled. A plurality of bottom supports 122 (such as oxides) are formed in the opening and in the step area SA, as shown in the steps of Figures 1 to 3 and related content. In addition, a plurality of holes 180p may be formed in the step area SA. The hole 180p represents a predetermined position of the vertical support 180. For clearer distinction, the cross-section of the hole 180p is represented by a square, and the cross-section of the bottom support 122 is represented by a circle. However, the cross-section of the hole 180p is different from that of the bottom support 122. The shape is not limited to this.

Please refer to Figure 18B to form a plurality of landing pads 124 and a plurality of discharge columns 126. The structure, function and formation steps of the landing pad 124 and the discharge column 126 are shown in Figures 4 to 5 and related contents. Adjacent landing pads 124 are separated by bottom supports 122 . As shown in FIG. 18B , in this embodiment, the discharge column 126 can be further away from the array area AA than the landing pad 124 .

Please refer to Figure 18C to form the memory column MP and the top spacer SSLC. The structure, function and formation steps of the memory column MP and the top spacer SSLC are shown in Figures 7A and 7B and their related contents.

Referring to Figure 18D, the support pillar 152, the vertical contact member 162 and the vertical support member 180 are formed through the same process. The structure, function and formation steps of the support column 152 and the vertical contact 162 are shown in Figures 8A to 10B and related contents. Support posts 152 in the stepped area SA are formed on the landing pad 124 . The vertical contacts 162 extend through the base plate 120 along a first direction (eg, the Z direction) to the corresponding wires 116 . The formation manner and structure of the vertical support member 180 located in the step area SA are similar to the formation manner and structure of the vertical contact member 162 located in the peripheral area PA. The vertical support 180 located in the step area SA extends through the bottom plate 120 along the first direction (eg, Z direction) to the corresponding conductor 116 . The vertical support 180 includes a third conductive pillar (not shown) and a third lining (not shown) surrounding the third conductive pillar. In one example, the material of the third conductive pillar (not shown) is the same as the material of the first conductive pillar 1522 and the second conductive pillar 1622 . The material of the third lining (not shown) is a dielectric material. In some examples, the third lining (not shown) is made of the same material as the first lining 1521 and the second lining 1621 . The third conductive pillar (not shown) is in electrical contact with the corresponding wire 116 . The vertical contacts 162 in the peripheral area PA may have a signal transmission function (eg, word line signal transmission). The support pillars 152 in the step area SA have the function of supporting the overall structure during the gate replacement process. The vertical support 180 in the step area SA not only has the function of signal transmission, but also has the function of supporting the overall structure during the gate replacement process.

Please refer to Figure 18E to form the trench LT and perform the gate replacement process. The formation of trench LT and the steps of the gate replacement process are shown in Figures 11A to 16B and related content. The trench LT extends from the array area AA to the step area SA along the second direction (for example, the X direction).

Referring to Figure 18F, a plurality of extended contacts 174 are formed in the step area SA. After that, the back-end process is performed. The formation method of the back-end process is shown in Figures 17A~17B and its related contents.

As shown in FIG. 18F , in the step area SA, the discharge pillar 126 is further away from the trench LT than the support pillar 152 . For example, in the step area SA, there is a first distance D1 in the second direction (for example, the X direction) between the end of the trench LT and the center point of the discharge column 126 . There is a second distance D2 in the second direction (for example, the X direction) between the end of the trench LT and the center point of the support pillar 152 (eg, the support pillar 152 closest to the discharge pillar 126). The first distance D1 is greater than the second distance D2.

Figure 19 illustrates a cross-sectional view of a landing pad 224 according to yet another embodiment of the present invention. Figure 20A shows a top view of the landing pad 324 according to another embodiment of the present invention, and Figure 20B shows a cross-sectional view of the landing pad 324 according to another embodiment of the present invention. Figures 19 and 20B correspond to the plane formed by the first direction (for example, the Z direction) and the second direction (for example, the X direction). Figure 20A corresponds to the plane formed by the second direction (eg, X direction) and the third direction (eg, Y direction).

Please refer to Figure 19. The difference between the landing pad 224 and the landing pad 124 shown in Figure 6 is that the landing pad 224 has a double-layer structure and includes an insulating part 2241 and a conductive part 2242. The insulating part 2241 covers the side walls and bottom of the conductive part 2242, exposing the upper surface of the conductive part 2242, so that the landing pad 224 is electrically isolated from the third conductive layer 129 below (that is, it is electrically isolated from the subsequently formed bottom conductive layer CSL). . In this embodiment, the material of the insulating part 2241 may include oxide, and the material of the conductive part 2242 may include conductive material, such as tungsten. The upper surface of the landing pad 224 is still made of conductive material, so it can provide a good etching selectivity like the landing pad 124 . Furthermore, the insulating portion 2241 of the landing pad 224 also has the advantage of reducing the resistance-capacitance delay (RC delay) of the bottom conductive layer.

Please refer to Figures 20A and 20B. The landing pad 324 includes an insulating part 3241 and a conductive part 3242. The material of the insulating portion 3241 may include an oxide, and the material of the conductive portion 3242 may include a conductive material, such as tungsten. The difference between the landing pad 324 and the landing pad 224 is that the landing pad 324 extends downward from the third conductive layer 129 to the first conductive layer 121 , that is, the landing pad 324 can extend to the bottom of the bottom conductive layer CSL. Thereby, the landing pad 324 can be used as a support member in the process of forming the bottom conductive layer CSL (as shown in FIGS. 12A and 12B ), so the bottom support member 122 can be omitted. Similarly, landing pad 324 can provide good etch selectivity and has the advantage of reducing the resistance-capacitance delay of the bottom conductive layer CSL.

In summary, although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the appended patent application scope.

10,20:Semiconductor device 110:Circuit board 112:Substrate 114:Circuit structure 116:Wire 118:Insulating materials 120: Base plate 121: First conductive layer 122: Bottom support 123: First insulation layer 124,224,324 124p: Top opening 125: Second conductive layer 126:Discharge column 126p:through opening 127: Second insulation layer 129:Third conductive layer 130:Stacking 130’:Laminated structure 132:Insulation layer 134: Conductive layer 135:Sacrificial layer 136:Memory layer 138: Channel layer 140:Insulation column 142: Solder pad 144:Insulating materials 150p: First opening 152:Support column 160p:Second opening 162:Vertical contacts 172:Internal connection 174:Extension contact 176: Connector 180p:hole 180:Vertical support 1521:First lining 1522:The first conductive pillar 1621: Second lining 1622: Second conductive pillar 2241,3241: Insulation part 2242,3242: Conductive part AA: array area CSL: bottom conductive layer DA, DB: distance L1: first conductive layer L2: The second conductive layer L3: Insulated side wall MP: memory column PA:surrounding area SA: step area SSLC: top spacer D1: first distance D2: second distance

Figures 1 to 17B illustrate a manufacturing flow chart of a semiconductor device according to an embodiment of the present invention; Figures 18A to 18F illustrate a manufacturing flow chart of a semiconductor device according to another embodiment of the present invention; Figure 19 shows a cross-sectional view of a landing pad according to another embodiment of the present invention; Figure 20A shows a top view of a landing pad according to another embodiment of the present invention; and Figure 20B shows a cross-sectional view of a landing pad according to another embodiment of the present invention.

10:Semiconductor device

110:Circuit board

112:Substrate

114:Circuit structure

116:Wire

118:Insulating materials

120: Base plate

121: First conductive layer

122: Bottom support

123: First insulation layer

124: Landing Pad

124p: Top opening

125: Second conductive layer

126:Discharge column

126p:through opening

127: Second insulation layer

129:Third conductive layer

130:Stacking

130’:Laminated structure

132:Insulation layer

134: Conductive layer

135:Sacrificial layer

136:Memory layer

138: Channel layer

140:Insulation column

142: Solder pad

144:Insulating materials

150p: First opening

152:Support column

160p:Second opening

162:Vertical contacts

172:Internal connection

174:Extension contact

176: Connector

1521:First lining

1522:The first conductive pillar

1621: Second lining

1622: Second conductive pillar

AA: array area

CSL: bottom conductive layer

DA, DB: distance

MP: memory column

PA:surrounding area

SA: step area

Claims (10)

A semiconductor device including: A circuit board includes a plurality of circuit structures and a plurality of conductors, the circuit structures are electrically connected to the corresponding conductors, and the circuit board has a peripheral area, an array area and is disposed in the peripheral area and the array area a stepped area between; A base plate is provided on the circuit board, and the base plate includes a bottom conductive layer; A plurality of landing pads are embedded in at least a top portion of the bottom conductive layer in the step area and are in contact with the bottom conductive layer; A stack is provided on the base plate, the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked along a first direction; a plurality of support columns passing through the stack along the first direction in the step area and extending to the landing pads; and A plurality of memory columns pass through the stack along the first direction in the array area. The semiconductor device according to claim 1, further comprising a plurality of vertical contacts extending along the first direction in the peripheral area and electrically contacting the corresponding conductors, wherein the supports The posts include the same conductive material as the vertical contacts. The semiconductor device of claim 1, wherein each landing pad has a conductive portion. The semiconductor device of claim 3 further includes an insulating part covering the sidewalls and the bottom of the conductive part. The semiconductor device according to claim 1, further comprising a plurality of discharge pillars, the discharge pillars passing through the bottom conductive layer along the first direction in the step region and electrically contacting the corresponding conductors. The semiconductor device of claim 5, wherein a top surface of the landing pads and a top surface of the discharge columns are substantially coplanar. The semiconductor device of claim 5, further comprising at least one trench passing through the stack along the first direction and extending from the array region to the step region along a second direction, The second direction is different from the first direction, wherein, Compared with the support pillars, the discharge pillars are further away from the at least one trench. A method of manufacturing a semiconductor device, including: A circuit board is formed. The circuit board includes a plurality of circuit structures and a plurality of conductors. The circuit structures are electrically connected to the corresponding conductors. The circuit board has a peripheral area, an array area and is disposed on the periphery. A stepped area between the area and the array area; Forming a base plate on the circuit board, and the base plate includes a bottom conductive layer; forming a plurality of landing pads embedded in at least a top portion of the bottom conductive layer in the stepped region and in contact with the bottom conductive layer; Forming a stack placed on the base plate, the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked along a first direction; forming a plurality of support columns that pass through the stack along the first direction in the step area and extend to the landing pads; and A plurality of memory columns are formed that pass through the stack along the first direction in the array area. The method of manufacturing a semiconductor device as claimed in claim 8, wherein the step of forming the base plate further includes: A first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer and a third conductive layer are sequentially formed on the circuit board in the first direction. The method for manufacturing a semiconductor device as claimed in claim 8 further includes: A plurality of top openings are formed in a top portion of the third conductive layer in the stepped region, the top openings being spaced apart from each other; and A conductive material is filled into the top openings to form the landing pads.

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