TW202347287A - Pixel circuit - Google Patents

Abstract

A pixel circuit is provided. The pixel circuit includes a light-emitting diode, a control block and a light-emitting driving block. The control block provides an internal node voltage, and forms a first voltage compensation path between a swing signal and a first data voltage to compensate a first threshold voltage of a first core transistor. The light-emitting driving block provides light-emitting current to an anode of the light-emitting diode, and forms a second voltage compensation path between a system high voltage and a second data voltage to compensate a second threshold voltage of a second core transistor.

Description

Pixel circuit

The present invention relates to a pixel circuit, and in particular to a light emitting diode pixel circuit.

Due to the rise in environmental awareness, energy saving, service life, color saturation and power quality have gradually become factors that consumers consider purchasing. At the same time, the rapid development of semiconductor technology and cost reduction have driven light-emitting components to become the future development of the lighting and display market. mainstream. Among them, organic light-emitting diodes (OLEDs) and micro-light-emitting diodes (uLEDs) are the main components currently used in self-luminous display panels.

However, the luminous brightness curves of micro-light-emitting diodes (uLEDs) and organic light-emitting diodes (OLEDs) are different, that is, the luminous efficiency of the light-emitting diodes is very low when operating at the same brightness. Moreover, since the current range operated by the organic light-emitting diode drive circuit falls within the low luminous efficiency range of micro-light-emitting diodes, the earlier-developed organic light-emitting diode drive circuit cannot be directly applied to micro-light-emitting diodes. polar body. Therefore, in order to drive micro light-emitting diodes, the existing driving circuit needs to be correspondingly modified or redesigned.

The present invention provides a pixel circuit that can be driven by pulse width modulation and pulse amplitude modulation, and can prevent the critical voltage of the first core transistor from being affected by other nodes in the pulse width modulation driving method. In the pulse amplitude modulation circuit compensation mode, the positive/negative offset critical voltage of the second core transistor can be compensated.

The pixel circuit of the present invention includes a light-emitting diode, a control block and a light-emitting driving block. The light-emitting diode has an anode and a cathode that receives the system's low voltage. The control block receives the data high voltage, the data low voltage, the first data voltage, the pixel lighting signal, the swing signal, the first gate signal and the pulse width modulation signal to provide an internal node voltage. The control block forms a first voltage compensation path between the swing signal and the first data voltage to compensate the first critical voltage of the first core transistor. The light-emitting driving block is coupled to the control block and the anode of the light-emitting diode, and receives the internal node voltage, the system high voltage, the anode reset signal, the reset voltage, the second data voltage, and the second gate signal to provide Luminous current flows to the anode of the light-emitting diode. The light-emitting driving block forms a second voltage compensation path between the system high voltage and the second data voltage to compensate the second critical voltage of the second core transistor.

Based on the above, in the pixel circuit of the embodiment of the present invention, the control block sets the pulse width of the internal node voltage based on the first data voltage, and forms a first voltage compensation path that compensates the critical voltage of the first core transistor; the light-emitting driving area The block sets the current amplitude of the light-emitting current based on the second data voltage and sets the supply time of the light-emitting current based on the pulse width of the internal node voltage, and forms a second voltage compensation path that compensates the critical voltage of the second core transistor. In this way, the pixel circuit can drive the light-emitting diode using pulse width modulation and pulse amplitude modulation, and in the pulse width modulation driving mode, the critical voltage of the first core transistor can be controlled by other nodes. In the circuit compensation mode of pulse amplitude modulation, the positive/negative offset critical voltage of the second core transistor can be compensated.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed to have meanings consistent with their meanings in the context of the relevant technology and the present invention, and are not to be construed as idealistic or excessive Formal meaning, unless expressly defined as such herein.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or sections or parts thereof shall not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element", "component", "region", "layer" or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms including "at least one" unless the content clearly dictates otherwise. "or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will also be understood that when used in this specification, the terms "comprises" and/or "includes" designate the presence of stated features, regions, integers, steps, operations, elements and/or components but do not exclude one or more The presence or addition of other features, regions, steps, operations, elements, parts and/or combinations thereof.

FIG. 1A is a schematic circuit diagram of a pixel circuit according to the first embodiment of the present invention. Please refer to FIG. 1A. In this embodiment, the pixel circuit 100 includes a light-emitting element, a control block 110, and a light-emitting driving block 120. The light-emitting element is a micro light-emitting diode ED1 as an example. However, the embodiment of the present invention Any type of light-emitting diode may be used, and the embodiment of the present invention is not limited thereto. The miniature light-emitting diode ED1 has an anode and a cathode that receives the system low voltage VSS.

The control block 110 receives the data high voltage Data_H, the data low voltage Data_L, the first data voltage Data1, the pixel emission signal EM, the swing signal TCS, the first gate signal RG1 and the pulse width modulation signal Spwm to provide the internal node voltage. VQ, in which the control block 110 forms a first voltage compensation path VPath1 between the swing signal TCS and the first data voltage Data1 to compensate the first critical voltage of the first core transistor (that is, the third transistor T3). The light-emitting driving block 120 is coupled to the control block 110 and the anode of the micro light-emitting diode ED1, and receives the internal node voltage VQ, the system high voltage OVDD, the anode reset signal R_anode, the reset voltage Vsus, the second data voltage Data2, The pixel light-emitting signal EM, the modulated light-emitting signal EM_D and the second gate signal RG2 are used to provide the light-emitting current Iem to the anode of the micro-light-emitting diode ED1, in which the light-emitting driving block 120 operates between the system high voltage OVDD and the second data voltage. A second voltage compensation path VPath2 is formed between Data2 to compensate the second critical voltage of the second core transistor.

In this embodiment, the control block 110 sets the pulse width of the internal node voltage VQ based on the first data voltage Data1, and the light-emitting driving block 120 sets the current amplitude of the light-emitting current Iem based on the second data voltage Data2 and based on the internal The pulse width of the node voltage VQ sets the supply time of the light-emitting current Iem. Thereby, the pixel circuit 100 can drive the micro light-emitting diode ED1 using pulse width modulation and pulse amplitude modulation, and can keep the critical voltage of the first core transistor constant under the pulse width modulation driving method. Affected by other nodes, the positive/negative offset critical voltage of the second core transistor can be compensated in the circuit compensation mode of pulse amplitude modulation.

In this embodiment, the control block 110 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a first capacitor C1, where the first The transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are NMOS as an example, but the embodiment of the present invention is not limited thereto.

The first transistor T1 has a first terminal receiving the data high voltage Data_H, a control terminal receiving the first gate signal RG1, and a second terminal. The second transistor T2 has a first terminal for receiving the data low voltage Data_L, a control terminal for receiving the pixel light emitting signal EM, and a second terminal. The third transistor T3 serves as the first core transistor and has a first terminal coupled to the second terminal of the second transistor T2, a control terminal coupled to the second terminal of the first transistor T1, and an internal node voltage VQ. Second end.

The fourth transistor T4 has a first terminal receiving the first data voltage Data1, a control terminal receiving the pulse width modulation signal Spwm, and a second terminal coupled to the second terminal of the second transistor T2. The fifth transistor T5 has a first terminal coupled to the second terminal of the first transistor T1, a control terminal receiving the pulse width modulation signal Spwm, and a second terminal coupled to the second terminal of the third transistor T3. The first capacitor C1 is coupled between the swing signal TCS and the second terminal of the first transistor T1.

The light emitting driving block 120 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a second capacitor C2, and a third capacitor C3, wherein the sixth transistor T6 The transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are NMOS as an example, but the embodiment of the present invention is not limited thereto.

The sixth transistor T6 has a first terminal receiving the second data voltage Data2, a control terminal receiving the second gate signal RG2, and a second terminal receiving the internal node voltage VQ. The seventh transistor T7 serves as the second core transistor and has a first terminal, a control terminal receiving the internal node voltage VQ, and a second terminal.

The eighth transistor T8 has a first terminal coupled to the second terminal of the seventh transistor T7, a control terminal receiving the anode reset signal R_anode, and a second terminal receiving the reset voltage Vsus. The second capacitor C2 is coupled between the internal node voltage VQ and the second terminal of the seventh transistor T7. The ninth transistor T9 has a first terminal for receiving the system high voltage OVDD, a control terminal for receiving the modulated light emitting signal EM_D, and a second terminal coupled to the first terminal of the seventh transistor T7, wherein the seventh transistor T7 The first terminal is coupled to the system high voltage OVDD through the ninth transistor T9.

The third capacitor C3 is coupled between the first terminal of the ninth transistor T9 and the second terminal of the seventh transistor T7. The tenth transistor T10 has a first terminal coupled to the second terminal of the seventh transistor T7, a control terminal receiving the pixel light emitting signal EM, and a second terminal coupled to the anode of the micro light emitting diode ED1. The second terminal of the seventh transistor T7 is coupled to the anode of the micro light-emitting diode ED1 through the tenth transistor T10.

In the present invention, the pixel circuit 100 further includes a fourth capacitor C4, wherein the fourth capacitor C4 is coupled between the anode and the cathode of the micro light-emitting diode ED1.

FIG. 1B is a schematic diagram of the driving waveform of the pixel circuit during a single picture period according to the first embodiment of the present invention. Referring to FIG. 1A and FIG. 1B , a single picture period is divided into a pulse width modulation period P_pwm and a pulse amplitude modulation period P_pam. During the pulse width modulation period P_pwm, multiple first gate signals (such as RG1(n), RG1(n+1)) are enabled sequentially, and multiple pulse width modulation signals (such as Spwm(n) , Spwm(n+1)) are enabled sequentially, in which each pulse width modulation signal (such as Spwm(n), Spwm(n+1)) is followed by the corresponding first gate signal (such as RG1(n), RG1(n+1)) is enabled, and n is a pilot number.

During the pulse amplitude modulation period P_pam, the second gate signal RG2 is enabled, and during the period when the second gate signal RG2 is enabled, the anode reset signal R_anode and the modulated light emitting signal EM_D are enabled in sequence. When the second gate signal RG2 is enabled, the voltage level of the swing signal TCS climbs from low to upward. After the period in which the second gate signal RG2 is enabled, the pixel luminescence signal EM and the modulation luminescence signal EM_D are simultaneously enabled until the pulse amplitude modulation period P_pam ends.

Furthermore, in the first reset period Pr1 in the pulse width modulation period P_pwm, the corresponding first gate signal (taking RG1(n) as an example) is enabled, and the pixel luminescence signal EM, the corresponding The pulse width modulation signal (taking Spwm(n) as an example), the second gate signal RG2, the anode reset signal R_anode and the modulation light emitting signal EM_D maintain the disabled level, and the swing signal TCS stays at the common voltage level. At this time, the first transistor T1 and the third transistor T3 will be turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T7 will be turned on. The transistor T8, the ninth transistor T9, and the tenth transistor T10 are turned off.

In the first compensation period Pcw in the pulse width modulation period P_pwm, the corresponding pulse width modulation signal (taking Spwm(n) as an example) will be enabled, the pixel luminescence signal EM, and the corresponding first gate signal (Take RG1(n) as an example), the second gate signal RG2, the anode reset signal R_anode and the modulated light emitting signal EM_D maintain the disabled level, and the swing signal TCS stays at the common voltage level. At this time, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 will be turned on, and the first transistor T1, the second transistor T2, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T7 will be turned on. The transistor T8, the ninth transistor T9, and the tenth transistor T10 are turned off. Thereby, the first voltage compensation path VPath1 can be formed between the swing signal TCS and the first data voltage Data1, and the voltage level of the control terminal of the third transistor T3 will be the voltage level of the first data voltage Data1 and the third transistor T3. The sum of the first threshold voltages is used to compensate the first threshold voltage of the third transistor T3. The operations of the pixel circuit 100 on other first gate signals (such as RG1(n+1)) and other pulse width modulation signals (such as Spwm(n+1)) can be referred to the above, and will not be described again here.

In the second reset period Pr2 of the pulse amplitude modulation period P_pam, the second gate signal RG2 and the anode reset signal R_anode are enabled, and the first gate signal (such as RG1(n), RG1(n+1 )), pulse width modulation signals (such as Spwm(n), Spwm(n+1)), pixel luminescence signal EM, and modulation luminescence signal EM_D maintain the disabled level, and the swing signal TCS is lower than the common voltage The low voltage level of the level climbs upward. At this time, the sixth transistor T6 and the eighth transistor T8 will be turned on, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T5 will be turned on. The transistor T7, the ninth transistor T9, and the tenth transistor T10 are turned off. Moreover, the voltage level of the control terminal of the seventh transistor T7 will be reset by the voltage level of the second data voltage Data2, and the voltage level of the second terminal of the seventh transistor T7 will be affected by the reset voltage Vsus. Reset due to impact.

In the second compensation period Pca of the pulse amplitude modulation period P_pam, the second gate signal RG2 and the modulated light emitting signal EM_D are enabled, and the first gate signal (such as RG1(n), RG1(n+1) ), pulse width modulation signals (such as Spwm(n), Spwm(n+1)), pixel luminescence signal EM, and anode reset signal R_anode maintain the disabled level, and the swing signal TCS continues to climb upward. At this time, the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9 will be turned on, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T9 will be turned on. The transistor T5, the eighth transistor T8, and the tenth transistor T10 are turned off. Thereby, a second voltage compensation path VPath2 is formed between the system high voltage OVDD and the second data voltage Data2, and the voltage level of the control terminal of the seventh transistor T7 will be higher than the voltage level of the second terminal of the seventh transistor T7. The bit is the second critical voltage of the seventh transistor T7 to compensate the second critical voltage of the seventh transistor T7.

During the data writing period Pdw of the pulse amplitude modulation period P_pam, the second gate signal RG2 is partially enabled, and the first gate signal (such as RG1(n), RG1(n+1)), pulse width modulation Variable signals (such as Spwm(n), Spwm(n+1)), pixel luminescence signal EM, modulation luminescence signal EM_D and anode reset signal R_anode maintain the disabled level, and the swing signal TCS continues to climb upward. At this time, the sixth transistor T6 will be turned on, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T6 will be turned on. The crystal T8, the ninth transistor T9, and the tenth transistor T10 are turned off. Thereby, the second data voltage Data2 will be transmitted to the control end of the seventh transistor T7 to set the current amplitude of the light-emitting current Iem.

In the light-emitting period Pem of the pulse amplitude modulation period P_pam, the pixel light-emitting signal EM and the modulated light-emitting signal EM_D are enabled, and the first gate signal (such as RG1(n), RG1(n+1)), pulse The wide modulation signal (such as Spwm(n), Spwm(n+1)), the second gate signal RG2 and the anode reset signal R_anode maintain the disabled level, and the swing signal TCS continues to climb upward. At this time, the seventh transistor T7, the ninth transistor T9, and the tenth transistor T10 will be turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor will be turned on. The crystal T6 and the eighth transistor T8 are cut off.

Furthermore, the third transistor T3 will be turned off at first, but when the rise of the swing signal TCS causes the voltage level of the control terminal of the third transistor T3 to be high enough, the third transistor T3 will change from being turned off to being turned on. The data low voltage Data_L is transmitted to the control end of the seventh transistor T7. After receiving the data low voltage Data_L, the seventh transistor T7 changes from on to off. Thereby, the micro light-emitting diode ED1 can be driven by pulse width modulation and pulse amplitude modulation.

According to the above, the function of the first transistor T1 is to perform reset, the function of the second transistor T2 is to be connected to the seventh transistor T7, and the function of the third transistor T3 is to serve as the third transistor for pulse width modulation. A core transistor, the fourth transistor T4 is used for data writing, the fifth transistor T5 is used for compensation, and the sixth transistor T6 is used for reset and data writing. , the function of the seventh transistor T7 is as the second core transistor for pulse amplitude modulation, the function of the eighth transistor T8 is for reset, and the function of the ninth transistor T9 is for compensation and lighting. , the function of the tenth transistor T10 is to emit light.

FIG. 2 is a schematic circuit diagram of a pixel circuit according to a second embodiment of the present invention. Please refer to FIG. 1A and FIG. 2 . The pixel circuit 200 is substantially the same as the pixel circuit 100 . The difference lies in that the light-emitting driving block 220 of the pixel circuit 200 further includes an eleventh transistor T11 , in which the same or similar components are used. Same or similar numbers. In this embodiment, the eleventh transistor T11 has a first terminal that receives the reference voltage Vnef, a control terminal that receives the third gate signal RG3, and a second terminal that receives the internal node voltage VQ.

FIG. 3 is a schematic circuit diagram of a pixel circuit according to a third embodiment of the present invention. Please refer to FIG. 1A and FIG. 3 . The pixel circuit 300 is substantially the same as the pixel circuit 100 . The difference lies in that the light emitting driving block 320 of the pixel circuit 300 further includes an eleventh transistor T11 and omits the tenth transistor T10 . , where the same or similar components use the same or similar numbers, and the coupling relationship of the eleventh transistor T11 is shown in the embodiment of FIG. 2 , which will not be described again here.

FIG. 4 is a schematic circuit diagram of a pixel circuit according to a fourth embodiment of the present invention. Please refer to FIG. 1A and FIG. 4 . The pixel circuit 400 is substantially the same as the pixel circuit 100 . The difference lies in that the pixel circuit 400 further includes an eleventh transistor T11 and omits the ninth transistor T9 and the tenth transistor T10 . , where the same or similar components use the same or similar numbers, and the coupling relationship of the eleventh transistor T11 is shown in the embodiment of FIG. 2 , which will not be described again here.

FIG. 5 is a schematic circuit diagram of a pixel circuit according to a fifth embodiment of the present invention. Referring to FIG. 1A and FIG. 5 , the pixel circuit 500 is substantially the same as the pixel circuit 100 . The difference lies in that the pixel circuit 500 omits the tenth transistor T10 , and the same or similar components use the same or similar numbers.

FIG. 6 is a schematic circuit diagram of a pixel circuit according to a sixth embodiment of the present invention. Please refer to FIG. 1A and FIG. 6 . The pixel circuit 600 is substantially the same as the pixel circuit 100 . The difference lies in that the pixel circuit 600 omits the ninth transistor T9 and the tenth transistor T10 . The same or similar components use the same or similar components. Similar labels.

To sum up, in the pixel circuit of the embodiment of the present invention, the control block sets the pulse width of the internal node voltage based on the first data voltage, and forms a first voltage compensation path that compensates the critical voltage of the first core transistor; and emits light. The driving block sets the current amplitude of the light-emitting current based on the second data voltage and sets the supply time of the light-emitting current based on the pulse width of the internal node voltage, and forms a second voltage compensation path that compensates the critical voltage of the second core transistor. Thereby, the pixel circuit can drive the micro light-emitting diode using pulse width modulation and pulse amplitude modulation, and in the pulse width modulation driving mode, the critical voltage of the first core transistor can be controlled by other devices. Node influence, and in the circuit compensation mode of pulse amplitude modulation, the positive/negative offset critical voltage of the second core transistor can be compensated.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

100, 200, 300, 400, 500, 600: pixel circuit 110:Control block 120, 220, 320, 420, 520, 620: Luminous drive block C1: first capacitor C2: second capacitor C3: The third capacitor C4: The fourth capacitor Data_H: data high voltage Data_L: data low voltage Data1: first data voltage Data2: Second data voltage ED1: Micro LED EM: Pixel luminescence signal EM: Pixel luminescence signal EM_D: Modulated luminous signal Iem: luminous current OVDD: system high voltage P_pam: pulse amplitude modulation period P_pwm: pulse width modulation period Pca: second compensation period Pcw: first compensation period Pdw: data writing period Pem: glowing period Pr1: First reset period Pr2: Second reset period R_anode: anode reset signal RG1, RG1(n), RG1(n+1): first gate signal RG2: Second gate signal RG3: The third gate signal Spwm, Spwm(n), Spwm(n+1): pulse width modulation signal T1: the first transistor T10: The tenth transistor T11: The eleventh transistor T2: Second transistor T3: The third transistor T4: The fourth transistor T5: The fifth transistor T6: The sixth transistor T7: The seventh transistor T8: The eighth transistor T9: Ninth transistor TCS: swing signal VPath1: first voltage compensation path VPath2: Second voltage compensation path VQ: internal node voltage Vnef: reference voltage VSS: system low voltage Vsus: reset voltage

FIG. 1A is a schematic circuit diagram of a pixel circuit according to the first embodiment of the present invention. FIG. 1B is a schematic diagram of the driving waveform of the pixel circuit during a single picture period according to the first embodiment of the present invention. FIG. 2 is a schematic circuit diagram of a pixel circuit according to a second embodiment of the present invention. FIG. 3 is a schematic circuit diagram of a pixel circuit according to a third embodiment of the present invention. FIG. 4 is a schematic circuit diagram of a pixel circuit according to a fourth embodiment of the present invention. FIG. 5 is a schematic circuit diagram of a pixel circuit according to a fifth embodiment of the present invention. FIG. 6 is a schematic circuit diagram of a pixel circuit according to a sixth embodiment of the present invention.

100: Pixel circuit

110:Control block

120: Luminous drive block

C1: first capacitor

C2: second capacitor

C3: The third capacitor

C4: The fourth capacitor

Data_H: data high voltage

Data_L: data low voltage

Data1: first data voltage

Data2: Second data voltage

ED1: Micro LED

EM: Pixel luminescence signal

EM_D: Modulated luminous signal

Iem: luminous current

OVDD: system high voltage

R_anode: anode reset signal

RG1: first gate signal

RG2: Second gate signal

Spwm: pulse width modulation signal

T1: the first transistor

T10: The tenth transistor

T2: Second transistor

T3: The third transistor

T4: The fourth transistor

T5: The fifth transistor

T6: The sixth transistor

T7: The seventh transistor

T8: The eighth transistor

T9: Ninth transistor

TCS: swing signal

VPath1: first voltage compensation path

VPath2: Second voltage compensation path

VQ: internal node voltage

VSS: system low voltage

Vsus: reset voltage

Claims (9)

A pixel circuit including: A light-emitting diode having an anode and a cathode receiving a system low voltage; A control block receives a data high voltage, a data low voltage, a first data voltage, a pixel lighting signal, a swing signal, a first gate signal and a pulse width modulation signal to provide an internal Node voltage, wherein the control block forms a first voltage compensation path between the swing signal and the first data voltage to compensate a first critical voltage of a first core transistor; A light-emitting driving block is coupled to the control block and the anode of the light-emitting diode, and receives the internal node voltage, a system high voltage, an anode reset signal, a reset voltage, and a second data voltage. , and a second gate signal to provide a light-emitting current to the anode of the light-emitting diode, wherein the light-emitting driving block forms a second voltage compensation path between the system high voltage and the second data voltage. , to compensate a second critical voltage of a second core transistor. The pixel circuit as claimed in claim 1, wherein the control block includes: A first transistor has a first terminal that receives the data high voltage, a control terminal that receives the first gate signal, and a second terminal; a second transistor having a first terminal for receiving the data low voltage, a control terminal for receiving the pixel light-emitting signal, and a second terminal; A third transistor serves as the first core transistor and has a first terminal coupled to the second terminal of the second transistor, a control terminal coupled to the second terminal of the first transistor, and a second terminal providing the internal node voltage; a fourth transistor having a first terminal receiving the first data voltage, a control terminal receiving the pulse width modulation signal, and a second terminal coupled to the second terminal of the second transistor; a fifth transistor having a first terminal coupled to the second terminal of the first transistor, a control terminal receiving the pulse width modulation signal, and a first terminal coupled to the second terminal of the third transistor second end; and A first capacitor is coupled between the swing signal and the second terminal of the first transistor. The pixel circuit as claimed in claim 1, wherein the control block includes: a sixth transistor having a first terminal receiving the second data voltage, a control terminal receiving the second gate signal, and a second terminal receiving the internal node voltage; A seventh transistor serves as the first core transistor and has a first terminal coupled to the system high voltage, a control terminal receiving the internal node voltage, and a first terminal coupled to the anode of the light-emitting diode. a second end; an eighth transistor having a first terminal coupled to the second terminal of the seventh transistor, a control terminal receiving the anode reset signal, and a second terminal receiving the reset voltage; and A second capacitor is coupled between the internal node voltage and the second terminal of the seventh transistor. The pixel circuit as claimed in claim 3, wherein the control block further includes: A ninth transistor has a first terminal for receiving the system high voltage, a control terminal for receiving a modulated light-emitting signal, and a second terminal coupled to the first terminal of the seventh transistor. The pixel circuit of claim 4, wherein the control block further includes: A third capacitor is coupled between the first terminal of the ninth transistor and the second terminal of the seventh transistor. The pixel circuit as claimed in claim 3, wherein the control block further includes: A tenth transistor having a first terminal coupled to the second terminal of the seventh transistor, a control terminal receiving the light emitting signal of the pixel, and a second terminal coupled to the anode of the light emitting diode. end. The pixel circuit as claimed in claim 3, wherein the control block further includes: An eleventh transistor has a first terminal receiving a reference voltage, a control terminal receiving a third gate signal, and a second terminal receiving the internal node voltage. The pixel circuit as described in claim 1, further including: A fourth capacitor is coupled between the anode and the cathode of the light-emitting diode. The pixel circuit of claim 1, wherein the light-emitting diode includes a micro light-emitting diode.

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