TW202345132A - Display device - Google Patents

Abstract

A display device includes a plurality of pixels, a plurality of multiplexers and a compensation circuit. Each pixel includes a light-emitting element, first to third transistors, a capacitor and a display control circuit. The first transistor receives a data signal and is controlled by a first scan signal. The capacitor is coupled between the first transistor and the light-emitting element. The first terminal of the second transistor is coupled to the light-emitting element, and the control terminal receives the data signal through the first transistor. The third transistor is coupled to the light-emitting element and the capacitor, and is controlled by a second scan signal. The display control circuit conducts the second terminal of the second transistor with a first working power source according to a display control signal. Each multiplexer is coupled to a corresponding row of pixels, and outputs sensing/reference voltage to the third transistor. The compensation circuit uses the sensing voltage to detect a threshold voltage of the second transistor, and the display device adjusts the data signal according to the threshold voltage.

Description

display device

This disclosure document relates to a display device, and in particular to a display device that adjusts data signals through an external compensation circuit.

Light emitting diode (LED) display devices have the advantages of high brightness, low power consumption, and weather resistance. They can be used not only indoors but also often in outdoor environments. However, due to process factors and the aging of internal components of the display device, the critical voltage of each thin film transistor will be different, which will lead to uneven brightness in the display screen. Therefore, a compensation circuit that can adjust the data signal according to the critical voltage of the thin film transistor is needed in the LED display device.

This disclosure document proposes a display device that includes multiple pixel circuits, multiplexers, and compensation circuits. Each pixel circuit includes a light-emitting element, a first transistor, a capacitor, a second transistor, a third transistor and a display control circuit. The first transistor is used for receiving data signals and is selectively turned on according to the first scanning signal. The capacitor is coupled between the first transistor and the light-emitting element. The first terminal of the second transistor is coupled to the light-emitting element, and the control terminal of the second transistor receives the data signal through the first transistor. The third transistor is coupled to the light-emitting element and the capacitor, and is selectively turned on according to the second scan signal. The display control circuit selectively conducts the second terminal of the second transistor and the first operating power supply to each other according to the display control signal. Each multiplexer is coupled to a corresponding row of the plurality of pixel circuits, and is used to output the detection voltage and the reference voltage to the third transistor in the compensation mode and the normal mode respectively. The compensation circuit is coupled to a plurality of multiplexers and is configured to detect the critical voltage of the second transistor of each pixel circuit by detecting the voltage, wherein the display device adjusts the data signal transmitted to each pixel circuit according to the critical voltage. .

This disclosure document further proposes a display device including a plurality of pixel circuits and a compensation circuit. Each pixel circuit includes a light-emitting element, a seventh transistor, a capacitor, an eighth transistor, a ninth transistor, a tenth transistor and a display control circuit. The seventh transistor is used to receive data signals and is selectively turned on according to the first scan signal. The first terminal of the capacitor is coupled to the seventh transistor. The first terminal of the eighth transistor is coupled to the second terminal of the capacitor, and the control terminal of the eighth transistor is coupled to the seventh transistor and the first terminal of the capacitor to receive the data signal through the seventh transistor. The ninth transistor is coupled to the second terminal of the capacitor and is controlled by the second scan signal to deliver the reference voltage in the normal mode. The tenth transistor is coupled to the second terminal of the eighth transistor and is selectively turned on according to the first scan signal. The display control circuit is used to selectively connect the first terminal of the eighth transistor and the light-emitting element to each other according to the first display control signal, and to selectively connect the second terminal of the eighth transistor to the light-emitting element according to the second display control signal. One working power supply is connected to each other. The compensation circuit is used to provide a detection voltage to the second terminal of the eighth transistor in the compensation mode to detect the critical voltage of the eighth transistor of each pixel circuit, and adjust the transmission to each pixel circuit according to the critical voltage. data signal.

By using the display device of this disclosure document, the data signal can be adjusted according to the variation of the threshold voltage of the transistor, thereby overcoming the problem of uneven screen brightness caused by the variation of the threshold voltage of the transistor.

In this disclosure document, when a component is referred to as "connected" or "coupled," it may mean "electrically connected" or "electrically coupled." "Connection" or "coupling" can also be used to indicate the coordinated operation or interaction between two or more elements. In addition, although terms such as “first”, “second”, etc. are used in this disclosure document to describe different components, these terms are only used to distinguish components or operations described by the same technical terms. Unless the context clearly indicates otherwise, such terms do not specifically refer to or imply a sequence or sequence, nor are they intended to limit this disclosure document.

The embodiments of this disclosure document will be described below with reference to relevant drawings. In the drawings, the same reference numbers represent the same or similar elements or process flows.

Figure 1 is a simplified functional block diagram of a display device 1 according to some embodiments. In some embodiments, the display device 1 includes a plurality of pixel circuits 10_11~10_MN, a plurality of multiplexers 12_1~12_N, a compensation circuit 14, a scan driving circuit 16, a display driving circuit 17 and a timing control circuit 18. The pixel circuits 10_11~10_MN are arranged in an array of M columns and N rows. Each multiplexer 12_1 ~ 12_N is coupled to a corresponding row of the pixel circuits 10_11 ~ 10_MN, and the multiplexers 12_1 ~ 12_N are coupled to the compensation circuit 14 . For example, the pixel circuits 10_11~10_M1 are coupled in parallel to the multiplexer 12_1 and coupled to the compensation circuit 14 through the multiplexer 12_1. The connection relationships of the remaining pixel circuits 10_12~10_MN, multiplexers 12_2~12_N and the compensation circuit 14 are similar to the connection relationships of the aforementioned pixel circuits 10_11~10_M1, the multiplexer 12_1 and the compensation circuit 14. For the sake of simplicity, in This will not be repeated.

The scan driver circuit 16 is coupled to the M columns of the pixel circuits 10_11 ~ 10_MN through the scan lines SL[1]~SL[M], and the display driver circuit 17 is coupled to the M columns through the data lines DL[1]~DL[N]. N rows in pixel circuits 10_11~10_MN. Among them, M and N are integers greater than or equal to 1. The timing control circuit 18 is coupled to the compensation circuit 14 , the scan driving circuit 16 and the display driving circuit 17 .

In some embodiments, the timing control circuit 18 is used to provide video input (such as an image signal generated by a graphics processor or a central processing unit) to the display driving circuit 17 in the normal mode, and is used to control the scan driving circuit 16 and the display. The output timing of the driving circuit 17 is used to control the brightness of the pixel circuits 10_11~10_MN to display the image. In the normal mode, the multiplexers 12_1~12_N are used to provide the reference voltage Vref to the pixel circuits 10_11~10_MN, and electrically isolate the compensation circuit 14 from the pixel circuits 10_11~10_MN.

In some embodiments, the timing control circuit 18 is used to control the output timing of the compensation circuit 14, the scan driving circuit 16 and the display driving circuit 17 in the compensation mode, so as to control the compensation circuit 14 to detect the electrical characteristics of the pixel circuits 10_11~10_MN. Variation (such as variation in the critical voltage of a transistor), in which the timing control circuit 18 can compensate the brightness of the pixel circuits 10_11~10_MN in the normal mode based on the detected variation in electrical characteristics. The detailed compensation method will be described in subsequent paragraphs. In the compensation mode, the multiplexers 12_1 ~ 12_N are used to conduct the compensation circuit 14 and the pixel circuits 10_11 ~ 10_MN to each other, and stop providing the reference voltage Vref to the pixel circuits 10_11 ~ 10_MN.

The pixel circuits 10_11~10_MN have similar components, connection relationships, and operation methods to each other, and the multiplexers 12_1~12_N also have similar components, connection relationships, and operation methods to each other. For the sake of simplicity, the following is for the pixel circuits 10_11 and Multiplexer 12_1 is explained.

Figure 2 is a schematic circuit diagram of the pixel circuit 10_11 according to some embodiments. In some embodiments, the pixel circuit 10_11 includes a light-emitting element EL1, a first transistor T1, a capacitor C1, a second transistor T2, a third transistor T3, and a display control circuit DC1. The first transistor T1, the second transistor T2 and the third transistor T3 each include a first terminal, a second terminal and a control terminal. The light emitting element EL1 includes a first end and a second end.

The first end of the first transistor T1 is coupled to the data line DL[1] to receive the data signal Data from the data line DL[1]. The control end is used to receive the first scan signal Scan1 to select according to the first scan signal Scan1. Sexual conduction. The capacitor C1 is coupled between the second terminal of the first transistor T1 and the first terminal of the light-emitting element EL1. The first terminal of the second transistor T2 is coupled to the first terminal of the light emitting element EL1, and the control terminal is used to receive the data signal Data through the first transistor T1. The first terminal of the third transistor T3 is coupled to the first terminal of the light-emitting element EL1, and the control terminal is used to receive the second scan signal Scan2 and be selectively turned on according to the second scan signal Scan2. The display control circuit DC1 is used to selectively conduct the second end of the second transistor T2 and the first operating power supply V1 to each other according to the display control signal EM. The second end of the light-emitting element EL1 is coupled to the second working power supply V2, wherein the voltage level of the first working power supply V1 is lower than the voltage level of the second working power supply V2.

In some embodiments, display control circuit DC1 includes a fourth transistor T4. The fourth transistor T4 includes a first terminal, a second terminal and a control terminal. The first terminal of the fourth transistor T4 is coupled to the second terminal of the second transistor T2, and the second terminal is coupled to the first operating power supply V1. The control terminal is used to receive the display control signal EM and to adjust the display control signal EM according to the display control signal EM. Selective conduction.

In some embodiments, the light-emitting element EL1 is implemented as a light-emitting diode (LED), such as an organic light-emitting diode (AMOLED).

In some embodiments, each of the scan lines SL[1]~SL[M] includes a plurality of traces. For example, the scan line SL[1] includes a line for transmitting the first scan signal Scan1, the second scan signal Scan2 and the display Three traces of control signal EM.

Referring again to FIG. 2 , the multiplexer 12_1 is coupled to the pixel circuit 10_11 for outputting the reference voltage Vref and the detection voltage Vsen to the second end of the third transistor T3 in the normal mode and the compensation mode respectively. In some embodiments, the detection voltage Vsen is greater than the voltage level of the second operating power supply V2 to turn off the light emitting element EL1 in the compensation mode. In some embodiments, the multiplexer 12_1 includes a fifth transistor T5 and a sixth transistor T6. The fifth transistor T5 and the sixth transistor T6 each include a first terminal, a second terminal and a control terminal. The first terminal of the fifth transistor T5 is coupled to the second terminal of the third transistor T3, the second terminal is coupled to the compensation circuit 14, and the control terminal is used to receive the first switching signal SW1. In the compensation mode, the fifth transistor T5 is used to output the detection voltage Vsen to the third transistor T3 according to the first switch signal SW1. The first terminal of the sixth transistor T6 is coupled to the second terminal of the third transistor T3. The second terminal is used to receive the reference voltage Vref, and the control terminal is used to receive the second switching signal SW2. In the normal mode, the sixth transistor T6 is used to output the reference voltage Vref to the third transistor T3 according to the second switch signal SW2.

In some embodiments, the first transistor T1 , the second transistor T2 , the third transistor T3 , the fourth transistor T4 , the fifth transistor T5 and the sixth transistor T6 are P-type. Transistors are implemented.

Figure 3 is a simplified functional block diagram of the compensation circuit 14 according to some embodiments. The compensation circuit 14 is used to output the detection voltage Vsen to the third transistor T3 in each pixel circuit 10_11~10_MN through the multiplexers 12_1~12_N in the compensation mode, so as to detect each pixel circuit 10_11~10_MN. The threshold voltage Vth of the second transistor T2 is calculated, and the adjustment amount of the data signal Data corresponding to each pixel circuit 10_11~10_MN is calculated based on these threshold voltages Vth. The timing control circuit 18 can adjust the data signal Data transmitted to each pixel circuit 10_11~10_MN in the normal mode according to the adjustment amount of the data signal Data, so as to improve the brightness uniformity of the display device 1.

In some embodiments, the compensation circuit 14 includes a voltage generator 140, a current detector 143, and a logic calculation circuit 144. The voltage generator 140 is used to generate the detection voltage Vsen and transmit the detection voltage Vsen to the multiplexers 12_1˜12_N. In some embodiments, the voltage generator 140 also includes a switch array 141 and a reference voltage source 142. The switch array 141 includes a plurality of channels, and these channels are respectively coupled to a plurality of multiplexers 12_1˜12_N. In some embodiments, the switch array 141 is used to sequentially couple the multiplexers 12_1 to 12_N to the reference voltage source 142 and the current detector 143 in the compensation mode. The reference voltage source 142 is coupled to the switch array 141 for generating the detection voltage Vsen, and transmits the detection voltage Vsen to the multiplexers 12_1~12_N through the switch array 141.

The current detector 143 is coupled to the switch array 141 and is used to detect the magnitude of the detection current generated by each second transistor T2 due to the input detection voltage Vsen through the switch array 141 during the compensation phase.

The logic calculation circuit 144 is used to calculate the threshold voltage Vth of each second transistor T2 according to the detection current of each second transistor T2. In some embodiments, the logic calculation circuit 144 also includes a calculation unit 145 and a storage unit 146. The calculation unit 145 is used to calculate the threshold voltage Vth of each second transistor T2 based on the detection current. In some embodiments, the storage unit 146 may store a lookup table that records the corresponding relationship between the threshold voltage Vth and the adjustment amount of the data signal Data, and the calculation unit 145 may access the lookup table to determine each pixel. The calculation unit 145 can then transmit the adjustment amounts of the data signal Data corresponding to the circuits 10_11 to 10_MN to the timing control circuit 18, so that the timing control circuit 18 adjusts the adjustment amounts and transmits them to each pixel in the normal mode. Data signal Data of circuits 10_11~10_MN. In some embodiments, adjusting the data signal Data refers to increasing the level of the corresponding data signal Data when the critical voltage Vth of the second transistor T2 is higher than a threshold, and when the critical voltage Vth of the second transistor T2 is lower than the threshold. When lowering the level of the corresponding data signal Data.

In some embodiments, the storage unit 146 is a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), or other components with similar functions.

In operation, the display device 1 can enter the compensation mode and the normal mode in each frame; it can enter the compensation mode only when it is turned on and then stay in the normal mode; or it can enter the compensation mode every time it stays in the normal mode for a fixed time. The display device 1 can provide a display image according to the video input in the normal mode, and adjust the data voltage Data provided to each of the pixel circuits 10_11~10_MN in the normal mode according to the adjustment amount of the data signal Data calculated in the compensation mode.

Figure 4A is a timing diagram of signals received by the pixel circuit 10_11 in the normal mode according to some embodiments. In the period P1, the pixel circuit 10_11 is in the stage of inputting the data signal Data. At this time, the first scan signal Scan1, the second scan signal Scan2 and the second switch signal SW2 will be at the enable level (for example, low level), and The first switch signal SW1 and the display control signal EM will be at a disable level (for example, a high level). Referring to Figures 1 and 2, at this time, the second transistor T2 and the fifth transistor T5 will be turned off, and the first transistor T1, the third transistor T3, the fourth transistor T4 and the sixth transistor T6 will be turned on, so the pixel circuit 10_11 will not be connected to the compensation circuit 14, but will store the input data signal Data. In some embodiments, the detection voltage Vsen may be greater than or equal to the voltage level of the second operating power supply V2 to prevent the light-emitting element EL1 from emitting false light.

During the period P2, the first scan signal Scan1, the second scan signal Scan2 and the second switch signal SW2 are switched to the disable level, the first switch signal SW1 is maintained at the disable level, and the display control signal EM is switched to the disable level. Switch alternately between enabled and disabled levels. At this time, the first transistor T1 and the third transistor T3 are turned off. On the other hand, the second transistor T2 will be turned on, and the fourth transistor T4 will be switched between the on state and the off state according to the display control signal EM. In other words, during the period P2, the light-emitting element EL1 emits light in a pulse width modulation manner according to the display control signal EM. At this time, the second transistor T2 will provide a driving current to the light-emitting element EL1 so that the light-emitting element EL1 generates corresponding brightness. The magnitude of the driving current can be expressed by the following "Formula 1". "Formula 1" Among them, "Vdata" is the voltage level of the data signal Data, and "Id" is the driving current.

According to "Formula 1", it can be known that the driving current Id will not be affected by the critical voltage Vth of the second transistor T2. Therefore, the driving current Id will not change due to the process variation of different second transistors T2, thereby maintaining the brightness. of stability.

In some embodiments, the aforementioned "maintaining in the normal mode" means that the display device 1 repeatedly performs the operations in the periods P1 to P2.

Figure 4B is a timing diagram of signals received by the pixel circuit 10_11 in the compensation mode according to some embodiments. During the period P3, the first scan signal Scan1, the second scan signal Scan2, the display control signal EM and the first switch signal SW1 will be at the enable level, and the second switch signal SW2 will be at the disable level. At this time, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 will be turned on, and the sixth transistor T6 will be turned off. In other words, during the period P3, the compensation circuit 14 will provide the detection voltage Vsen to the first terminal of the second transistor T2, and the data signal Data with a preset level will be transmitted to the second transistor T2. The control terminal is used to cause the second transistor T2 to generate a detection current.

Figure 5 is a simplified functional block diagram of the display device 5 according to some embodiments. The display device 5 is similar to the display device 1 in FIG. 1 , except that the display device 5 does not need to be provided with multiplexers 12_1 to 12_N.

In some embodiments, the display device 5 in Figure 5 includes a plurality of pixel circuits 50_11~50_MN, a compensation circuit 54, a scan driving circuit 56, a display driving circuit 57 and a timing control circuit 58. The scan driving circuit 56, the display driving circuit 57 and the timing control circuit 58 in Figure 5 are respectively similar to the scanning driving circuit 16, the display driving circuit 17 and the timing control circuit 18 in Figure 1. For the sake of simplicity, they will not be repeated here. its operations and connections.

In FIG. 5 , the pixel circuits 50_11 ~ 50_MN are arranged into an array of M columns and N rows, and the compensation circuit 54 is coupled to a corresponding row of the pixel circuits 50_11 ~ 50_MN. Among them, M and N are integers greater than or equal to 1. For example, the pixel circuits 50_11~50_M1 are coupled to the compensation circuit 54 in parallel. The connection relationship between the remaining pixel circuits 50_12~50_MN and the compensation circuit 54 is similar to the connection relationship between the aforementioned pixel circuits 50_11~50_M1 and the compensation circuit 54. For the sake of simplicity, the details will not be repeated here.

The pixel circuits 50_11~50_MN have similar components, connection relationships, and operating methods. For the sake of simplicity, the following description is for the pixel circuit 50_11.

Figure 6 is a circuit schematic diagram of the pixel circuit 50_11 according to some embodiments. In some embodiments, the pixel circuit 50_11 includes a light-emitting element EL2, a seventh transistor T7, a capacitor C2, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and a display control circuit DC2. The seventh transistor T7 , the eighth transistor T8 , the ninth transistor T9 and the tenth transistor T10 each include a first terminal, a second terminal and a control terminal. The light emitting element EL2 and the capacitor C2 each include a first terminal and a second terminal.

The first terminal of the seventh transistor T7 is used to receive the data signal Data, and the control terminal is used to receive the first scan signal Scan1 so as to be selectively turned on according to the first scan signal Scan1. The first terminal of the capacitor C2 is coupled to the second terminal of the seventh transistor T7, and the second terminal is coupled to the first terminal of the eighth transistor T8. The first terminal of the eighth transistor T8 is coupled to the second terminal of the capacitor C2, and the control terminal is used to receive the data signal Data through the seventh transistor T7. The ninth transistor T9 is coupled to the first terminal of the eighth transistor T8, and the control terminal is used to receive the second scan signal Scan2, so as to be selectively turned on according to the second scan signal Scan2. The tenth transistor T10 is coupled to the second terminal of the eighth transistor T8, and the control terminal is used to receive the first scan signal Scan1, so as to be selectively turned on according to the first scan signal Scan1. The display control circuit DC2 is used to selectively conduct the first terminal of the eighth transistor T8 and the first terminal of the light-emitting element EL2 to each other according to the first display control signal EM1, and is used to selectively connect the eighth transistor T8 to the first terminal of the light-emitting element EL2 according to the second display control signal EM2. The second terminal of the transistor T8 is electrically connected to the first operating power source V1.

In some embodiments, the display control circuit DC2 includes an eleventh transistor T11 and a twelfth transistor T12. The eleventh transistor T11 and the twelfth transistor T12 each include a first terminal, a second terminal and a control terminal. The first terminal of the eleventh transistor T11 is coupled to the first terminal of the light-emitting element EL2, and the second terminal is coupled to the first terminal of the eighth transistor T8. The control terminal is used to receive the first display control signal EM1. to be selectively turned on according to the first display control signal EM1. The first terminal of the twelfth transistor T12 is coupled to the second terminal of the eighth transistor T8, and the second terminal is coupled to the first operating power supply V1. The control terminal is used to receive the second display control signal EM2 according to The second display control signal EM2 is selectively turned on.

In some embodiments, the light-emitting element EL2 is implemented as a light-emitting diode (LED), and the first end (such as the cathode) of the light-emitting element EL2 is coupled to the second end of the eleventh transistor T11, and with Its second end (eg, the anode) is coupled to the second operating power supply V2.

In some embodiments, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11 and the twelfth transistor T12 are P-type (P- type) transistor to achieve.

The compensation circuit 54 is used to output the detection voltage Vsen to the second terminal of the eighth transistor T8 in the compensation mode, so that the eighth transistor T8 generates a detection current, and then detects the eighth transistor T8 through the detection current. The critical voltage Vth. The compensation circuit 54 is used to detect the threshold voltage Vth of each eighth transistor T8 in the compensation mode, and calculate the adjustment amount of the data signal Data corresponding to each of the pixel circuits 50_11~50_MN. The timing control circuit 58 can adjust the data signal Data provided to each of the pixel circuits 50_11~50_MN in the normal mode according to the adjustment amounts of the data signals Data. The operation details of the compensation circuit 54 are similar to those described in the above three accompanying figures, and for the sake of simplicity, they are not repeated here.

In operation, the display device 5 is similar to the display device 1 in that it can enter the compensation mode and the normal mode in each frame; it can enter the compensation mode only when it is turned on and then remain in the normal mode; or it can remain in the normal mode for a fixed period. time to enter compensation mode. The display device 5 can provide a display image according to the video input in the normal mode, and adjust the data voltage Data provided to each of the pixel circuits 50_11~50_MN in the normal mode according to the adjustment amount of the data signal Data calculated in the compensation mode.

Figure 7A is a timing diagram of signals received by the pixel circuit 50_11 in the normal mode according to some embodiments. In the period P4, the pixel circuit 50_11 is in the stage of inputting the data signal Data. At this time, the first scan signal Scan1 will be at an enable level (for example, a low level), and the second scan signal Scan2 and the first display control signal EM1 And the second display control signal EM2 will be at a disabled level (for example, a high level). Referring to Figure 6, at this time, the ninth transistor T9, the eleventh transistor T11 and the twelfth transistor T12 will be turned off, while the seventh transistor T7, the eighth transistor T8 and the tenth transistor T10 will be turned on. , therefore the pixel circuit 50_11 will store the data signal Data. Since the eleventh transistor T11 and the twelfth transistor T12 are turned off, the light-emitting element EL2 will not emit light at this time.

During the period P5, the second scan signal Scan2 will be switched to the enable level, the first scan signal Scan1 will be maintained at the enable level, and the first display control signal EM1 and the second display control signal EM2 will be maintained at the disable level. accurate position. Referring to Figure 6, at this time, the eleventh transistor T11 and the twelfth transistor T12 will be turned off, while the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 will be turned on. , therefore the first terminal of the eighth transistor T8 receives the reference voltage Vref. Since the eleventh transistor T11 and the twelfth transistor T12 are turned off, the light-emitting element EL2 will not emit light at this time.

During the period P6, the first scan signal Scan1 and the second scan signal Scan2 will be switched to the disable level, and the first display control signal EM1 and the second display control signal EM2 will be between the enable level and the disable level. Switching is alternately, and the first display control signal EM1 and the second display control signal EM2 have the same phase. At this time, the seventh transistor T7 is turned off, the ninth transistor T9 and the tenth transistor T10 are turned off. On the other hand, the eighth transistor T8 will be turned on, and the eleventh transistor T11 and the twelfth transistor T12 will be switched between the on state and the off state simultaneously. In other words, during the period P6, the light-emitting element EL2 emits light in a pulse width modulation manner according to the first display control signal EM and the second display control signal EM2. At this time, the eighth transistor T8 provides a driving current to the light-emitting element EL2 so that the light-emitting element EL2 generates corresponding brightness. The magnitude of the driving current can be expressed by the above-mentioned "Formula 1".

According to "Formula 1", it can be known that the driving current Id will not be affected by the critical voltage Vth of the eighth transistor T8. Therefore, the driving current Id will not change due to the process variation of different eighth transistors T8, thereby maintaining the brightness. of stability.

In some embodiments, the aforementioned "maintaining in the normal mode" means that the display device 5 repeatedly performs operations in periods P4 to P6.

Figure 7B is a timing diagram of signals received by the pixel circuit 50_11 in the compensation mode according to some embodiments. In the period P7, the first scan signal Scan1 will be at the enable level, and the second scan signal Scan2, the first display control signal EM1 and the second display control signal EM2 will be at the disable level. Referring to Figure 6, at this time, the ninth transistor T9, the eleventh transistor T11 and the twelfth transistor T12 will be turned off, while the seventh transistor T7, the eighth transistor T8 and the tenth transistor T10 will be turned on. . In other words, during the period P7, the compensation circuit 54 will provide the detection voltage Vsen to the second terminal of the eighth transistor T8, and the data signal Data with a preset level will be transmitted to the eighth transistor T8. Control terminal.

During the period P8, the second scan signal Scan2 will be switched to the enable level, the first scan signal Scan1 will be maintained at the enable level, and the first display control signal EM1 and the second display control signal EM2 will be maintained at the disable level. accurate position. Referring to Figure 6, at this time, the eleventh transistor T11 and the twelfth transistor T12 will be turned off, while the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 will be turned on. , therefore the first terminal of the eighth transistor T8 receives the reference voltage Vref. At this time, the eighth transistor T8 will generate a compensation current.

The detection voltage Vsen of the display device 5 in Figure 5 does not need to be greater than the second operating voltage V2, which can save power consumption in the compensation mode. The pixel circuits 10_11~10_MN of the display device 1 in Figure 1 use fewer transistors, which can save manufacturing costs and increase the pixels per inch (PPI) of the display device 1.

The display device 1 and the display device 5 proposed in this disclosure document can use external compensation technology to adjust the data signal Data according to the variation of the critical voltage Vth of the transistor, thereby overcoming the picture brightness caused by the variation of the critical voltage Vth of the transistor. uneven problem.

The above are only preferred embodiments of this disclosure document. All equivalent changes and modifications made in accordance with the requirements of this disclosure document shall fall within the scope of this disclosure document.

1:Display device 10_11~10_MN: Pixel circuit 12_1~12_N: Multiplexer 14: Compensation circuit 16:Scan driver circuit 17:Display drive circuit 18: Timing control circuit 140:Voltage generator 141:Switch array 142: Reference voltage source 143:Current detector 144: Logic calculation circuit 145:Computing unit 146:Storage unit 5:Display circuit 50_11~50_MN: Pixel circuit 54: Compensation circuit 56:Scan driver circuit 57:Display drive circuit 58: Timing control circuit C1, C2: capacitor Data: data signal DC1, DC2: display control circuit DL[1]~DL[N]: data line EL1, EL2: light emitting element EM: display control signal EM1: first display control signal EM2: Second display control signal P1~P8: time period Scan1: first scan signal Scan2: The second scan signal SL[1]~SL[M]: scan line SW1: first switch signal SW2: The second switch signal T1~T12: transistor V1: first working power supply V2: Second working power supply Vsen: detection voltage Vref: reference voltage

In order to make the above and other objects, features, advantages and embodiments of the present disclosure more obvious and understandable, the accompanying drawings are described as follows: Figure 1 is a simplified functional block diagram of a display device according to some embodiments; Figure 2 is a circuit schematic diagram of a pixel circuit according to some embodiments; Figure 3 is a functional block diagram of a compensation circuit according to some embodiments; Figure 4A is a timing diagram of signals received by the pixel circuit in normal mode according to some embodiments; Figure 4B is a timing diagram of signals received by the pixel circuit in the compensation mode according to some embodiments; Figure 5 is a simplified functional block diagram of a display device according to some embodiments; Figure 6 is a circuit schematic diagram of a pixel circuit according to some embodiments; Figure 7A is a timing diagram of signals received by the pixel circuit in normal mode according to some embodiments; Figure 7B is a timing diagram of signals received by the pixel circuit in the compensation mode according to some embodiments.

Domestic storage information (please note in order of storage institution, date and number) without Overseas storage information (please note in order of storage country, institution, date, and number) without

5:Display circuit

50_11~50_MN: Pixel circuit

54: Compensation circuit

56:Scan driver circuit

57:Display drive circuit

58: Timing control circuit

DL[1]~DL[N]: data line

SL[1]~SL[M]: scan line

Vsen: detection voltage

Claims (10)

A display device including: Multiple pixel circuits, each of which contains: a light-emitting element; a first transistor for receiving a data signal and controlled by a first scan signal; a capacitor coupled between the first transistor and the light-emitting element; a second transistor, wherein a first terminal of the second transistor is coupled to the light-emitting element, and a control terminal of the second transistor receives the data signal through the first transistor; a third transistor coupled to the light-emitting element and the capacitor, controlled by a second scan signal; and a display control circuit that selectively conducts the second end of the second transistor and a first operating power supply to each other according to a display control signal; A plurality of multiplexers, each of which is coupled to a corresponding row of the plurality of pixel circuits, is used to respectively output a detection voltage and a reference voltage to the third voltage in a compensation mode and a normal mode. transistors; and a compensation circuit, coupled to the plurality of multiplexers, for detecting a critical voltage of the second transistor of each pixel circuit through the detection voltage, wherein the display device adjusts the transmission according to the critical voltage This data signal to each pixel circuit. The display device according to claim 1, wherein the light-emitting element is a light-emitting diode. The display device of claim 1, wherein the display control circuit includes a fourth transistor, coupled to the second transistor, and selectively turned on according to the display control signal. The display device as claimed in claim 1, wherein each multiplexer includes: a fifth transistor, coupled to the third transistor corresponding to a row in the plurality of pixel circuits, for outputting the detection voltage to the third transistor according to a first switching signal in the compensation mode ;as well as A sixth transistor, coupled to the third transistor of a corresponding row in the plurality of pixel circuits, is used to output the reference voltage to the third transistor according to a second switch signal in the normal mode. The display device as claimed in claim 1, wherein the compensation circuit includes: A voltage generator, the voltage generator includes: a reference voltage source for generating the detection voltage; and a switch array coupled between the multiplexers and the reference voltage source, the reference voltage source transmits the detection voltage to the multiplexers through the switch array; a current detector coupled to the switch array for detecting the magnitude of a detection current generated by each second transistor through the switch array during the compensation phase; and A logic calculation circuit coupled to the current detector, wherein the logic calculation circuit includes: a calculation unit for calculating the critical voltage of each second transistor based on the magnitude of the detection current of each second transistor; and A storage unit is used for adjusting the data signal transmitted to each pixel circuit according to the threshold voltage of each second transistor. A display device including: Multiple pixel circuits, each of which contains: a light-emitting element; a seventh transistor for receiving a data signal and controlled by a first scan signal; a capacitor, a first terminal of the capacitor coupled to the seventh transistor; An eighth transistor, wherein a first terminal of the eighth transistor is coupled to a second terminal of the capacitor, and a control terminal of the eighth transistor is coupled to the seventh transistor and the capacitor. The first end receives the data signal through the seventh transistor; a ninth transistor coupled to the second terminal of the capacitor and controlled by a second scan signal to deliver a reference voltage in a normal mode; a tenth transistor coupled to a second terminal of the eighth transistor and selectively turned on according to the first scan signal; and A display control circuit for selectively connecting the first end of the eighth transistor and the light-emitting element to each other according to a first display control signal, and for selectively connecting the eighth transistor according to a second display control signal. The second end of the transistor is electrically connected to a first operating power supply; and A compensation circuit for providing a detection voltage to the second terminal of the eighth transistor in a compensation mode to detect a critical voltage of the eighth transistor of each pixel circuit, wherein the display device The data signal delivered to each pixel circuit is adjusted based on the threshold voltage. The display device of claim 6, wherein the light-emitting element is a light-emitting diode. The display device as claimed in claim 6, wherein the display control circuit includes: An eleventh transistor is coupled between the light-emitting element and the first end of the eighth transistor, and is selectively turned on according to the first display control signal; and A twelfth transistor is coupled to the second terminal of the eighth transistor and is selectively turned on according to the second display control signal. The display device as claimed in claim 6, wherein the compensation circuit includes: A voltage generator, the voltage generator includes: a reference voltage source for generating the detection voltage; and a switch array coupled between the multiplexers and the reference voltage source, the reference voltage source transmits the detection voltage to the multiplexers through the switch array; a current detector coupled to the switch array for detecting the magnitude of a detection current generated by each second transistor through the switch array during the compensation phase; and A logic calculation circuit coupled to the current detector, wherein the logic calculation circuit includes: a calculation unit for calculating the critical voltage of each second transistor based on the magnitude of the detection current of each second transistor; and A storage unit is used for adjusting the data signal transmitted to each pixel circuit according to the threshold voltage of each second transistor. The display device as claimed in claim 6, wherein the compensation mode includes: A detection phase, in which the first scanning signal is at a disabling level, and the second scanning signal, the first display control signal and the second display control signal are at a disabling level; as well as A compensation phase is located after the detection phase. In the compensation phase, the first scan signal and the second scan signal are at the enable level, and the first display control signal and the second display control signal are at The level of disablement.

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