TW202341137A - memory device - Google Patents

Abstract

According to one embodiment, a memory device includes: a first memory cell; a second memory cell; a first circuit configured to supply a write current to the first memory cell and the second memory cell; a first wiring coupled to the first circuit; a first electrode configured to electrically couple the first memory cell to the first wiring; and a second electrode configured to electrically couple the second memory cell to the first wiring. A length of the first wiring from the first circuit to the first electrode is smaller than a length of the first wiring from the first circuit to the second electrode. A resistance value of the first electrode is higher than a second resistance value of the second electrode.

Description

memory device

An embodiment of the present invention relates to a memory device.

Memory devices using variable resistance elements as memory elements are known. Magnetic memory devices (MRAM: Magnetoresistive Random Access Memory) using magnetoresistive effect elements as variable resistance elements are known.

The problem to be solved by the present invention is to provide a memory device that can reduce misreading.

The memory device of the embodiment includes: a first memory cell, a second memory cell, a first circuit that supplies write current to the first memory cell and the second memory cell, a first wiring connected to the first circuit, and a first wiring electrically connected to the first memory cell. A first plug for the first memory cell and the first wiring, and a second plug for electrically connecting the second memory cell and the first wiring. The length of the first wiring from the first circuit to the first plug is shorter than the length of the first wiring from the first circuit to the second plug. The resistance value of the first plug is higher than the resistance value of the second plug.

Hereinafter, embodiments will be described with reference to the drawings. In addition, in the following description, the same reference numerals are assigned to components having substantially the same function and configuration. When there is no particular distinction between elements having the same composition, different letters or digits may be appended to the end of the same symbol.

1. First embodiment The memory device of the first embodiment will be described. The memory device of the first embodiment uses, for example, an element that has a magnetoresistance effect through a magnetic tunnel junction (MTJ) (called an MTJ element or a magnetoresistance effect element). )) as a magnetic memory device with a variable resistance element. In this embodiment, as well as the embodiments and modifications described below, the case where the MTJ element is used as the variable resistance element will be described, and the description will be described as the magnetoresistive effect element MTJ.

1.1 Composition 1.1.1 Structure of memory device The structure of the memory device of the first embodiment will be described using FIG. 1 . Figure 1 is a block diagram showing the structure of a memory device. The memory device 1 includes a memory cell array 10, an input/output circuit 11, a control circuit 12, a decoding circuit 13, a column selection circuit 14, a row selection circuit 15, a voltage generation circuit 16, a writing circuit 17, and a readout circuit 18.

The memory cell array 10 is a non-volatile memory. The memory cell array 10 includes a plurality of memory cells MC each corresponding to a row and a column group. Memory cells MC store data non-volatilely. For example, memory cells MC located in the same column are connected to the same word line WL. Memory cells MC located in the same row are connected to the same bit line BL.

The input/output circuit 11 is a circuit for transmitting and receiving data. The input/output circuit 11 receives the control signal CNT, the command CMD, the bit address ADD, and the data (write data) DAT from outside the memory device 1 . The input/output circuit 11 sends the control signal CNT and the command CMD to the control circuit 12 . The input/output circuit 11 sends the bit address ADD to the decoding circuit 13 . The input/output circuit 11 sends data (write data) DAT to the write circuit 17 . The input/output circuit 11 receives data (read data) DAT from the read circuit 18 . The input/output circuit 11 sends data (read data) DAT to the outside of the memory device 1 .

The control circuit 12 is a circuit that controls the overall operation of the memory device 1 . The control circuit 12 controls the operations of the input/output circuit 11, the decoding circuit 13, the column selection circuit 14, the row selection circuit 15, the voltage generation circuit 16, the writing circuit 17, and the reading circuit 18 based on the control signal CNT and the command CMD.

The decoding circuit 13 is a circuit that decodes the bit address ADD. The decoding circuit 13 receives the bit address ADD from the input/output circuit 11 . The decoding circuit 13 decodes the bit address ADD. The decoding circuit 13 sends the decoding result of the bit address ADD to the column selection circuit 14 and the row selection circuit 15 . Address ADD includes column address and row address.

The column selection circuit 14 is a circuit that selects the word line WL corresponding to the column of the memory cell array 10 . The column selection circuit 14 is connected to the memory cell array 10 via the word line WL. The column selection circuit 14 receives the decoding result (column address) of the bit address ADD from the decoding circuit 13 . The column selection circuit 14 selects the word line WL corresponding to the column based on the decoding result of the bit address ADD.

The row selection circuit 15 is a circuit that selects the bit line BL corresponding to the row of the memory cell array 10 . The row selection circuit 15 is connected to the memory cell array 10 via the bit line BL. The row selection circuit 15 receives the decoding result (row address) of the bit address ADD from the decoding circuit 13 . The row selection circuit 15 selects the bit line BL corresponding to the row based on the decoding result of the bit address ADD.

The voltage generating circuit 16 is a circuit that uses the power supply voltage applied from the outside of the memory device 1 to generate voltages for various operations of the memory cell array 10 . For example, the voltage generation circuit 16 generates a voltage used in the write operation (hereinafter also described as "write voltage"). The voltage generation circuit 16 supplies the writing voltage to the writing circuit 17 . In addition, the voltage generating circuit 16 generates a voltage used in the readout operation (hereinafter also described as "readout voltage"). The voltage generation circuit 16 supplies the readout voltage to the readout circuit 18 .

The writing circuit 17 is a circuit for writing data into the memory cell MC. The write circuit 17 includes a write driver 19 . The writing circuit 17 receives the writing data DAT from the input/output circuit 11 . The writing circuit 17 applies a writing voltage from the voltage generating circuit 16 . The write driver 19 is a constant current driver circuit, for example. The write driver 19 supplies a current based on the write voltage (current used for the write operation. Hereinafter also referred to as "write current") to the column selection circuit 14 and the row selection circuit 15 . The column selection circuit 14 and the row selection circuit 15 supply write current to the memory cell array 10 via the selected word line WL and bit line BL.

The readout circuit 18 is a circuit for reading data from the memory cell MC. The readout circuit 18 includes a sense amplifier (not shown). The readout circuit 18 applies a readout voltage from the voltage generating circuit 16 . The readout circuit 18 supplies the readout voltage to the row selection circuit 15 . The row selection circuit 15 supplies the read voltage to the memory cell array 10 via the selected bit line BL. The readout circuit 18 self-selects the voltage applied to the bit line BL by the circuit 15. The sense amplifier calculates the data stored in the memory cell MC based on the voltage of the bit line BL. The readout circuit 18 sends the calculated data to the input/output circuit 11 as readout data DAT.

1.1.2 Circuit structure of memory cell array The circuit structure of the memory cell array 10 will be described using FIG. 2 . FIG. 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array 10. In FIG. 2 , memory cells MC, word lines WL, and bit lines BL are classified and displayed by a suffix including an index ""＜＞"".

As shown in Figure 2, the memory cells MC are arranged in a matrix in the memory cell array 10. One of the plurality of word element lines WL (WL<0>, WL<1>,..., WL<M>) and the plurality of word element lines WL are A group of one of the bit lines BL (BL<0>, BL<1>,..., BL<N>) establishes a corresponding relationship (M and N are arbitrary integers). That is, the memory cell MC<i,j> (0≦i≦M, 0≦j≦N) is connected between the word line WL<i> and the bit line BL<j>. The memory cell MC<i,j> includes a switching element SEL<i,j> and a magnetoresistive effect element MTJ<i,j> connected in series.

The switching element SEL has a function as a selector that controls the supply of current to the magnetoresistive effect element MTJ when writing and reading data to the corresponding magnetoresistive effect element MTJ.

The switching element SEL of this embodiment will be described as having two terminals. When the voltage applied between the two terminals does not reach a certain first threshold value, the switching element SEL is in a high resistance state, such as an electrically non-conducting state (off state). When the voltage applied between the two terminals rises and is equal to or higher than the first threshold value, the switching element SEL enters a low resistance state, for example, an electrically conductive state (on state). When the voltage applied between the two terminals of the switching element SEL in the low-resistance state decreases and becomes less than the second threshold value, the switching element SEL enters the high-resistance state. The switching element SEL also has the same function as switching between a high resistance state and a low resistance state based on the magnitude of the voltage applied in the first direction in the second direction opposite to the first direction. That is, the switching element SEL is a bidirectional switching element. By turning on or off the switching element SEL, the supply of current to the TJ element MTJ connected to the switching element SEL can be controlled, that is, the selection or non-selection of the MTJ element MTJ.

In this embodiment, a switching element having the following characteristics can be used: the resistance value drops sharply at a certain voltage, and accordingly, the applied voltage drops sharply and the current increases (snapback).

Alternatively, for example, a material containing silicon (Si), oxygen (O), arsenic (As), phosphorus (P), indium (Sb), sulfur (S), selenium (Se), and tellurium (Te) may be used. A composition of specific elements (such as silicon oxide (SiOx) containing the above-mentioned specific elements) essentially forms a switching element.

In addition, the inclusion of the description "substantially" (for example, substantially formed) and the same description means that the material (composition) that is substantially formed is allowed to contain unintentional impurities.

The magnetoresistive effect element MTJ can be switched between a low resistance state and a high resistance state by controlling the current supplied by the switching element SEL. The magnetoresistive effect element MTJ functions as a memory element that can write data based on changes in the resistance state and can store and read the written data in a non-volatile manner.

1.1.3 Structure of memory cell array An example of the structure of the memory cell array 10 will be described. In addition, in the drawings referred to below, the X direction corresponds to the extending direction of the word line WL, the Y direction corresponds to the extending direction of the bit line BL, and the Z direction corresponds to the semiconductor substrate used for the formation of the memory device 1 The vertical direction of the front.

(planar structure) The planar structure of the memory cell array 10 will be described using FIG. 3 . FIG. 3 is a top view showing an example of the planar structure of the memory cell array 10 . FIG. 3 shows the word lines WL between the plurality of memory cells MC and the column selection circuit 14 and the bit lines BL between the plurality of memory cells MC and the row selection circuit 15 in the memory cell array 10 . In addition, in FIG. 3 , word lines WL<5>~WL<M>, bit lines BL<5>~BL<N>, and a plurality of memory cells MC corresponding thereto are omitted.

In addition, the planar structure here means that in the Z direction, the memory cell MC can select the structure of one memory cell MC through the combination of one word line WL and one bit line BL ( 1 layer structure). The following descriptions of planar structures shall also be used with the same meaning.

As shown in FIG. 3 , in the memory cell array 10 , for example, the memory cell MC is arranged above the word line WL. The bit line BL is arranged above the memory cell MC.

Each of the word lines WL is connected to the column selection circuit 14 and a plurality of memory cells MC arranged in the X direction. The column selection circuit 14 supplies a write current to the memory cell MC via the word line WL. Hereinafter, the regions including the plurality of memory cells MC connected to each of the word lines WL<0> to WL<4> will be described as regions R0w to R4w respectively. Region R0w includes memory cells MC<0,0>～MC<0,N>. Region R1w includes memory cells MC<1,0>～MC<1,N>. Region R2w includes memory cells MC<2,0>～MC<2,N>. Region R3w includes memory cells MC<3,0>～MC<3,N>. Region R4w includes memory cells MC<4,0>～MC<4,N>.

The areas R0w to R4w are arranged on the self-selecting circuit 15 side in the order of area R4w, area R3w, area R2w, area R1w, and area R0w. The length of the bit line BL between the memory cell MC and the row selection circuit 15 is the closer the memory cell MC is to the area (for example, the area R4w) of the row selection circuit 15 (hereinafter also described as "the cell close to the row selection circuit 15"). ") is shorter. In other words, the length of the bit line BL between the memory cell MC and the row selection circuit 15 is the farther the memory cell MC is from the area (for example, the area R0w) of the row selection circuit 15 (hereinafter also described as "far from the row selection circuit 15 "cell") is longer. Therefore, the resistance value of the bit line BL between the memory cell MC and the row selection circuit 15 is lower as the cell is closer to the row selection circuit 15 .

Each of the bit lines BL is connected to the row selection circuit 15 and a plurality of memory cells MC arranged in the Y direction. The row selection circuit 15 supplies a write current to the memory cell MC via the bit line BL. Hereinafter, the regions including the plurality of memory cells MC connected to each of the bit lines BL<0> to BL<4> will be described as regions R0b to R4b respectively. Region R0b includes memory cells MC<0,0>～MC<M,0>. Region R1b includes memory cells MC<0,1>～MC<M,1>. Region R2b includes memory cells MC<0,2>～MC<M,2>. Region R3b includes memory cells MC<0,3>～MC<M,3>. Region R4b includes memory cells MC<0,4>～MC<M,4>.

Regions R0b to R4b are arranged in the order of region R0b, region R1b, region R2b, region R3b, and region R4b from the column selection circuit 14 side. The length of the word line WL between the memory cell MC and the column selection circuit 14 is the closer the memory cell MC is to the area (for example, the area R0b) of the column selection circuit 14 (hereinafter described as "the cell close to the column selection circuit 14"). ) is shorter. In other words, the length of the word line WL between the memory cell MC and the column selection circuit 14 is the longer the memory cell MC is in the area far away from the column selection circuit 14 (for example, the area R4b) (hereinafter also described as "the distance away from the column selection circuit 14"). "cell") is longer. Therefore, the resistance value of the word line WL between the memory cell MC and the column selection circuit 14 is lower as the cell is closer to the column selection circuit 14 .

(section structure) The cross-sectional structure of the memory cell array 10 will be described using FIGS. 4 to 6 . Figure 4 is a cross-sectional view along line I-I of Figure 3. Figure 5 is a cross-sectional view along line II-II of Figure 3. FIG. 6 is a perspective view of a part of the memory cell array 10 . In addition, in the examples shown in FIGS. 4 to 6 , the insulating layer is omitted.

As shown in FIGS. 4 to 6 , the memory cell array 10 is disposed above the semiconductor substrate 30 .

A plurality of conductors 32 are provided above the semiconductor substrate 30 with an insulating layer 31 interposed therebetween. The plurality of conductors 32 are made of conductive material and function as word lines WL. The plurality of conductors 32 are arranged in an array in the Y direction, for example, and each extends in the X direction. In addition, the semiconductor substrate 30 and the insulating layer 31 are omitted in FIG. 6 .

A plurality of contact plugs CP1 (hereinafter also referred to as "first electrodes, or upper electrodes") are provided on the upper surface of one conductor 32. The contact plugs CP1 electrically connect the memory cells MC and the conductor 32. They are provided at 1 A plurality of contact plugs CP1 on the upper surface of each conductor 32 are arranged in an array in the X direction, for example.

Contact plug CP1 in region R0b includes conductor 33a. The contact plug CP1 of each of the regions R1b to R4b includes conductors 33a and 33b. The conductors 33a and 33b are made of conductive material. The conductor 33b includes a material with a lower resistivity than the conductor 33a. The conductors 33a and 33b may include, for example, carbon, boron nitride (BN), metal oxide, metal nitride, polycrystalline silicon (poly-Si), tungsten, titanium, aluminum, copper, etc. For example, two materials are selected from these materials, and among the two selected materials, the conductor 33a includes a material with a relatively high resistivity (hereinafter also described as a "high-resistance material"). The conductor 33b contains a material with a relatively low resistivity (hereinafter also referred to as a "low resistance material"). In addition, the conductors 33a and 33b are not limited to these materials as long as the resistivity of the conductor 33a is higher than the resistivity of the conductor 33b.

The high-resistance material used for the conductor 33a and the low-resistance material used for the conductor 33b can be selected as follows, for example. When at least one of copper and aluminum is selected as the low-resistance material, at least one of tungsten, tungsten nitride (WN), titanium, titanium nitride (TiN), carbon, and polycrystalline silicon can be selected as the high-resistance material. In the case where at least one of tungsten, tungsten nitride, titanium, and titanium nitride is selected as the low-resistance material, at least one of carbon and polycrystalline silicon can be selected as the high-resistance material. In the case where carbon is selected as the low-resistance material, polycrystalline silicon can be selected as the high-resistance material.

The diameters of the contact plugs CP1 in the regions R0b to R4b are approximately the same. In addition, the shape of the cross section (XY cross section) of the contact plug CP1 is not limited to a circular shape. For example, the shape of the cross section of the contact plug CP1 may be an ellipse or a rectangle. Regardless of the shape of the cross section of the contact plug CP1, the area (contact area) of the contact plug CP1 in contact with the word line WL in each of the regions R0b to R4b is approximately the same.

The ratio of the conductor 33b included in the contact plug CP1 in each of the regions R1b to R4b is lower as the contact plug CP1 is provided in a region closer to the column selection circuit 14. The height of the conductor 33b included in the contact plug CP1 in each of the regions R1b to R4b is lower as the contact plug CP1 is disposed in a region closer to the column selection circuit 14. Therefore, the resistance value of the contact plug CP1 is higher as the contact plug CP1 is disposed in a region closer to the column selection circuit 14 .

The length of the word line WL from the column selection circuit 14 to the contact plug CP1 disposed in the region R0b is shorter than the length of the word line WL from the column selection circuit 14 to the contact plug CP1 disposed in the region R1b. The length of the word line WL from the column selection circuit 14 to the contact plug CP1 disposed in the region R1b is shorter than the length of the word line WL from the column selection circuit 14 to the contact plug CP1 disposed in the region R2b. Below, the same.

The conductor 33b is provided on the conductor 33a. In addition, the conductor 33a may be provided on the conductor 33b. In addition, the contact plug CP1 of each of the regions R1b to R4b may be composed of three or more conductors with different resistivities.

The conductors 33a and 33b may include two or more materials. For example, in the case where the conductors 33a and 33b each include two materials A and B with different resistance values, the ratio of the material A to the material B contained in the conductor 33a is the same as the ratio of the material A contained in the conductor 33b. The ratio to material B can be different. Thereby, the resistivity of the conductor 33a and the resistivity of the conductor 33b may be different.

An element 34 functioning as the switching element SEL is provided on the upper surface of the contact plug CP1.

An element 35 functioning as a magnetoresistive effect element MTJ is provided on the upper surface of the element 34 . Details of the structure of component 35 will be described later.

A conductor 36 is provided on the upper surface of the element 35 . The conductor 36 is made of a conductive material and functions as a hard mask when processing the component 35 .

A contact plug CP2 (hereinafter also referred to as the "second electrode, or lower electrode") is provided on the upper surface of the conductor 36. The contact plug CP2 electrically connects the memory cell MC and the conductor 38 described later via the conductor 36. Contact Plug CP2 includes an electrical conductor 37a. The electrical conductor 37a is composed of an electrically conductive material.

An electrical conductor 38 is provided on the upper surface of the contact plug CP2. The plurality of conductors 38 are made of conductive material and function as bit lines BL. The plurality of conductors 38 are arranged in an array in the X direction, for example, and each extends in the Y direction. For example, a plurality of contact plugs CP2 arranged in the Y direction are connected to one conductor 38 .

As shown in FIG. 6 , one memory cell MC is provided at each intersection point of the conductor 32 and the conductor 38 .

Furthermore, element 34 and element 35 may be arranged in contact with each other. For example, the element 34 and the element 35 can be electrically connected through a conductor (not shown). Furthermore, although the case where the element 35 and the conductor 36 are provided on the element 34 has been demonstrated using FIGS. 4-6, it is not limited to this. For example, the element 34 can be disposed on the element 35 and the conductor 36 .

With the above configuration, the memory cell array 10 has a structure in which memory cells MC are provided between corresponding word lines WL and bit lines BL.

Using Figures 3 to 6, the case where the memory cell MC can select the structure of one memory cell MC (called a 1-layer structure) by using the combination of one word line WL and one bit line BL is explained. But it is not limited to this. For example, any array structure such as an array structure in which a plurality of structures are stacked in the Z direction can be applied.

In FIG. 6 , a structure in which the diameters of CP1 and CP2 are smaller than the diameter of MC is explained as an example of the structure. However, the structure is not limited to this structure. In the case where the diameters of CP1 and CP2 are substantially the same as the diameter of MC, the same effect can be obtained.

1.1.4 Structure of magnetoresistive effect element The structure of the magnetoresistive effect element MTJ will be explained using Figure 7. FIG. 7 is a cross-sectional view showing an example of the cross-sectional structure of the magnetoresistive effect element MTJ.

As shown in FIG. 7 , the element 35 (magnetoresistive element MTJ) includes: a ferromagnetic body 39 that functions as a reference layer RL (Reference layer), and a non-magnetic body that functions as a tunnel barrier layer TB (Tunnel barrier layer). 40, and the ferromagnetic body 41 that functions as a memory layer SL (Storage layer).

For example, the magnetoresistive effect element MTJ is stacked with a plurality of materials in the order of the ferromagnetic body 39 , the nonmagnetic body 40 , and the ferromagnetic body 41 from the word line WL side to the bit line BL side (along the Z-axis direction). The magnetoresistive effect element MTJ functions, for example, as a perpendicular magnetization type magnetoresistive effect element MTJ in which the magnetization directions of the magnetic bodies constituting the magnetoresistive effect element MTJ are oriented perpendicularly to the film surface.

The ferromagnetic body 39 has ferromagnetic properties and has an easy magnetization axis in the direction perpendicular to the film surface. The ferromagnetic body 39 has a magnetization direction directed toward either the bit line BL side or the word line WL side. The ferromagnetic body 39 contains, for example, cobalt iron boron (CoFeB) or iron boride (FeB). The magnetization direction of the ferromagnetic body 39 is fixed. In the example of FIG. 7 , the direction is opposite to the surface on which the non-magnetic body 40 is disposed. In addition, "the magnetization direction is fixed" means that the magnetization direction does not change due to a current (spin torque) of a magnitude that can reverse the magnetization direction of the ferromagnetic body 41 .

The nonmagnetic body 40 is a nonmagnetic insulating film, including magnesium oxide (MgO), for example. The nonmagnetic body 40 is provided between the ferromagnetic body 39 and the ferromagnetic body 41 . Thereby, the ferromagnetic body 39, the non-magnetic body 40, and the ferromagnetic body 41 form a magnetic tunnel junction.

The ferromagnetic body 41 has ferromagnetic properties and has an easy axis of magnetization in a direction perpendicular to the film surface. The ferromagnetic body 41 has a magnetization direction directed toward either the bit line BL side or the word line WL side. The ferromagnetic body 41 may include, for example, cobalt iron boron (CoFeB) or iron boride (FeB), and have a body-centered cubic (bcc: Body-centered cubic) crystal structure.

In the memory device 1, for example, a write current is directly passed through the magnetoresistive element MTJ configured as above, and the spin torque is injected into the memory layer SL and the reference layer RL by the write current, thereby controlling the magnetization direction of the memory layer SL. and the magnetization direction of the reference layer RL. This writing method is also called spin injection writing method. The magnetoresistive effect element MTJ can obtain either a low resistance state or a high resistance state according to whether the relative relationship between the magnetization directions of the memory layer SL and the reference layer RL is parallel or antiparallel.

If a write current Iw0 of a certain size flows in the magnetoresistive element MTJ in the direction of the arrow A1 in Figure 7, that is, from the memory layer SL toward the reference layer RL, then the memory layer SL and the reference layer RL The relative relationship between magnetization directions is parallel. In this parallel state, the resistance value of the magnetoresistive effect element MTJ is the lowest, and the magnetoresistive effect element MTJ is set to a low resistance state. This low-resistance state is called a "P (Parallel) state" and is defined as a state of data "0", for example.

Furthermore, if a write current Iw1 larger than the write current Iw0 flows in the magnetoresistive element MTJ in the direction of arrow A2 in FIG. 7, that is, in the direction from the reference layer RL toward the memory layer SL, then the memory layer The relative relationship between the magnetization directions of SL and reference layer RL is antiparallel. In the case of this anti-parallel state, the resistance value of the magnetoresistive effect element MTJ is the highest, and the magnetoresistive effect element MTJ is set to a high resistance state. This high-resistance state is called an "AP (Anti-Parallel, anti-parallel) state" and is defined as a state of data "1", for example.

In addition, the method of specifying data "1" and data "0" is not limited to the above example. For example, the P status may be specified as data "1" and the AP status may be specified as data "0".

1.2 Manufacturing method of memory device The manufacturing method of the memory device 1 of the first embodiment will be described using FIGS. 8 to 14 . FIG. 8 is a flow chart showing an example of a method of manufacturing the contact plug CP1 in the memory device 1 . Each of FIGS. 9 to 14 is a cross-sectional view showing an example of a cross-sectional structure in the manufacturing steps of the memory device 1 . Hereinafter, the case where the contact plug CP1 in the regions R0b to R2b in FIG. 4 is formed is taken as an example for description. The contact plugs CP1 in the regions R0b to R2b in FIG. 4 are shown in FIGS. 9 to 14 . In addition, the semiconductor substrate 30, the insulating layer 31, the element 34, the element 35, the conductor 36, the contact plug CP2, and the conductor 38 are omitted in FIGS. 9 to 14 .

As shown in FIG. 8 , the processes S100 to S105 are sequentially performed in the manufacturing steps of the contact plug CP1. Hereinafter, an example of the manufacturing steps of the contact plug CP1 will be described with reference to FIG. 8 .

First, as shown in FIG. 9 , a conductor 33 a is formed that penetrates the insulating layer 42 and has a bottom surface reaching the conductor 32 ( S100 ). More specifically, first, a hole is formed that penetrates the insulating layer 42 and has a bottom surface that reaches the conductor 32 . The hole corresponds to the contact plug CP1. Next, the conductor 33a is formed into a film by burying holes. After that, the conductor 33a on the insulating layer 42 is removed by CMP (Chemical Mechanical Polishing) or the like.

Next, as shown in FIG. 10 , a resist mask 43 for the conductor 33 a in the processing region R2 b is formed on the conductor 33 a and the insulating layer 42 by photolithography or the like ( S101 ). The opening of the resist mask 43 is provided in the region R2b. Therefore, the upper surface of the conductor 33a provided in the region R2b is exposed (not covered by the resist mask 43). The upper surface of the conductor 33a provided in the regions R0b and R1b is covered by the resist mask 43.

Next, as shown in FIG. 11 , the conductor 33a is processed by, for example, RIE (reactive ion etching) (S102). In S102, the upper part of the conductor 33a in the region R2b is removed. The upper surface of the conductor 33a in the region R2b is located below the upper surface of the insulating layer 42. In addition, the conductor 33a can be processed by wet etching. After processing the conductor 33a, the resist mask 43 is peeled off.

Next, as shown in FIG. 12 , a resist mask 44 for processing the conductor 33 a in the region R2 b and the conductor 33 a in the region R1 b is formed on the conductor 33 a and the insulating layer 42 by photolithography or the like. Go up (S103). The openings of the resist mask 44 are provided in the regions R1b and R2b. Therefore, the upper surface of the conductor 33a provided in the regions R1b and R2b is exposed (not covered by the resist mask 44). The upper surface of the conductor 33a provided in the region R0b is covered by the resist mask 44.

Next, as shown in FIG. 13 , for example, the conductor 33a is processed by RIE (S104). In S104, the upper portions of each of the conductor 33a in the region R2b and the conductor 33a in the region R1b are removed. The upper surface of the conductor 33 a in the region R1 b is located below the upper surface of the insulating layer 42 . The upper surface of the conductor 33a in the region R2b is located lower than the upper surface of the conductor 33a in the region R1b. That is, through S102 and S104, the conductor 33a in the region R2b is cut deeper than the conductor 33a in the region R1b. In addition, the conductor 33a can be processed by wet etching. After the conductor 33a is processed, the resist mask 44 is peeled off.

Next, as shown in FIG. 14 , the conductor 33b is formed on the conductor 33a in the region R2b and the conductor 33a in the region R1b (S105). More specifically, the conductor 33b is formed into a film so as to bury the area where the conductor 33a was removed in S102 and S104. After that, the conductor 33b on the insulating layer 42 is removed by CMP or the like.

In addition, generally speaking, since materials with higher resistivity tend to have better affinity for RIE than materials with lower resistivity, the conductor 33a is preferably disposed under the conductor 33b.

In the case where there are k bit lines BL (k is an integer greater than 1), photolithography and RIE for changing the ratio of the conductor 33b are repeated (k-1) times.

Through the manufacturing steps described above, the contact plug CP1 is formed. In addition, the manufacturing steps described above are ultimately just an example and are not limited thereto. For example, other processes can be inserted between each manufacturing step, and some steps can be omitted or integrated. In addition, each manufacturing step can be replaced to the extent possible.

1.3 Effects of this embodiment According to the first embodiment, erroneous readings can be reduced. This effect is explained below.

As mentioned above, the resistance value of the word line WL between the memory cell MC and the column selection circuit 14 is lower as the cell is closer to the column selection circuit 14 . It is assumed that the resistance values of the plurality of contact plugs CP1 connected to the word line WL are the same. In this case, corresponding to the length of the word line WL from the column selection circuit 14 to the contact plug CP1, the wiring path formed by the word line WL from the column selection circuit 14 to the memory cell MC and the contact plug CP1 ( The change in resistance value is also described below as "column selection circuit - inter-cell wiring path"). The time from the start of driving the write driver 19 until the element 34 (switching element SEL) of the memory cell MC is turned on varies depending on the resistance value of the column selection circuit-inter-cell wiring path. Therefore, the length of the time during which the write driver 19 supplies the write current to the memory cell MC (hereinafter also described as "current supply time") varies according to the length of the word line WL.

The current supply time is longer for cells closer to the column selection circuit 14 and shorter for cells farther away from the column selection circuit 14 . In memory cells MC that have a short current supply time, that is, cells that are far away from the column selection circuit 14, writing failure may occur due to insufficient current supply time. On the other hand, in the memory cell MC where the current supply time is long, that is, the cell close to the column selection circuit 14, damage failure of the magnetoresistive element MTJ caused by the current supply time being too long may occur.

Therefore, in this embodiment, the resistance value of the contact plug CP1 is changed corresponding to the length of the word line WL from the column selection circuit 14 to the contact plug CP1. In other words, the resistance value of the contact plug CP1 is different corresponding to the configuration of the column selection circuit 14 and the memory cell MC.

More specifically, the contact plug CP1 of the region R0b includes the conductor 33a. The contact plug CP1 of each of the regions R1b to R4b includes a conductor 33a and a conductor 33 having a lower resistivity than the conductor 33a. The closer the contact plug CP1 is to the column selection circuit 14, the lower the ratio of the conductor 33b included in the contact plug CP1. Thereby, the resistance value of the contact plug CP1 becomes higher as the contact plug CP1 is disposed closer to the region of the column selection circuit 14 . Therefore, in the area close to the column selection circuit 14, compared with the area farther away, the resistance value of the word line WL becomes lower, and the resistance value of the contact plug CP1 becomes higher. On the other hand, in the area far away from the column selection circuit 14, the resistance value of the word line WL becomes higher and the resistance value of the contact plug CP1 becomes lower than in the closer area. In this way, by combining the resistance value of the word line WL and the resistance value of the contact plug CP1, the change in the resistance value of the column selection circuit-to-cell wiring path caused by the length of the word line WL can be suppressed. Therefore, misreading of data can be reduced.

1.4 The first variation The memory device according to the first variation of the first embodiment will be described. In the memory device 1 according to the first modification of the first embodiment, the method of distributing the ratio of the conductors 33b included in the contact plug CP1 is different from that in the first embodiment. In the following description, the description of the same configuration as the first embodiment will be omitted, and the configuration different from the first embodiment will be mainly described.

1.4.1 Structure of memory cell array The structure of the memory cell array 10 is the same as that of the first embodiment.

The cross-sectional structure of the memory cell array 10 will be described using FIG. 15 . Fig. 15 is a cross-sectional view along line I-I of Fig. 3. In addition, the insulating layer is omitted in the example shown in FIG. 15 .

As shown in FIG. 15 , the diameters of the contact plugs CP1 in the regions R0b to R4b are approximately the same. In addition, the cross-sectional shape of the contact plug CP1 is not limited to a circular shape. Regardless of the shape of the cross section of the contact plug CP1, the area of contact between the contact plug CP1 and the word line WL in each of the regions R0b to R4b is approximately the same.

The regions R1b to R4b are divided into a group G0 including two adjacent regions R1b and R2b, and a group G1 including two adjacent regions R3b and R4b. The ratio of the conductors 33b included in the contact plugs CP1 in each of the regions R1b and R2b is the same. The ratio of the conductors 33b included in the contact plugs CP1 in each of the regions R3b and R4b is the same. The contact plug CP1 of each of regions R1b and R2b contains a lower ratio of conductor 33b than the contact plug CP1 of each of regions R3b and R4b. In this way, the ratio of the conductor 33b included in the contact plug CP1 of each of the groups G0 and G1 is lower as the contact plug CP1 of the group closer to the column selection circuit 14 is lower. The height of the conductor 33b included in the contact plug CP1 of each of the groups G0 and G1 is lower as the contact plug CP1 of the group closer to the column selection circuit 14 is lower. Therefore, the resistance value of the contact plug CP1 is higher as the group of contact plugs CP1 is closer to the column selection circuit 14 . In addition, the case where each group includes two adjacent areas has been described using FIG. 15 , but the invention is not limited to this. For example, each group may include more than three adjacent areas. In addition, the number of regions included in the group may be different from each other.

The other parts of the cross-sectional structure of the memory cell array 10 are the same as those in the first embodiment.

1.4.2 Effects of this variation According to this variation, the same effects as those of the first embodiment are achieved.

Furthermore, according to this variation, the ratio of the conductors 33b included in the contact plug CP1 is different for each group. Therefore, the ratio of the conductor 33b included in the contact plug CP1 does not need to be changed for each region R1b to R4b. Thereby, compared to the case where the ratio of the conductors 33b included in the contact plugs CP1 is individually changed, the types of contact plugs CP1 having different ratios of the conductors 33b are reduced. Therefore, the number of repetitions of photolithography and RIE for changing the ratio of the conductor 33b can be reduced. Therefore, the process cost can be reduced.

1.5 Second variation The memory device according to the second variation of the first embodiment will be described. In the memory device 1 of the second modification of the first embodiment, the material of the conductors 33a and 33b included in the contact plug CP1 is different from that of the first embodiment. In the following description, the description of the same configuration as the first embodiment will be omitted, and the configuration different from the first embodiment will be mainly described.

1.5.1 Structure of memory cell array The planar structure and cross-sectional structure of the memory cell array 10 are the same as those in the first embodiment.

In FIG. 4 , the conductors 33a and 33b are, for example, n-type semiconductors or p-type semiconductors. The conductors 33a and 33b include at least one of silicon and germanium, for example. Conductors 33a and 33b contain impurities (dopants). Examples of impurities include boron, phosphorus, arsenic and indium. The impurity concentration of the conductor 33b is higher than that of the conductor 33a. That is, the resistivity of the conductor 33b is lower than that of the conductor 33a. Therefore, the resistance value of the contact plug CP1 is higher as the contact plug CP1 is disposed in a region closer to the column selection circuit 14 .

1.5.2 Manufacturing method of memory device A method of manufacturing the memory device 1 according to the second variation of the first embodiment will be described using FIGS. 16 to 18 . FIG. 16 is a flowchart showing an example of a method of manufacturing the contact plug CP1 in the memory device 1 . 17 and 18 are each a cross-sectional view showing an example of a cross-sectional structure in the manufacturing steps of the memory device 1. In the method of manufacturing the contact plug CP1 in the memory device 1 according to the second modification of the first embodiment, S102 and S104 in FIG. 8 of the first embodiment are replaced with S106 and S107. Furthermore, S105 of FIG. 8 in the first embodiment is eliminated. S100, S101, and S103 are the same as those in the first embodiment. The following description will focus on S106 and S107.

Hereinafter, an example of the manufacturing steps of the contact plug CP1 will be described with reference to FIG. 16 .

In S100, the conductor 33a with a low impurity concentration is formed, and in S101, the resist mask 43 is formed. Thereafter, as shown in FIG. 17 , impurity ions are implanted into the conductor 33 a in the region R2 b ( S106 ). Thereby, the conductor 33b which has a higher impurity concentration than the conductor 33a is formed in the upper part of the conductor 33a of the region R2b. If the concentration of impurities in the conductor 33a in each of the regions R0b to R2b is set to the concentrations D10a to D12a, respectively, the concentrations D10a to D12a will be the same. After the ions are implanted, the resist mask 43 is peeled off.

In S103, a resist mask 44 is formed. Thereafter, as shown in FIG. 18 , impurity ion implantation is performed into each of the conductor 33 a in the region R2 b and the conductor 33 a in the region R1 b ( S107 ). At this time, the accelerating voltage used for ion implantation is lower than the accelerating voltage used for ion implantation in S106. Thereby, the depth of ion implantation into the conductor 33a in the region R1b is shallower than the depth of the ion implantation into the conductor 33a in the region R2b in S106. As a result, the conductor 33b having a higher impurity concentration than the conductor 33a is formed on each of the conductor 33a in the region R2b and the conductor 33a in the region R1b. If the concentration of impurities in the conductor 33b in the region R2b is D12b, the concentration D12b is higher than the concentration D12a. If the concentration of impurities in the conductor 33b in the region R1b is D11b, the concentration D11b is higher than the concentration D11a. In addition, concentration D12b may be the same as concentration D11b, or may be different. After the ions are implanted, the resist mask 44 is stripped.

Through S106 and S107, the closer the contact plug CP1 is provided to the region of the column selection circuit 14, the more the ratio of the conductor 33b included in the contact plug CP1 can be reduced. The closer the contact plug CP1 is disposed to the area of the column selection circuit 14, the lower the height of the conductor 33b included in the contact plug CP1 can be reduced.

1.5.3 Effects of this variation According to this variation, the same effects as those of the first embodiment are achieved. Of course, the first modification of the first embodiment can also be applied to the contact plug CP1 included in the memory device 1 of this modification.

1.6 The third variation The memory device according to the third variation of the first embodiment will be described. In the memory device 1 of the third modification of the first embodiment, the structure of the contact plug CP1 is different from that of the second modification of the first embodiment. In the following description, the description of the same configuration as the second modification of the first embodiment will be omitted, and the description will mainly focus on the configuration that is different from the second modification of the first embodiment.

1.6.1 Structure of memory cell array The planar structure of the memory cell array 10 is the same as that of the second modification of the first embodiment.

The cross-sectional structure of the memory cell array 10 will be described using FIG. 19 . Figure 19 is a cross-sectional view along line I-I of Figure 3. In addition, the insulating layer is omitted in the example shown in FIG. 19 .

As shown in FIG. 19 , the contact plug CP1 in the region R0b includes a conductor 33a. Contact plug CP1 in region R1b includes conductor 33b1. Contact plug CP1 in region R2b includes conductor 33b2. Contact plug CP1 in region R3b includes conductor 33b3. Contact plug CP1 in region R4b includes conductor 33b4. The conductors 33a and 33b1 to 33b4 are made of the same material as the second modification example of the first embodiment. The conductors 33a and 33b1 to 33b4 are, for example, n-type semiconductors or p-type semiconductors. The conductors 33a and 33b1 to 33b4 include at least one of silicon and germanium, for example. Conductors 33a and 33b1 to 33b4 contain impurities (dopants). The impurities are made of the same material as the second modification of the first embodiment.

The diameters of the contact plugs CP1 in the regions R0b to R4b are approximately the same. In addition, the cross-sectional shape of the contact plug CP1 is not limited to a circular shape. Regardless of the shape of the cross section of the contact plug CP1, the area of contact between the contact plug CP1 and the word line WL in each of the regions R0b to R4b is approximately the same.

If the impurity concentrations of the contact plugs CP1 (conductors 33a and 33b1 to 33b4) in the regions R0b to R4b are respectively the concentrations D10a and D11b to D14b, the concentration D10a is lower than the concentration D11b. The concentration D11b is lower than the concentration D12b. The concentration D12b is lower than the concentration D13b. The concentration D13b is lower than the concentration D14b. In this way, the impurity concentration of the contact plug CP1 in each of the regions R0b to R4b is lower as the contact plug CP1 is disposed in a region closer to the column selection circuit 14. For example, the acceleration voltage used for ion implantation is set to the same voltage for the contact plugs CP1 (conductors 33b1 to 33b4) of each of the regions R1b to R4b. The more CP1 is plugged, the more ion injection volume can be reduced. Therefore, the resistance value of the contact plug CP1 is higher as the contact plug CP1 is disposed in a region closer to the column selection circuit 14 .

The other parts of the cross-sectional structure of the memory cell array 10 are the same as the second modification of the first embodiment.

In the case where there are k bit lines BL (k is an integer greater than 1), ion implantation for changing the concentration of impurities is repeated (k-1) times.

1.6.2 Effects of this variation According to this variation, the same effects as those of the first embodiment are achieved.

1.7 The fourth variation The memory device according to the fourth variation of the first embodiment will be described. In the memory device 1 of the fourth modification of the first embodiment, the method of distributing the concentration of impurities in the contact plug CP1 is different from that of the third modification of the first embodiment. In the following description, the description of the same configuration as the third variation of the first embodiment will be omitted, and the description will mainly focus on the configuration that is different from the third variation of the first embodiment.

1.7.1 Structure of memory cell array The planar structure of the memory cell array 10 is the same as that of the third variation of the first embodiment.

The cross-sectional structure of the memory cell array 10 will be described using FIG. 20 . FIG. 20 is a cross-sectional view along line I-I of FIG. 3 . In addition, the insulating layer is omitted in the example shown in FIG. 20 .

As shown in FIG. 20 , the diameters of the contact plugs CP1 in each of the regions R0b to R4b are approximately the same. In addition, the cross-sectional shape of the contact plug CP1 is not limited to a circular shape. Regardless of the shape of the cross section of the contact plug CP1, the area of contact between the contact plug CP1 and the word line WL in each of the regions R0b to R4b is approximately the same.

The regions R1b to R4b are divided into a group G0 including two adjacent regions R1b and R2b, and a group G1 including two adjacent regions R3b and R4b. The impurity concentrations D11b and D12b of the contact plugs CP1 (conductors 33b1 and 33b2) of each of the regions R1b and R2b are the same. The impurity concentrations D13b and D14b of the contact plugs CP1 (conductors 33b3 and 33b4) of each of the regions R3b and R4b are the same. Concentration D10a is lower than concentrations D11b and D12b. Concentrations D11b and D12b are lower than concentrations D13b and D14b. In this way, the impurity concentration of the contact plug CP1 in the groups G0 and G1 is lower as the contact plug CP1 of the group closer to the column selection circuit 14 is lower. Therefore, the resistance value of the contact plug CP1 is higher as the group of contact plugs CP1 is closer to the column selection circuit 14 . In addition, the case where each group includes two adjacent areas has been described using FIG. 20 , but the invention is not limited to this. For example, each group may include more than three adjacent areas. In addition, the number of regions included in the group may be different from each other.

The other parts of the cross-sectional structure of the memory cell array 10 are the same as the third variation of the first embodiment.

1.7.2 Effects of this variation According to this variation, the same effects as those of the first embodiment are achieved.

Furthermore, according to this variation, the concentration of impurities in the contact plug CP1 is different for each group. Therefore, the impurity concentration of the contact plug CP1 does not need to be changed for each region R1b to R4b. Accordingly, compared to the case where the impurity concentration of the contact plug CP1 is individually changed, the types of contact plugs CP1 having different impurity concentrations are reduced. Therefore, the number of repetitions of ion implantation for changing the concentration of impurities can be reduced. Therefore, the process cost can be reduced.

2. Second embodiment The memory device of the second embodiment will be described. In the memory device 1 of the second embodiment, the structure of the contact plug CP1 is different from that of the first embodiment. In the following description, the description of the same configuration as the first embodiment will be omitted, and the configuration different from the first embodiment will be mainly described.

2.1 Structure of memory cell array The planar structure of the memory cell array 10 is the same as that of the first embodiment.

The cross-sectional structure of the memory cell array 10 will be described using FIG. 21 . Figure 21 is a cross-sectional view along line I-I of Figure 3. In addition, the insulating layer is omitted in the example shown in FIG. 21 .

As shown in FIG. 21 , the contact plug CP1 in each of the regions R0b to R4b includes a conductor 33a. The conductor 33a is made of the same material as the first embodiment.

If the diameters of the contact plugs CP1 in the regions R0b to R4b are respectively set to diameters dm0 to dm4, the diameter dm0 is smaller than the diameter dm1. The diameter dm1 is smaller than the diameter dm2. The diameter dm2 is smaller than the diameter dm3. The diameter dm3 is smaller than the diameter dm4. In addition, the shape of the cross section (XY cross section) of the contact plug CP1 is not limited to a circular shape. For example, the shape of the cross section of the contact plug CP1 may be an ellipse or a rectangle. Regardless of the shape of the cross section of the contact plug CP1, the area of contact between the contact plug CP1 and the word line WL in each of the regions R0b to R4b is smaller as the contact plug CP1 is disposed closer to the column selection circuit 14. The smaller. Therefore, the resistance value of the contact plug CP1 is higher as the contact plug CP1 is disposed in a region closer to the column selection circuit 14 .

The length of the word line WL from the column selection circuit 14 to the contact plug CP1 disposed in the region R0b is shorter than the length of the word line WL from the column selection circuit 14 to the contact plug CP1 disposed in the region R1b. The length of the word line WL from the column selection circuit 14 to the contact plug CP1 disposed in the region R1b is shorter than the length of the word line WL from the column selection circuit 14 to the contact plug CP1 disposed in the region R2b. Below, the same.

The other parts of the cross-sectional structure of the memory cell array 10 are the same as those in the first embodiment.

2.2 Effects of this embodiment According to the second embodiment, the same effect as that of the first embodiment is achieved.

2.3 Examples of changes A description will be given of a memory device according to a modified example of the second embodiment. In the memory device 1 according to the variation of the second embodiment, the method of distributing the diameter of the contact plug CP1 is different from that in the second embodiment. In the following description, the description of the same configuration as that of the second embodiment will be omitted, and the configuration that is different from the second embodiment will be mainly described.

2.3.1 Structure of memory cell array The planar structure of the memory cell array 10 is the same as that of the second embodiment.

The cross-sectional structure of the memory cell array 10 will be described using FIG. 22 . Figure 22 is a cross-sectional view along line I-I of Figure 3. In addition, the insulating layer is omitted in the example shown in FIG. 22 .

As shown in FIG. 22 , the regions R1b to R4b are divided into a group G0 including two adjacent regions R1b and R2b, and a group G1 including two adjacent regions R3b and R4b. The diameters dm1 and dm2 of the contact plugs CP1 in each of the regions R1b and R2b are the same. The diameters dm3 and dm4 of the contact plugs CP1 in each of the regions R3b and R4b are the same. The diameter dm0 is smaller than the diameters dm1 and dm2. The diameters dm1 and dm2 are smaller than the diameters dm3 and dm4. In this way, the diameter of the contact plug CP1 of each group G0 and G1 becomes smaller as the contact plug CP1 of the group closer to the column selection circuit 14 is smaller. In addition, the cross-sectional shape of the contact plug CP1 is not limited to a circular shape. Regardless of the shape of the cross section of the contact plug CP1, the area of contact between the contact plug CP1 of each group G0 and G1 and the word line WL is the closer to the contact plug CP1 of the group selection circuit 14. The smaller. Therefore, the resistance value of the contact plug CP1 is higher as the group of contact plugs CP1 is closer to the column selection circuit 14 . In addition, the case where each group includes two adjacent areas has been described using FIG. 22 , but the invention is not limited to this. For example, each group may include more than three adjacent areas. In addition, the number of regions included in the group may be different from each other.

The other parts of the cross-sectional structure of the memory cell array 10 are the same as those in the second embodiment.

2.3.2 Effects of this variation According to this variation, the same effects as those of the first embodiment are achieved.

Furthermore, according to this variation, the diameter of the contact plug CP1 is different for each group. The structure in which all contact plugs CP1 have different diameters may complicate the manufacturing process. However, according to this variation, this concern is eliminated.

3. Third embodiment The memory device of the third embodiment will be described. In the memory device 1 of the third embodiment, the arrangement of the word line WL, the contact plugs CP1 and CP2, and the bit line BL is different from that of the first embodiment. In the following description, the description of the same configuration as the first embodiment will be omitted, and the configuration different from the first embodiment will be mainly described.

3.1 Structure of memory cell array An example of the structure of the memory cell array 10 will be described.

(planar structure) The planar structure of the memory cell array 10 will be described using FIG. 23 . FIG. 23 is a top view showing an example of the planar structure of the memory cell array 10. FIG. 23 shows the word lines WL between the plurality of memory cells MC and the column selection circuit 14 in the memory cell array 10, and the bit lines BL between the plurality of memory cells MC and the row selection circuit 15. In addition, in FIG. 23 , word lines WL<5> to WL<M>, bit lines BL<5> to BL<N>, and a plurality of memory cells MC corresponding thereto are omitted.

As shown in FIG. 23 , in the memory cell array 10 , for example, the memory cell MC is arranged above the bit line BL. The word line WL is arranged above the memory cell MC.

(section structure) The cross-sectional structure of the memory cell array 10 will be described using FIGS. 24 to 26 . Fig. 24 is a cross-sectional view along line I-I of Fig. 23. Fig. 25 is a cross-sectional view along line II-II of Fig. 23. FIG. 26 is a perspective view of a portion of the memory cell array 10 . In addition, in the examples shown in FIGS. 24 to 26 , the insulating layer is omitted.

As shown in FIGS. 24 to 26 , a plurality of conductors 38 are provided above the semiconductor substrate 30 with an insulating layer 31 interposed therebetween. The plurality of conductors 38 are arranged in an array in the X direction, for example, and each extends in the Y direction. In addition, the semiconductor substrate 30 and the insulating layer 31 are omitted in FIG. 26 .

A plurality of contact plugs CP2 are provided on the upper surface of one conductor 38 . A plurality of contact plugs CP2 provided on the upper surface of one conductor 38 are arranged in an array in the Y direction, for example. Contact plug CP2 contains electrical conductor 37a.

Component 34 is provided on the upper surface of contact plug CP2.

A contact plug CP1 is provided on the upper surface of the conductor 36 . Contact plug CP1 in region R0b includes conductor 33a. The contact plug CP1 of each of the regions R1b to R4b includes conductors 33a and 33b. The conductors 33a and 33b are made of the same material as in the first embodiment.

The diameters of the contact plugs CP1 in the regions R0b to R4b are approximately the same. In addition, the shape of the cross section (XY cross section) of the contact plug CP1 is not limited to a circular shape. For example, the shape of the cross section of the contact plug CP1 may be an ellipse or a rectangle. Regardless of the shape of the cross section of the contact plug CP1, the area of contact between the contact plug CP1 and the word line WL in each of the regions R0b to R4b is approximately the same.

The ratio of the conductor 33b included in the contact plug CP1 in each of the regions R1b to R4b is lower as the contact plug CP1 is provided in a region closer to the column selection circuit 14. The height of the conductor 33b included in the contact plug CP1 in each of the regions R1b to R4b is lower as the contact plug CP1 is disposed in a region closer to the column selection circuit 14. The conductor 33b is provided on the conductor 33a. In addition, the conductor 33a may be provided on the conductor 33b. In addition, the contact plug CP1 of each of the regions R1b to R4b may be composed of three or more conductors with different resistivities. The conductors 33a and 33b may include two or more materials.

A conductor 32 is provided on the upper surface of the contact plug CP1. The plurality of conductors 32 are arranged in an array in the Y direction, for example, and each extends in the X direction. For example, a plurality of contact plugs CP1 arranged in the X direction are connected to one conductor 32 .

As shown in FIG. 26 , one memory cell MC is provided at each intersection point of the conductor 32 and the conductor 38 .

3.2 Effects of this embodiment According to the third embodiment, the same effect as that of the first embodiment is achieved. Of course, the first to fourth modifications of the first embodiment can be applied to the contact plug CP1 included in the memory device 1 of this embodiment.

4. Fourth embodiment The memory device of the fourth embodiment will be described. In the memory device 1 of the fourth embodiment, the structure of the contact plug CP1 is different from that of the third embodiment. In the following description, the description of the same structure as that of the third embodiment will be omitted, and the structure that is different from the third embodiment will be mainly described.

4.1 Structure of memory cell array The planar structure of the memory cell array 10 is the same as that of the third embodiment.

The cross-sectional structure of the memory cell array 10 will be described using FIG. 27 . Fig. 27 is a cross-sectional view along line I-I of Fig. 23. In addition, the insulating layer is omitted in the example shown in FIG. 27 .

As shown in FIG. 27 , the contact plug CP1 in each of the regions R0b to R4b includes a conductor 33a. The conductor 33a is made of the same material as that of the second embodiment.

The diameter dm0 is smaller than the diameter dm1. The diameter dm1 is smaller than the diameter dm2. The diameter dm2 is smaller than the diameter dm3. The diameter dm3 is smaller than the diameter dm4. In addition, the shape of the cross section (XY cross section) of the contact plug CP1 is not limited to a circular shape. For example, the shape of the cross section of the contact plug CP1 may be an ellipse or a rectangle. Regardless of the shape of the cross section of the contact plug CP1, the area of contact between the contact plug CP1 and the word line WL in each of the regions R0b to R4b is smaller as the contact plug CP1 is disposed closer to the column selection circuit 14. The smaller.

The other parts of the cross-sectional structure of the memory cell array 10 are the same as those in the third embodiment.

4.2 Effects of this embodiment According to the fourth embodiment, the same effect as that of the first embodiment is achieved. Of course, the modification of the second embodiment can also be applied to the contact plug CP1 included in the memory device 1 of this embodiment.

5. Fifth embodiment The memory device according to the fifth embodiment will be described. In the memory device 1 of the fifth embodiment, the structure of the contact plug CP2 is different from that of the first embodiment. In the following description, the description of the same configuration as the first embodiment will be omitted, and the configuration different from the first embodiment will be mainly described.

5.1 Structure of memory cell array The planar structure of the memory cell array 10 is the same as that of the first embodiment.

The cross-sectional structure of the memory cell array 10 will be described using FIGS. 28 and 29 . Figure 28 is a cross-sectional view along line I-I of Figure 3. Figure 29 is a cross-sectional view along line II-II of Figure 3. In addition, in the examples shown in FIGS. 28 and 29 , the insulating layer is omitted.

As shown in FIGS. 28 and 29 , the contact plug CP2 in the region R4w includes the conductor 37a. The contact plug CP2 of each of the regions R0w to R3w includes conductors 37a and 37b. The conductor 37a is made of the same material as the conductor 33a. The conductor 37b is made of the same material as the conductor 33b.

The diameters of the contact plugs CP2 in the regions R0w to R4w are approximately the same. In addition, the shape of the cross section (XY cross section) of the contact plug CP2 is not limited to a circular shape. For example, the shape of the cross section of the contact plug CP2 may be an ellipse or a rectangle. Regardless of the shape of the cross section of the contact plug CP2, the area of contact between the contact plug CP2 and the word line WL in each of the regions R0w to R4w is approximately the same.

The ratio of the conductor 37b included in the contact plug CP2 in each of the regions R0w to R3w is lower as the contact plug CP2 is provided in a region closer to the row selection circuit 15. The height of the conductor 37b included in the contact plug CP2 of each of the regions R0w to R3 is lower as the contact plug CP2 is provided in the region closer to the row selection circuit 15. Therefore, the resistance value of the contact plug CP2 is higher as the contact plug CP2 is disposed in a region closer to the row selection circuit 15 . The conductor 37b is provided on the conductor 37a. In addition, the conductor 37a may be provided on the conductor 37b. In addition, the contact plug CP2 of each of the regions R0w to R3w may be composed of three or more conductors with different resistivities. The conductors 37a and 37b may include two or more materials.

The length of the bit line BL from the self-selecting circuit 15 to the contact plug CP2 disposed in the region R4w is shorter than the length of the bit line BL from the self-selecting circuit 15 to the contact plug CP2 disposed in the region R3w. The length of the bit line BL from the self-selecting circuit 15 to the contact plug CP2 disposed in the region R3w is shorter than the length of the bit line BL from the self-selecting circuit 15 to the contact plug CP2 disposed in the region R2w. Below, the same.

The other parts of the cross-sectional structure of the memory cell array 10 are the same as those in the first embodiment.

5.2 Effects of this embodiment According to the fifth embodiment, the same effect as that of the first embodiment is achieved.

In addition, as described in the first embodiment, the resistance value of the bit line BL between the memory cell MC and the row selection circuit 15 becomes lower as the cell is closer to the row selection circuit 15 . It is assumed that the resistance values of the plurality of contact plugs CP2 connected to the bit line BL are the same. In this case, corresponding to the length of the bit line BL from the self-selecting circuit 15 to the contact plug CP2, the wiring path formed by the bit line BL from the self-selecting circuit 15 to the memory cell MC and the contact plug CP2 (hereinafter also The change in the resistance value described as "row selection circuit - inter-cell wiring path").

According to this embodiment, by combining the resistance value of the bit line BL and the resistance value of the contact plug CP2, the resistance value of the selection circuit-to-cell wiring path caused by the length of the bit line BL can be suppressed. changes.

Of course, the first to fourth modifications of the first embodiment, and the second embodiment and the modifications of the second embodiment can also be applied to the contact plug CP1 included in the memory device 1 of this embodiment. and CP2.

6. Sixth embodiment The memory device of the sixth embodiment will be described. In the memory device 1 of the sixth embodiment, the structure of the contact plug CP2 is different from that of the third embodiment. In the following description, the description of the same structure as that of the third embodiment will be omitted, and the structure that is different from the third embodiment will be mainly described.

6.1 Structure of memory cell array The planar structure of the memory cell array 10 is the same as that of the third embodiment.

The cross-sectional structure of the memory cell array 10 will be described using FIGS. 30 and 31 . Fig. 30 is a cross-sectional view taken along line I-I of Fig. 23. Fig. 31 is a cross-sectional view along line II-II of Fig. 23. In addition, in the examples shown in FIGS. 30 and 31 , the insulating layer is omitted.

As shown in FIGS. 30 and 31 , the contact plug CP2 in the region R4w includes a conductor 37a. The contact plug CP2 of each of the regions R0w to R3w includes conductors 37a and 37b. The conductor 37a is made of the same material as the conductor 33a. The conductor 37b is made of the same material as the conductor 33b.

The diameters of the contact plugs CP2 in the regions R0w to R4w are approximately the same. In addition, the shape of the cross section (XY cross section) of the contact plug CP2 is not limited to a circular shape. For example, the shape of the cross section of the contact plug CP2 may be an ellipse or a rectangle. Regardless of the shape of the cross section of the contact plug CP2, the area of contact between the contact plug CP2 and the word line WL in each of the regions R0w to R4w is approximately the same.

The ratio of the conductor 37b included in the contact plug CP2 in each of the regions R0w to R3w is lower as the contact plug CP2 is provided in a region closer to the row selection circuit 15. The height of the conductor 37b included in the contact plug CP2 of each of the regions R0w to R3w is lower as the contact plug CP2 is disposed closer to the row selection circuit 15. The conductor 37b is provided on the conductor 37a. In addition, the conductor 37a may be provided on the conductor 37b. In addition, the contact plug CP2 of each of the regions R0w to R3w may be composed of three or more conductors with different resistivities. The conductors 37a and 37b may include two or more materials.

The length of the bit line BL from the self-selecting circuit 15 to the contact plug CP2 disposed in the region R4w is shorter than the length of the bit line BL from the self-selecting circuit 15 to the contact plug CP2 disposed in the region R3w. The length of the bit line BL from the self-selecting circuit 15 to the contact plug CP2 disposed in the region R3w is shorter than the length of the bit line BL from the self-selecting circuit 15 to the contact plug CP2 disposed in the region R2w. Below, the same.

The other parts of the cross-sectional structure of the memory cell array 10 are the same as those in the third embodiment.

6.2 Effects of this implementation form According to the sixth embodiment, the same effect as that of the first embodiment is achieved. Moreover, according to this embodiment, the same effect as that of the fifth embodiment is exerted. Of course, the first to fourth modifications of the first embodiment, and the second embodiment and the modifications of the second embodiment can also be applied to the contact plug CP1 included in the memory device 1 of this embodiment. and CP2.

7. Examples of changes, etc. As described above, the memory device of the embodiment includes: a first memory cell (MC), a second memory cell (MC), a first circuit (14) that supplies write current to the first memory cell and the second memory cell, and a connection The first wiring (WL) of the first circuit, the first plug (CP1) electrically connecting the first memory cell and the first wiring, and the second plug (CP1) electrically connecting the second memory cell and the first wiring CP1). The length of the first wiring (WL) from the first circuit to the first plug is shorter than the length of the first wiring (WL) from the first circuit to the second plug. The resistance value of the first plug (CP1) is higher than the resistance value of the second plug (CP1).

In addition, the embodiment is not limited to the above-described form, and various changes are possible.

In addition, the flowchart described in the above-mentioned embodiment can change the order of the processing as much as possible.

In addition, in each of the above embodiments, the structure of one memory cell MC (referred to as a 1-layer structure) can be selected mainly for the memory cell MC through the combination of one word line WL and one bit line BL. Said, but not limited to this. For example, any array structure such as an array structure in which a plurality of structures are stacked in the Z direction can be applied.

Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope of the invention described in the patent application and their equivalents in the same way that they are included in the scope and gist of the invention.

[Reference to related applications] The application for this invention enjoys the priority of applications based on Japanese Patent Application No. 2022-044000 (filing date: March 18, 2022) and U.S. Patent Application No. 17/843084 (filing date: June 17, 2022). right. The present application includes the entire contents of the basic application by reference to the basic application.

1: Memory device 10: Memory cell array 11: Input and output circuit 12:Control circuit 13: Decoding circuit 14: Column selection circuit/1st circuit 15: Row selection circuit 16: Voltage generation circuit 17:Writing circuit 18: Readout circuit 19:Write to drive 30:Semiconductor substrate 31:Insulation layer 32,33a,33b,33b1~33b4,36,37a,37b,38: conductor 34,35:Component 39:Ferromagnetic 40:Nonmagnetic body 41:Ferromagnetic 42:Insulation layer 43,44: Resist mask A1,A2: arrow ADD:address AP: anti-parallel BL, BL＜0＞~BL＜N＞: bit lines CP1,CP2: Contact plug CNT: control signal CMD: command dm0~dm4: diameter D10a~D12a: concentration D11b~D14b: concentration DAT: data (write data) (read data) G0,G1: group I-I,II-II: line MC, MC＜0,0＞~MC＜0,N＞, MC＜1,0＞~MC＜1,N＞, MC＜M,0＞~MC＜M,N＞: memory cell MTJ: Magnetic Tunneling Junction MTJ＜0,0＞: Magnetoresistive effect element P: parallel R0b~R4b,R0w~R4w: area RL: reference layer SEL,SEL＜0,0＞: switching element SL: memory layer TB: tunneling barrier layer WL, WL＜0＞, WL＜1＞~WL＜M＞: character line X,Y,: direction Z: direction/axis

FIG. 1 is a block diagram showing the structure of the memory device according to the first embodiment. FIG. 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array included in the memory device of the first embodiment. FIG. 3 is a top view showing an example of the planar structure of the memory cell array included in the memory device of the first embodiment. FIG. 4 is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device of the first embodiment. FIG. 5 is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device of the first embodiment. FIG. 6 is a perspective view of a part of the memory cell array included in the memory device of the first embodiment. FIG. 7 is a cross-sectional view showing an example of the cross-sectional structure of the magnetoresistive effect element included in the memory device of the first embodiment. FIG. 8 is a flow chart showing an example of the manufacturing method of the memory device according to the first embodiment. FIG. 9 is a cross-sectional view showing an example of the cross-sectional structure in the manufacturing steps of the memory device according to the first embodiment. FIG. 10 is a cross-sectional view showing an example of the cross-sectional structure in the manufacturing steps of the memory device according to the first embodiment. FIG. 11 is a cross-sectional view showing an example of the cross-sectional structure in the manufacturing steps of the memory device according to the first embodiment. FIG. 12 is a cross-sectional view showing an example of the cross-sectional structure in the manufacturing steps of the memory device according to the first embodiment. FIG. 13 is a cross-sectional view showing an example of the cross-sectional structure in the manufacturing steps of the memory device according to the first embodiment. FIG. 14 is a cross-sectional view showing an example of the cross-sectional structure in the manufacturing steps of the memory device according to the first embodiment. FIG. 15 is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device according to the first variation of the first embodiment. FIG. 16 is a flowchart showing an example of a method of manufacturing a memory device according to the second variation of the first embodiment. FIG. 17 is a cross-sectional view showing an example of the cross-sectional structure in the manufacturing steps of the memory device according to the second modification of the first embodiment. FIG. 18 is a cross-sectional view showing an example of the cross-sectional structure in the manufacturing steps of the memory device according to the second modification of the first embodiment. FIG. 19 is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device according to the third variation of the first embodiment. FIG. 20 is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device according to the fourth variation of the first embodiment. FIG. 21 is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device of the second embodiment. 22 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array included in a memory device according to a variation of the second embodiment. FIG. 23 is a plan view showing an example of the planar structure of the memory cell array included in the memory device of the third embodiment. FIG. 24 is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device of the third embodiment. FIG. 25 is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device of the third embodiment. FIG. 26 is a perspective view of a part of the memory cell array included in the memory device of the third embodiment. FIG. 27 is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device of the fourth embodiment. FIG. 28 is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device according to the fifth embodiment. FIG. 29 is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device according to the fifth embodiment. FIG. 30 is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device according to the sixth embodiment. FIG. 31 is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device according to the sixth embodiment.

10: Memory cell array

30:Semiconductor substrate

31:Insulation layer

32,33a,33b,36,37a,38: conductor

34,35:Component

BL<0>~BL<4>: bit lines

CP1,CP2: Contact plug

MC: memory cell

MTJ: Magnetic Tunneling Junction

R0b~R4b: area

SEL: switching element

WL<0>: character line

X,Y: direction

Z: direction/axis

Claims (20)

A memory device containing: 1st memory cell; 2nd memory cell; a first circuit that supplies write current to the aforementioned first memory cell and the aforementioned second memory cell; a first wiring connected to the aforementioned first circuit; a first plug electrically connecting the first memory cell and the first wiring; and a second plug electrically connecting the aforementioned second memory cell and the aforementioned first wiring; and The length of the first wiring from the first circuit to the first plug is shorter than the length of the first wiring from the first circuit to the second plug; The resistance value of the first plug is higher than the resistance value of the second plug. The memory device of claim 1, wherein the first plug includes a first conductor and a second conductor; The aforementioned second plug includes a third conductor and a fourth conductor; The resistivity of the aforementioned second conductor is lower than the resistivity of the aforementioned first conductor; The resistivity of the aforementioned fourth conductor is lower than the resistivity of the aforementioned third conductor; The ratio of the second conductor included in the first plug is lower than the ratio of the fourth conductor included in the second plug. The memory device of claim 2, wherein the first conductor and the third conductor include at least one of tungsten, tungsten nitride, titanium, titanium nitride, carbon, and polycrystalline silicon; and The second conductor and the fourth conductor include at least one of copper and aluminum. The memory device of claim 2, wherein the first conductor and the third conductor include at least one of carbon and polycrystalline silicon; and The second conductor and the fourth conductor include at least one of tungsten, tungsten nitride, titanium, and titanium nitride. The memory device of claim 2, wherein the first conductor and the third conductor include a first semiconductor; and The aforementioned second conductor and the aforementioned fourth conductor include a second semiconductor; The impurity concentration of the first semiconductor is lower than the impurity concentration of the second semiconductor. The memory device of claim 2, wherein the second conductor is disposed on the first conductor; and The fourth conductor is provided on the third conductor. The memory device of claim 1, wherein the first plug includes a first semiconductor; and The aforementioned second plug includes a second semiconductor; and The impurity concentration of the first semiconductor is lower than the impurity concentration of the second semiconductor. The memory device of claim 1, wherein the contact area of the first plug and the first wiring is smaller than the contact area of the second plug and the first wiring. The memory device of claim 8, wherein the cross-sectional shapes of the first plug and the second plug are circular. The memory device of claim 9, wherein the diameter of the first plug is smaller than the diameter of the second plug. The memory device of claim 1, wherein the first memory cell and the second memory cell are arranged above the first wiring. The memory device of claim 1, wherein the first wiring is arranged above the first memory cell and the second memory cell. The memory device of claim 1 further includes: 3rd memory cell; 4th memory cell; a third plug electrically connecting the aforementioned third memory cell and the aforementioned first wiring; and a fourth plug electrically connecting the aforementioned fourth memory cell and the aforementioned first wiring; and The length of the first wiring from the first circuit to the third plug is longer than the length of the first wiring from the first circuit to the first plug, and is longer than the length from the first circuit to the first plug. 2. The length of the first wiring before the plug is short; The length of the first wiring from the first circuit to the fourth plug is longer than the length of the first wiring from the first circuit to the second plug; The resistance value of the aforementioned third plug is equal to the resistance value of the aforementioned first plug; The resistance value of the aforementioned fourth plug is equal to the resistance value of the aforementioned second plug. The memory device of claim 13, wherein the first plug includes a first conductor and a second conductor; The aforementioned second plug includes a third conductor and a fourth conductor; The aforementioned third plug includes a fifth conductor and a sixth conductor; The aforementioned fourth plug includes a seventh conductor and an eighth conductor; The resistivity of the aforementioned second conductor is lower than the resistivity of the aforementioned first conductor; The resistivity of the aforementioned fourth conductor is lower than the resistivity of the aforementioned third conductor; The proportion of the aforementioned second conductor contained in the aforementioned first plug is lower than the proportion of the aforementioned fourth conductor contained in the aforementioned second plug; The resistivity of the aforementioned fifth conductor is equal to the resistivity of the aforementioned first conductor; The resistivity of the aforementioned sixth conductor is equal to the resistivity of the aforementioned second conductor; The resistivity of the aforementioned seventh conductor is equal to the resistivity of the aforementioned third conductor; The resistivity of the aforementioned eighth conductor is equal to the resistivity of the aforementioned fourth conductor; The proportion of the aforementioned sixth conductor contained in the aforementioned third plug is equal to the proportion of the aforementioned second conductor contained in the aforementioned first plug; The ratio of the eighth conductor included in the fourth plug is equal to the ratio of the fourth conductor included in the second plug. The memory device of claim 13, wherein the contact area of the first plug and the first wiring is smaller than the contact area of the second plug and the first wiring; and The area of contact between the aforementioned third plug and the aforementioned first wiring is equal to the area of contact between the aforementioned first plug and the aforementioned first wiring; The area of contact between the fourth plug and the first wiring is equal to the area of contact between the second plug and the first wiring. The memory device of claim 1 further includes: 5th memory cell; 6th memory cell; a second circuit that supplies write current to the aforementioned fifth memory cell and the aforementioned sixth memory cell; a second wiring connected to the aforementioned second circuit; a fifth plug electrically connecting the aforementioned fifth memory cell and the aforementioned second wiring; and a sixth plug electrically connecting the aforementioned sixth memory cell and the aforementioned second wiring; and The length of the second wiring from the aforementioned second circuit to the aforementioned fifth plug is shorter than the length of the aforementioned second wiring from the aforementioned second circuit to the aforementioned sixth plug; The resistance value of the aforementioned fifth plug is higher than the resistance value of the aforementioned sixth plug. The memory device of claim 16, wherein the second wiring is arranged above the fifth memory cell and the sixth memory cell. The memory device of claim 16, wherein the fifth memory cell and the sixth memory cell are arranged above the second wiring. The memory device of claim 1, wherein the first memory cell and the second memory cell include variable resistance elements. The memory device of claim 19, wherein the variable resistance element is a magnetoresistance effect element.