CN116778989A

CN116778989A - Storage device

Info

Publication number: CN116778989A
Application number: CN202310168342.3A
Authority: CN
Inventors: 杉浦邦晃; 五十岚太一
Original assignee: Kioxia Corp
Current assignee: Kioxia Corp
Priority date: 2022-03-18
Filing date: 2023-02-27
Publication date: 2023-09-19

Abstract

Embodiments provide a memory device capable of reducing erroneous reading. The storage device of the embodiment is provided with: a 1 st storage unit; a 2 nd memory cell; a 1 st circuit that supplies write currents to the 1 st memory cell and the 2 nd memory cell; a 1 st wiring connected to the 1 st circuit; a 1 st plug electrically connecting the 1 st memory cell and the 1 st wiring; and a 2 nd plug electrically connecting the 2 nd memory cell and the 1 st wiring. The length of the 1 st wiring from the 1 st circuit to the 1 st plug is shorter than the length of the 1 st wiring from the 1 st circuit to the 2 nd plug. The resistance value of the 1 st plug is higher than that of the 2 nd plug.

Description

Storage device

The present application enjoys priority of Japanese patent application No. 2022-044000 (application day: 2022, 3, 18) and U.S. patent application No. 17/843084 (application day: 2022, 6, 17). The present application includes the entire content of the basic application by referring to the basic application.

Technical Field

Embodiments of the present application relate to a storage device.

Background

A memory device using a variable resistance element as a memory element is known. For example, a magnetic memory device (MRAM: magnetoresistive Random Access Memory, magnetoresistive random access memory) using a magnetoresistive effect element as a variable resistance element is known.

Disclosure of Invention

The invention provides a memory device capable of reducing error reading.

The storage device according to the embodiment includes: a 1 st storage unit; a 2 nd memory cell; a 1 st circuit that supplies write currents to the 1 st memory cell and the 2 nd memory cell; a 1 st wiring connected to the 1 st circuit; a 1 st plug electrically connecting the 1 st memory cell and the 1 st wiring; and a 2 nd plug electrically connecting the 2 nd memory cell and the 1 st wiring. The length of the 1 st wiring from the 1 st circuit to the 1 st plug is shorter than the length of the 1 st wiring from the 1 st circuit to the 2 nd plug. The resistance value of the 1 st plug is higher than that of the 2 nd plug.

Drawings

Fig. 1 is a block diagram showing the structure of a storage device according to embodiment 1.

Fig. 2 is a circuit diagram showing an example of a circuit configuration of a memory cell array included in the memory device according to embodiment 1.

Fig. 3 is a plan view showing an example of a planar structure of a memory cell array included in the memory device according to embodiment 1.

Fig. 4 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array included in the memory device according to embodiment 1.

Fig. 5 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array included in the memory device according to embodiment 1.

Fig. 6 is a perspective view of a part of a memory cell array included in the memory device according to embodiment 1.

Fig. 7 is a cross-sectional view showing an example of a cross-sectional structure of a magnetoresistance effect element included in the memory device according to embodiment 1.

Fig. 8 is a flowchart showing an example of a method for manufacturing the memory device according to embodiment 1.

Fig. 9 is a cross-sectional view showing an example of a cross-sectional structure in the manufacturing process of the memory device according to embodiment 1.

Fig. 10 is a cross-sectional view showing an example of a cross-sectional structure in the manufacturing process of the memory device according to embodiment 1.

Fig. 11 is a cross-sectional view showing an example of a cross-sectional structure in the manufacturing process of the memory device according to embodiment 1.

Fig. 12 is a cross-sectional view showing an example of a cross-sectional structure in the manufacturing process of the memory device according to embodiment 1.

Fig. 13 is a cross-sectional view showing an example of a cross-sectional structure in the manufacturing process of the memory device according to embodiment 1.

Fig. 14 is a cross-sectional view showing an example of a cross-sectional structure in the manufacturing process of the memory device according to embodiment 1.

Fig. 15 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array included in the memory device according to modification 1 of embodiment 1.

Fig. 16 is a flowchart showing an example of a method for manufacturing a memory device according to modification 2 of embodiment 1.

Fig. 17 is a cross-sectional view showing an example of a cross-sectional structure in a manufacturing process of a memory device according to modification 2 of embodiment 1.

Fig. 18 is a cross-sectional view showing an example of a cross-sectional structure in a manufacturing process of the memory device according to modification 2 of embodiment 1.

Fig. 19 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array included in a memory device according to modification 3 of embodiment 1.

Fig. 20 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array included in the memory device according to modification 4 of embodiment 1.

Fig. 21 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array included in the memory device according to embodiment 2.

Fig. 22 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array included in the memory device according to the modification of embodiment 2.

Fig. 23 is a plan view showing an example of a planar structure of a memory cell array included in the memory device according to embodiment 3.

Fig. 24 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array included in the memory device according to embodiment 3.

Fig. 25 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array included in the memory device according to embodiment 3.

Fig. 26 is a perspective view of a part of a memory cell array included in the memory device according to embodiment 3.

Fig. 27 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array included in the memory device according to embodiment 4.

Fig. 28 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array included in the memory device according to embodiment 5.

Fig. 29 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array included in the memory device according to embodiment 5.

Fig. 30 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array included in the memory device according to embodiment 6.

Fig. 31 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array included in the memory device according to embodiment 6.

Description of the reference numerals

1 a storage device; 10 memory cell arrays; an 11 input/output circuit; 12 a control circuit; 13 a decoding circuit; a 14-row selection circuit; a 15-column selection circuit; a 16 voltage generation circuit; a 17 write circuit; 18 a readout circuit; 19 write drivers; a 30 semiconductor substrate; 31 an insulating layer; 32. 33a, 33b1 to 33b4 conductors; 34. a 35 element; 36. 37a, 37b, 38 electrical conductors; 39 ferromagnetic body; 40 a nonmagnetic body; a 41 ferromagnetic body; 42 an insulating layer; 43. 44 a resist mask; CP1, CP2 contact plugs.

Detailed Description

Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having substantially the same functions and structures are denoted by the same reference numerals. In particular, when distinguishing elements having the same structure from each other, different letters or numerals may be attached to the ends of the same reference numerals.

1. Embodiment 1

A storage device according to embodiment 1 will be described. The memory device according to embodiment 1 is a magnetic memory device using an element having a magnetoresistance effect (Magnetoresistance effect) through a magnetic tunnel junction (MTJ: magnetic Tunnel Junction) (also referred to as an MTJ element or Magnetoresistance effect element (magnetoresistance effect element)) as a variable resistance element, for example. In this embodiment, an MTJ element is used as a variable resistive element in the embodiments and modifications described later, and a magnetoresistance element MTJ is described.

1.1 constitution

1.1.1 construction of memory device

The configuration of the storage device according to embodiment 1 will be described with reference to fig. 1. Fig. 1 is a block diagram showing a configuration of a storage device. The memory device 1 includes a memory cell array 10, an input/output circuit 11, a control circuit 12, a decoding circuit 13, a row selection circuit 14, a column selection circuit 15, a voltage generation circuit 16, a write circuit 17, and a read circuit 18.

The memory cell array 10 is a nonvolatile memory. The memory cell array 10 includes a plurality of memory cells MC each associated with a group of rows (row) and columns (column). The memory cell MC stores data in a nonvolatile manner. For example, memory cells MC in the same row are connected to the same word line WL. Memory cells MC in the same column are connected to the same bit line BL.

The input/output circuit 11 is a circuit for transmitting and receiving data. The input/output circuit 11 receives a control signal CNT, a command CMD, an address ADD, and data (write data) DAT from outside the memory device 1. The input-output circuit 11 transmits a control signal CNT and a command CMD to the control circuit 12. The input-output circuit 11 transmits the address ADD to the decoding circuit 13. The input-output circuit 11 transmits data (write data) DAT to the write circuit 17. The input/output circuit 11 receives data (read data) DAT from the read circuit 18. The input/output circuit 11 transmits data (read data) DAT to the outside of the memory device 1.

The control circuit 12 is a circuit that controls the operation of the entire memory device 1. The control circuit 12 controls operations of the input/output circuit 11, the decoder circuit 13, the row selection circuit 14, the column selection circuit 15, the voltage generation circuit 16, the write circuit 17, and the read circuit 18 based on the control signal CNT and the command CMD.

The decoding circuit 13 is a circuit that decodes the address ADD. The decoding circuit 13 receives the address ADD from the input-output circuit 11. The decoding circuit 13 decodes the address ADD. The decoding circuit 13 transmits the decoding result of the address ADD to the row selection circuit 14 and the column selection circuit 15. Address ADD includes a row address and a column address.

The row selection circuit 14 is a circuit for selecting a word line WL corresponding to a row of the memory cell array 10. The row selection circuit 14 is connected to the memory cell array 10 via a word line WL. The row selection circuit 14 receives a decoding result (row address) of the address ADD from the decoding circuit 13. The row selection circuit 14 selects the word line WL corresponding to the row based on the decoding result of the address ADD.

The column selection circuit 15 is a circuit for selecting the bit line BL corresponding to a column of the memory cell array 10. The column selection circuit 15 is connected to the memory cell array 10 via a bit line BL. The column selection circuit 15 receives a decoding result (column address) of the address ADD from the decoding circuit 13. The column selection circuit 15 selects the bit line BL corresponding to the column based on the decoding result of the address ADD.

The voltage generation circuit 16 is a circuit that generates voltages for various operations of the memory cell array 10 using a power supply voltage applied from outside the memory device 1. For example, the voltage generation circuit 16 generates a voltage (hereinafter also referred to as "write voltage") used in the write operation. The voltage generation circuit 16 supplies a write voltage to the write circuit 17. The voltage generation circuit 16 generates a voltage (hereinafter also referred to as "read voltage") to be used in the read operation. The voltage generation circuit 16 supplies a read voltage to the read circuit 18.

The write circuit 17 is a circuit for writing data into the memory cell MC. Write circuit 17 includes write driver 19. The write circuit 17 receives write data DAT from the input/output circuit 11. The write circuit 17 is applied with a write voltage from the voltage generation circuit 16. The write driver 19 is, for example, a constant current driver circuit. The write driver 19 supplies a current (a current used in a write operation, hereinafter also referred to as a "write current") based on a write voltage to the row selection circuit 14 and the column selection circuit 15. The row selection circuit 14 and the column selection circuit 15 supply write currents to the memory cell array 10 via the selected word line WL and bit line BL.

The read circuit 18 is a circuit for reading data from the memory cell MC. The sense circuit 18 includes a sense amplifier, not shown. The sense circuit 18 is applied with a sense voltage from the voltage generation circuit 16. The sense circuit 18 supplies a sense voltage to the column selection circuit 15. The column selection circuit 15 supplies a read voltage to the memory cell array 10 via the selected bit line BL. The sense circuit 18 is applied with a voltage of the bit line BL from the column selection circuit 15. The sense amplifier deduces the data stored in the memory cell MC based on the voltage of the bit line BL. The read circuit 18 transmits the inferred data to the input/output circuit 11 as read data DAT.

1.1.2 Circuit configuration of memory cell array

The circuit configuration of the memory cell array 10 will be described with reference to fig. 2. Fig. 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array 10. In fig. 2, the memory cell MC, the word line WL, and the bit line BL are represented by being classified by an index ("< >") included in the subscripts.

As shown in fig. 2, the memory cells MC are arranged in a matrix in the memory cell array 10, and are associated with groups of one of a plurality of word lines WL (WL < 0 >, WL < 1 >, … …, WL < M >) and one of a plurality of bit lines BL (BL < 0 >, BL < 1 >, … …, BL < N >) (M and N are arbitrary integers). That is, the memory cell MC < i, j > (0.ltoreq.i.ltoreq.M, 0.ltoreq.j.ltoreq.N) is connected between the word line WL < i > and the bit line BL < j >. The memory cell MC < i, j > includes a switching element SEL < i, j > and a magnetoresistance effect element MTJ < i, j > connected in series.

The switching element SEL has a function as a selector that controls current supply to the magnetoresistance effect element MTJ at the time of data writing and reading to the corresponding magnetoresistance effect element MTJ.

The switching element SEL according to the present embodiment will be described with two terminals. The switching element SEL is in a high-resistance state, for example, in an electrically non-conductive state (OFF state) when the voltage applied between the two terminals is less than a certain 1 st threshold value. When the voltage applied between the two terminals increases to be equal to or greater than the 1 st threshold, the switching element SEL is in a low resistance state, for example, an electrically conductive state (ON state). When the voltage drop applied between the two terminals of the switching element SEL in the low resistance state is low and becomes equal to or less than the 2 nd threshold value, the switching element SEL is in the high resistance state. The switching element SEL also has the same function as the switching function between the high-resistance state and the low-resistance state based on the magnitude of the voltage applied in the 1 st direction with respect to the 2 nd direction opposite to the 1 st direction. That is, the switching element SEL is a bidirectional switching element. By turning on or off the switching element SEL, the presence or absence of current supply to the MTJ element MTJ connected to the switching element SEL, that is, the selection or non-selection of the MTJ element MTJ can be controlled.

In this embodiment mode, a switching element having the following characteristics can be used: at a certain voltage, the resistance value decreases rapidly, and the applied voltage decreases rapidly and the current increases (snapback) accordingly.

For example, a switching element formed substantially of a composition containing silicon (Si), oxygen (O), and a predetermined element selected from the group consisting of arsenic (As), phosphorus (P), antimony (Sb), sulfur (S), selenium (Se), and tellurium (Te) (for example, silicon oxide (SiOx) containing the predetermined element) may be used.

In addition, the inclusion of "substantial" descriptions (e.g., substantial formation) and the like means that the material (composition) that is allowed to be substantially formed contains undesirable impurities.

The magnetoresistance effect element MTJ can be switched between a low resistance state and a high resistance state by controlling the supplied current by the switching element SEL. The magnetoresistance effect element MTJ functions as a memory element capable of writing data by a change in its resistance state and storing and reading the written data in a nonvolatile manner.

1.1.3 Structure of memory cell array

An example of the structure of the memory cell array 10 will be described. In the drawings referred to below, the X direction corresponds to the extending direction of the word line WL, the Y direction corresponds to the extending direction of the bit line BL, and the Z direction corresponds to the vertical direction with respect to the surface of the semiconductor substrate used for forming the memory device 1.

(planar Structure)

The planar structure of the memory cell array 10 will be described with reference to fig. 3. Fig. 3 is a plan view showing an example of a planar structure of the memory cell array 10. Fig. 3 shows word lines WL between a plurality of memory cells MC and a row selection circuit 14 and bit lines BL between a plurality of memory cells MC and a column selection circuit 15 within the memory cell array 10. In fig. 3, word lines WL < 5 > -WL < M >, bit lines BL < 5 > -BL < N > and a plurality of memory cells MC corresponding to these lines are omitted.

The planar structure herein means a structure (single-layer structure) of: as in the structure of fig. 6, regarding the memory cell MC, one memory cell MC can be selected by a group of one word line WL and one bit line BL in the Z direction. The description of the planar structure hereinafter is also used in the same sense.

As shown in fig. 3, in the memory cell array 10, for example, the memory cell MC is arranged above the word line WL. The bit line BL is disposed above the memory cell MC.

The word lines WL are connected to the row selection circuit 14 and the plurality of memory cells MC arranged in the X direction. The row selection circuit 14 supplies a write current to the memory cell MC via the word line WL. In the following, the regions including the plurality of memory cells MC connected to the word lines WL < 0 > -WL < 4 > are referred to as regions R0w to R4w, respectively. Region R0w contains memory cells MC < 0,0 > -MC < 0, N >. Region R1w includes memory cells MC < 1,0 > -MC < 1, N >. Region R2w contains memory cells MC < 2,0 > -MC < 2, N >. Region R3w contains memory cells MC < 3,0 > -MC < 3, N >. Region R4w contains memory cells MC < 4,0 > -MC < 4, N >.

The regions R0w to R4w are arranged in the order of the region R4w, the region R3w, the region R2w, the region R1w, and the region R0w from the column selection circuit 15 side. The shorter the memory cell MC (hereinafter also referred to as "cell close to the column selection circuit 15") in the region close to the column selection circuit 15 (for example, region R4 w), the shorter the length of the bit line BL between the memory cell MC and the column selection circuit 15. In other words, the longer the memory cell MC (hereinafter also referred to as "cell far from the column selection circuit 15") in the region far from the column selection circuit 15 (for example, region R0 w), the longer the bit line BL between the memory cell MC and the column selection circuit 15. Therefore, the closer to the cell of the column selection circuit 15, the lower the resistance value of the bit line BL between the memory cell MC and the column selection circuit 15.

The bit lines BL are each connected to a plurality of memory cells MC arranged in the Y direction in the column selection circuit 15. The column selection circuit 15 supplies a write current to the memory cell MC via the bit line BL. In the following, the regions including the plurality of memory cells MC connected to the bit lines BL < 0 > -BL < 4 > are referred to as regions R0b to R4b, respectively. Region R0b contains memory cells MC < 0,0 > -MC < M,0 >. Region R1b includes memory cells MC < 0,1 > -MC < M,1 >. Region R2b contains memory cells MC < 0,2 > -MC < M,2 >. Region R3b contains memory cells MC < 0,3 > -MC < M,3 >. Region R4b contains memory cells MC < 0,4 > -MC < M,4 >.

The regions R0b to R4b are arranged in the order of the region R0b, the region R1b, the region R2b, the region R3b, and the region R4b from the row selection circuit 14 side. The shorter the memory cell MC (hereinafter also referred to as "cell close to the row selection circuit 14") in the region close to the row selection circuit 14 (for example, region R0 b), the shorter the length of the word line WL between the memory cell MC and the row selection circuit 14. In other words, the longer the memory cell MC (hereinafter also referred to as "cell far from the row selection circuit 14") in the region far from the row selection circuit 14 (for example, region R4 b), the longer the length of the word line WL between the memory cell MC and the row selection circuit 14. Therefore, the resistance value of the word line WL between the memory cell MC and the row selection circuit 14 is lower as the memory cell MC is closer to the cell of the row selection circuit 14.

(Cross-sectional Structure)

The cross-sectional structure of the memory cell array 10 will be described with reference to fig. 4 to 6. Fig. 4 is a cross-sectional view taken along line I-I of fig. 3. Fig. 5 is a sectional view taken along line II-II of fig. 3. Fig. 6 is a perspective view of a part of the memory cell array 10. In the examples shown in fig. 4 to 6, the insulating layer is omitted.

As shown in fig. 4 to 6, the memory cell array 10 is disposed above the semiconductor substrate 30.

A plurality of conductors 32 are provided above the semiconductor substrate 30, for example, with an insulating layer 31 interposed therebetween. The plurality of conductors 32 are made of a conductive material and function as word lines WL. The plurality of conductors 32 are arranged in the Y direction, for example, and extend in the X direction. In fig. 6, the semiconductor substrate 30 and the insulating layer 31 are omitted.

A plurality of contact plugs CP1 (hereinafter also referred to as "1 st electrode", or "upper electrode") are provided on the upper surface of one conductor 32. The contact plug CP1 electrically connects the memory cell MC and the conductor 32. The plurality of contact plugs CP1 provided on the upper surface of one conductor 32 are arranged in an X direction, for example.

The contact plug CP1 of the region R0b includes a conductor 33a. The contact plugs CP1 of the regions R1b to R4b each include conductors 33a and 33b. The conductors 33a and 33b are made of a conductive material. The conductor 33b includes a material having a lower resistivity than the conductor 33a. The conductors 33a and 33b may contain, for example, carbon, boron Nitride (BN), metal oxide, metal nitride, polysilicon (poly-Si), tungsten, titanium, aluminum, copper, or the like. For example, two materials are selected from these materials, and the conductor 33a includes a material having a relatively high resistivity (hereinafter also referred to as a "high-resistance material"). The conductor 33b includes a material having a relatively low resistivity (hereinafter also referred to as "low-resistance material"). The electric conductors 33a and 33b are not limited to these materials as long as the electric conductor 33a has higher resistivity than the electric conductor 33b.

The high-resistance material used for the conductor 33a and the low-resistance material used for the conductor 33b can be selected as follows, for example. In the case where at least one of copper and aluminum is selected as the low-resistance material, at least one of tungsten, tungsten nitride (WN), titanium nitride (TiN), carbon, and polysilicon can be selected as the high-resistance material. In the case where at least one of tungsten, tungsten nitride, titanium, and titanium nitride is selected as the low-resistance material, at least one of carbon and polysilicon can be selected as the high-resistance material. In the case where carbon is selected as the low-resistance material, polysilicon can be selected as the high-resistance material.

The diameters of the contact plugs CP1 in the regions R0b to R4b are substantially the same. The shape of the cross section (XY cross section) of the contact plug CP1 is not limited to a circular shape. For example, the cross-section of the contact plug CP1 may have an elliptical shape or a rectangular shape. The contact plugs CP1 of the regions R0b to R4b have substantially the same contact area (contact area) with the word line WL regardless of the shape of the contact plug CP 1.

The ratio of the conductors 33b included in the contact plugs CP1 in the regions R1b to R4b is lower as the contact plugs CP1 are provided in the region closer to the row selection circuit 14. The lower the contact plug CP1 provided in the region close to the row selection circuit 14, the lower the height of the conductor 33b included in the contact plug CP1 in each of the regions R1b to R4 b. Therefore, the resistance value of the contact plug CP1 increases as the contact plug CP1 is provided in the region close to the row selection circuit 14.

The length of the word line WL from the row selection circuit 14 to the contact plug CP1 provided in the region R0b is shorter than the length of the word line WL from the row selection circuit 14 to the contact plug CP1 provided in the region R1 b. The length of the word line WL from the row selection circuit 14 to the contact plug CP1 provided in the region R1b is shorter than the length of the word line WL from the row selection circuit 14 to the contact plug CP1 provided in the region R2 b. The same applies to the following.

The conductor 33b is provided on the conductor 33 a. Further, the conductor 33a may be provided on the conductor 33 b. The contact plugs CP1 in the regions R1b to R4b may be composed of 3 or more conductors having different resistivities.

The conductors 33a and 33b may contain two or more materials. For example, in the case where the conductors 33a and 33B each include two materials a and B having different resistance values, the ratio of the material a to the material B included in the conductor 33a and the ratio of the material a to the material B included in the conductor 33B may be different. Thus, the resistivity of the conductor 33a and the resistivity of the conductor 33b may also be different.

An element 34 functioning as a switching element SEL is provided on the upper surface of the contact plug CP 1.

An element 35 functioning as a magnetoresistance effect element MTJ is provided on the upper surface of the element 34. The details of the constitution of the element 35 will be described later.

An electrical conductor 36 is provided on the upper surface of the element 35. The conductor 36 is made of a conductive material and functions as a hard mask when the element 35 is processed.

A contact plug CP2 (hereinafter also referred to as "2 nd electrode", or "lower electrode") is provided on the upper surface of the conductor 36. The contact plug CP2 electrically connects the memory cell MC and a conductor 38 described later via the conductor 36. The contact plug CP2 includes a conductor 37a. The conductor 37a is made of a conductive material.

A conductor 38 is provided on the upper surface of the contact plug CP 2. The plurality of conductors 38 are made of a conductive material and function as bit lines BL. The plurality of conductors 38 are arranged in an X-direction, for example, and each extend in a Y-direction. For example, a plurality of contact plugs CP2 arranged in a row in the Y direction are connected to one conductor 38.

As shown in fig. 6, one memory cell MC is provided at each intersection of the conductor 32 and the conductor 38.

Further, the element 34 and the element 35 may not be disposed so as to be connected to each other. For example, the element 34 and the element 35 may be electrically connected via an electric conductor (not shown). The case where the element 35 and the conductor 36 are provided on the element 34 is described with reference to fig. 4 to 6, but the present invention is not limited thereto. For example, the element 34 may be provided on the element 35 and the conductor 36.

With the above-described configuration, the memory cell array 10 has a structure in which the memory cells MC are provided between the corresponding word lines WL and bit lines BL.

With reference to fig. 3 to 6, the case of a structure (referred to as a single-layer structure) in which one memory cell MC can be selected by a group of one word line WL and one bit line BL will be described, but the present invention is not limited thereto. For example, any array structure such as an array structure having a structure in which a plurality of these structures are stacked in the Z direction may be applied.

In fig. 6, the configuration in which the diameters of CP1 and CP2 are smaller than the diameter of MC is described as an example, but the present invention is not limited to this configuration. Even in the case of the configuration in which the diameters of CP1 and CP2 are substantially the same as the diameter of MC, the same effect can be obtained.

1.1.4 Structure of magneto-resistance effect element

The structure of the magnetoresistance effect element MTJ will be described with reference to fig. 7. Fig. 7 is a cross-sectional view showing an example of a cross-sectional structure of the magnetoresistance effect element MTJ.

As shown in fig. 7, the element 35 (magnetoresistance effect element MTJ) includes a ferromagnetic body 39 functioning as a reference layer RL (Reference layer), a nonmagnetic body 40 functioning as a tunnel barrier layer TB (Tunnel barrier layer), and a ferromagnetic body 41 functioning as a storage layer SL (Storage layer).

The magnetoresistance effect element MTJ is formed by stacking a plurality of materials in the order of the ferromagnetic body 39, the nonmagnetic body 40, and the ferromagnetic body 41 from the word line WL side toward the bit line BL side (in the Z-axis direction), for example. For the magnetoresistive element MTJ, for example, the magnetoresistive element MTJ functions as a perpendicular magnetization type in which the magnetization directions of the magnetic bodies constituting the magnetoresistive element MTJ are oriented in directions perpendicular to the film surface.

The ferromagnetic body 39 has ferromagnetic properties, and has an easy axis direction in a direction perpendicular to the film surface. The ferromagnetic body 39 has a magnetization direction oriented in either one of the bit line BL side and the word line WL side. The ferromagnetic body 39 includes cobalt-iron-boron (CoFeB) or iron boride (FeB), for example. The magnetization direction of the ferromagnetic body 39 is fixed, and in the example of fig. 7, the direction is opposite to the surface on which the nonmagnetic body 40 is provided. The term "the magnetization direction is fixed" means that the magnetization direction does not change according to a current (spin torque) having a magnitude capable of reversing the magnetization direction of the ferromagnetic body 41.

The nonmagnetic material 40 is a nonmagnetic insulating film, and contains magnesium oxide (MgO), for example. The nonmagnetic material 40 is disposed between the ferromagnetic body 39 and the ferromagnetic body 41. Thus, the ferromagnetic body 39, the nonmagnetic body 40, and the ferromagnetic body 41 constitute a magnetic tunnel junction (Magnetic Tunnel junction).

The ferromagnetic body 41 has ferromagnetic properties, and has an easy axis direction (easy axis of magnetization) in a direction perpendicular to the film surface. The ferromagnetic body 41 has a magnetization direction oriented in either one of the bit line BL side and the word line WL side. The ferromagnetic Body 41 may have a Body-centered cubic (bcc) crystal structure, and may include cobalt-iron-boron (CoFeB) or iron boride (FeB), for example.

For example, the memory device 1 directly supplies a write current to the magnetoresistance element MTJ configured as described above, and the spin torque is injected into the memory layer SL and the reference layer RL by the write current, thereby controlling the magnetization direction of the memory layer SL and the magnetization direction of the reference layer RL. Such a writing method is also called spin injection writing method. The magnetoresistance effect element MTJ can achieve either one of a low resistance state and a high resistance state by whether the relative relationship of the magnetization directions of the memory layer SL and the reference layer RL is parallel or antiparallel.

When a write current Iw0 of a certain magnitude flows in the magnetoresistive element MTJ in the direction of the arrow A1 in fig. 7, that is, in the direction from the memory layer SL toward the reference layer RL, the relative relationship between the magnetization directions of the memory layer SL and the reference layer RL becomes parallel. In this parallel state, the resistance value of the magnetoresistance effect element MTJ is the lowest, and the magnetoresistance effect element MTJ is set to a low resistance state. This low resistance state is referred to as a "P (Parallel) state", and is defined as a state of data "0", for example.

In addition, when a write current Iw1 larger than the write current Iw0 flows in the direction of arrow A2 in fig. 7, that is, in the direction from the reference layer RL toward the memory layer SL, the relative relationship between the magnetization directions of the memory layer SL and the reference layer RL becomes antiparallel. In this antiparallel state, the resistance value of the magnetoresistive element MTJ becomes highest, and the magnetoresistive element MTJ is set to a high resistance state. This high resistance state is referred to as an "AP (Anti-Parallel) state", and is defined as a state of data "1", for example.

The manner of defining data "1" and data "0" is not limited to the above-described examples. For example, the P state may be defined as data "1", and the AP state may be defined as data "0".

1.2 method of manufacturing memory device

A method for manufacturing the memory device 1 according to embodiment 1 will be described with reference to fig. 8 to 14. Fig. 8 is a flowchart showing an example of a method for manufacturing the contact plug CP1 in the memory device 1. Fig. 9 to 14 are cross-sectional views each showing an example of a cross-sectional structure in the manufacturing process of the storage device 1. In the following, a case of forming the contact plugs CP1 of the regions R0b to R2b in fig. 4 will be described as an example. Fig. 9 to 14 show contact plugs CP1 in regions R0b to R2b in fig. 4. In fig. 9 to 14, the semiconductor substrate 30, the insulating layer 31, the element 34, the element 35, the conductor 36, the contact plug CP2, and the conductor 38 are omitted.

As shown in fig. 8, in the process of manufacturing the contact plug CP1, the processes of S100 to S105 are sequentially performed. Hereinafter, an example of a process for manufacturing the contact plug CP1 will be described with reference to fig. 8 as appropriate.

First, as shown in fig. 9, a conductor 33a penetrating the insulating layer 42 and reaching the conductor 32 from the bottom surface is formed (S100). More specifically, first, a hole is formed which penetrates the insulating layer 42 and reaches the conductor 32 from the bottom surface. The hole corresponds to the contact plug CP 1. Next, the conductor 33a is formed into a film so as to fill the hole. Then, the conductor 33a on the insulating layer 42 is removed by CMP (Chemical Mechanical Polishing ) or the like.

Next, as shown in fig. 10, a resist mask 43 for processing the conductor 33a of the region R2b is formed on the conductor 33a and the insulating layer 42 by photolithography or the like (S101). An opening of the resist mask 43 is provided in the region R2b. Therefore, the upper surface of the conductor 33a provided in the region R2b is exposed (not covered with the resist mask 43). The upper surfaces of the conductors 33a provided in the regions R0b and R1b are covered with a resist mask 43.

Next, as shown in fig. 11, the conductor 33a is processed by RIE (reactive ion etching ), for example (S102). Through S102, the upper portion of the conductor 33a of the region R2b is removed. The upper surface of the conductor 33a of the region R2b is located below the upper surface of the insulating layer 42. The conductor 33a may be processed by wet etching. After the processing of the conductor 33a, the resist mask 43 is peeled off.

Next, as shown in fig. 12, a resist mask 44 for processing the conductor 33a of the region R2b and the conductor 33a of the region R1b is formed on the conductor 33a and the insulating layer 42 by photolithography or the like (S103). The openings of the resist mask 44 are provided in the regions R1b and R2b. Accordingly, the upper surfaces of the conductors 33a provided in the regions R1b and R2b are exposed (not covered by the resist mask 44). The upper surface of the conductor 33a provided in the region R0b is covered with a resist mask 44.

Next, as shown in fig. 13, the conductor 33a is processed by RIE, for example (S104). Through S104, the upper portions of the conductors 33a of the region R2b and the conductors 33a of the region R1b are removed. The upper surface of the conductor 33a of the region R1b is located below the upper surface of the insulating layer 42. The upper surface of the conductor 33a of the region R2b is located lower than the upper surface of the conductor 33a of the region R1 b. That is, the conductor 33a of the region R2b is shaved deeper than the conductor 33a of the region R1b by S102 and S104. The conductor 33a may be processed by wet etching. After the processing of the conductor 33a, the resist mask 44 is peeled off.

Next, as shown in fig. 14, a conductor 33b is formed on the conductor 33a of the region R2b and the conductor 33a of the region R1b (S105). More specifically, the conductor 33b is formed in a film so as to fill the region from which the conductor 33a was removed in S102 and S104. Then, the conductor 33b on the insulating layer 42 is removed by CMP or the like.

In general, since a material having a relatively high resistivity has a relatively high affinity for RIE as compared with a material having a relatively low resistivity, it is preferable that the conductor 33a is disposed below the conductor 33 b.

When the bit lines BL are k (k is an integer of 1 or more), photolithography and RIE for changing the ratio of the conductors 33b are repeated (k-1) times.

Through the manufacturing process described above, the contact plug CP1 is formed. The manufacturing steps described above are merely examples, and are not limited thereto. For example, other processes may be interposed between the respective manufacturing steps, or some of the steps may be omitted or combined. In addition, each manufacturing process may be exchanged as far as possible.

1.3 effects according to the present embodiment

According to embodiment 1, erroneous reading can be reduced. The present effect will be described below.

As described above, the resistance value of the word line WL between the memory cell MC and the row selection circuit 14 decreases as the memory cell MC approaches the cell of the row selection circuit 14. The plurality of contact plugs CP1 connected to the word line WL have the same resistance value. In this case, the resistance value of a wiring path (hereinafter also referred to as "row selection circuit-cell wiring path") formed by the word line WL from the row selection circuit 14 to the memory cell MC and the contact plug CP1 varies according to the length of the word line WL from the row selection circuit 14 to the contact plug CP1. The time from the start of driving of the write driver 19 to the turning on of the element 34 (switching element SEL) of the memory cell MC varies depending on the resistance value of the row selection circuit-cell wiring path. Therefore, the length of time (hereinafter also referred to as "current supply time") for which the write driver 19 supplies a write current to the memory cell MC varies according to the length of the word line WL.

The longer the current supply time is for the cells closer to the row selection circuit 14, the shorter the current supply time is for the cells farther from the row selection circuit 14. In a memory cell MC having a relatively short current supply time, that is, a cell distant from the row selection circuit 14, a write failure may occur due to insufficient current supply time. On the other hand, in the memory cell MC having a relatively long current supply time, that is, in a cell close to the row selection circuit 14, a failure in the magnetoresistance effect element MTJ may occur due to an excessive current supply time.

Then, in the present embodiment, the resistance value of the contact plug CP1 is changed according to the length of the word line WL from the row selection circuit 14 to the contact plug CP 1. In other words, the resistance value of the contact plug CP1 differs depending on the configuration of the row selection circuit 14 and the memory cell MC.

More specifically, the contact plug CP1 of the region R0b includes the electric conductor 33a. The contact plugs CP1 in the regions R1b to R4b each include a conductor 33a and a conductor 33b having a lower resistivity than the conductor 33a. The ratio of the conductors 33b included in the contact plug CP1 decreases as the contact plug CP1 is provided in a region close to the row selection circuit 14. Thus, the resistance value of the contact plug CP1 increases as the contact plug CP1 is provided in the region close to the row selection circuit 14. Therefore, in the region close to the row selection circuit 14, the resistance value of the word line WL becomes lower and the resistance value of the contact plug CP1 becomes higher than in the region farther. On the other hand, in a region far from the row selection circuit 14, the resistance value of the word line WL becomes higher and the resistance value of the contact plug CP1 becomes lower than in a region nearer thereto. By combining the resistance value of the word line WL and the resistance value of the contact plug CP1, it is possible to suppress the variation in the resistance value of the row selection circuit-cell wiring path due to the length of the word line WL. This can reduce erroneous data reading.

1.4 1 st modification example

A storage device according to modification 1 of embodiment 1 will be described. In the memory device 1 according to modification 1 of embodiment 1, the method of distributing the ratio of the conductors 33b included in the contact plugs CP1 is different from embodiment 1. In the following description, the same configuration as in embodiment 1 will be omitted, and mainly the configuration different from embodiment 1 will be described.

1.4.1 memory cell array Structure

The structure of the memory cell array 10 is the same as that of embodiment 1.

The cross-sectional structure of the memory cell array 10 will be described with reference to fig. 15. Fig. 15 is a cross-sectional view taken along line I-I of fig. 3. In addition, the insulating layer is omitted in the example shown in fig. 15.

As shown in fig. 15, the diameters of the contact plugs CP1 in the regions R0b to R4b are substantially the same. The shape of the cross section of the contact plug CP1 is not limited to a circular shape. The contact plugs CP1 of the regions R0b to R4b have substantially the same contact area with the word line WL regardless of the shape of the contact plug CP 1.

The regions R1b to R4b are divided into a group G0 including two adjacent regions R1b and R2b, and a group G1 including two adjacent regions R3b and R4 b. The contact plugs CP1 of the regions R1b and R2b include the same ratio of the conductors 33 b. The contact plugs CP1 of the regions R3b and R4b each include the same ratio of the conductors 33 b. The ratio of the electric conductor 33b included in the contact plug CP1 of each of the regions R1b and R2b is lower than the ratio of the electric conductor 33b included in the contact plug CP1 of each of the regions R3b and R4 b. Thus, the closer to the contact plug CP1 of the group of the row selection circuit 14, the lower the ratio of the conductors 33b included in the contact plugs CP1 of the groups G0 and G1, respectively. The closer to the contact plug CP1 of the group of the row selection circuit 14, the lower the height of the conductor 33b included in the contact plug CP1 of each of the groups G0 and G1. Therefore, the closer to the contact plug CP1 of the group of the row selection circuit 14, the higher the resistance value of the contact plug CP 1. The case where each group includes two adjacent regions is described with reference to fig. 15, but the present invention is not limited thereto. For example, each group may include 3 or more adjacent regions. The number of regions included in the group may be different from each other.

Other portions of the cross-sectional structure of the memory cell array 10 are the same as those of embodiment 1.

1.4.2 effects according to the present modification

According to this modification, the same effects as those of embodiment 1 are achieved.

In addition, according to the present modification, the ratio of the conductors 33b included in the contact plug CP1 is different for each group. Therefore, the ratio of the conductors 33b included in the contact plug CP1 may not be changed for each of the regions R1b to R4 b. Thereby, the kind of the contact plug CP1 having a different ratio of the conductors 33b is reduced as compared with the case where the ratio of the conductors 33b included in the contact plug CP1 is changed individually. Therefore, the number of repetitions of photolithography and RIE for changing the ratio of the conductive body 33b can be reduced. This can reduce the process cost.

1.5 modification No. 2

A storage device according to modification 2 of embodiment 1 will be described. In the memory device 1 according to modification 2 of embodiment 1, the material of the conductors 33a and 33b included in the contact plug CP1 is different from embodiment 1. In the following description, the same configuration as in embodiment 1 will be omitted, and mainly the configuration different from embodiment 1 will be described.

1.5.1 memory cell array Structure

The planar structure and the cross-sectional structure of the memory cell array 10 are the same as those of embodiment 1.

In fig. 4, the conductors 33a and 33b are, for example, n-type semiconductors or p-type semiconductors. The conductors 33a and 33b contain, for example, at least one of silicon and germanium. The conductors 33a and 33b contain impurities (dopants). Examples of impurities are boron, phosphorus, arsenic, antimony. The impurity concentration of the conductor 33b is higher than that of the conductor 33 a. That is, the electrical conductor 33b has a lower resistivity than the electrical conductor 33 a. Therefore, the resistance value of the contact plug CP1 increases as the contact plug CP1 is provided in the region close to the row selection circuit 14.

1.5.2 method of manufacturing memory device

A method for manufacturing the memory device 1 according to modification 2 of embodiment 1 will be described with reference to fig. 16 to 18. Fig. 16 is a flowchart showing an example of a method for manufacturing the contact plug CP1 in the memory device 1. Fig. 17 and 18 are cross-sectional views each showing an example of a cross-sectional structure in the manufacturing process of the storage device 1. In the method for manufacturing the contact plug CP1 in the memory device 1 according to modification 2 of embodiment 1, S102 and S104 in fig. 8 of embodiment 1 are replaced with S106 and S107. Further, S105 of fig. 8 of embodiment 1 is discarded. S100, S101, and S103 are the same as those of embodiment 1. Hereinafter, S106 and S107 will be mainly described.

Hereinafter, an example of a process for manufacturing the contact plug CP1 will be described with reference to fig. 16.

In S100, a conductor 33a having a relatively low impurity concentration is formed, and in S101, a resist mask 43 is formed. Then, as shown in fig. 17, ion implantation of impurities is performed on the conductor 33a of the region R2b (S106). Thereby, the conductor 33b having a higher impurity concentration than the conductor 33a is formed on the upper portion of the conductor 33a in the region R2 b. When the concentrations of the impurities of the conductors 33a in the regions R0b to R2b are set to the concentrations D10a to D12a, respectively, the concentrations D10a to D12a are the same. After being implanted with ions, the resist mask 43 is stripped.

In S103, a resist mask 44 is formed. Then, as shown in fig. 18, ion implantation of impurities is performed for each of the conductor 33a of the region R2b and the conductor 33a of the region R1b (S107). At this time, the acceleration voltage used for ion implantation is set to be lower than the acceleration voltage used for ion implantation in S106. Thereby, the implantation depth of ions into the conductor 33a of the region R1b becomes shallower than the implantation depth of ions into the conductor 33a of the region R2b in S106. As a result, the conductor 33b having a higher impurity concentration than the conductor 33a is formed on the upper portion of each of the conductor 33a in the region R2b and the conductor 33a in the region R1 b. When the impurity concentration of the conductor 33b in the region R2b is D12b, the concentration D12b is higher than the concentration D12 a. When the impurity concentration of the conductor 33b in the region R1b is D11b, the concentration D11b is higher than the concentration D11 a. The concentration D12b may be the same as the concentration D11b or may be different from the concentration D11 b. After being implanted with ions, the resist mask 44 is stripped.

With S106 and S107, the ratio of the conductors 33b included in the contact plug CP1 can be reduced as the contact plug CP1 is provided in the region close to the row selection circuit 14. The more the contact plug CP1 is provided in the region close to the row selection circuit 14, the more the height of the conductor 33b included in the contact plug CP1 can be reduced.

1.5.3 effects according to the present modification

According to this modification, the same effects as those of embodiment 1 are achieved. Of course, modification 1 of embodiment 1 may be applied to the contact plug CP1 included in the memory device 1 of the present modification.

1.6 modification No. 3

A storage device according to modification 3 of embodiment 1 will be described. In the memory device 1 according to modification 3 of embodiment 1, the structure of the contact plug CP1 is different from that of modification 2 of embodiment 1. In the following description, the same configuration as in modification 2 of embodiment 1 will be omitted, and a configuration different from modification 2 of embodiment 1 will be mainly described.

1.6.1 memory cell array Structure

The planar structure of the memory cell array 10 is the same as that of modification 2 of embodiment 1.

The cross-sectional structure of the memory cell array 10 will be described with reference to fig. 19. Fig. 19 is a sectional view taken along line I-I of fig. 3. In addition, the insulating layer is omitted in the example shown in fig. 19.

As shown in fig. 19, the contact plug CP1 of the region R0b includes a conductor 33a. The contact plug CP1 of the region R1b includes a conductor 33b1. The contact plug CP1 of the region R2b includes a conductor 33b2. The contact plug CP1 of the region R3b includes a conductor 33b3. The contact plug CP1 of the region R4b includes a conductor 33b4. The conductors 33a and 33b1 to 33b4 are made of the same material as in modification 2 of embodiment 1. The conductors 33a and 33b1 to 33b4 are, for example, n-type semiconductors or p-type semiconductors. The conductors 33a and 33b1 to 33b4 contain, for example, at least one of silicon and germanium. The conductors 33a and 33b1 to 33b4 contain impurities (dopants). The impurity is composed of the same material as in modification 2 of embodiment 1.

The diameters of the contact plugs CP1 in the regions R0b to R4b are substantially the same. The shape of the cross section of the contact plug CP1 is not limited to a circular shape. The contact plugs CP1 of the regions R0b to R4b have substantially the same contact area with the word line WL regardless of the shape of the contact plug CP 1.

When the concentrations of the impurities of the contact plugs CP1 (the conductors 33a and 33b1 to 33b 4) in the regions R0b to R4b are set to the concentrations D10a and D11b to D14b, respectively, the concentration D10a is lower than the concentration D11 b. The concentration D11b is lower than the concentration D12 b. Concentration D12b is lower than concentration D13 b. Concentration D13b is lower than concentration D14 b. Thus, the concentration of impurities in the contact plugs CP1 in the regions R0b to R4b is lower as the contact plugs CP1 are provided in the regions closer to the row selection circuit 14. For example, the acceleration voltage used for ion implantation is set to be the same for the contact plugs CP1 (conductors 33b1 to 33b 4) in the regions R1b to R4b, and the amount of ion implantation is reduced as the contact plug CP1 is provided in a region close to the row selection circuit 14. Therefore, the resistance value of the contact plug CP1 increases as the contact plug CP1 is provided in the region close to the row selection circuit 14.

Other portions of the cross-sectional structure of the memory cell array 10 are the same as those of modification 2 of embodiment 1.

When the number of bit lines BL is k (k is an integer of 1 or more), ion implantation for changing the concentration of the impurity is repeated (k-1) times.

1.6.2 effects according to the present modification

1.7 modification No. 4

A storage device according to modification 4 of embodiment 1 will be described. In the memory device 1 according to modification 4 of embodiment 1, the method for distributing the impurity concentration of the contact plug CP1 is different from modification 3 of embodiment 1. In the following description, the same configuration as in modification 3 of embodiment 1 will be omitted, and a configuration different from modification 3 of embodiment 1 will be mainly described.

1.7.1 memory cell array Structure

The planar structure of the memory cell array 10 is the same as that of modification 3 of embodiment 1.

The cross-sectional structure of the memory cell array 10 will be described with reference to fig. 20. Fig. 20 is a cross-sectional view taken along line I-I of fig. 3. In addition, the insulating layer is omitted in the example shown in fig. 20.

As shown in fig. 20, the diameters of the contact plugs CP1 in the regions R0b to R4b are substantially the same. The shape of the cross section of the contact plug CP1 is not limited to a circular shape. The contact plugs CP1 of the regions R0b to R4b have substantially the same contact area with the word line WL regardless of the shape of the contact plug CP 1.

The regions R1b to R4b are divided into a group G0 including two adjacent regions R1b and R2b, and a group G1 including two adjacent regions R3b and R4 b. Impurity concentrations D11b and D12b of the contact plugs CP1 (conductors 33b1 and 33b 2) of the regions R1b and R2b are the same. Impurity concentrations D13b and D14b of the contact plugs CP1 (conductors 33b3 and 33b 4) of the regions R3b and R4b are the same. Concentration D10a is lower than concentration D11b and D12 b. The concentrations D11b and D12b are lower than the concentrations D13b and D14 b. Thus, the closer to the contact plug CP1 of the group of the row selection circuit 14, the lower the impurity concentration of the contact plug CP1 in the groups G0 and G1. Therefore, the closer to the contact plug CP1 of the group of the row selection circuit 14, the higher the resistance value of the contact plug CP 1. The case where each group includes two adjacent regions is described with reference to fig. 20, but the present invention is not limited thereto. For example, each group may include 3 or more adjacent regions. The number of regions included in the group may be different from each other.

Other portions of the cross-sectional structure of the memory cell array 10 are the same as in modification 3 of embodiment 1.

1.7.2 effects according to the present modification

Further, according to the present modification, the concentration of impurities of the contact plug CP1 differs for each group. Therefore, the impurity concentration of the contact plug CP1 may not be changed for each of the regions R1b to R4 b. Thereby, the kind of the contact plug CP1 having a different impurity concentration is reduced as compared with the case where the impurity concentration of the contact plug CP1 is changed alone. Therefore, the number of repetitions of ion implantation for changing the impurity concentration can be reduced. This can reduce the process cost.

2. Embodiment 2

A storage device according to embodiment 2 will be described. In the memory device 1 according to embodiment 2, the structure of a contact plug CP1 is different from that of embodiment 1. In the following description, the same configuration as in embodiment 1 will be omitted, and mainly the configuration different from embodiment 1 will be described.

2.1 memory cell array Structure

The planar structure of the memory cell array 10 is the same as that of embodiment 1.

The cross-sectional structure of the memory cell array 10 will be described with reference to fig. 21. Fig. 21 is a cross-sectional view taken along line I-I of fig. 3. In addition, the insulating layer is omitted in the example shown in fig. 21.

As shown in fig. 21, the contact plugs CP1 of the regions R0b to R4b each include a conductor 33a. The conductor 33a is made of the same material as in embodiment 1.

When the diameters of the contact plugs CP1 in the regions R0b to R4b are set to the diameters dm0 to dm4, respectively, the diameter dm0 is smaller than the diameter dm 1. Diameter dm1 is smaller than diameter dm 2. Diameter dm2 is smaller than diameter dm 3. Diameter dm3 is smaller than diameter dm 4. The shape of the cross section (XY cross section) of the contact plug CP1 is not limited to a circular shape. For example, the cross-section of the contact plug CP1 may have an elliptical shape or a rectangular shape. Regardless of the shape of the cross section of the contact plug CP1, the contact plug CP1 provided in the region closer to the row selection circuit 14 has a smaller contact area with the word line WL in each of the regions R0b to R4 b. Therefore, the resistance value of the contact plug CP1 increases as the contact plug CP1 is provided in the region close to the row selection circuit 14.

2.2 effects according to the present embodiment

According to embodiment 2, the same effects as those of embodiment 1 are achieved.

2.3 modification examples

A storage device according to a modification of embodiment 2 will be described. In the memory device 1 according to the modification of embodiment 2, the method for distributing the diameter of the contact plug CP1 is different from embodiment 2. In the following description, the same configuration as in embodiment 2 will be omitted, and mainly the configuration different from embodiment 2 will be described.

2.3.1 memory cell array Structure

The planar structure of the memory cell array 10 is the same as that of embodiment 2.

The cross-sectional structure of the memory cell array 10 will be described with reference to fig. 22. Fig. 22 is a cross-sectional view taken along line I-I of fig. 3. In addition, the insulating layer is omitted in the example shown in fig. 22.

As shown in fig. 22, the regions R1b to R4b are divided into a group G0 including two adjacent regions R1b and R2b, and a group G1 including two adjacent regions R3b and R4 b. The diameters dm1 and dm2 of the contact plugs CP1 of the respective regions R1b and R2b are the same. The diameters dm3 and dm4 of the contact plugs CP1 of the respective regions R3b and R4b are the same. Diameter dm0 is smaller than diameter dm1 and dm 2. Diameters dm1 and dm2 are smaller than diameters dm3 and dm 4. Thus, the closer to the contact plug CP1 of the group of the row selection circuit 14, the smaller the diameter of the contact plug CP1 of each of the groups G0 and G1. The shape of the cross section of the contact plug CP1 is not limited to a circular shape. Regardless of the shape of the cross section of the contact plug CP1, the contact plug CP1 of the group closer to the row selection circuit 14 has a smaller contact area with the word line WL for the contact plugs CP1 of the groups G0 and G1. Therefore, the closer to the contact plug CP1 of the group of the row selection circuit 14, the higher the resistance value of the contact plug CP 1. The case where each group includes two adjacent regions is described with reference to fig. 22, but the present invention is not limited thereto. For example, each group may include 3 or more adjacent regions. The number of regions included in the group may be different from each other.

Other portions of the cross-sectional structure of the memory cell array 10 are the same as those of embodiment 2.

2.3.2 effects according to the present modification

In addition, according to the present modification, the diameter of the contact plug CP1 differs for each group. With all the structures having different diameters of the contact plugs CP1, there is a concern that the manufacturing process is complicated, but according to this modification, this concern can be eliminated.

3. Embodiment 3

A storage device according to embodiment 3 will be described. In the memory device 1 according to embodiment 3, the arrangement of the word line WL, the contact plugs CP1 and CP2, and the bit line BL is different from embodiment 1. In the following description, the same configuration as in embodiment 1 will be omitted, and mainly the configuration different from embodiment 1 will be described.

3.1 memory cell array Structure

An example of the structure of the memory cell array 10 will be described.

(planar Structure)

The planar structure of the memory cell array 10 will be described with reference to fig. 23. Fig. 23 is a plan view showing an example of the planar structure of the memory cell array 10. Fig. 23 shows word lines WL between the plurality of memory cells MC and the row selection circuit 14 and bit lines BL between the plurality of memory cells MC and the column selection circuit 15 within the memory cell array 10. In fig. 23, word lines WL < 5 > -WL < M >, bit lines BL < 5 > -BL < N > and a plurality of memory cells MC corresponding to these lines are omitted.

As shown in fig. 23, in the memory cell array 10, for example, the memory cell MC is arranged above the bit line BL. The word line WL is disposed above the memory cell MC.

(Cross-sectional Structure)

The cross-sectional structure of the memory cell array 10 will be described with reference to fig. 24 to 26. Fig. 24 is a cross-sectional view taken along line I-I of fig. 23. Fig. 25 is a sectional view taken along line II-II of fig. 23. Fig. 26 is a perspective view of a part of the memory cell array 10. In the examples shown in fig. 24 to 26, the insulating layer is omitted.

As shown in fig. 24 to 26, a plurality of conductors 38 are provided above the semiconductor substrate 30, for example, with an insulating layer 31 interposed therebetween. The plurality of conductors 38 are arranged in an X-direction, for example, and each extend in a Y-direction. In fig. 26, the semiconductor substrate 30 and the insulating layer 31 are omitted.

A plurality of contact plugs CP2 are provided on the upper surface of one conductor 38. The plurality of contact plugs CP2 provided on the upper surface of one conductor 38 are arranged in an array, for example, in the Y direction. The contact plug CP2 includes a conductor 37a.

A member 34 is provided on the upper surface of the contact plug CP2.

A contact plug CP1 is provided on the upper surface of the conductor 36. The contact plug CP1 of the region R0b includes a conductor 33a. The contact plugs CP1 of the regions R1b to R4b each include conductors 33a and 33b. The conductors 33a and 33b are made of the same material as embodiment 1.

The diameters of the contact plugs CP1 in the regions R0b to R4b are substantially the same. The shape of the cross section (XY cross section) of the contact plug CP1 is not limited to a circular shape. For example, the cross-section of the contact plug CP1 may have an elliptical shape or a rectangular shape. The contact plugs CP1 of the regions R0b to R4b have substantially the same contact area with the word line WL regardless of the shape of the contact plug CP 1.

The ratio of the conductors 33b included in the contact plugs CP1 in the regions R1b to R4b is lower as the contact plugs CP1 are provided in the region closer to the row selection circuit 14. The lower the contact plug CP1 provided in the region close to the row selection circuit 14, the lower the height of the conductor 33b included in the contact plug CP1 in each of the regions R1b to R4 b. The conductor 33b is provided on the conductor 33 a. Further, the conductor 33a may be provided on the conductor 33 b. The contact plugs CP1 in the regions R1b to R4b may be composed of 3 or more conductors having different resistivities. The conductors 33a and 33b may contain two or more materials.

A conductive body 32 is provided on the upper surface of the contact plug CP 1. The plurality of conductors 32 are arranged in the Y direction, for example, and each extend in the X direction. For example, a plurality of contact plugs CP1 arranged in an aligned manner in the X direction are connected to one conductor 32.

As shown in fig. 26, one memory cell MC is provided at each intersection of the conductor 32 and the conductor 38.

3.2 effects according to the present embodiment

According to embodiment 3, the same effects as those of embodiment 1 are achieved. Of course, modification 1 to modification 4 of embodiment 1 may be applied to the contact plug CP1 included in the memory device 1 of the present embodiment.

4. Embodiment 4

A storage device according to embodiment 4 will be described. In the memory device 1 according to embodiment 4, the structure of the contact plug CP1 is different from that of embodiment 3. In the following description, the same components as those in embodiment 3 will be omitted, and mainly the different components from embodiment 3 will be described.

4.1 memory cell array Structure

The planar structure of the memory cell array 10 is the same as that of embodiment 3.

The cross-sectional structure of the memory cell array 10 will be described with reference to fig. 27. Fig. 27 is a cross-sectional view taken along line I-I of fig. 23. In addition, the insulating layer is omitted in the example shown in fig. 27.

As shown in fig. 27, the contact plugs CP1 of the regions R0b to R4b each include a conductor 33a. The conductor 33a is made of the same material as in embodiment 2.

Diameter dm0 is smaller than diameter dm 1. Diameter dm1 is smaller than diameter dm 2. Diameter dm2 is smaller than diameter dm 3. Diameter dm3 is smaller than diameter dm 4. The shape of the cross section (XY cross section) of the contact plug CP1 is not limited to a circular shape. For example, the cross-section of the contact plug CP1 may have an elliptical shape or a rectangular shape. Regardless of the shape of the cross section of the contact plug CP1, the contact plug CP1 provided in the region closer to the row selection circuit 14 has a smaller contact area with the word line WL in each of the regions R0b to R4 b.

Other portions of the cross-sectional structure of the memory cell array 10 are the same as those of embodiment 3.

4.2 effects according to the present embodiment

According to embodiment 4, the same effects as those of embodiment 1 are achieved. Of course, the modification of embodiment 2 can be applied to the contact plug CP1 included in the memory device 1 of the present embodiment.

5. Embodiment 5

A storage device according to embodiment 5 will be described. In the memory device 1 according to embodiment 5, the structure of the contact plug CP2 is different from that of embodiment 1. In the following description, the same configuration as in embodiment 1 will be omitted, and mainly the configuration different from embodiment 1 will be described.

5.1 memory cell array Structure

The cross-sectional structure of the memory cell array 10 will be described with reference to fig. 28 and 29. Fig. 28 is a cross-sectional view taken along line I-I of fig. 3. Fig. 29 is a sectional view taken along line II-II of fig. 3. In addition, the insulating layer is omitted in the examples shown in fig. 28 and 29.

As shown in fig. 28 and 29, the contact plug CP2 of the region R4w includes a conductor 37a. The contact plugs CP2 of the regions R0w to R3w each include conductors 37a and 37b. The conductor 37a is made of the same material as the conductor 33 a. The conductor 37b is made of the same material as the conductor 33 b.

The diameters of the contact plugs CP2 in the regions R0w to R4w are substantially the same. The shape of the cross section (XY cross section) of the contact plug CP2 is not limited to a circular shape. For example, the cross-section of the contact plug CP2 may have an elliptical shape or a rectangular shape. The contact plugs CP2 of the regions R0w to R4w have substantially the same contact area with the bit line BL regardless of the shape of the contact plug CP 2.

The ratio of the conductors 37b included in the contact plugs CP2 in the regions R0w to R3w is lower as the contact plugs CP2 are provided in the region closer to the column selection circuit 15. The height of the conductor 37b included in each of the contact plugs CP2 in the regions R0w to R3w is lower as the contact plug CP2 is provided in the region closer to the column selection circuit 15. Therefore, the resistance value of the contact plug CP2 increases as the contact plug CP2 is provided in the region close to the column selection circuit 15. The conductor 37b is provided on the conductor 37a. Further, the conductor 37a may be provided on the conductor 37b. The contact plugs CP2 in the regions R0w to R3w may be composed of 3 or more conductors having different resistivities. The conductors 37a and 37b may also contain two or more materials.

The length of the bit line BL from the column selection circuit 15 to the contact plug CP2 provided in the region R4w is shorter than the length of the bit line BL from the column selection circuit 15 to the contact plug CP2 provided in the region R3 w. The length of the bit line BL from the column selection circuit 15 to the contact plug CP2 provided in the region R3w is shorter than the length of the bit line BL from the column selection circuit 15 to the contact plug CP2 provided in the region R2 w. The same applies to the following.

5.2 effects according to the present embodiment

According to embodiment 5, the same effects as those of embodiment 1 are achieved.

In addition, as described in embodiment 1, the closer to the cell of the column selection circuit 15, the lower the resistance value of the bit line BL between the memory cell MC and the column selection circuit 15. The resistance values of the plurality of contact plugs CP2 connected to the bit line BL are set to be the same. In this case, the resistance value of the wiring path (hereinafter also referred to as "column selection circuit-cell wiring path") formed by the bit line BL from the column selection circuit 15 to the memory cell MC and the contact plug CP2 varies according to the length of the bit line BL from the column selection circuit 15 to the contact plug CP 2.

According to the present embodiment, by combining the resistance value of the bit line BL and the resistance value of the contact plug CP2 described above, it is possible to suppress variations in the resistance value of the column selection circuit-cell wiring path due to the length of the bit line BL.

Of course, the 1 st to 4 th modifications of the 1 st embodiment, the 2 nd embodiment, and the 2 nd modification of the 2 nd embodiment can be applied to the contact plugs CP1 and CP2 included in the memory device 1 of the present embodiment.

6. Embodiment 6

A storage device according to embodiment 6 will be described. In the memory device 1 according to embodiment 6, the structure of the contact plug CP2 is different from that of embodiment 3. In the following description, the same components as those in embodiment 3 will be omitted, and mainly the different components from embodiment 3 will be described.

6.1 memory cell array Structure

The cross-sectional structure of the memory cell array 10 will be described with reference to fig. 30 and 31. Fig. 30 is a cross-sectional view taken along line I-I of fig. 23. Fig. 31 is a sectional view taken along line II-II of fig. 23. In addition, the insulating layer is omitted in the examples shown in fig. 30 and 31.

As shown in fig. 30 and 31, the contact plug CP2 of the region R4w includes a conductor 37a. The contact plugs CP2 of the regions R0w to R3w each include conductors 37a and 37b. The conductor 37a is made of the same material as the conductor 33 a. The conductor 37b is made of the same material as the conductor 33 b.

The ratio of the conductors 37b included in the contact plugs CP2 in the regions R0w to R3w is lower as the contact plugs CP2 are provided in the region closer to the column selection circuit 15. The height of the conductor 37b included in each of the contact plugs CP2 in the regions R0w to R3w is lower as the contact plug CP2 is provided in the region closer to the column selection circuit 15. The conductor 37b is provided on the conductor 37a. Further, the conductor 37a may be provided on the conductor 37b. The contact plugs CP2 in the regions R0w to R3w may be composed of 3 or more conductors having different resistivities. The conductors 37a and 37b may also contain two or more materials.

6.2 effects according to the present embodiment

According to embodiment 6, the same effects as those of embodiment 1 are achieved. In addition, according to the present embodiment, the same effects as those of embodiment 5 are achieved. Of course, the 1 st to 4 th modifications of the 1 st embodiment and the 2 nd and 2 nd modifications of the 2 nd embodiment can be applied to the contact plugs CP1 and CP2 included in the memory device 1 of the present embodiment.

7. Modification and the like

As described above, the memory device according to the embodiment includes the 1 st Memory Cell (MC), the 2 nd Memory Cell (MC), the 1 st circuit (14) that supplies write currents to the 1 st memory cell and the 2 nd memory cell, the 1 st Wiring (WL) connected to the 1 st circuit, the 1 st plug (CP 1) that electrically connects the 1 st memory cell and the 1 st wiring, and the 2 nd plug (CP 1) that electrically connects the 2 nd memory cell and the 1 st wiring. The length of the 1 st Wiring (WL) from the 1 st circuit to the 1 st plug is shorter than the length of the 1 st Wiring (WL) from the 1 st circuit to the 2 nd plug. The resistance value of the 1 st plug (CP 1) is higher than the resistance value of the 2 nd plug (CP 1).

The embodiments are not limited to the above-described embodiments, and various modifications are possible.

The flowcharts described in the above embodiments can be changed in order of processing as long as they are applicable.

In the above embodiments, the description has been made mainly of the case where the structure (referred to as a single-layer structure) of one memory cell MC can be selected by the group of one word line WL and one bit line BL with respect to the memory cell MC, but the present invention is not limited thereto. For example, any array structure such as an array structure having a structure in which a plurality of these structures are stacked in the Z direction may be applied.

While the present invention has been described with reference to several embodiments, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. The present invention is not limited to the above embodiments and modifications, and is intended to be included in the scope and spirit of the present invention.

Claims

1. A storage device is provided with:

A 1 st storage unit;

a 2 nd memory cell;

a 1 st circuit that supplies write currents to the 1 st memory cell and the 2 nd memory cell;

a 1 st wiring connected to the 1 st circuit;

a 1 st plug electrically connecting the 1 st memory cell and the 1 st wiring; and

a 2 nd plug electrically connecting the 2 nd memory cell and the 1 st wiring,

the length of the 1 st wiring from the 1 st circuit to the 1 st plug is shorter than the length of the 1 st wiring from the 1 st circuit to the 2 nd plug,

the resistance value of the 1 st plug is higher than that of the 2 nd plug.

2. The storage device according to claim 1,

the 1 st plug includes a 1 st conductor and a 2 nd conductor,

the 2 nd plug includes a 3 rd conductor and a 4 th conductor,

the resistivity of the 2 nd conductor is lower than the resistivity of the 1 st conductor,

the 4 th conductor has a lower resistivity than the 3 rd conductor,

the 1 st plug includes the 2 nd conductor at a lower ratio than the 4 th conductor included in the 2 nd plug.

3. The storage device according to claim 2,

the 1 st conductor and the 3 rd conductor comprise at least one of tungsten, tungsten nitride, titanium nitride, carbon, and polysilicon,

The 2 nd conductor and the 4 th conductor include at least one of copper and aluminum.

4. The storage device according to claim 2,

the 1 st conductor and the 3 rd conductor comprise at least one of carbon and polysilicon,

the 2 nd conductor and the 4 th conductor include at least one of tungsten, tungsten nitride, titanium, and titanium nitride.

5. The storage device according to claim 2,

the 1 st conductor and the 3 rd conductor comprise a 1 st semiconductor,

the 2 nd conductor and the 4 th conductor comprise a 2 nd semiconductor,

the 1 st semiconductor has an impurity concentration lower than that of the 2 nd semiconductor.

6. The storage device according to claim 2,

the 2 nd conductor is disposed on the 1 st conductor,

the 4 th conductor is disposed on the 3 rd conductor.

7. The storage device according to claim 1,

the 1 st plug comprises a 1 st semiconductor,

the 2 nd plug comprises a 2 nd semiconductor,

8. The storage device according to claim 1,

the area of the 1 st plug in contact with the 1 st wiring is smaller than the area of the 2 nd plug in contact with the 1 st wiring.

9. The storage device according to claim 8,

the cross-sectional shapes of the 1 st plug and the 2 nd plug are circular.

10. The storage device according to claim 9,

the 1 st plug has a smaller diameter than the 2 nd plug.

11. The storage device according to claim 1,

the 1 st memory cell and the 2 nd memory cell are arranged above the 1 st wiring.

12. The storage device according to claim 1,

the 1 st wiring is disposed above the 1 st memory cell and the 2 nd memory cell.

13. The storage device according to claim 1, further comprising:

a 3 rd storage unit;

a 4 th storage unit;

a 3 rd plug electrically connecting the 3 rd memory cell and the 1 st wiring; and

a 4 th plug electrically connecting the 4 th memory cell and the 1 st wiring,

the length of the 1 st wiring from the 1 st circuit to the 3 rd plug is longer than the length of the 1 st wiring from the 1 st circuit to the 1 st plug and shorter than the length of the 1 st wiring from the 1 st circuit to the 2 nd plug,

the length of the 1 st wiring from the 1 st circuit to the 4 th plug is longer than the length of the 1 st wiring from the 1 st circuit to the 2 nd plug,

The resistance value of the 3 rd plug is equal to the resistance value of the 1 st plug,

the resistance value of the 4 th plug is equal to the resistance value of the 2 nd plug.

14. The storage device according to claim 13,

the 1 st plug includes a 1 st conductor and a 2 nd conductor,

the 2 nd plug includes a 3 rd conductor and a 4 th conductor,

the 3 rd plug includes a 5 th conductor and a 6 th conductor,

the 4 th plug includes a 7 th conductor and an 8 th conductor,

the 4 th conductor has a lower resistivity than the 3 rd conductor,

the 1 st plug includes a lower ratio of the 2 nd conductor than the 2 nd plug includes a lower ratio of the 4 th conductor,

the resistivity of the 5 th conductor is equal to the resistivity of the 1 st conductor,

the resistivity of the 6 th conductor is equal to the resistivity of the 2 nd conductor,

the resistivity of the 7 th conductor is equal to the resistivity of the 3 rd conductor,

the resistivity of the 8 th conductor is equal to the resistivity of the 4 th conductor,

the ratio of the 6 th conductor included in the 3 rd plug is equal to the ratio of the 2 nd conductor included in the 1 st plug,

The ratio of the 8 th electrical conductor included in the 4 th plug is equal to the ratio of the 4 th electrical conductor included in the 2 nd plug.

15. The storage device according to claim 13,

the area of the 1 st plug in contact with the 1 st wiring is smaller than the area of the 2 nd plug in contact with the 1 st wiring,

the area of contact of the 3 rd plug with the 1 st wiring is equal to the area of contact of the 1 st plug with the 1 st wiring,

the area of the 4 th plug in contact with the 1 st wiring is equal to the area of the 2 nd plug in contact with the 1 st wiring.

16. The storage device according to claim 1, further comprising:

a 5 th storage unit;

a 6 th storage unit;

a 2 nd circuit that supplies write currents to the 5 th memory cell and the 6 th memory cell;

a 2 nd wiring connected to the 2 nd circuit;

a 5 th plug electrically connecting the 5 th memory cell and the 2 nd wiring; and

a 6 th plug electrically connecting the 6 th memory cell and the 2 nd wiring,

the length of the 2 nd wiring from the 2 nd circuit to the 5 th plug is shorter than the length of the 2 nd wiring from the 2 nd circuit to the 6 th plug,

The resistance value of the 5 th plug is higher than that of the 6 th plug.

17. The storage device according to claim 16,

the 2 nd wiring is disposed above the 5 th memory cell and the 6 th memory cell.

18. The storage device according to claim 16,

the 5 th memory cell and the 6 th memory cell are disposed above the 2 nd wiring.

19. The storage device according to claim 1,

the 1 st memory cell and the 2 nd memory cell include variable resistance elements.

20. The storage device according to claim 19,

the variable resistive element is a magnetoresistance effect element.