TW202339444A - Electronic device and key scan method thereof - Google Patents

Abstract

An electronic device and a key scan method thereof are provided herein. The electronic device includes an input module and a processing module. The input module includes a plurality of key circuits arranged in an array, and each key circuit is configured to transform from turn-off state into turn-on state in response to a user input. The key scan method includes: during a detection period, by the processing module, calculating an output number of each row of the key circuits; by the processing module, calculating at least one voltage threshold according to the output number of each row of the key circuits; and during a scan period, by the processing module, comparing each row of return signals with the at least one voltage threshold to confirm the position of the key circuits which receive the user input.

Description

Electronic device and key scanning method

The present disclosure relates to an electronic device, and in particular, to an electronic device with a keyboard and a key scanning method thereof.

Keyboards of commercially available electronic devices are usually designed in a key matrix manner. Taking a 4x4 key matrix as an example, when three of the keys are pressed at the same time, the keyboard should theoretically generate three corresponding signals. However, keyboards usually generate four signals due to the interconnected matrix circuits, causing the electronic device to mistakenly believe that four keys are pressed. Among them, the key that is not actually pressed but is mistakenly thought to be pressed is a ghost key. . Therefore, it is necessary to improve the keyboard of the existing electronic device.

One aspect of the present disclosure is an electronic device. The electronic device includes an input module and a processing module. The input module includes a plurality of reference resistors and a plurality of key circuits arranged in an array. Each reference resistor is coupled to a corresponding column of the key circuits. Each key circuit includes a switch and a resistor connected in series. , and each switch is configured to transition from an off state to an on state in response to a user input. The processing module is coupled to the key circuits through a plurality of scan lines and a plurality of retrace lines, and is used to perform the following steps: during a detection period, calculate an output number of the key circuits in each column. ; Calculate at least one voltage threshold based on the output number of the key circuits in each column; and during a scanning period after the detection period, combine a plurality of retrace signals output through the retrace lines with the at least A voltage threshold is compared to confirm the positions of the key circuits that receive input from the user.

Another aspect of this disclosure is a button scanning method. The key scanning method is suitable for an electronic device, wherein the electronic device includes a processing module and an input module. The input module includes a plurality of reference resistors and a plurality of key circuits arranged in an array. Each reference resistor is coupled to In a corresponding column of the key circuits, each key circuit includes a switch and a resistor connected in series. Each switch is used to change from an off state to an on state in response to a user input. The processing module The key circuits are coupled to the key circuits by a plurality of scan lines and a plurality of retrace lines, and the key scanning method includes: during a detection period, using the processing module to calculate the key circuits of each column. an output quantity; through the processing module, calculate at least one voltage threshold value according to the output quantity of the key circuits in each column; and during a scanning period after the detection period, through the processing module, A plurality of retrace signals output through the retrace lines are compared with the at least one voltage threshold to confirm the positions of the key circuits that receive input from the user.

By setting the reference resistor and resistance in the input module, the electronic device of the present disclosure can calculate the appropriate key circuit for each column based on the number of keys pressed by the user each time (which affects the number of key circuits that generate output signals). The voltage threshold is used to filter out the signals output by the button circuit that are not actually pressed. In this way, the electronic device of the disclosure can avoid ghost keys.

The following is a detailed description of the embodiments together with the accompanying drawings. However, the specific embodiments described are only used to explain the present case and are not used to limit the present case. The description of the structural operations is not intended to limit the order of execution. Any components Recombining the structure to produce a device with equal functions is within the scope of this disclosure.

Unless otherwise noted, the terms used throughout the specification and patent application generally have their ordinary meanings as used in the field, in the disclosure and in the specific content.

As used herein, “coupling” or “connection” may refer to two or more components that are in direct physical or electrical contact with each other, or that are in indirect physical or electrical contact with each other. It may also refer to two or more components that are in direct physical or electrical contact with each other. Components interact or act with each other.

For the convenience of explanation, the uppercase English indexes 1~N in the component numbers used in the description and drawings of this case are only for the convenience of referring to individual components, and are not intended to limit the number of the aforementioned components to a specific number. In the description and drawings of this case, if a certain component number is used without specifying the index of the component number, it means that the component number refers to any unspecific component in the component group to which it belongs. For example, the component number CL[0] refers to the scan line CL[0], while the component number CL refers to any unspecified scan line among the scan lines CL[0]~CL[N].

Please refer to FIG. 1 , which is a schematic diagram of an electronic device 100 according to some embodiments of the present disclosure. In some embodiments, the electronic device 100 includes a processing module 110 and an input module 120 . As shown in FIG. 1 , the electronic device 100 may be a computer device with a keyboard (for example, a notebook computer, a mobile device, a remote control, a phone, etc. in FIG. 1 ). It should be understood that the processing module 110 can be implemented by a microprocessor, and the input module 120 can be implemented by a keyboard. In other embodiments, the processing module 110 is configured within the input module 120 (ie, the keyboard). That is, the input module 120 includes the processing module 110 .

Please refer to FIG. 2 , which is a schematic circuit diagram of an electronic device 100 according to some embodiments of the present disclosure. In some embodiments, the input module 120 includes a plurality of key circuits K arranged in an array to form multiple keys on the electronic device 100 . To simplify the explanation, in Figure 2, only the key circuit K[6,N] in the 7th column and row (N+1) is marked as a representative, where N is a positive integer greater than 0, and the number of rows of the key circuit K is is (N+1). In this embodiment, the input module 120 in Figure 2 has 7*(N+1) key switches K, but the disclosure is not limited thereto. As shown in Figure 2, each key circuit K includes a resistor R and a switch SW connected in series. For example, the key circuit K[6,N] includes a resistor R[6,N] and a switch SW[6,N], and the resistor R[6,N] and the switch SW[6,N] are connected in series. Specifically, the resistor R can be implemented by a thin film resistor, and the switch SW can be implemented by a mechanical switch or a membrane switch.

In some embodiments, as shown in FIG. 2 , the electronic device 100 further includes a plurality of retrace lines RL and a plurality of scan lines CL arranged vertically and staggered with each other. The processing module 110 is coupled to a plurality of first ends of the key circuit K in the same column (that is, one end directly coupled to the resistor R) through a corresponding retrace line RL, and is coupled through a plurality of scan lines CL. A plurality of second terminals of the key circuit K in the same column (ie, one terminal directly coupled to the switch SW). For example, the retrace line RL[0] is coupled to the (N+1) first ends of the (N+1) key circuits K in the first column, and the plurality of scan lines CL[0]~CL[ N] are respectively coupled to the (N+1) second terminals of the (N+1) key circuits K in the first column. The settings of the key circuit K of the remaining columns can be deduced in the same way, so they will not be described in detail here. It can be seen that each key circuit K is coupled between the corresponding retrace line RL and the corresponding scan line CL.

In some embodiments, as shown in FIG. 2 , the input module 120 further includes a plurality of reference resistors Rfb. One end of each reference resistor Rfb is coupled to a plurality of first ends of the key circuit K in the same column, and the other end of each reference resistor Rfb is coupled to a ground terminal. For example, one end of the reference resistor Rfb[0] is coupled to the (N+1) first ends of the (N+1) key circuits K in the first column, and the other end of the reference resistor Rfb[0] is coupled to ground. The settings of the remaining reference resistors Rfb[1]~Rfb[6] can be deduced in the same way, so they will not be repeated here. It can be seen that each reference resistor Rfb is coupled to a corresponding column in the plurality of key circuits K.

In some embodiments, each switch SW (or each key circuit K) is configured to transition from an off state to an on state in response to receiving a user input (eg, a pressing action performed by the user). For example, when the user presses the keys corresponding to the switches SW[0,0] and SW[0,1] on the electronic device 100, the switches SW[0,0] and SW[0,1] will be turned off. The state changes to a conductive state, and then at least one loop is formed with the processing module 110 through the corresponding retrace line RL[0] and the scan lines CL[0]~CL[1]. Specifically, when the switch SW[0,0] is turned on, the signal can be output from the processing module 110 and pass through the scan line CL[0], the switch SW[0,0], the resistor R[0,0] and the return signal in sequence. The line RL[0] is swept and input to the processing module 110 . When the switch SW[0,1] is turned on, the signal can be output from the processing module 110 and pass through the scan line CL[1], the switch SW[0,1], the resistor R[0,1] and the retrace line RL[ 0], and input to the processing module 110. That is to say, at this time, the processing module 110 can send and receive signals through the retrace line RL[0] and the scan lines CL[0]~CL[1]. In addition, the remaining switches SW corresponding to the unpressed keys remain in the off state and cannot transmit the signal output by the processing module 110 through the scan line CL back to the processing module 110 .

In some embodiments, as shown in FIG. 2 , the processing module 110 further includes an analog-to-digital converter (ADC) 112 . The analog-to-digital converter 112 is coupled to a plurality of retrace lines RL, and is used to receive signals output by a plurality of key circuits K through the retrace lines RL for subsequent processing. The operation of the analog-to-digital converter 112 will be described in detail in subsequent paragraphs.

Please refer to FIG. 3 , which is a flow chart of a key scanning method 200 of the electronic device 100 according to some embodiments of the present disclosure. The key scanning method 200 can be executed by the processing module 110 in Figure 1 or 2, so that the processing module 110 can determine whether multiple keys on the electronic device 100 are actually pressed and can find out whether the keys are pressed. exact location. It should be understood that the key scanning method 200 of the present disclosure is also applicable to general keyboard devices and is not limited to the electronic device 100 . In some embodiments, the key scanning method 200 includes multiple steps S201 to S203. For convenience and clear explanation, the key scanning method 200 will be explained in detail below with reference to Figures 4 to 8.

Please refer to FIG. 4 , which is a key scanning timing diagram of the electronic device 100 according to some embodiments of the present disclosure. In some embodiments, as shown in FIG. 4 , in order to prevent the processing module 110 from misjudging a button that is not actually pressed as being pressed (i.e., a ghost key), a complete key scan cycle of the electronic device 100 includes a A detection period P1, a scanning period P2 and a non-scanning period P3.

In step S201, the processing module 110 calculates an output quantity of the key circuit K of each column during the detection period P1. Step S201 will be explained in detail below with reference to Figures 5, 6 and 7A~7B.

Please refer to Figures 5, 6 and 7A first. Figure 5 is a schematic diagram of the operation of the electronic device 100 during the detection period P1 according to some embodiments of the present disclosure. Figure 6 is a schematic diagram of the operation of the electronic device 100 during the detection period P1 according to some embodiments of the present disclosure. The circuit schematic diagram of the electronic device 100 at a time point t1 during the detection period P1 is shown, and FIG. 7A is a circuit diagram of the electronic device 100 at a time point t2 during the detection period P1 according to some embodiments of the present disclosure. Circuit diagram. For convenience of explanation, in the embodiments of Figures 6 and 7, a plurality of key circuits K are arranged in a 3x3 array (ie, including 9 key circuits K), but the arrangement of the plurality of key circuits K in this disclosure is not based on The diagram shows the limit. In addition, to simplify the explanation, Figure 5 only shows two scan lines CL[0]~CL[1] and two retrace lines RL[0]~RL[1] (i.e., scan line CL[2] and retrace line RL[2] are omitted).

In one of the scanning cycles of the electronic device 100, as shown in FIG. 6, the user presses three buttons corresponding to the three button circuits K[0,0], K[1,0] and K[1,1]. , making three key circuits K[0,0], K[1,0] and K[1,1] (or three switches SW[0,0], SW[1,0] and SW[1,1 ]) transitions from the off state to the on state in response to user input.

In some embodiments, the processing module 110 sequentially outputs corresponding scan signals to a plurality of scan lines CL during the detection period P1, and receives corresponding retrace signals through a plurality of retrace lines RL. For example, as shown in Figures 5 and 6, the processing module 110 outputs a scan signal Vscan[0] to the key circuit K in the first row through the scan line CL[0] at time point t1. At this time, as shown in Figure 6, since only the switches SW[0,0] and SW[1,0] in the key circuit K in the first row are turned on, the voltage value of the scanning signal Vscan[0] is not only based on the reference resistor The resistance values of Rfb[0] and resistor R[0,0] are distributed between the reference resistor Rfb[0] and resistor R[0,0], so that a voltage value Vr0(t1) is generated between the reference resistor Rfb[0] and resistor R[0,0]. The node between the resistors R[0,0] is also allocated to the reference resistor Rfb[1] and the resistor R[1,0] according to the resistance values of the reference resistor Rfb[1] and the resistor R[1,0], so that Another voltage value Vr1(t1) is generated at the node between the reference resistor Rfb[1] and the resistor R[1,0]. Accordingly, as shown in Figure 5, at time point t1, the processing module 110 receives the retrace signal Vread[0] with the voltage value Vr0(t1) through the retrace line RL[0], and uses the retrace line RL[0] to Line RL[1] receives the retrace signal Vread[1] with voltage value Vr1(t1). In addition, since the switch SW[2,0] of the first row of the third column remains open, the processing module 110 may receive a retrace signal of approximately 0 volts through the retrace line RL[2] at the time point t1 ( Not shown in the picture).

In this embodiment, the resistance values of the reference resistors Rfb[0]~Rfb[1] and the resistors R[0,0] and R[1,0] are all 1 ohm, and the scan signal Vscan[0] The voltage value at time point t1 is 3.3 volts (volt). Accordingly, the voltage value Vr0(t1) is 1.65 volts, and the voltage value Vr1(t1) is also 1.65 volts. It should be understood that the above numerical values are only used as examples and the present disclosure is not limited thereto.

As shown in Figures 5 and 7A, the processing module 110 outputs another scan signal Vscan[1] to the key circuit K in the second row through the scan line CL[1] at time point t2. At this time, as shown in Figure 7A, although only the switch SW[1,1] in the key circuit K in the second row is turned on, because the two switches SW[0,0] and SW[ 1,0], causing the processing module 110 to receive the retrace signal Vread[0] with the voltage value Vr0(t2) through the two retrace lines RL[0] and RL[1] respectively at the time point t2. Retrace signal Vread[1] with voltage value Vr1(t2). In addition, the processing module 110 may also receive a retrace signal of approximately 0 volts through the retrace line RL[2] at time point t2 (not shown in the figure). The generation of voltage values Vr0(t2) and Vr1(t2) will be described in detail below with reference to Figure 7B.

Please refer to FIG. 7B , which is a schematic equivalent circuit diagram of the input module 120 of FIG. 7A according to some embodiments of the present disclosure. As shown in Figure 7B, the voltage value of the scan signal Vscan[1] will be based on the resistor R[1,1] and an equivalent resistor Req (which is equivalent to the reference resistors Rfb[0] and Rfb[1] and the resistor R [1,0] and R[0,0] are connected in series and parallel), so that the voltage value Vr1(t2) is generated from the reference resistor Rfb[1] and the resistors R[1,1] and R[1, 0] nodes. Then, the voltage value Vr1(t2) will be distributed according to the resistance values of the reference resistor Rfb[0] and the resistors R[1,0] and R[0,0], so that the voltage value Vr0(t2) is generated from the reference resistor Rfb[0 ] and the node between resistor R[0,0].

In this embodiment, the resistance values of the reference resistors Rfb[0]~Rfb[1] and the resistors R[0,0], R[1,0] and R[1,1] are all 1 ohm, and the scanning signal The voltage value of Vscan[1] at time point t2 is 3.3 volts. Accordingly, the voltage value Vr0(t2) is 0.47 volts, and the voltage value Vr1(t2) is 1.41 volts. It should be understood that the above numerical values are only used as examples and the present disclosure is not limited thereto.

At another time point (not shown in the figure) after time points t1 and t2, the processing module 110 also outputs the corresponding scan signal (not shown in the figure) through the scan line CL[2] to the key circuit of the third row. K[0,2], K[1,2] and K[2,2]. At this time, since the switches SW[0,2], SW[1,2] and SW[2,2] in the third row remain off, the processing module 110 passes through the retrace lines RL[0]~RL[ 2] A retrace signal of approximately 0 volts may be received (not shown in the figure).

After the processing module 110 receives the retrace signal Vread of each column, the analog-to-digital converter 112 in the processing module 110 compares the voltage value of the retrace signal Vread of each column at each time point with an initial voltage threshold value Vinit. Compare, and output a first logical value or a second logical value based on the comparison result. It should be understood that the first logic value and the second logic value may be different from each other (eg, the first logic value is "1" and the second logic value is "0"). It should be understood that the initial voltage threshold value Vinit can be pre-stored in a memory (not shown) included in the processing module 110 or the electronic device 100, where the memory can be implemented by a register or a memory.

The operation of the analog-to-digital converter 112 will be described below using the aforementioned numerical values as examples. Assume that the initial voltage threshold Vinit ranges from 0.1 to 0.37 volts. At time point t1, the voltage value of the retrace signal Vread[0] is 1.65 volts (ie, Vr0(t1)) and is higher than or equal to the initial voltage threshold Vinit, and the voltage value of the retrace signal Vread[1] is 1.65 volts. (i.e., Vr1(t1)) and is higher than or equal to the initial voltage threshold Vinit, and the voltage value of the retrace signal output by the retrace line RL[2] is approximately 0 volts and lower than the initial voltage threshold Vinit. Accordingly, the analog-to-digital converter 112 will output the results of “1”, “1” and “0” at time point t1. Based on this result, the processing module 110 can determine that among the key circuits K in the first row, only the key circuits K[0,0] and K[1,0] generate output signals, while the key circuit K[2,0] does not. Generate an output signal.

At time point t2, the voltage value of the retrace signal Vread[0] is 0.47 volts (ie, Vr0(t2)) and is higher than or equal to the initial voltage threshold Vinit, and the voltage value of the retrace signal Vread[1] is 1.41 Volts (i.e., Vr1(t2)) and is higher than or equal to the initial voltage threshold Vinit, and the voltage value of the retrace signal output by the retrace line RL[2] is approximately 0 volts and lower than the initial voltage threshold Vinit. Accordingly, the analog-to-digital converter 112 will output the results of “1”, “1” and “0” at time point t2. Based on this result, the processing module 110 can determine that among the key circuits K in the second row, only the key circuits K[0,1] and K[1,1] generate output signals, while the key circuit K[2,1] does not. Generate an output signal.

At another time point after time points t1 and t2 (not shown in the figure), the voltage values of the retrace signals output by the multiple retrace lines RL[0]~RL[2] are all about 0 volts and lower than Initial voltage threshold Vinit. Accordingly, the analog-to-digital converter 112 will output results of “0”, “0” and “0” at another time point after time points t1 and t2. The processing module 110 can determine based on this result that none of the key circuits K[0,2], K[1,2], and K[2,2] in the third row generate an output signal.

It can be seen from the above description that after sequentially scanning the key circuits K of each row, the processing module 110 can generate a detection of whether each of the key circuits K of each column generates an output signal through the analog-to-digital converter 112 . Measurement results (for example: the 3x3 matrix shown in Figure 5). Although the key circuit K[0,1] in column 1 and row 2 is judged to have an output signal during the detection period P1 (because its corresponding logic value is "1"), the user has not actually pressed the key corresponding to The keys of the key circuit K[0,1] in row 2 and column 1 (i.e., ghost keys). Specifically, during the detection period P1, the processing module 110 only determines whether the key circuit K generates an output signal, but does not determine whether the output signal generated by the key circuit K is a ghost key signal.

Then, the processing module 110 adds multiple logical values corresponding to the plurality of key circuits K in the same column in the detection results to calculate the output number of the key circuits K in each column. For example, as shown in Figure 5, the output quantity Nr[0] of the key circuit K in the first column is 2, the output quantity Nr[1] of the key circuit K in the second column is 2, and the output quantity Nr[1] of the key circuit K in the third column is 2. The output number Nr[2] of the key circuit K is 0. It should be understood that the detection results and the output number of the key circuit K of each column can be stored in the processing module 110 or the memory of the electronic device 100 after being calculated. After calculating the output number of the key circuit K in each column, the processing module 110 may execute step S202.

In step S202, the processing module 110 calculates the voltage threshold value Vth[M] corresponding to the key circuit K in each column according to the output number of the key circuit K in each column. In some embodiments, the processing module 110 calculates the voltage threshold Vth[M] corresponding to the key circuit K of each column through a calculation formula. For example, the calculation formula can be expressed as the following formula (1): …(1) Among them, Vth[M] is the voltage threshold value corresponding to the key circuit K of each column, Vsc is the voltage value of the scanning signal Vscan, Rk is the resistance value of the resistor R in the key circuit K, and P[M] is a parameter associated with the number of outputs of the key circuit K in each column.

In some embodiments, the parameter P[M] can be expressed by the following formula (2): ...(2) Among them, Nr[M] is the output number of the key circuit K in each column, and Rref is the resistance of the reference resistor Rfb.

In some embodiments, M is a positive integer greater than 0, and the maximum value of M is the number of columns of the key circuit K minus 1. For example, in the embodiment of Figure 6 or 7, M in formulas (1) and (2) can be 0, 1 or 2.

The following will take the above-mentioned values and the output quantities Nr[0]~Nr[2] shown in Figure 5 as examples for explanation. The voltage value Vsc of the scan signal Vscan is 3.3 volts, the output number Nr[0] of the key circuit K in the first column is 2, the resistance Rk of the resistor R in the key circuit K is 1 ohm, and the resistance Rref of the reference resistor Rfb Also 1 ohm. Through the above formula (2), the processing module 110 can calculate that the parameter P[0] associated with the output quantity Nr[0] of the key circuit K in the first column is 0.5. Next, through the above formula (1), the processing module 110 can calculate that the voltage threshold Vth[0] corresponding to the key circuit K in the first column is 1.1 volts (this is the first voltage threshold). By analogy, the processing module 110 can also calculate that the voltage threshold Vth[1] corresponding to the key circuit K in the second column is 1.1 volts (this is the second voltage threshold). In addition, since the output number Nr[2] of the key circuit K in the third column is 0, the processing module 110 can use the initial voltage threshold Vinit as the voltage threshold Vth corresponding to the key circuit K in the third column.

During the detection period P1, the key circuit K of each column corresponds to the initial voltage threshold Vinit, so the analog-to-digital converter 112 compares the voltage value of the retrace signal Vread at each time point with the initial voltage threshold Vinit. After calculating the voltage threshold value Vth[M] corresponding to the key circuit K of each column, the processing module 110 can set the analog-to-digital converter 112 so that the key circuit K of each column corresponds to a voltage threshold value Vth[ M]. It should be understood that the voltage threshold Vth[M] corresponding to the key circuit K of each column can be stored in the processing module 110 or the memory of the electronic device 100 after being calculated.

Next, step S203 is executed. In step S203, the processing module 110 compares the retrace signal Vread of each column with the corresponding voltage threshold Vth[M] during the scanning period P2 to confirm the position of the key circuit K that receives the user input. Step S203 will be explained in detail below with reference to Figure 8.

Please refer to FIG. 8 , which is a schematic diagram of the operation of the electronic device 100 during the scanning period P2 according to some embodiments of the present disclosure. Similar to the operation during the detection period P1, the processing module 110 sequentially outputs corresponding scan signals to the plurality of scan lines CL during the scan period P2, and receives corresponding retrace signals through the plurality of retrace lines RL. As shown in Figure 8, at a time point t3 in the scanning period P2, the processing module 110 outputs the scanning signal Vscan[0] (the voltage value of which can be, for example, 3.3 volts) to the first line through the scanning line CL[0]. The key circuit K receives two retrace signals Vread[0] and Vread[1] through two retrace lines RL[0] and RL[1] respectively (the voltage values thereof can be, for example, 1.65 volts respectively). At a time point t4 in the scanning period P2, the processing module 110 outputs the scanning signal Vscan[1] (the voltage value of which can be, for example, 3.3 volts) to the key circuit K in the second row through the scanning line CL[1], and respectively Two retrace signals Vread[0] and Vread[1] are received through two retrace lines RL[0] and RL[1] (the voltage values thereof may be, for example, 0.47 and 1.41 volts respectively).

Then, the analog-to-digital converter 112 in the processing module 110 compares the voltage value of the retrace signal Vread of the same column at each time point with the corresponding voltage threshold value Vth[M], and outputs the first value based on the comparison result. A logical value (for example: "1") or a second logical value (for example: "0"). As explained above, the voltage threshold Vth[0] corresponding to the key circuit K in the first column is 1.1 volts. Therefore, the analog-to-digital converter 112 converts the retrace signal Vread[0] of 1.65 volts and the retrace signal Vread[0] of 1.1 volts at time point t3. The voltage threshold value Vth[0] is compared and outputs "1" (because the voltage value of the retrace signal Vread[0] at time point t3 is higher than or equal to the voltage threshold value Vth[0]), and the voltage value at time point t4 is The retrace signal Vread[0] of 0.47 volts is compared with the voltage threshold Vth[0] of 1.1 volts and outputs "0" (because the voltage value of the retrace signal Vread[0] at time point t4 is lower than the voltage threshold Vth[0]).

In addition, the voltage threshold Vth[1] corresponding to the key circuit K in the second column is 1.1 volts. Therefore, the analog-to-digital converter 112 converts the retrace signal Vread[1] of 1.65 volts to the voltage threshold of 1.1 volts at time point t3. The value Vth[1] is compared and outputs "1" (because the voltage value of the retrace signal Vread[1] at time point t3 is higher than or equal to the voltage threshold value Vth[1]), and 1.41 volts is converted to 1.41 volts at time point t4. The retrace signal Vread[1] is compared with the voltage threshold Vth[1] of 1.1 volts and outputs "1" (because the voltage value of the retrace signal Vread[1] at time point t4 is higher than or equal to the voltage threshold Vth[1]). The operations of other columns can be deduced in the same way, so we will not go into details here. Accordingly, the processing module 110 can obtain a scan result (for example: the 3x3 matrix shown in Figure 8). It should be understood that the present disclosure is not limited to the above numerical values. The multiple voltage thresholds Vth[M] corresponding to the key circuit K of each column may be all the same or different, or may be partially the same and partially different.

It can be seen from the above description that during the detection period P1, the processing module 110 determines that the key circuit K[0,1] in the first column and the second row has an output signal, but the key circuit K[0,1] in the first column and the second row ] does not actually receive user input. It is worth noting that during the scanning period P2, by replacing or updating the initial voltage threshold Vinit with the voltage threshold Vth[0] corresponding to the key circuit K[0,1] in the first column, the processing module 110 determines The key circuit K[0,1] in column 1 and row 2 has no output signal (because its corresponding logic value is "0"), thus confirming that there are actually only three key circuits K[0,0] and K[ 1,0] and K[1,1] receive user input. It should be understood that this judgment result is consistent with the user's actual operation. That is to say, the scanning results generated by the processing module 110 during the scanning period P2 can reflect the actually pressed keys and their positions.

As shown in FIG. 4 , after the processing module 110 generates a scan result, the processing module 110 can transmit the scan result to a host unit (not shown in the figure) of the electronic device 100 during the non-scan period P3, so that the host unit can Relevant operations are performed according to the buttons pressed by the user. In some embodiments, the host unit may be implemented by one or more central processing units (CPUs). In addition, as shown in FIG. 3 , when the user changes the button he presses again, the processing module can enter the next scan cycle (ie, start execution from step S201 again).

In some embodiments, in order to avoid the physical bounce (bounce) caused by the button being pressed from affecting the scanning results, the processing module 110 only confirms the scanning results when several identical scanning results are obtained continuously during the scanning period P2. . It should be understood that each scan result generated can be stored in the processing module 110 or the memory of the electronic device 100 for the processing module 110 to compare and confirm the scan results. In addition, if the two scan results are different, the processing module 110 may end the current scan cycle and enter the next scan cycle (ie, start execution from step S201 again).

It can be seen from the above embodiments of the present disclosure that by setting the reference resistor Rfb and the resistor R in the input module 110, the electronic device 100 of the present disclosure can generate an output signal based on the number of keys pressed by the user each time (this affects The number of key circuits) calculates an appropriate voltage threshold for each column of key circuits to filter out signals output by key circuits that are not actually pressed. In this way, the electronic device 100 of the present disclosure can avoid ghost keys from occurring.

Although the present disclosure has been disclosed in the above embodiments, it is not intended to limit the present disclosure. Those with ordinary skill in the technical field can make various modifications and modifications without departing from the spirit and scope of the present disclosure. Therefore, this disclosure The scope of protection of the disclosed content shall be determined by the scope of the patent application attached.

100: Electronic devices 110: Processing module 112:Analog-to-digital converter 120:Input module 200:Key scanning method CL: scan line K: Button circuit RL: retrace line Rfb: reference resistor Req: equivalent resistance R: Resistor SW: switch P1: During detection P2: During scanning P3: During non-scanning period t1,t2,t3,t4: time points Nr: output quantity Vscan: scan signal Vread: retrace signal Vinit: initial voltage threshold Vth: voltage threshold Vr0(t1),Vr1(t1),Vr0(t2),Vr1(t2): voltage value S201~S203: steps

Figure 1 is a schematic diagram of an electronic device according to some embodiments of the present disclosure. FIG. 2 is a schematic circuit diagram of an electronic device according to some embodiments of the present disclosure. FIG. 3 is a flow chart of a key scanning method of an electronic device according to some embodiments of the present disclosure. FIG. 4 is a key scanning timing diagram of an electronic device according to some embodiments of the present disclosure. FIG. 5 is a schematic diagram illustrating the operation of an electronic device during detection according to some embodiments of the present disclosure. FIG. 6 is a circuit schematic diagram of an input module at a time point during the detection period according to some embodiments of the present disclosure. FIG. 7A is a circuit schematic diagram of an input module at another time point during the detection period according to some embodiments of the present disclosure. Figure 7B is a schematic equivalent circuit diagram of the input module of Figure 7A according to some embodiments of the present disclosure. FIG. 8 is a schematic diagram illustrating the operation of an electronic device during scanning according to some embodiments of the present disclosure.

Domestic storage information (please note in order of storage institution, date and number) without Overseas storage information (please note in order of storage country, institution, date, and number) without

200:Key scanning method

S201~S203: Operation

Claims (10)

An electronic device containing: An input module includes a plurality of reference resistors and a plurality of key circuits arranged in an array, wherein each reference resistor is coupled to a corresponding column of the key circuits, and each key circuit includes a switch and a series connection resistors, each switch configured to transition from an off state to an on state in response to a user input; and A processing module is coupled to the key circuits through a plurality of scan lines and a plurality of retrace lines, and is used for: During a detection period, calculate an output quantity of the key circuits in each column; Calculate at least one voltage threshold based on the output number of the key circuits in each column; and During a scanning period after the detection period, a plurality of retrace signals output through the retrace lines are compared with the at least one voltage threshold to confirm receipt of the user input of the key circuits. Location. The electronic device of claim 1, wherein the processing module includes an analog-to-digital converter, and the analog-to-digital converter is coupled to the retrace lines and used to receive the retrace lines output through the retrace lines. Retrace signal. The electronic device according to claim 2, wherein during the detection period, the processing module is used to sequentially output one of the plurality of scan signals corresponding to the scan lines, During the detection period, the analog-to-digital converter is used to compare a plurality of voltage values of each retrace signal at a plurality of time points with a pre-stored initial voltage threshold, and to generate a voltage value based on the comparison result. detection results, The processing module is used to add a plurality of logical values corresponding to the key circuits in the same column in the detection result to calculate the output number of the key circuits in each column. The electronic device of claim 2, wherein the at least one voltage threshold includes a first voltage threshold and a second voltage threshold, the first voltage threshold corresponding to a first column of the key circuits, The second voltage threshold corresponds to a second column of the key circuits. The electronic device according to claim 4, wherein during the scanning period, the processing module is used to sequentially output one of the plurality of scanning signals to the scanning lines corresponding to the scanning signal coupled to the key circuits. A first retrace line among the retrace lines of the first column outputs a first retrace signal of the retrace signals, and is coupled to the retrace lines of the second column of the key circuits. A second retrace line in the line outputs a second retrace signal of the retrace signals, The analog-to-digital converter is used to compare a first voltage value of the first retrace signal at a first time point with the first voltage threshold, and to compare the first retrace signal to a second Comparing a second voltage value at the time point with the first voltage threshold value to compare a third voltage value of the second retrace signal at the first time point with the second voltage threshold value , used to compare a fourth voltage value of the second retrace signal at the second time point with the second voltage threshold, and to generate a scan result based on the comparison result, The processing module is used to confirm the positions of the key circuits input by the user according to a plurality of logical values corresponding to the key circuits in the scan result. A key scanning method is suitable for an electronic device. The electronic device includes a processing module and an input module. The input module includes a plurality of reference resistors and a plurality of key circuits arranged in an array. Each reference resistor is coupled to Connected to a corresponding column of the key circuits, each key circuit includes a switch and a resistor connected in series. Each switch is used to change from an off state to an on state in response to a user input. The processing model The group is coupled to the key circuits through a plurality of scan lines and a plurality of retrace lines, and the key scanning method includes: During a detection period, the processing module is used to calculate an output quantity of the key circuits in each column; Using the processing module, calculate at least one voltage threshold based on the output number of the key circuits in each column; and During a scanning period after the detection period, the processing module compares a plurality of retrace signals output through the retrace lines with the at least one voltage threshold to confirm receipt of the user signal. Input the location of the key circuits. The key scanning method as described in claim 6, wherein the processing module includes an analog-to-digital converter, and the key scanning method also includes: The analog-to-digital converter receives the retrace signals output through the retrace lines. The key scanning method as described in claim 7, wherein during the detection period, calculating the output number of the key circuits in each column includes: Through the processing module, one of the plurality of scanning signals corresponding to the scanning signals is outputted to the scanning lines in sequence; Through the analog-to-digital converter, a plurality of voltage values of each retrace signal at a plurality of time points are compared with a pre-stored initial voltage threshold, and used to generate a detection result based on the comparison result; and The processing module adds a plurality of logical values corresponding to the key circuits in the same column in the detection result to calculate the output number of the key circuits in each column. The key scanning method of claim 7, wherein the at least one voltage threshold includes a first voltage threshold and a second voltage threshold, the first voltage threshold corresponding to a first column of the key circuits , and the second voltage threshold corresponds to a second column of the key circuits. The key scanning method of claim 9, wherein during the scanning period, the retrace signals output through the retrace lines are compared with the at least one voltage threshold to confirm receipt of the user input. The locations of these key circuits include: Through the processing module, one of the plurality of scan signals corresponding to the scan signals is output to the scan lines in sequence, wherein a first of the retrace lines coupled to the first column of the key circuits The retrace line outputs a first retrace signal among the retrace signals, and a second retrace line coupled to the retrace lines of the second column of the key circuits outputs the retrace signals. A second retrace signal in the signal; The analog-to-digital converter compares a first voltage value of the first retrace signal at a first time point with the first voltage threshold value, and converts the first retrace signal at a second time point. A second voltage value at the point is compared with the first voltage threshold, a third voltage value of the second retrace signal at the first time point is compared with the second voltage threshold, and the Compare a fourth voltage value of the second retrace signal at the second time point with the second voltage threshold, and generate a scan result based on the comparison result; and Through the processing module, the positions of the key circuits input by the user are confirmed based on a plurality of logical values corresponding to the key circuits in the scan result.

Images