TW202339239A - Image sensor - Google Patents

Abstract

The present description concerns an image acquisition device (1), wherein photodetectors (2) have a pattern following lines (14, 16) of interconnection of readout circuits (3) and first electrodes (27) of the photodetectors (2) have a cross-shaped pattern (57) having two branches respectively vertically in line with the lines (14, 16) interconnecting the readout circuits (3).

Description

Image sensor

The present disclosure relates generally to image capture devices or image sensors, and more specifically to organic light-based detectors.

Image capture devices containing a plurality of organic light detectors, for example organized in an array, have been provided. In some applications, the image capture device has a display screen on top or covers the display screen.

There is a need to improve known image capture devices based on organic light detectors.

Embodiments are based on organic light detectors that overcome all or part of the shortcomings of known image capture devices.

Embodiments provide an image capture device in which the photodetector has a pattern of interconnect lines that follows the readout circuit.

According to one embodiment, the first electrodes of the photodetectors have a cross-shaped pattern with branches respectively vertically aligned with the lines interconnecting the readout circuits.

According to one embodiment, the hole injection layer common to the photodetectors has a grid pattern that is vertically consistent with the lines interconnecting the readout circuits.

According to one embodiment, the active layer of each photodetector has the grid patterns of the hole injection layer.

According to one embodiment, the active layer of each photodetector has a cross-shaped pattern of its first electrode.

According to one embodiment, the active layer and the first electrode of each photodetector extend beyond the pattern.

According to an embodiment, each readout circuit includes a transistor, and the interconnection lines respectively correspond to interconnecting the sources of the transistors according to the first direction and the gates of the transistors according to the second direction. String.

According to one embodiment, the pattern upon which the photodetectors are formed is also vertically aligned with the drain contacts of the transistors of the readout circuit.

According to an embodiment, the surface area masked by the active layer of the light detectors represents for each pixel less than 50%, preferably less than 30%, of the surface area of the pixel.

The embodiments and implementation models provide a method of manufacturing an image capture device, which method includes the following steps: Formation of an array of readout circuits having transistors interconnected in source lines in a first direction and gate lines in a second direction; Deposition of a stack based on the array of readout circuits, the stack comprising at least: electrode; active layer; and Hole injection layer, The layers of the stack are etched individually or simultaneously according to a pattern that at least follows the interconnect lines of the readout circuit.

According to one embodiment, the etching of the layers of the stack causes the surface area to be increasingly masked by the electrode layer, and the active layer represents for each pixel less than 50% of the surface area of the pixel, less than Good land is less than 30%.

According to an embodiment, the active layer and the hole injection layer are etched simultaneously.

According to an embodiment, optical filters are placed on the stack.

According to one embodiment, the layers of the stack further cover the drain contacts of the transistors of the readout circuits.

According to an embodiment, the steps of the method are suitable for the manufacture of a device such as that described.

The same features have been designated by the same reference in the various drawings. Specifically, structural and/or functional elements common to different embodiments and implementation modes may be designated by the same reference numerals and may have the same structure, size, and material properties.

For purposes of clarity, only those steps and elements that are useful for understanding the described embodiments and modes of practice are described in detail. In particular, the formation of the photodetectors used to control the described devices and the electronic circuitry that reads from the photodetectors has not been described in detail. Furthermore, the various possible applications of the described transistors have not yet been described in detail.

Unless otherwise indicated, when referring to two elements connected together, this means a direct connection without any intervening elements other than conductors, and when referring to two elements coupled together, this means that both Elements may be connected, or they may be coupled via one or more other elements.

In the following disclosure, unless otherwise specified, when referring to absolute positional qualifiers such as the terms "front", "rear", "top", "bottom", "left", "right", etc., or referring to the terms such as Relative position qualifiers such as "above", "below", "upper", "lower", etc., or orientation qualifiers such as "horizontal", "vertical", etc. refer to the orientation shown in the figure.

Unless otherwise specified, the expressions "about", "approximately", "substantially" and "approximately" mean plus or minus 10% or 10°, preferably plus or minus 5% or 5°.

In the following description, visible light designates electromagnetic radiation having a wavelength in the range from 400 nm to 700 nm, and infrared radiation designates electromagnetic radiation having a wavelength in the range from 700 nm to 1 mm. Among infrared radiation, the skilled person can distinguish in particular near-infrared radiation having wavelengths in the range from 700 nm to 1.7 μm.

In the remainder of this disclosure, a layer or film is said to be transparent to radiation when the transmission of radiation through the layer or film is greater than 10%, preferably greater than 50%.

FIG. 1 partially and schematically shows an electrical diagram of an embodiment of the image capture device 1 .

The function of the image capturing device 1 is to acquire images representing radiation (visible radiation and/or infrared radiation depending on the application).

The described embodiments and modes of practice are applicable to an image capture device 1 or an image detector of the type comprising an array of photonic sensors each associated with a readout circuit 3, which photonic sensors are called photodetectors. Device 2. In Figure 1, four photodetectors and four readout circuits are shown. In practice, the image capturing device 1 includes a large number (eg, from hundreds to millions) of photodetectors 2 and readout circuits 3 . The photodetectors 2 are for example identical or similar (within manufacturing variations). Similarly, the readout circuits may be identical or similar (within manufacturing variations), for example.

Optionally, the association of the light detector 2 and its readout circuit 3 is specified by the "pixel" 12 of the image capture device 1 . However, it should be noted that depending on the application and organization of the image capture device 1 and other devices associated with the image capture device, this pixel 12 may represent sub-pixels.

In Figure 1, each photodetector 2 is symbolized in the form of a photodiode and each readout circuit 3 is symbolized in the form of a transistor. Preferably, the transistor is a thin-film transistor (TFT) that can be formed on a transparent substrate.

Each photodetector 2 includes an active layer 21 and an electron injecting layer 25 between electrodes or hole injecting layers (HIL) 23, symbolized by the anode of the photodiode in Figure 1. (electron injecting layer, EIL), and the electrode 27 symbolized by the cathode of the photodiode in Figure 1. The active layer 21 is the layer that captures the photon radiation and restores the electrical signal of the readout circuit 3 corresponding to the pixel 12 of interest via the electrode 27 of the photodetector 2 . The HIL and EIL layers facilitate the biasing of the active layer. The HIL layer can also serve as an electrode or metal electrodes can be placed on the HIL layer. The HIL layer is biased (biased) directly or through electrodes associated with the HIL layer. The photodetectors 2 are organic photodetectors (OPD), that is, the layers forming them, and especially the active layer 21, are made of organic semiconductor (OSC) materials.

The readout circuit 3 is formed in a substrate (not shown in Figure 1), and the channel area, source and drain areas, gate area of the transistor, and the contact areas of these areas are formed inside the substrate and/or on top. In the example of Figure 1, it is assumed that the drain 33 of each transistor forming the readout circuit 3 is coupled to, preferably to the cathode electrode 27 of the photodetector 2 of the pixel 12 of interest. The sources 35 of the transistors 3 of different pixels 12 are electrically coupled, preferably in columns 14 (in the orientation of Figure 1). The gates 37 of the transistors of the different pixels 12 are electrically coupled, preferably in row 16 (in the orientation of Figure 1). The ends of columns 14 and rows 16 are coupled to electronic control and interpretation circuits, not shown, which are themselves conventional. These electronic circuits are also formed, for example, on the inside and/or on the top of the substrate on which the transistors of the readout circuit 3 are formed. Biasing of the HIL layer is provided by these circuits and is distributed around the perimeter of the array layout. The orientation of column 14 and row 16 is naturally arbitrary. For simplicity, reference will be made below to gate line 16 and source line 14 . Lines 14 and 16 are preferably along two perpendicular directions.

Figure 2 is a partially simplified cross-sectional view of an embodiment of the image capture device.

In the example of FIG. 2 , the image capture device is formed by stacking layers of different properties, and the pattern for each layer is determined to represent the array layout of the photodetector 2 and the readout circuit 3 .

The stacking of layers from bottom to top in the orientation of Figure 2 includes for example: - a substrate 41 on which the readout circuit or the transistor 3 is formed on the inside and/or on the top; - one or more conductive or semiconducting layers 42, the source and drain contacts 35 and 33 of the transistor 3 and the source contact line 14 formed inside the conductive or semiconducting layer or layers; - one or a plurality of (insulating) dielectric layers 43, having the gate insulator of the transistor 3 formed therein and generally laterally insulating the patterns formed in the layer 42 from each other; - one or a plurality of conductive or semiconducting Layer 44 having the gate contacts 37 of the transistor and the gate contact line 16 formed therein; - one or more dielectric (insulating) layers 45, separating the array of readout circuits 3 from the array of photodetectors 2 and generally laterally insulating the patterns formed in layer 44 from each other; - one or a plurality of layers forming electrode 27; - Electron injecting layer 25 (EIL); - Active layer 21; - Hole injecting layer 23 (HIL).

HIL layer 23 is typically covered with a planarization layer and covered with a protective or barrier layer, symbolized by layer 46 in Figure 2 .

Finally, other layers or layers not shown may be associated with the image capture device. Such other layers or strata may be, for example: - One or more optical fibers that only allow certain wavelengths in the visible range and/or infrared region to pass through, and these wavelengths reach the HIL layer 23; - display screen; - Touch interface; and - More generally, any common component depending on the application concerned.

Among the layers forming the image capture device, some are opaque and others are more or less transparent.

In some applications, it is desirable to associate an image capture device with a display screen or to integrate the image capture device into the display screen.

An application example involves display control, that is, the use of an image capture device to control the content of a display on a screen. In this case, the radiation collected by the image capturing device is the radiation of the display screen. The image capture device is located between the screen and the user observing the screen. Display devices may be opaque, or even self-transparent (for example, a display screen integrated into a glass pane or a "heads-up" display in a motor vehicle). The display screen is above layer 46 in the stack in Figure 2.

Another application example involves an image capture device in front of a display screen, with an image detector oriented to capture an image in front of the screen, which may be transparent or opaque. The display screen is located, for example, under the substrate 41 or between the array of readout circuits 3 and the array of photodetectors 2 in the stack of FIG. 2 .

In this type of application, it is desirable that the image capture device be as transparent as possible within the visible range to avoid interfering with the user's perception of the display.

Now, among the layers used to form the image detector, some are more or less transparent and others are opaque in the visible range.

In particular, the materials typically used in photodetectors and in particular one or those of layers 27 (electrodes) and 21 (OSC) are opaque.

Even when some layers are 10%, or even 50% transparent, the accumulation of different layers results in a quasi-opaque stack.

Furthermore, taking the example of image capture devices used to capture in the infrared region, these sensors are equipped with optical filters that cut off visible radiation.

In common image capture devices, it is often desirable to maximize the surface area occupied by the light detector to increase sensitivity. However, in the target application, the size of the pixels of the image capture device is tied to those of the device's associated display screen, which enables acceptable sensitivity to be maintained by reducing the surface area occupied by the light detector.

Furthermore, in the target application, the size of the pixel 12 corresponding to the pitch of the gate line 16 in one direction and the pitch of the source line 14 in the other direction is high compared to the size of the readout circuit 3 .

According to the described embodiment and mode of execution, the presence of an opaque layer (eg metal) at the level of the readout circuits 3 is utilized to form approximately all parts of the photodetector layer according to the same pattern as the opaque layers of these readout circuits. .

In other words, the photodetector 2 and the readout circuit 3 are vertically aligned to maximize the surface area ratio of the pixels without an opaque layer. This distribution enables adjusting the size between photosensitive areas (between photodetectors) according to the desired performance, especially in terms of sensitivity, resolution, and transparency. In fact, the size of the readout circuit 3 does not depend on the size of the photodetectors 2, but on the pitch of these photodetectors. This enables the transparency ratio of the pixels to be varied depending on the desired size of the pixel 12 .

Figure 3 is a partially simplified exploded perspective view of an embodiment of the image capture device.

Figures 4A, 4B, and 4C are simplified top views of the layers of the embodiment of the image capture device of Figure 3.

Figure 3 shows in perspective view the stacking and respective patterns of layers forming the image capture device. Not all layers are shown. Specifically, the insulating layers 43 and 45 that separate the conductive layers 42 and 44, and the conductive layers 44 and 27 respectively are not shown in FIG. Made of materials that transmit greater than 70% transparency. The EIL layer 25 is also not shown in Figure 3 as this layer can be local or non-local.

Figures 4A, 4B, and 4C are top views corresponding to Figure 3 and respectively illustrating the following patterns: Source and drain contacts and source lines, as well as gate contacts and gate lines, conductive layers (e.g. metallic); The electrode layer 27 of the photodetector; and Active layer 21 and HIL layer 23.

The patterns of different layers illustrated in Figures 3 and 4 represent the array structure of an image capture device such as that shown in Figure 1 .

From bottom to top in the orientation of Figure 3 you can find: - a substrate 41 in which the transistors of the readout transistor 3 and possibly other semiconductor circuits associated with the control of the readout circuit and with the interpretation of the electrical signals captured from the photodetector are formed; - a conductive or semiconducting layer(s) 42 having the source and drain contacts 35 and 33 of the transistor 3 and the source contact line 14 formed therein; - Dielectric (insulating) layer(s) 43; - conductive or semiconducting layer(s) 44 having the gate contact 37 of the transistor formed therein and the gate contact line 16; - Dielectric (insulating) layer(s) 45; - electrode layer 27; and - a stack, which in this embodiment is formed according to the same pattern by an active layer 21 (OSC) and a hole injecting layer (HIL) 23 . This stack may include an electroinjection layer 25 (electron injecting layer, EIL) not shown in FIGS. 3 and 4 .

Respective vertical electrical connections between the drain 33 of the transistor and the electrode 27 of the photodetector are ensured by coupling, preferably vertical conductive vias 51 of the connecting layers 42 and 27 . The pattern of at least layer 27, preferably both of layers 27, 25, and 21, is such that each electrode 27 includes a drain contact 33 that is vertically aligned with the transistor 3 of the pixel of interest. area 53. Not only does this maximize the surface area of the photodetector without adversely affecting pixel transparency (drain contact 33 is opaque anyway), but it enables easy positioning of via 51 .

The pixel specificity of the structures shown in Figures 3 and 4 is that the layers 23, 21, 25, and 27 forming the photodetector 2 are formed according to the pattern of the conductive layers 42 and 44. In other words, knowing that conductive layers 42 and 44 are made of opaque materials, the pattern of the layers of photodetector 2 is chosen such that the layers of photodetectors follow the pattern of layers 42 and 44 . Thus, since the size of the pixel 12 is significant compared to the size of the readout circuit 3, a significant size transparent area 55 in the surface of the image capture device is retained. These areas 55 further exist at the level of each pixel 12 such that display performed by a display screen (not shown) is preserved.

Thus, in the examples of Figures 3 and 4, the pattern formed in layer 27 represents a cross 57 having its two branches parallel to source line 14 and parallel to gate line 16, respectively. Position its intersection point approximately perpendicular to the overlap area between the source and gate lines. Each cross 57 contains lateral projections forming a region 53 . The crosses 57 are separated from each other because they define different pixel light detectors. The branches of a given cross 57 are separated from it by the branches of four crosses 57 that are subsequently aligned with spaces or spacings filled with insulating or semiconducting material (not shown in Figure 3).

The active layer 21 and the HIL layer 23 can be common to different pixels, and the separate cross pattern 57 of the representation layer 27 is not required. The electrode formed by layer 23 is preferably common to all photodetectors of the image capture device. The active layer 21 is usually made of an opaque material, however, the active layer is formed according to a grid having two directions of the grid aligned with the source lines 14 and the gate lines 16 respectively. The active layer 21 and the HIL layer 23 also preferably include a region 59 that is vertically consistent with the region 33 .

As a variant, the active layer 21 represents a cross-shaped pattern 57 of the electrode layer 27 (a cross-shaped pattern with protrusions 53). However, the HIL layer remains common to all pixels. Specifically, if the HIL layer is transparent, the HIL layer may not be etched and remain common to the entire capture device.

In the case where layers 21 and 23 are etched simultaneously, the widths of the lines of the grid of the active layer 21 and the HIL layer 23 are preferably the same as or larger than those of the branches of the cross 57 . The width of the branches of the cross 57 is preferably chosen to be at least equal to the respective widths of the source lines 14 and gate lines 16 with which they are positioned in vertical alignment, in order to take advantage of the constraints already imposed by these source or gate lines. Maximum opaque surface area. The width of the branches is chosen based on transparency and based on the desired sensitivity and resolution. This choice is best performed by making a trade-off between these two criteria. The branches of cross 57 may therefore be wider than the source and gate lines. The spacing between the crosses in the direction of the source and gate lines has at a minimum a value that allows electrical isolation between the electrodes 27 of adjacent pixels.

The width of the lines of the active layer 21 and the HIL layer 23 is chosen, for example, to be approximately equal to, preferably greater than, the width of the branches of the cross 57 .

The size of regions 53 and 59 is selected based on the size of drain contact 33. For example, the dimensions of regions 53 and 59 are at least equal to, and preferably approximately equal to, the dimensions of drain contact 33 to take advantage of the maximum opaque surface area already imposed by these source and gate lines. In practice, they may even have larger dimensions than those of the drain contacts 33 .

Transparency may be defined at the level of pixel 12 by the ratio of the surface area of region 55 to the surface area of the pixel.

In the example of Figure 3, transistor 3 is assumed to be a horizontal transistor, that is, having substantially coplanar source and drain regions, as opposed to a vertical transistor in which the source and drain regions are vertically aligned.

However, the described embodiments and modes of implementation change to the formation of readout circuits based on vertical transistors provided for opaque areas formed by conductive layers, similar to those for lateral or horizontal structures. while occupying a small surface area compared to the pixel surface area.

As a specific example of an embodiment, for a pixel 12 having a size of approximately 50 μm, and thus a pitch of approximately 50 μm in both directions of the plane, a branch width of approximately 10 μm may be provided. Furthermore, square areas 53 and 59 having a side length of approximately 10 μm may be provided. In the case of such proportions, the transparency obtained is approximately 70%.

An advantage of the described architecture is that it enables improved overall transparency of the image capture device without adversely affecting the sensitivity of the image capture device or the resolution of the image capture device.

Another advantage is that the transparency is directly linked to the factor filling the pixels of the opaque layer. This facilitates decisions on trade-offs between transparency and sensitivity and resolution.

Table 1 below gives an example of transparency for a plurality of pixel pitch values, assuming that the branches of cross 57 exactly cover gate line 16 and source line 14 with a width of approximately 10 μm, and assuming 30 μm by 40 μm drain contact 33.

[Table 1] Pitch fill factor/transparency 50 μm 12% 85 μm 60% 100 μm 68% 105 μm 70% 125 μm 76% 300 μm 92%

As an example, electrode 27 corresponds to one or more opaque and/or transparent conductive layers made of: Transparent conductive oxide (TCO), such as gallium-doped zinc oxide, tin oxide, fluorine doped tin oxide (FTO), zinc oxide, aluminum-doped zinc oxide, Indium-doped cadmium oxide, titanium nitride TiN, indium tin oxide (ITO), etc.; Metals, such as gold, silver, lead, palladium, copper, nickel, tungsten, or chromium; carbon, silver, or copper nanowires; Graphene; or Mixtures of two or more of these materials.

Preferably, the electrode 27 is made of a metal layer and a layer of a transparent conductive oxide, such as a layer of ITO. The ITO layer covers and is in contact with the metal layer. In this case, the ITO layer may have the same pattern as the active layer 21 and extend in the area 55 provided for each pixel positioned pixel by pixel, as will be seen with respect to Figure 9. Preferably, the metal layer of the electrode 27 has a smaller size and represents the pattern of FIGS. 3 and 4 .

As an example, EIL layer 25 covers and contacts electrode 27, more specifically, the ITO layer of this electrode.

As an example, EIL layer 25 is made of polymeric material. The EIL layer 25 is obtained, for example, from an ink containing a polymer in a dissolved state in a solvent. The polymer of the EIL layer 25 is, for example, polyethyleneimine (PEI) or polyethylenimine ethoxylated (PEIE).

According to another example, the EIL layer is selected from the group comprising: - metal oxides, in particular titanium oxide or zinc oxide; - host/molecular dopant systems, in particular by Novaled under the name NET-5/ Products commercialized with NDN-1 or NET-8/MDN-26; - Conductive or doped semiconducting polymers, for example, PEDOT: tosylate polymer, which is poly(3,4)-ethylenedioxythiophene and mixtures of tosylate esters; - polyethyleneimine (PEI) or ethoxylated, propoxylated, and/or butoxylated polyethyleneimine (PEIE); - carbonates, such as CsCO ₃ ; - poly Electrolyte, for example, poly[9,9-bis(3'-(N,N-dimethylamino)propyl)-2,7-fluoro-alternanth-2,7-(9,9-dioctyl fluoride)] (PFN), poly[3-(6-trimethylammonohexyl)thiophene (P3TMAHT), or poly[9,9-bis(2-ethylhexyl)fluoride]-b-poly[3-( 6-trimethylammoniumhexyl]thiophene (PF2/6-b-P3TMAHT); and - mixtures of two or more of these materials.

As an example, active layer 21 covers EIL layer 25 and is in contact with the EIL layer.

As an example, the active layer 21 is made of an organic semiconductor material (OSC) deposited by, for example, liquid deposition. Active layer 21 may comprise a ambipolar semiconductor material, or a mixture of N-type and P-type semiconductor materials, for example in the form of a stacked layer or an intimate mixture on a nanoscale, to form an overall heterojunction. The thickness of the active layer 21 may range from 50 nm to 2 μm, such as approximately 200 nm. Examples of P-type semiconducting polymers suitable for the formation of the active layer 21 are poly(3-hexylthiophene) (P3HT), poly[N-9'-heptadecyl-2,7-carbazole-alternating-5, 5-(4,7-bis-2-thienyl-2',1',3'-benzothiadiazole)] (PCDTBT), poly[(4,8-bis-(2-ethylhexyloxy) yl)-benzo[1,2-b;4,5-b']dithiophene)-2,6-diyl-alternating-(4-(2-ethylhexyl)-thieno[3, 4-b]thiophene)-2,6-diyl] (PBDTTT-C), poly[2-methoxy-5-(2-ethyl-hexyloxy)-1,4-phenylene- vinylene] (MEH-PPV) or poly[2,6-(4,4-bis-(2-ethylhexyl) -4H -cyclopenta[2,1- b ; 3,4- b ']di Thiophene) -Alternate -4,7(2,1,3-benzothiadiazole)] ( PCPDTBT). Examples of N-type semiconductor materials capable of forming the active layer 21 are fullerenes, specifically C60, [6,6]-phenyl-C ₆₁ -methylbutyrate ([60]PCBM), and [6,6 ]-phenyl-C ₇₁ -methylbutyrate ([70]PCBM).

As an example, HIL layer 23 covers active layer 21 and is in contact with the active layer.

As an example, HIL layer 23 is: Made of conductive or semiconducting polymers, such as organic, such as doped, such as poly(3,4)-ethylenedioxythiophene (PEDOT) known under the name PEDOT:PSS, and polystyrene A mixture of sodium polystyrene sulfonate (PSS), or polyaniline or polymers known under the trade names Plexcore OC RG-1100 and Plexcore OC RG-1200 (commercialized by Sigma-Aldrich); Molecular host/dopant systems, such as those known under the trade names NHT-5/NDP-2 and NHT-18/NDP-9 (commercialized by Novaled); Polyelectrolytes, such as tetrafluoroethylene sulfonate-based copolymers, fluoropolymers, such as nanofiber membranes; Conjugated polymers, such as polytriarylamine (PTAA); Organic compounds such as N,N'-diphenyl-N,N'-bis(1-naphthyl)(1,1'-biphenyl)-4,4'-diamine (NPB) or N,NT- Diphenyl-N,N'-(3-methylphenyl)-1,1T-biphenyl-4,4T-diamine (TPD); or Mixtures of two or more of these materials.

Figure 5A, Figure 5B, Figure 5C, Figure 5D, Figure 5E, Figure 5F, Figure 5G, Figure 5H, and Figure 5I are steps illustrating the execution mode of the method of manufacturing the image capture device Simplified cross-sectional view of part.

These figures schematically show examples of structures obtained at the end of the manufacturing steps of the image capture device. Their representation is simplified and not all details such as previously described patterns are shown. Patterns only useful for understanding the method have been shown. Furthermore, other steps than those described may be included in the fabrication but are not described in detail. Specifically, assume that the ITO layer of the lower electrode 27 of the photodetector has the same pattern as the metal layer of this electrode. As will be seen later, the ITO layer may alternatively have the same pattern as the active layer 21 . Furthermore, the EIL layer 25 is not shown since the pattern of the EIL layer at least covers the metal layer of the electrode 27 but may extend beyond the metal layer.

Layers that may be made of opaque or non-transparent materials are hatched in the following drawings.

The fabrication of the image capture device starts with the fabrication of the readout circuit 3 on the inside and/or on the top of the substrate 41 (Fig. 5A). This substrate is transparent. Preferably, the material forming the substrate 41 has a transparency of at least 80%, more preferably at least 95%. For example, the substrate is made of glass.

The readout circuit 3 is manufactured using common electronic circuit manufacturing techniques. At the end of fabrication of the readout circuit, source and drain contacts 35 and 33 and gate and source lines 16 and 14 are formed in the conductive layer. In Figure 5A, the presence at the edge of the array of conductive rods 61 for biasing the hole injection layer 23, which conductive rods form the photodetector upper electrodes, is illustrated. This rod 61 is formed, for example, in one of the layers 42 and 44 . For simplicity and because these figures are schematic, the gate and source lines are not shown above.

The assembly is completely covered with an insulating layer 45, which also has the function of planarizing the surface of the device before the formation of the photodetector 2.

To form the photodetector, the step begins by forming an electrode layer 27 (at least the metal sublayer of the electrode layer) according to a pattern of crosses 57 (Figures 3 and 4B). The crosses 57 are insulated from each other by the insulating or semiconducting material produced by subsequent steps.

Then (Fig. 5C), EIL layer 25 (not shown), active layer 21, and HIL layer 23 are deposited to completely cover the assembly. These depositions are performed in liquid form, for example, by slot die coating or spin coating.

Then (Fig. 5D), layers 23, 21 (and 25) are etched vertically consistent with bias rod 61 so as to expose the bias rod (region 63). This etching is, for example, reactive ion etching (RIE).

Then (Fig. 5E), conductive material 65 is deposited to connect HIL layer 23 to rod 61. Material 65 is, for example, the same material used for HIL layer 23 .

The next step illustrated in Figures 5F and 5G includes etching the stack to form region 55.

The step begins by depositing a resin layer 67 (Fig. 5F), which is opened by photolithography (openings 69) according to the desired pattern of areas 55. The resin is deposited, for example, by spin coating.

Then (FIG. 5G), etching of layers 23, 21, 25, and layer 45 is performed, that is, etching through the resin mask 69 up to the transparent substrate 41, and this resin mask is then removed. This etching is, for example, reactive ion etching.

The structure of the photodetector 2 is then obtained with the pattern required according to the desired surface filling factor.

The resulting assembly is then packaged (Fig. 5H). According to one example, a buffer layer 71 is deposited throughout the structure and covered with an atomic layer 73 (ALD, for atomic layer deposition). According to another example, layer 71 is a glue layer and layer 73 is an encapsulation film. Layer 71 fills opening 55 and planarizes the surface.

According to an embodiment, the image capture device is then complete.

As an example, layer 73 is generally oxidatively impermeable to water and air to protect the underlying organic layer. Layer 27 may be made of an inorganic material, for example, aluminum oxide (Al2O3), silicon dioxide (SiO2), or silicon nitride (Si3N4). Layer 73 may have a thickness ranging from 2 nm to 200 nm. Layer 73 is deposited, for example, by sequential atomic layer deposition (ALD, for atomic layer deposition), by physical vapor deposition (PVD), or by chemical vapor deposition (CVD), for example , deposited by plasma-enhanced chemical vapor deposition (PECVD).

According to another embodiment (Fig. 5I), the device is associated with an optical filter 8. This filter is formed, for example, separately from a glass plate or substrate 81 having a black resin 83 deposited thereon by lamination or by selective deposition according to the desired pattern. For example, the black resin areas are arranged to coincide vertically with the opaque areas of the capture device. The separately formed filter 8 is then placed on the structure resulting from Figure 5G, with an intervening adhesive layer 85 to obtain the device illustrated in Figure 5I.

This execution mode is particularly suitable for situations where the optical filter is formed separately. This mode of implementation particularly enables the standardization of the manufacture of the same image capture device (the image capture device of Figures 5A to 5H) for applications with filters of different properties or with and without filters.

6A and 6B are partially simplified cross-sectional views illustrating steps of another implementation mode of an image capture device manufacturing method.

This mode of execution uses the steps previously described with respect to Figures 5A-5E, which will not be described again.

Starting from the structure produced in Figure 5E, optical filters are formed here directly in the form of etched masks of layers 23, 21, and 25.

The step begins by depositing a black resin layer 67 (Fig. 6A), which is opened by photolithography (openings 89) according to the desired pattern of areas 55. The resin is deposited, for example, by spin coating. Resin 87 is selected to be transparent to infrared radiation and opaque in the visible range. The filter 8 then serves as an etching mask up to the transparent substrate 41 .

The resulting assembly is then packaged, for example as described with respect to Figure 5H (layers 71 and 73).

According to another example, once the glue or buffer layer 71 has been deposited to fill the opening 55 and planarize the surface, a glass plate 81 is placed on top.

The implementation modes of Figures 6A and 6B are more specifically intended for applications with filters and enable the entire device to be formed in the same process. The advantage is that this avoids possible misalignment when the filter 8 of the implementation mode of Figure 5I is placed on the structure of Figure 5H.

Figures 7A, 7B, and 7C are partially simplified cross-sectional views illustrating steps of another implementation mode of the image capture device manufacturing method.

This mode of implementation uses the steps previously described with respect to Figures 5A-5G, which will not be described again.

Starting from the structure produced in Figure 5G, a buffer layer 71 is deposited across the surface (Figure 7A), which fills openings 55 and planarizes the surface. Layer 71 is optionally covered with an atomic layer 73 (ALD, for atomic layer deposition).

Then (FIG. 7B), the optical filter is formed by developing the black resin layer 87.

The resulting assembly is then packaged (Fig. 7C). According to one example, a second buffer layer 71' is deposited throughout the structure and covered with an atomic layer 73' (ALD, for atomic layer deposition). According to another example, layer 71' is a glue layer and layer 73' is an encapsulation film. The material of layer 71 fills the spaces between the blocks of black resin and planarizes the surface. Figure 7C further illustrates a variation without layer 73 underneath layer 87.

Figure 8 is a partially simplified cross-section illustrating an alternative embodiment of an image capture device.

This mode of implementation uses the steps previously described with respect to Figures 5A-5G, which will not be described again.

Starting from the structure produced in Figure 5G, a transparent conductive or semiconducting layer 91 is deposited over the surface, etched according to the grid pattern of the HIL layer 23 and reaching layer 65. This enables improved conduction of the electrode 23 on the photodetector. Layer 91 may fill opening 55. The insulation between the crosses 57 is ensured by an OSC layer that is then etched according to a pattern wider than the layer 27, or by coating the sides of the crosses with a different insulating layer. This layer on either side of the vertical insulating cross may be present in other embodiments.

The material of layer 91 is, for example, the same material as the material of HIL layer 23 .

The next step may use any of the previously described execution modes (layers 71 and/or 73, Figure 5H, black resin layer 87 (Figure 6A), layers 71 and/or 73, Figure 7A).

Figure 9 is a partially simplified top view illustrating another alternative embodiment of an image capture device.

Compared to the embodiment illustrated with respect to Figure 4B, this variant consists of a different pattern for the ITO layer 27' of the electrode 27, which ITO layer is inserted between the metal layer 27" of the lower electrode 27 and the active layer 21 (more precisely Ground is between layer 27" and EIL layer 25).

According to this variant, the cross-shaped pattern 57 and the preferred area 53 remain for the metal electrode layer 27", but the pattern formed in the ITO layer 27' and the active layer 21 (and the simultaneously etched IL layer 25) is enlarged, The active layer 21 and the ITO layer 27" occupy a larger surface area. This amounts to giving the active layer 21 , the EIL layer, and the ITO layer 27 ′ a cross-shaped pattern 57 associated with a rectangle 93 that extends to reduce the surface area of the transparent region 55 .

However, the formation of the variant of Figure 9 requires etching in at least three steps (layer 27", layer 27', layer 25, and layer 21, layer 23) the layers forming the stack of photodetectors separately from each other.

This variant enables adjusting the transparency of the device by changing only the surface area occupied by the ITO layer 27" and the active layer 21 (OSC).

This variant is compatible with embodiments in which the electrode 27 is made exclusively of ITO.

Figure 9 also illustrates an example of dimensions with a pitch of 40 μm. According to this example, the branches of the cross 57 have a width of 10 μm and an area 53 with dimensions of 10 μm by 10 μm.

It should be noted that the variant of Figure 9 is incompatible with the one of Figure 8.

An advantage of the described embodiments and modes of implementation is that they enable improved transparency of image capture devices.

Another advantage of the described embodiments and modes of implementation is that they are compatible with common readout circuitry and organic photodetector manufacturing technologies.

Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations may be combined, and those skilled in the art will appreciate other variations.

Finally, practical implementation of the described embodiments and variations is within the ability of one skilled in the art based on the functional instructions given above.

1:Image capture device 2:Light detector 3: Readout circuit 8: Optical filter 12:pixel 14: Column/source line 16: Row/gate line 21:Active layer 23: Hole injection layer/upper electrode 25:Electronic injection layer 27:Electrode 27':ITO layer 27":Metal layer 33:Jiji 35: Source 37: Gate 41: Substrate/Transparent substrate 42: Conductive layer 43: Dielectric layer/insulating layer 44: Conductive layer/semiconductor layer 45: Dielectric layer/insulating layer 51:Vertical conductive via 53:Area/Protrusion 55: Transparent area/opening 57: Cross shape 59:Area 61: Conductive Rod 63:Area 65: Conductive materials 69: Opening/resin mask 71:Buffer layer 71': Second buffer layer 73':Atomic layer 73:Atomic layer 81:Glass plate/substrate 83:Black resin 85:Insert adhesive layer 87:Black resin layer 89:Open your mouth 91: Transparent conductive or semiconducting layer 93: Rectangle

The previous and other features and advantages of the present invention are discussed in detail in the following non-limiting description of specific embodiments and modes of practice, taken in conjunction with the accompanying drawings:

Figure 1 partially and schematically shows an electrical diagram of an embodiment of an image capture device;

Figure 2 is a partially simplified cross-sectional view of an embodiment of the image capture device;

Figure 3 is a partially simplified exploded perspective view of an embodiment of the image capture device;

Figures 4A, 4B, and 4C are simplified top views of the layers of the embodiment of the image capture device of Figure 3;

Figure 5A, Figure 5B, Figure 5C, Figure 5D, Figure 5E, Figure 5F, Figure 5G, Figure 5H, and Figure 5I are steps illustrating the execution mode of the method of manufacturing the image capture device Simplified cross-sectional view of part of;

Figures 6A and 6B are partially simplified cross-sectional views illustrating steps of another implementation mode of a method of manufacturing an image capture device;

Figures 7A, 7B and 7C are partially simplified cross-sectional views illustrating steps of another execution mode of a method of manufacturing an image capture device;

Figure 8 is a partially simplified cross-sectional view illustrating an alternative embodiment of an image capture device; and

Figure 9 is a partially simplified top view illustrating another alternative embodiment of an image capture device.

Domestic storage information (please note in order of storage institution, date and number) without Overseas storage information (please note in order of storage country, institution, date, and number) without

14: Column/source line

16: Row/gate line

21:Active layer

23: Hole injection layer/upper electrode

27:Electrode

33:Jiji

35: Source

37: Gate

41: Substrate/Transparent substrate

42: Conductive layer

43: Dielectric layer/insulating layer

44: Conductive layer/semiconductor layer

45: Dielectric layer/insulating layer

51:Vertical conductive via

53:Area/Protrusion

55: Transparent area/opening

57: Cross shape

59:Area

Claims (14)

An image capture device (1), wherein the light detectors (2) have a pattern of interconnected lines (14, 16) following the readout circuit (3), and the light detectors (2) The first electrode (27) has a cross-shaped pattern (57) with two branches respectively corresponding to the lines (14, 16) interconnecting the readout circuits (3). The device of claim 1, wherein a hole injection layer (23) common to the photodetectors (2) has the lines (14, 16) interconnecting the readout circuits (3) Vertically consistent grid pattern. The device of claim 2, wherein an active layer (21) of each photodetector has the grid pattern of the hole injection layer (23). The device of claim 1, wherein an active layer (21) of each photodetector has the cross-shaped pattern (57) of its first electrode (27). The device of claim 3, wherein the active layer (21) and the first electrode of each photodetector extend (93) beyond the pattern. The device of claim 1, wherein each readout circuit (3) includes a transistor, and the interconnection lines respectively correspond to the sources (35) and interconnections of the transistors according to a first direction. Lines (14, 16) of the gates (37) of the transistors according to a second direction. The device of claim 5, wherein the pattern on which the photodetectors (2) are formed is also vertically aligned with the drain contacts (33) of the transistors of the readout circuit (3) . The device of claim 1, wherein the surface area masked by the active layer (21) of the light detectors (2) represents for each pixel less than 50% of the surface area of the pixel, which is less than 50% of the surface area of the pixel. Good land is less than 30%. A method of manufacturing an image capture device (1), the method includes the following steps: Formation of an array of readout circuits (3) having transistors interconnected in a source line (14) in a first direction and a gate line (16) in a second direction ; Deposition of a stack based on the array of readout circuits, the stack comprising at least: One layer of first electrode (27); an active layer (21); and A hole injection layer (23) The first electrodes (27) have a cross shape according to etching the layers of the stack individually or simultaneously according to a pattern following at least one of the interconnection lines (14, 16) of the readout circuit (3) Pattern (57), the cross-shaped pattern has two branches respectively vertically consistent with the lines (14, 16) interconnecting the readout circuits (3). The method of claim 9, wherein the etching of the layers of the stack causes the surface area to be increasingly masked by the electrode layer (27), and the active layer (21) represents the The surface area of the pixel is less than 50%, preferably less than 30%. The method of claim 9, wherein the active layer (21) and the hole injection layer (23) are etched simultaneously. The method of claim 9, wherein an optical filter (8) is placed on the stack. The method of claim 9, wherein the stacked layers further cover the drain contacts (33) of the transistors of the readout circuits (3). The method of claim 9, wherein the steps are suitable for manufacturing a device according to any one of claim 1.