TW202339144A - Electronic packaging and manufacturing method thereof - Google Patents

Electronic packaging and manufacturing method thereof Download PDF

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Publication number
TW202339144A
TW202339144A TW111111159A TW111111159A TW202339144A TW 202339144 A TW202339144 A TW 202339144A TW 111111159 A TW111111159 A TW 111111159A TW 111111159 A TW111111159 A TW 111111159A TW 202339144 A TW202339144 A TW 202339144A
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circuit structure
electronic package
layer
sheets
ground layer
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TW111111159A
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Chinese (zh)
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TWI796180B (en
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周庭暘
姜亦震
江東昇
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矽品精密工業股份有限公司
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Priority to TW111111159A priority Critical patent/TWI796180B/en
Priority to CN202210355197.5A priority patent/CN116845050A/en
Priority to US17/748,920 priority patent/US20230307339A1/en
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Publication of TWI796180B publication Critical patent/TWI796180B/en
Publication of TW202339144A publication Critical patent/TW202339144A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Containers And Plastic Fillers For Packaging (AREA)

Abstract

An electronic package, the manufacturing method of which is to form a plurality of conductive pillars and arrange an electronic component on a first circuit structure, and cover the plurality of conductive pillars and the electronic component with a encapsulating layer, and then form a second circuit structure on the encapsulating layer, so that the plurality of conductive pillars are electrically connected to the first and second circuit structures, and the electronic element is electrically connected to the first circuit structure, wherein a fan-out RDL is configured in the first and second circuit structures with at least one ground layer including a plurality of flakes arranged in an array and at least one groove arranged between two adjacent flakes. Therefore, so that flexibility of the second circuit structure is improved by the design of the flakes and the groove of the ground layer.

Description

電子封裝件及其製法 Electronic packages and manufacturing methods

本發明係有關一種電子封裝件及其製法，尤指一種具有接地層之電子封裝件及其製法。 The present invention relates to an electronic package and a manufacturing method thereof, in particular to an electronic package with a ground layer and a manufacturing method thereof.

隨著近年來可攜式電子產品的蓬勃發展，各類相關產品逐漸朝向高密度、高性能以及輕、薄、短、小之趨勢而走，各式樣封裝堆疊(package on package，簡稱PoP)製程也因而配合推陳出新，以期能符合輕薄短小與高密度的要求。 With the vigorous development of portable electronic products in recent years, various related products are gradually moving towards high density, high performance, lightness, thinness, shortness and smallness. Various package on package (PoP) processes Therefore, it cooperates with the innovation, in order to meet the requirements of lightness, short size and high density.

如圖1所示，係為習知封裝堆疊裝置1的剖視示意圖，該封裝堆疊裝置1包括兩相疊之封裝結構1a,1b。 As shown in FIG. 1 , it is a schematic cross-sectional view of a conventional package stacking device 1 . The package stacking device 1 includes two stacked packaging structures 1 a and 1 b.

下方之封裝結構1a係包含具有相對之第一表面11a及第二表面11b之第一基板11、覆晶結合該第一基板11之第一電子元件10、設於該第一表面11a上之電性接觸墊111、形成於該第一基板11上以包覆該第一電子元件10之第一封裝膠體13、形成於該第一封裝膠體13之開孔130中之電性接觸墊111上之銲錫材114、以及設於該第二表面11b上用於結合銲球14之植球墊112。 The lower package structure 1a includes a first substrate 11 having an opposite first surface 11a and a second surface 11b, a first electronic component 10 flip-chip bonded to the first substrate 11, and an electrical circuit disposed on the first surface 11a. The electrical contact pads 111 are formed on the first encapsulating compound 13 formed on the first substrate 11 to cover the first electronic component 10 and are formed on the electrical contact pads 111 in the openings 130 of the first encapsulating compound 13 The solder material 114 and the ball mounting pad 112 provided on the second surface 11 b for combining the solder balls 14 .

上方之封裝結構1b係包含第二基板12、以打線方式結合於該第二基板12上之複數第二電子元件15a,15b、及形成於該第二基板12上以包覆該複數第二電子元件15a,15b之第二封裝膠體16，以令該第二基板12藉由該銲錫材114疊設且電性連接於該第一基板11之電性接觸墊111上。 The upper package structure 1b includes a second substrate 12, a plurality of second electronic components 15a, 15b bonded to the second substrate 12 by wire bonding, and a plurality of second electronic components 15a, 15b formed on the second substrate 12 to cover the second electronic components. The second encapsulant 16 of the components 15a and 15b enables the second substrate 12 to be stacked and electrically connected to the electrical contact pads 111 of the first substrate 11 through the solder material 114.

惟，習知封裝堆疊裝置1中，由於該第一基板11與第二基板12間之結構及材料性質差異，導致於製程過程中該第一基板11與第二基板12容易發生翹曲(warpage)。 However, in the conventional package stacking device 1, due to differences in structure and material properties between the first substrate 11 and the second substrate 12, the first substrate 11 and the second substrate 12 are prone to warpage during the manufacturing process. ).

再者，習知第一基板11與第二基板12均採用傳統封裝基板規格，其具有核心層，致使該第一基板11與第二基板12之板厚難以縮減，而無法有效降低該封裝堆疊裝置1之整體封裝高度。 Furthermore, it is known that both the first substrate 11 and the second substrate 12 adopt traditional packaging substrate specifications and have core layers, which makes it difficult to reduce the thickness of the first substrate 11 and the second substrate 12 and cannot effectively reduce the packaging stack. Overall package height of device 1.

因此，如何克服上述習知技術之種種問題，實已成為目前業界亟待克服之難題。 Therefore, how to overcome the various problems of the above-mentioned conventional technologies has become an urgent problem that the industry needs to overcome.

鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝件，係包括：包覆層，係具有相對之第一表面與第二表面；第一線路結構，係設於該包覆層之第一表面上，並配置有扇出型線路重佈層；第二線路結構，係設於該包覆層之第二表面上，並配置有扇出型線路重佈層；複數導電柱，係嵌埋於該包覆層中且電性連接該第一線路結構與第二線路結構；電子元件，係設於該第一線路結構上並嵌埋於該包覆層中且電性連接該第一線路結構或第二線路結構；以及至少一接地層，係設於該第一線路結構及該第二線路結構之至少一者中，其中， 該至少一接地層係包含複數陣列排設之片體，每二相鄰之該片體之間設置有至少一溝槽。 In view of the deficiencies of the above-mentioned conventional technologies, the present invention provides an electronic package, which includes: a coating layer having opposite first and second surfaces; and a first circuit structure provided on the coating layer. A fan-out circuit redistribution layer is disposed on the first surface; a second circuit structure is disposed on the second surface of the cladding layer, and a fan-out circuit redistribution layer is disposed; a plurality of conductive pillars are Embedded in the cladding layer and electrically connected to the first circuit structure and the second circuit structure; electronic components are provided on the first circuit structure and embedded in the cladding layer and electrically connected to the third circuit structure. a circuit structure or a second circuit structure; and at least one ground layer provided in at least one of the first circuit structure and the second circuit structure, wherein, The at least one ground layer includes a plurality of sheets arranged in an array, and at least one trench is provided between every two adjacent sheets.

本發明亦提供一種電子封裝件之製法，係包括：於第一線路結構上形成複數導電柱及設置電子元件；形成包覆層於該第一線路結構上以包覆該複數導電柱及該電子元件；以及形成一第二線路結構於該包覆層上，以令該複數導電柱電性連接該第一線路結構與第二線路結構，且令該電子元件電性連接該第一線路結構或第二線路結構，其中，於該第一線路結構與第二線路結構中係配置有扇出型線路重佈層，且於該第一線路結構及該第二線路結構之至少一者中設置有至少一接地層，該至少一接地層係包含複數陣列排設之片體，且每二相鄰之該片體之間設置有至少一溝槽。 The invention also provides a method for manufacturing an electronic package, which includes: forming a plurality of conductive pillars and arranging electronic components on a first circuit structure; forming a coating layer on the first circuit structure to cover the plurality of conductive pillars and the electronic components component; and forming a second circuit structure on the cladding layer, so that the plurality of conductive pillars are electrically connected to the first circuit structure and the second circuit structure, and the electronic component is electrically connected to the first circuit structure, or A second circuit structure, wherein a fan-out circuit redistribution layer is configured in the first circuit structure and the second circuit structure, and a fan-out circuit redistribution layer is provided in at least one of the first circuit structure and the second circuit structure. At least one ground layer, the at least one ground layer includes a plurality of sheets arranged in an array, and at least one trench is provided between every two adjacent sheets.

前述之電子封裝件及其製法中，該第一線路結構及該第二線路結構之至少一者中係設有複數層該接地層，且相鄰兩層該接地層的該片體之位置係上下對應，並使相鄰兩層該接地層之該溝槽於垂直方向不重疊。進一步，還包括分別對應該複數片體且設置於相鄰兩層該接地層之間的複數導電體，且相鄰兩層該接地層的該片體藉由該複數導電體之至少其中一者電性連接。 In the aforementioned electronic package and its manufacturing method, at least one of the first circuit structure and the second circuit structure is provided with a plurality of layers of the ground layer, and the positions of the pieces of the two adjacent layers of the ground layer are Correspond to the top and bottom, and ensure that the trenches of the two adjacent ground layers do not overlap in the vertical direction. Further, it also includes a plurality of conductors respectively corresponding to the plurality of sheets and disposed between two adjacent layers of the ground layer, and the sheets of the two adjacent layers of the ground layer are connected by at least one of the plurality of conductors. Electrical connection.

前述之電子封裝件及其製法中，每一該片體具有至少一開孔。例如，該第一線路結構及該第二線路結構之至少一者中係設有複數層該接地層，且相鄰兩層該接地層的該片體之位置係上下對應，並使相鄰兩層該接地層之該開孔於垂直方向不重疊。或者，該至少一開孔的總面積佔各該片體外邊輪廓之垂直投影之面積的至少10%以上。 In the aforementioned electronic package and its manufacturing method, each piece has at least one opening. For example, at least one of the first circuit structure and the second circuit structure is provided with a plurality of layers of the ground layer, and the positions of the pieces of the ground layer of two adjacent layers are corresponding up and down, so that the adjacent two layers The openings of the ground layer do not overlap in the vertical direction. Alternatively, the total area of the at least one opening accounts for at least 10% of the area of the vertical projection of the outer contour of each piece.

前述之電子封裝件及其製法中，該至少一溝槽係設置於其對應各該片體之邊緣的中央位置。 In the aforementioned electronic package and its manufacturing method, the at least one groove is disposed at a central position corresponding to the edge of each piece.

前述之電子封裝件及其製法中，該複數片體之相鄰兩者之間設置有複數陣列排設之溝槽。 In the aforementioned electronic package and its manufacturing method, a plurality of trenches arranged in an array are provided between two adjacent pieces of the plurality of pieces.

前述之電子封裝件及其製法中，該複數片體之間所形成之複數該溝槽係相互連通而於對應各該片體之邊角處位置形成類十字形槽孔。進一步，相鄰之該類十字形槽孔之間設置有陣列排設且位置對應該片體之邊緣的中央位置之複數溝槽。 In the aforementioned electronic package and its manufacturing method, the plurality of grooves formed between the plurality of pieces are interconnected to form cross-shaped slots at corresponding corners of the pieces. Furthermore, a plurality of grooves arranged in an array and corresponding to the center position of the edge of the sheet body are provided between adjacent cross-shaped slots.

前述之電子封裝件及其製法中，該複數片體為矩形，且該至少一溝槽的總長度佔其對應之各該片體之平行該至少一溝槽長度的邊緣的邊長的至少60%以上。 In the aforementioned electronic package and its manufacturing method, the plurality of pieces are rectangular, and the total length of the at least one groove accounts for at least 60% of the side length of the corresponding edge of the piece that is parallel to the length of the at least one groove. %above.

前述之電子封裝件及其製法中，該複數片體為矩形，且該至少一溝槽的總寬度佔其對應之各該片體之平行該至少一溝槽寬度的邊緣的邊長的至少1%以上。 In the aforementioned electronic package and its manufacturing method, the plurality of pieces are rectangular, and the total width of the at least one groove accounts for at least 1 of the side length of the corresponding edge of the piece that is parallel to the width of the at least one groove. %above.

由上可知，本發明之電子封裝件及其製法中，主要藉由該扇出型線路重佈層製作該第一與第二線路結構，以取代傳統具有核心層之封裝基板，故相較於習知技術，本發明之電子封裝件能有效降低整體之封裝高度。 It can be seen from the above that in the electronic package and its manufacturing method of the present invention, the first and second circuit structures are mainly produced by the fan-out circuit redistribution layer to replace the traditional packaging substrate with a core layer. Therefore, compared with According to the conventional technology, the electronic package of the present invention can effectively reduce the overall package height.

再者，本發明藉由該接地層的片體、開孔及溝槽之設計，以提升整體線路結構的撓性，故相較於習知技術，本發明之電子封裝件可具有較佳的翹曲控制表現，以提升後續封裝模組設於該第二線路結構上的結合良率。 Furthermore, the present invention improves the flexibility of the overall circuit structure through the design of the ground layer body, openings and grooves. Therefore, compared with the conventional technology, the electronic package of the present invention can have better The warpage control performance is improved to improve the bonding yield of subsequent packaged modules installed on the second circuit structure.

1:封裝堆疊裝置 1: Package stacking device

1a,1b:封裝結構 1a,1b:Package structure

10:第一電子元件 10:The first electronic component

101:導電矽穿孔 101:Conductive silicon perforation

11:第一基板 11: First substrate

11a:第一表面 11a: First surface

11b:第二表面 11b: Second surface

111,262:電性接觸墊 111,262: Electrical contact pads

112:植球墊 112: Ball planting pad

114:銲錫材 114:Solder material

12:第二基板 12:Second substrate

13:第一封裝膠體 13: The first encapsulating colloid

130:開孔 130:Opening

14:銲球 14: Solder ball

15a,15b:第二電子元件 15a,15b: Second electronic component

16:第二封裝膠體 16:Second encapsulating colloid

2:電子封裝件 2: Electronic packages

20:第一線路結構 20: First line structure

200,260:介電層 200,260: dielectric layer

201,261:線路重佈層 201,261: Line redistribution layer

203:絕緣保護層 203: Insulating protective layer

21:電子元件 21:Electronic components

21a:作用面 21a:Action surface

21b:非作用面 21b: Non-active surface

210:電極墊 210:Electrode pad

212:底膠 212: Primer

22:導電凸塊 22: Conductive bumps

23:導電柱 23:Conductive pillar

23b:端面 23b:End face

24,54:接地層 24,54:Ground layer

24a,71a,72a:片體 24a, 71a, 72a: sheet body

24b,54b,84a,84b,94a,94b:連接段 24b,54b,84a,84b,94a,94b: connecting section

24c,54c:外緣 24c,54c: outer edge

240,710,720:開孔 240,710,720: opening

241,441,541,641,711,721,811,821,911,921:溝槽 241,441,541,641,711,721,811,821,911,921:Trench

25:包覆層 25: Cladding layer

25a:第一表面 25a: First surface

25b:第二表面 25b: Second surface

26:第二線路結構 26: Second line structure

27:導電元件 27:Conductive components

28:封裝模組 28:Packaging module

280:銲錫材料 280:Solder material

29:輔助功能元件 29: Auxiliary function components

34a:圖案化銅面 34a:Patterned copper surface

34b:片狀銅面 34b: Flake copper surface

540:橋接線 540: Bridge wire

71:第一接地層 71: First ground layer

72:第二接地層 72: Second ground layer

73:導電體 73: Electrical conductor

8:電子裝置 8: Electronic devices

9:承載板 9: Loading board

90:離形層 90: Release layer

91:黏著層 91:Adhesive layer

L,L’,W,W’:邊長 L, L’, W, W’: side length

D,D1,D2,D3,D3’,D4,D4’,D5,D5’,L1,L2,L3:長度 D,D1,D2,D3,D3’,D4,D4’,D5,D5’,L1,L2,L3: length

R,R1,R2,R3,R3’,R4,R4’,R5,R5’,R6,R6’,R7,R7’,R8,R8’:寬度 R, R1, R2, R3, R3’, R4, R4’, R5, R5’, R6, R6’, R7, R7’, R8, R8’: Width

R9,R9’,R10,R10’,W1:寬度 R9, R9’, R10, R10’, W1: Width

P,X1,X2,Z1,Z2:類十字形槽孔 P,X1,X2,Z1,Z2: Cross-shaped slotted holes

Y:直線狀槽孔 Y: Linear slot

P1,P2:邊緣 P1,P2: edge

T:開口 T:Open your mouth

S:切割路徑 S: cutting path

圖1係為習知封裝堆疊裝置之剖視示意圖。 FIG. 1 is a schematic cross-sectional view of a conventional package stacking device.

圖2A至圖2F係為本發明之電子封裝件之第一實施例之製法之剖視示意圖。 2A to 2F are schematic cross-sectional views of the manufacturing method of the electronic package according to the first embodiment of the present invention.

圖2G係為圖2F之應用之剖視示意圖。 Figure 2G is a schematic cross-sectional view of the application of Figure 2F.

圖3A係為圖2C之局部上視示意圖。 Figure 3A is a partial top view of Figure 2C.

圖3B係為圖2C之另一態樣之上視示意圖。 Figure 3B is a schematic top view of another aspect of Figure 2C.

圖4A至圖4C係為圖3A之其它態樣之平面上視示意圖。 FIGS. 4A to 4C are schematic plan views of other aspects of FIG. 3A .

圖5係為本發明之電子封裝件之第二實施例之局部上視示意圖。 FIG. 5 is a partial top view of the electronic package according to the second embodiment of the present invention.

圖6係為圖5之另一態樣之平面上視示意圖。 FIG. 6 is a schematic plan view of another aspect of FIG. 5 .

圖7A係為本發明之電子封裝件之第三實施例之局部剖視示意圖。 FIG. 7A is a partial cross-sectional view of the third embodiment of the electronic package of the present invention.

圖7B係為圖7A之上視分解示意圖。 Figure 7B is an exploded schematic view from above of Figure 7A.

圖7C係為圖7B之局部疊合上視示意圖。 FIG. 7C is a partially superimposed top view of FIG. 7B .

圖7D係為圖7A之另一態樣之局部上視示意圖。 FIG. 7D is a partial top view of another aspect of FIG. 7A .

圖7E係為圖7D之上視分解示意圖。 Figure 7E is an exploded schematic view from above of Figure 7D.

圖7F係為圖7E之局部疊合上視示意圖。 Figure 7F is a partially superimposed top view of Figure 7E.

圖8A係為本發明之電子封裝件之第四實施例之局部上視分解示意圖。 FIG. 8A is a partial top exploded schematic view of the fourth embodiment of the electronic package of the present invention.

圖8B係為圖8A之局部疊合上視示意圖。 FIG. 8B is a partially superimposed top view of FIG. 8A .

圖8C係為圖8A之另一態樣之局部上視分解示意圖。 FIG. 8C is a partial top exploded schematic diagram of another aspect of FIG. 8A .

圖8D係為圖8C之局部疊合上視示意圖。 Figure 8D is a partially superimposed top view of Figure 8C.

圖9A係為本發明之電子封裝件之第五實施例之局部上視分解示意圖。 FIG. 9A is a partial top exploded schematic diagram of the fifth embodiment of the electronic package of the present invention.

圖9B係為圖9A之局部疊合上視示意圖。 FIG. 9B is a partially superimposed top view of FIG. 9A .

圖9C係為圖9A之疊合上視示意圖。 Figure 9C is a schematic superimposed top view of Figure 9A.

圖9D係為圖9A之另一態樣之局部上視示意圖。 Figure 9D is a partial top view of another aspect of Figure 9A.

以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The following describes the implementation of the present invention through specific embodiments. Those familiar with the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」、「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to this specification are only used to coordinate with the content disclosed in the specification for the understanding and reading of those familiar with the art, and are not used to limit the implementation of the present invention. Therefore, it has no technical substantive significance. Any structural modifications, changes in proportions, or adjustments in size shall still fall within the scope of this invention without affecting the effects that can be produced and the purposes that can be achieved. The technical content disclosed by the invention must be within the scope that can be covered. At the same time, terms such as "above", "first", "second", "one", etc. cited in this specification are only for convenience of description and are not used to limit the scope of the present invention. Changes or adjustments in their relative relationships, provided there is no substantial change in the technical content, shall also be deemed to be within the scope of the present invention.

圖2A至圖2F係為本發明之電子封裝件2之第一實施例之製法之剖面示意圖。 2A to 2F are schematic cross-sectional views of the manufacturing method of the electronic package 2 according to the first embodiment of the present invention.

如圖2A所示，在一承載板9上設有一第一線路結構20，且於該第一線路結構20上形成有複數導電柱23，並將至少一電子元件21藉由複數導電凸塊22設於該第一線路結構20上。 As shown in FIG. 2A , a first circuit structure 20 is provided on a carrier board 9 , and a plurality of conductive pillars 23 are formed on the first circuit structure 20 , and at least one electronic component 21 is connected through a plurality of conductive bumps 22 disposed on the first circuit structure 20 .

於本實施例中，該第一線路結構20係為無核心層式(coreless)，其包含複數介電層200與設於該介電層200上之扇出型線路重佈層(Fan-out Redistribution layer，簡稱FORDL)201。例如，形成該線路重佈層201之材質係為 銅，且形成該介電層200之材質係如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)或其它等之介電材。 In this embodiment, the first circuit structure 20 is coreless and includes a plurality of dielectric layers 200 and a fan-out circuit redistribution layer (Fan-out) disposed on the dielectric layer 200. Redistribution layer, referred to as FORDL)201. For example, the material forming the circuit redistribution layer 201 is Copper, and the material forming the dielectric layer 200 is such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP) or other media. Electrical materials.

再者，該承載板9係例如為半導體材質(如矽或玻璃)之板體，其上可依需求依序形成有一離形層90與一黏著層91，以供該介電層200設於該黏著層91上。 Furthermore, the carrier plate 9 is, for example, a plate made of semiconductor material (such as silicon or glass), on which a release layer 90 and an adhesive layer 91 can be formed in sequence according to requirements, for the dielectric layer 200 to be disposed on on the adhesive layer 91.

又，該導電柱23係以電鍍方式形成於該線路重佈層201上以電性連接該線路重佈層201，且形成該導電柱23之材質係為如銅之金屬材或銲錫材。 In addition, the conductive pillar 23 is formed on the circuit redistribution layer 201 by electroplating to electrically connect the circuit redistribution layer 201 , and the conductive pillar 23 is made of a metal material such as copper or a solder material.

另外，該電子元件21係為主動元件、被動元件或其二者組合等，例如為半導體晶片、具有導電矽穿孔(Through-silicon via，簡稱TSV)101之矽中介板(Through Silicon interposer，簡稱TSI)、電阻、電容或電感。於本實施例中，該電子元件21係為半導體晶片，其具有相對之作用面21a與非作用面21b，且以其作用面21a之電極墊210藉由複數如銅柱、銲錫球等之導電凸塊22採用面下(face down)之覆晶方式設於該線路重佈層201上並電性連接該線路重佈層201，並以底膠212包覆該些導電凸塊22；或者，該電子元件21以其非作用面21b設於該第一線路結構20上，並可藉由複數銲線(圖略)以打線方式電性連接該線路重佈層201。然而，有關該電子元件21電性連接該線路重佈層201之方式不限於上述。 In addition, the electronic component 21 is an active component, a passive component, or a combination thereof, such as a semiconductor chip, a silicon interposer (TSI) with a conductive silicon via (Through-silicon via, TSV for short) 101 ), resistor, capacitor or inductor. In this embodiment, the electronic component 21 is a semiconductor chip, which has an opposite active surface 21a and a non-active surface 21b, and the electrode pad 210 of the active surface 21a is conductive through a plurality of copper pillars, solder balls, etc. The bumps 22 are disposed on the circuit redistribution layer 201 using a face down flip-chip method and are electrically connected to the circuit redistribution layer 201, and the conductive bumps 22 are covered with primer 212; or, The electronic component 21 has its non-active surface 21b disposed on the first circuit structure 20 and can be electrically connected to the circuit redistribution layer 201 through a plurality of bonding wires (not shown) in a wire bonding manner. However, the manner in which the electronic component 21 is electrically connected to the circuit redistribution layer 201 is not limited to the above.

如圖2B所示，形成一包覆層25於該第一線路結構20上，以令該包覆層25包覆該電子元件21、底膠212與該些導電柱23，其中，該包覆層25係具有相對之第一表面25a與第二表面25b，且其以第一表面25a結合該介電層200。接著，藉由整平製程，使該包覆層25之第二表面25b齊平該導電柱23之端面23b，令該導電柱23之端面23b外露出該包覆層25之第二表面25b。 As shown in FIG. 2B , a coating layer 25 is formed on the first circuit structure 20 so that the coating layer 25 covers the electronic component 21 , the primer 212 and the conductive pillars 23 , wherein the coating layer 25 The layer 25 has an opposite first surface 25a and a second surface 25b, and the first surface 25a is combined with the dielectric layer 200. Next, through a leveling process, the second surface 25b of the cladding layer 25 is flush with the end surface 23b of the conductive pillar 23, so that the end surface 23b of the conductive pillar 23 exposes the second surface 25b of the cladding layer 25.

於本實施例中，該包覆層25係為絕緣材，如環氧樹脂之封裝膠體，其可用壓合(lamination)或模壓(molding)之方式形成於該介電層200上。 In this embodiment, the coating layer 25 is an insulating material, such as epoxy resin encapsulant, which can be formed on the dielectric layer 200 by lamination or molding.

再者，該整平製程係藉由研磨方式，移除該導電柱23之部分材質與該包覆層25之部分材質。應可理解地，該包覆層25可覆蓋該電子元件21之非作用面21b或外露出該電子元件21之非作用面21b。 Furthermore, the leveling process removes part of the material of the conductive pillar 23 and part of the covering layer 25 through grinding. It should be understood that the coating layer 25 can cover the inactive surface 21 b of the electronic component 21 or expose the inactive surface 21 b of the electronic component 21 .

如圖2C所示，形成一第二線路結構26於該包覆層25之第二表面25b上，且令該第二線路結構26電性連接該些導電柱23，其中，該第二線路結構26係具有一接地層24。另外，該電子元件21亦可選擇以其非作用面21b設於該第一線路結構20上且採用面上(face up)之方式透過如金屬凸塊、導電膠或銲錫等導電材料(圖略)電性連接該第二線路結構26之線路重佈層261。 As shown in FIG. 2C , a second circuit structure 26 is formed on the second surface 25b of the coating layer 25 , and the second circuit structure 26 is electrically connected to the conductive pillars 23 , wherein the second circuit structure 26 is electrically connected to the conductive pillars 23 . Series 26 has a ground layer 24. In addition, the electronic component 21 can also choose to have its inactive surface 21b disposed on the first circuit structure 20 and use a face up method to pass through conductive materials such as metal bumps, conductive glue or solder (not shown in the figure). ) is electrically connected to the circuit redistribution layer 261 of the second circuit structure 26 .

於本實施例中，該第二線路結構26係為無核心層式，其包括複數介電層260、及設於該介電層260上之複數扇出型線路重佈層(FORDL)261，且最外層之介電層260可作為防銲層，以令最外層之線路重佈層261部分外露出該防銲層，供作為電性接觸墊262，以後續可於該第二線路結構26上藉由銲錫材料280接置及電性連接一如雙倍數據率(Double Data Rate，簡稱DDR)同步動態隨機存取記憶體結構之封裝模組28(如圖2G所示)，其中，該接地層24係配置於複數線路重佈層261之其中一層，如內部之任一層(即非最外層)。例如，形成該線路重佈層261之材質係為銅，且形成該介電層260之材質係為如聚對二唑苯(PBO)、聚醯亞胺(PI)、預浸材(PP)或其它等之介電材。 In this embodiment, the second circuit structure 26 is of a core-less type and includes a plurality of dielectric layers 260 and a plurality of fan-out line redistribution layers (FORDL) 261 disposed on the dielectric layers 260. And the outermost dielectric layer 260 can be used as a solder mask, so that the outermost circuit redistribution layer 261 is partially exposed and used as an electrical contact pad 262 for subsequent use in the second circuit structure 26 The package module 28 of a double data rate (DDR) synchronous dynamic random access memory structure is connected and electrically connected through a solder material 280 (as shown in FIG. 2G), where the The ground layer 24 is arranged on one of the plurality of circuit redistribution layers 261, such as any inner layer (ie, not the outermost layer). For example, the material that forms the circuit redistribution layer 261 is copper, and the material that forms the dielectric layer 260 is such as poly(p-oxadiazobenzene) (PBO), polyimide (PI), or prepreg (PP). or other dielectric materials.

再者，該接地層24之圖案設計係為規則化排列，如圖3A所示，其包含多個呈矩陣排列的矩形(如正方形)片體24a(如200×200微米(um)之長寬尺寸)，使該接地層24之整體圖案區域呈矩形輪廓區域，且相鄰兩片體24a之間藉 由連接段24b(其呈長方形區域)相連，其中，該連接段24b形成有至少一溝槽(slot)241，且於該片體24a上形成有至少一開孔(hole)240。例如，於該片體24a上係形成複數(如九個)陣列排設(如三行三列)之開孔240，且該開孔240可為矩形、圓形或其它形狀，並於該接地層24之圖案之最邊緣的溝槽241可具有一鄰接該接地層24外緣24c之開口T而呈開放式(如圖3A所示之上側邊緣P1)或不連通該接地層24外緣24c而呈封閉式(如圖3A所示之左側邊緣P2)。 Furthermore, the pattern design of the ground layer 24 is a regular arrangement, as shown in Figure 3A, which includes a plurality of rectangular (such as square) sheets 24a (such as 200×200 micrometers (um) in length and width) arranged in a matrix. size), so that the overall pattern area of the ground layer 24 is a rectangular outline area, and there is a gap between two adjacent pieces 24a They are connected by a connecting section 24b (which is a rectangular area). The connecting section 24b is formed with at least one groove (slot) 241, and the sheet body 24a is formed with at least one opening (hole) 240. For example, a plurality (such as nine) of openings 240 arranged in an array (such as three rows and three columns) are formed on the sheet 24a, and the openings 240 can be rectangular, circular or other shapes, and are connected to the connection. The edgemost trench 241 of the pattern of the ground layer 24 may have an opening T adjacent to the outer edge 24c of the ground layer 24 and be open (upper edge P1 as shown in FIG. 3A) or not connected to the outer edge 24c of the ground layer 24. It is closed (left edge P2 as shown in Figure 3A).

應可理解地，該接地層24可於該介電層260之整層之全部表面上形成上述之圖案化銅面，亦可依需求於該介電層260之整層之局部表面上形成上述之圖案化銅面34a，如圖3B所示之中央1/3區域，而其餘之上下1/3區域呈單一片狀(即無圖案化)銅面34b設計，故本發明並無特別限制該接地層24之圖案化佈設區域。 It should be understood that the ground layer 24 can form the above-mentioned patterned copper surface on the entire surface of the entire layer of the dielectric layer 260, or can also form the above-mentioned patterned copper surface on a partial surface of the entire layer of the dielectric layer 260 as required. The patterned copper surface 34a is the central 1/3 area as shown in Figure 3B, and the remaining upper and lower 1/3 areas are designed as a single sheet (ie, no pattern) copper surface 34b. Therefore, the present invention does not specifically limit this Patterned layout area of ground layer 24 .

又，該連接段24b係連接該複數片體24a之相鄰兩者之角落處，使該片體24a之邊緣的相對兩側之間形成一個溝槽241，使該溝槽241係設置於其對應各該片體24a之邊緣的中央位置。另於其它實施例中，相鄰兩片體24a之間可設置複數陣列排設之溝槽441，如圖4A至圖4C所示，以令該些溝槽441可沿兩片體24a之間的連接段24b(或長方形區域)之長度方向(如圖4A所示)、寬度方向(如圖4B所示)或上述兩方向(如圖4C所示)間隔配置。 In addition, the connecting section 24b is connected to the corners of two adjacent pieces of the plurality of pieces 24a, so that a groove 241 is formed between the opposite sides of the edge of the piece 24a, so that the groove 241 is disposed on it. Corresponds to the center position of the edge of each piece 24a. In other embodiments, a plurality of grooves 441 arranged in an array can be provided between two adjacent pieces 24a, as shown in FIGS. 4A to 4C, so that these grooves 441 can be arranged along the space between the two pieces 24a. The connecting sections 24b (or rectangular areas) are arranged at intervals in the length direction (as shown in FIG. 4A), the width direction (as shown in FIG. 4B), or both directions (as shown in FIG. 4C).

另外，單一該連接段24b上之溝槽241,441的總長度D,(D1+D2)佔其對應之片體24a之平行該溝槽241,441長度的邊緣的邊長L(即長度方向的邊長)的至少60%以上(如60~95%，較佳為80~95%之間)，且單一該連接段24b上之溝槽241,441的總寬度R,(R1+R2)佔其對應之片體24a之平行該溝槽241,441寬度的邊緣的邊長W(即寬度方向的邊長)的至少1%以上(如1~10%，較佳為5~10%之 間)，而單一該片體24a上之所有該開孔240的總面積B佔該片體24a四邊輪廓之垂直投影之面積A(即A=L*W)的至少10%以上(如10~40%，較佳為10~30%之間)。舉例而言，該片體24a之正方形為邊長10單位，其面積A即10*10=100平方單位，正方形開孔240為邊長2單位，其總面積B即9*(2*2)=36平方單位，故B/A=36/100=0.36=36%。 In addition, the total length D, (D1 + D2) of the grooves 241, 441 on the single connecting section 24b occupies the side length L of the edge of the corresponding piece 24a parallel to the length of the grooves 241, 441 (ie, the side length in the length direction) At least 60% (such as 60~95%, preferably between 80~95%), and the total width R, (R1+R2) of the groove 241, 441 on the single connecting section 24b occupies the corresponding sheet body The side length W (ie, the side length in the width direction) of the edge of 24a parallel to the width of the groove 241, 441 is at least 1% or more (such as 1~10%, preferably 5~10%) ), and the total area B of all the openings 240 on a single sheet body 24a accounts for at least 10% of the area A of the vertical projection of the four-sided outline of the sheet body 24a (i.e. A=L*W) (such as 10~ 40%, preferably between 10 and 30%). For example, the square body 24a has a side length of 10 units, and its area A is 10*10=100 square units. The square opening 240 has a side length of 2 units, and its total area B is 9*(2*2). =36 square units, so B/A=36/100=0.36=36%.

應可理解地，該第一線路結構20之其中一線路重佈層201亦可設計成上述接地層24。 It should be understood that one of the circuit redistribution layers 201 of the first circuit structure 20 can also be designed as the above-mentioned ground layer 24 .

如圖2D所示，移除該承載板9及其上之離形層90與黏著層91，以外露該第一線路結構20。 As shown in FIG. 2D , the carrier board 9 and the release layer 90 and adhesive layer 91 thereon are removed to expose the first circuit structure 20 .

如圖2E所示，於該第一線路結構20之外露側之線路重佈層201上形成複數如銲球之導電元件27，以令該複數導電元件27電性連接該導電柱23及/或該電子元件21。 As shown in FIG. 2E , a plurality of conductive elements 27 such as solder balls are formed on the circuit redistribution layer 201 on the exposed side of the first circuit structure 20 so that the plurality of conductive elements 27 are electrically connected to the conductive pillars 23 and/or The electronic component 21.

於本實施例中，可形成一如防銲層之絕緣保護層203於該介電層200上，且於該絕緣保護層203上形成複數開孔，以令該線路重佈層201外露出該些開孔，俾供結合該導電元件27。 In this embodiment, an insulating protective layer 203 such as a solder mask can be formed on the dielectric layer 200, and a plurality of openings can be formed on the insulating protective layer 203 to expose the circuit redistribution layer 201. Some openings are provided for coupling the conductive element 27.

再者，於該第一線路結構20之外露線路重佈層201上可接置至少一輔助功能元件29，如被動元件。 Furthermore, at least one auxiliary functional component 29, such as a passive component, can be connected to the exposed circuit redistribution layer 201 of the first circuit structure 20.

如圖2F所示，沿圖中所示之切割路徑S進行切單製程，以獲取該電子封裝件2，且於後續製程中，如圖2G所示，該電子封裝件2可藉由該些導電元件27接置於一如電路板之電子裝置8上。 As shown in Figure 2F, a cutting process is performed along the cutting path S shown in the figure to obtain the electronic package 2. In the subsequent process, as shown in Figure 2G, the electronic package 2 can be processed through these The conductive element 27 is connected to the electronic device 8 such as a circuit board.

因此，本發明之製法主要藉由扇出型線路重佈層(Fan-out Redistribution layer，簡稱FORDL)201,261製作該第一線路結構20與第二線路結 構26，以取代習知具有核心層(core)之封裝基板，故本發明之電子封裝件2能有效降低整體之封裝高度。 Therefore, the manufacturing method of the present invention mainly uses a fan-out redistribution layer (FORDL) 201, 261 to fabricate the first circuit structure 20 and the second circuit structure. The structure 26 is used to replace the conventional packaging substrate with a core layer, so the electronic package 2 of the present invention can effectively reduce the overall packaging height.

再者，將該接地層24之初始整面式銅片切割成多個矩陣排列的片體24a，且以連接段24b局部相連，使相鄰兩片體24a之間形成至少一溝槽241,441，以提升整體線路結構的撓性，故相較於習知技術，本發明之電子封裝件2可具有較佳的翹曲(warpage)控制表現，進而提升該封裝模組28設於該第二線路結構26上的結合良率。 Furthermore, the initial solid-surface copper sheet of the ground layer 24 is cut into a plurality of matrix-arranged sheets 24a, and partially connected by connecting sections 24b, so that at least one trench 241, 441 is formed between two adjacent sheets 24a. In order to improve the flexibility of the overall circuit structure, compared with the conventional technology, the electronic package 2 of the present invention can have better warpage control performance, thereby improving the packaging module 28 disposed on the second circuit. Bonding yield on structure 26.

又，該溝槽241,441的的總長度D,(D1+D2)(或總寬度R,(R1+R2))佔其對應之片體24a之邊長的比例關係可依相配合之該封裝模組28的翹曲狀況進行調整，使該電子封裝件2與該封裝模組28的翹曲程度可相互配合，以提升兩者的結合良率。同理地，該片體24a中所配置之開孔240可使線路結構之撓性更佳，故該開孔240的分布密度(即面積占比)可依該封裝模組28的翹曲狀況進行調整，使該電子封裝件2與該封裝模組28的翹曲程度可相互配合，以提升兩者的結合良率。 In addition, the ratio of the total length D, (D1+D2) (or total width R, (R1+R2)) of the trenches 241, 441 to the side length of the corresponding sheet 24a can be determined according to the matching package mold. The warpage condition of the group 28 is adjusted so that the warpage degrees of the electronic package 2 and the packaging module 28 can match each other to improve the combined yield of the two. Similarly, the openings 240 arranged in the sheet body 24a can make the circuit structure more flexible, so the distribution density (i.e., the area ratio) of the openings 240 can be determined according to the warpage condition of the package module 28 Adjustment is made so that the warpage degrees of the electronic package 2 and the packaging module 28 can match each other to improve the combined yield of the two.

另外，該接地層24之圖案之最邊緣的溝槽241,441可呈開放式或封閉式，且相較於封閉式，採用開放式的線路結構之撓性更佳，故該電子封裝件2可依該封裝模組28的翹曲狀況選擇開放式及/或封閉式，使該電子封裝件2與該封裝模組28的翹曲程度可相互配合，以提升兩者的結合良率。 In addition, the trenches 241 and 441 at the outermost edge of the pattern of the ground layer 24 can be open or closed. Compared with the closed type, the open circuit structure has better flexibility, so the electronic package 2 can be The warpage state of the packaging module 28 is selected to be open and/or closed, so that the warpage degrees of the electronic package 2 and the packaging module 28 can match each other to improve the combined yield of the two.

圖5係為本發明之電子封裝件之第二實施例之局部上視示意圖。本實施例與第一實施例之差異在於接地層之圖案，其它製程大致相同，故以下僅說明相異處，而不再贅述相同處。 FIG. 5 is a partial top view of the electronic package according to the second embodiment of the present invention. The difference between this embodiment and the first embodiment lies in the pattern of the ground layer, and other manufacturing processes are roughly the same. Therefore, only the differences will be described below, and the similarities will not be described again.

如圖5所示，該接地層54係包含多個呈矩陣排列的矩形片體24a，使該接地層54之整體圖案區域呈矩形輪廓區域，且相鄰兩片體24a之間藉由連接段54b(其呈長方形區域)相連，其中，該連接段54b對應該片體24a的角落處(corner)形成有溝槽541，使該複數片體24a之間所形成之該些溝槽541相互連通而於對應各該片體24a之邊角處位置形成類十字形槽孔P，且於該片體24a上形成有至少一開孔240。 As shown in Figure 5, the ground layer 54 includes a plurality of rectangular pieces 24a arranged in a matrix, so that the overall pattern area of the ground layer 54 is a rectangular outline area, and two adjacent pieces 24a are connected by connecting sections. 54b (which is a rectangular area) is connected, wherein the connecting section 54b is formed with a groove 541 corresponding to the corner of the sheet body 24a, so that the grooves 541 formed between the plurality of sheet bodies 24a are connected to each other. A cross-shaped slot P is formed at a position corresponding to the corner of each piece 24a, and at least one opening 240 is formed on the piece 24a.

於另一實施例中，該連接段54b可為包含至少一橋接線(bridge trace)540之樣式，如圖5所示之一條或圖6所示之二條，甚至更多條，並無特別限制。例如，該連接段54b於其中央位置處可增設至少一溝槽641，如圖6所示，使該連接段54b包含二條橋接線540，故相鄰之該類十字形槽孔P之間設置有位置對應該片體24a之邊緣的中央位置之溝槽641；可理解的是，若該連接段54b包含三條以上的橋接線540，則相鄰之該類十字形槽孔P之間設置有陣列排設且位置對應該片體24a之邊緣的中央位置之複數溝槽641(圖未示，可參考圖4A~圖4C的溝槽441配置)。 In another embodiment, the connection section 54b may be in a form including at least one bridge trace 540, one as shown in FIG. 5 or two as shown in FIG. 6, or even more, and is not particularly limited. For example, the connecting section 54b can be added with at least one groove 641 at its central position, as shown in Figure 6, so that the connecting section 54b includes two bridge lines 540, so adjacent cross-shaped slots P are provided between There is a groove 641 corresponding to the center position of the edge of the piece 24a; it can be understood that if the connecting section 54b includes more than three bridge lines 540, then adjacent cross-shaped slots P are provided with A plurality of grooves 641 are arranged in an array and positioned corresponding to the center position of the edge of the sheet body 24a (not shown in the figure, please refer to the configuration of the grooves 441 in Figures 4A to 4C).

再者，該開孔240可為圓形、矩形或其它形狀，並於該接地層54之圖案之最邊緣的溝槽541可具有一鄰接該接地層54外緣54c之開口T而呈開放式(如圖5所示之上側邊緣)或不連通該接地層54外緣54c而呈封閉式(如圖5所示之左側邊緣)。 Furthermore, the opening 240 can be circular, rectangular or other shapes, and the trench 541 at the edge of the pattern of the ground layer 54 can have an opening T adjacent to the outer edge 54c of the ground layer 54 and be open. (the upper edge as shown in Figure 5) or is not connected to the outer edge 54c of the ground layer 54 and is closed (the left edge as shown in Figure 5).

又，該接地層54可於該介電層260之整層之全部表面上形成圖案化銅面，亦可依需求於該介電層260之整層之局部表面上形成圖案化銅面。 In addition, the ground layer 54 can form a patterned copper surface on the entire surface of the entire layer of the dielectric layer 260, or can also form a patterned copper surface on a partial surface of the entire layer of the dielectric layer 260 as required.

另外，單一該連接段54b上之溝槽541的總長度(L1+L2),(L1+L2+L3)佔其對應之片體24a之平行該溝槽541長度的邊緣的邊長L (即長度方向的邊長)的至少60%以上(如60~95%，較佳為80~95%之間)，且單一該連接段54b上之溝槽541的總寬度W1佔其對應之片體24a之平行該溝槽541寬度的邊緣的邊長W(即寬度方向的邊長)的至少1%以上(如1~10%，較佳為5~10%之間)，而單一該片體24a上之所有該開孔240的總面積B佔該片體24a四邊輪廓之垂直投影之面積A的至少10%以上(如10~40%，較佳為10~30%之間)。舉例而言，該片體24a之正方形為邊長10單位，其面積A即10*10=100平方單位，正方形開孔240為邊長2單位，其總面積B即9*(2*2)=36平方單位，故B/A=36/100=0.36=36%。 In addition, the total length (L1+L2), (L1+L2+L3) of the groove 541 on the single connecting section 54b occupies the side length L of the edge of the corresponding piece 24a parallel to the length of the groove 541. (i.e., the side length in the length direction) is at least 60% (such as 60~95%, preferably between 80~95%), and the total width W1 of the groove 541 on the single connecting section 54b accounts for its corresponding The side length W (ie, the side length in the width direction) of the edge of the sheet body 24a that is parallel to the width of the groove 541 is at least 1% or more (such as 1~10%, preferably between 5~10%), and a single The total area B of all the openings 240 on the sheet body 24a accounts for at least 10% or more of the area A of the vertical projection of the four sides of the sheet body 24a (such as 10~40%, preferably between 10~30%). For example, the square body 24a has a side length of 10 units, and its area A is 10*10=100 square units. The square opening 240 has a side length of 2 units, and its total area B is 9*(2*2). =36 square units, so B/A=36/100=0.36=36%.

應可理解地，該第一線路結構20之其中一線路重佈層201亦可設計成上述接地層54。 It should be understood that one of the circuit redistribution layers 201 of the first circuit structure 20 can also be designed as the above-mentioned ground layer 54 .

因此，本實施例之接地層54係將複數溝槽541相互連通而形成十字形槽孔，以提升整體線路結構的撓性，但第一實施例之接地層24之圖案設計的結構撓性優於第二實施例之接地層54之圖案設計的結構撓性。 Therefore, the ground layer 54 of this embodiment connects a plurality of trenches 541 to form cross-shaped slots to improve the flexibility of the overall circuit structure. However, the pattern design of the ground layer 24 of the first embodiment has excellent structural flexibility. The pattern design of the ground layer 54 in the second embodiment is structurally flexible.

圖7A至圖7F係為本發明之電子封裝件之第三實施例之示意圖。本實施例與上述實施例之差異在於接地層之層數，其它製程大致相同，故以下僅說明相異處，而不再贅述相同處。 7A to 7F are schematic diagrams of an electronic package according to a third embodiment of the present invention. The difference between this embodiment and the above-mentioned embodiment lies in the number of ground layers, and other manufacturing processes are roughly the same. Therefore, only the differences will be described below, and the similarities will not be described again.

如圖7A及圖7B所示，在圖2C之該第一線路結構20及該第二線路結構26之至少一者中係設有兩層接地層，其定義為第一接地層71與第二接地層72，該第一與第二接地層71,72的片體71a,72a之位置係上下對應，且該第一與第二接地層71,72之溝槽711,721係形成於該片體71a,72a上。 As shown in FIGS. 7A and 7B , two ground layers are provided in at least one of the first circuit structure 20 and the second circuit structure 26 in FIG. 2C , which are defined as the first ground layer 71 and the second ground layer 71 . In the ground layer 72, the positions of the pieces 71a and 72a of the first and second ground layers 71 and 72 are corresponding up and down, and the grooves 711 and 721 of the first and second ground layers 71 and 72 are formed in the piece 71a. , 72a on.

於本實施例中，如圖7C所示，該第一與第二接地層71,72之溝槽711,721於垂直方向不重疊。例如，該溝槽711,721係形成於該片體71a,72a之相對 兩邊緣，且該溝槽711,721未延伸至片體71a,72a之角落處，以當該第一接地層71之溝槽711形成於矩形之橫向邊緣時，該第二接地層72之溝槽721形成於矩形之直向邊緣，而當該第一接地層71之溝槽711形成於矩形之直向邊緣時，該第二接地層72之溝槽721形成於矩形之橫向邊緣。 In this embodiment, as shown in FIG. 7C , the trenches 711 and 721 of the first and second ground layers 71 and 72 do not overlap in the vertical direction. For example, the grooves 711, 721 are formed on the opposite sides of the sheets 71a, 72a. Both edges, and the grooves 711, 721 do not extend to the corners of the sheets 71a, 72a, so that when the groove 711 of the first ground layer 71 is formed on the lateral edges of the rectangle, the groove 721 of the second ground layer 72 Formed at the vertical edge of the rectangle, and when the trench 711 of the first ground layer 71 is formed at the vertical edge of the rectangle, the trench 721 of the second ground layer 72 is formed at the lateral edge of the rectangle.

再者，該第一與第二接地層71,72之片體71a,72a上形成有至少一如圓形之開孔710,720，使該第一與第二接地層71,72之開孔710,720於垂直方向亦不重疊，如圖7A及圖7C所示。 Furthermore, at least one circular opening 710, 720 is formed on the sheets 71a, 72a of the first and second ground layers 71, 72, so that the openings 710, 720 of the first and second ground layers 71, 72 are in There is no overlap in the vertical direction, as shown in Figure 7A and Figure 7C.

又，該溝槽711,721的總長度D3,D3’佔其對應之片體71a,72a之平行該溝槽711,721長度的邊緣的邊長L,W’(即長度方向的邊長)的至少60%以上(如60~95%，較佳為80~95%之間)，且該溝槽711,721的總寬度(R3+R4),(R3’+R4’)佔其對應之片體71a,72a之平行該溝槽711,721寬度的邊緣的邊長W,L’(即寬度方向的邊長)的至少1%以上(如1~10%，較佳為5~10%之間)，而單一該片體71a,72a上之所有該開孔710,720的總面積B佔該片體71a,72a四邊輪廓之垂直投影之面積A的至少10%以上(如10~40%，較佳為10~30%之間)。舉例而言，該片體71a,72a之正方形為邊長10單位，其面積A即10*10=100平方單位，圓形開孔710,720為直徑1單位，其總面積B即20*(0.5*0.5)π=5 π平方單位，故B/A≒15.7/100≒0.16≒16%。 In addition, the total lengths D3 and D3' of the grooves 711 and 721 account for at least 60% of the side lengths L and W' (i.e. the length of the sides in the length direction) of the edges of the corresponding pieces 71a and 72a that are parallel to the length of the grooves 711 and 721. Above (such as 60~95%, preferably between 80~95%), and the total width (R3+R4), (R3'+R4') of the grooves 711, 721 occupies the corresponding width of the sheet 71a, 72a The side length W, L' (ie, the side length in the width direction) of the edge parallel to the width of the trench 711, 721 is at least 1% or more (such as 1~10%, preferably between 5~10%), and a single piece of The total area B of all the openings 710, 720 on the body 71a, 72a accounts for at least 10% or more (such as 10~40%, preferably 10~30%) of the vertical projection area A of the four-side outline of the body 71a, 72a. between). For example, the square of the sheet 71a, 72a has a side length of 10 units, and its area A is 10*10=100 square units. The circular openings 710, 720 have a diameter of 1 unit, and its total area B is 20*(0.5* 0.5)π=5 π square unit, so B/A≒15.7/100≒0.16≒16%.

因此，藉由上下溝槽711,721相互錯位而不重疊，以令該第一與第二接地層71,72於垂直方向上呈現全金屬覆蓋面而無孔形之圖案，使該第一與第二接地層71,72之接地及屏蔽效果更優於第一與第二實施例之接地及屏蔽效果。 Therefore, by dislocating the upper and lower trenches 711 and 721 without overlapping each other, the first and second ground layers 71 and 72 present a pattern of full metal coverage without holes in the vertical direction, so that the first and second ground layers 71 and 72 are The grounding and shielding effects of the ground layers 71 and 72 are better than those of the first and second embodiments.

再者，該第一與第二接地層71,72之間係未設有線路重佈層201,261，故可於該第一與第二接地層71,72之間分別對應該複數片體71a,72a處設 置複數導電體73，如圖7D至圖7F所示之金屬圓柱(如銅柱)，且該第一與第二接地層71,72的片體71a,72a藉由該複數導電體73之至少其中一者電性連接。例如，該導電體73係位於該片體71a,72a之中間位置。 Furthermore, there are no circuit redistribution layers 201,261 between the first and second ground layers 71,72, so the plurality of sheets 71a can be respectively corresponding between the first and second ground layers 71,72. 72a location A plurality of conductors 73 are placed, such as metal cylinders (such as copper columns) as shown in Figures 7D to 7F, and the sheets 71a, 72a of the first and second ground layers 71, 72 are connected by at least one of the plurality of conductors 73. One of them is electrically connected. For example, the conductor 73 is located in the middle of the sheets 71a and 72a.

因此，藉由該導電體73電性連通上下片體71a,72a，使接地傳輸距離更短，以減少訊號延遲(delay)，使電性表現更好。 Therefore, the conductor 73 electrically connects the upper and lower sheets 71a, 72a, thereby shortening the ground transmission distance, reducing signal delay, and achieving better electrical performance.

圖8A至圖8D係為本發明之電子封裝件之第四實施例之局部上視示意圖。本實施例與第三實施例之差異在於上下溝槽之錯位方式，其它製程大致相同，故以下僅說明相異處，而不再贅述相同處。 8A to 8D are partial top views of the fourth embodiment of the electronic package of the present invention. The difference between this embodiment and the third embodiment lies in the misalignment of the upper and lower grooves. The other manufacturing processes are roughly the same. Therefore, only the differences will be described below and the similarities will not be described again.

如圖8A及圖8B所示，該溝槽811,821係延伸至其片體71a,72a之角落處，並使同一片體71a,72a上之兩溝槽811,821朝不同方向延伸至角落處，且該溝槽811,821延伸至該片體71a,72a之邊緣，以於該第一與第二接地層71,72之各片體71a,72a之斜對角之角落處形成連接段84a,84b。 As shown in Figures 8A and 8B, the grooves 811, 821 extend to the corners of the pieces 71a, 72a, and the two grooves 811, 821 on the same piece 71a, 72a extend to the corners in different directions, and the grooves 811, 821 extend to the corners of the pieces 71a, 72a. The grooves 811, 821 extend to the edges of the pieces 71a, 72a to form connecting sections 84a, 84b at diagonally opposite corners of the pieces 71a, 72a of the first and second ground layers 71, 72.

於本實施例中，該複數片體71a,72a之間所形成之複數該溝槽811,821係相互連通而於對應各該片體71a,72a之邊角處位置形成類十字形槽孔Z1,Z2。 In this embodiment, the plurality of grooves 811, 821 formed between the plurality of pieces 71a, 72a are interconnected to form quasi-cross-shaped slots Z1, Z2 at the corners corresponding to the pieces 71a, 72a. .

再者，該溝槽811,821的總長度D4,D4’佔其對應之片體71a,72a之平行該溝槽811,821長度的邊緣的邊長L,W’(即長度方向的邊長)的至少60%以上(如60~95%，較佳為80~95%之間)，且該溝槽811,821的總寬度(R5+R6),(R5’+R6’)佔其對應之片體71a,72a之平行該溝槽811,821寬度的邊緣的邊長W,L’(即寬度方向的邊長)的至少1%以上(如1~10%，較佳為5~10%之間)，而單一該片體71a,72a上之所有該開孔710,720的總面積B佔該片體71a,72a四邊輪廓之垂直投影之面積A的至少10%以上(如10~40%，較佳為10~30%之間)。舉 例而言，該片體71a,72a之正方形為邊長10單位，其面積A即10*10=100平方單位，圓形開孔710,720為直徑1單位，其總面積B即20*(0.5*0.5)π=5 π平方單位，故B/A≒15.7/100≒0.16≒16%。 Furthermore, the total length D4, D4' of the groove 811, 821 accounts for at least 60% of the side length L, W' (i.e., the side length in the length direction) of the edge of the corresponding piece 71a, 72a parallel to the length of the groove 811, 821. % or more (such as 60~95%, preferably between 80~95%), and the total width (R5+R6), (R5'+R6') of the groove 811, 821 occupies the corresponding sheet body 71a, 72a The side length W, L' (ie, the side length in the width direction) of the edge parallel to the width of the groove 811, 821 is at least 1% (such as 1~10%, preferably between 5~10%), and a single The total area B of all the openings 710, 720 on the sheet body 71a, 72a accounts for at least 10% or more of the area A of the vertical projection of the four sides of the sheet body 71a, 72a (such as 10~40%, preferably 10~30% between). For example, the square of the sheet 71a, 72a has a side length of 10 units, and its area A is 10*10=100 square units. The circular openings 710, 720 have a diameter of 1 unit, and its total area B is 20*(0.5* 0.5) π =5 π square unit, so B/A≒15.7/100≒0.16≒16%.

因此，藉由上下溝槽811,821相互錯位而不重疊，以令該第一與第二接地層71,72於垂直方向上呈現全金屬覆蓋面而無孔形之圖案，使該第一與第二接地層71,72之接地及屏蔽效果更優於第一與第二實施例之接地及屏蔽效果。 Therefore, by dislocating the upper and lower trenches 811 and 821 without overlapping, the first and second ground layers 71 and 72 present a pattern of full metal coverage without holes in the vertical direction, so that the first and second ground layers 71 and 72 are The grounding and shielding effects of the ground layers 71 and 72 are better than those of the first and second embodiments.

再者，該第一與第二接地層71,72之間分別對應該複數片體71a,72a處亦可設置複數導電體73，如圖8C及圖8D所示，使該第一與第二接地層71,72的片體71a,72a藉由該複數導電體73之至少其中一者電性連接，以縮短接地傳輸距離而減少訊號延遲，進而優化電性表現。 Furthermore, a plurality of conductors 73 can also be provided between the first and second ground layers 71 and 72 respectively corresponding to the plurality of sheets 71a and 72a, as shown in FIG. 8C and FIG. 8D, so that the first and second ground layers 71 and 72 are connected to each other. The pieces 71a and 72a of the ground layers 71 and 72 are electrically connected through at least one of the plurality of conductors 73 to shorten the ground transmission distance and reduce signal delay, thereby optimizing the electrical performance.

圖9A至圖9D係為本發明之電子封裝件之第五實施例之局部上視示意圖。本實施例與上述實施例之差異在於溝槽之設計，其它製程大致相同，故以下僅說明相異處，而不再贅述相同處。 9A to 9D are partial top views of the fifth embodiment of the electronic package of the present invention. The difference between this embodiment and the above-mentioned embodiment lies in the design of the trench, and other manufacturing processes are roughly the same. Therefore, only the differences will be described below, and the similarities will not be described again.

如圖9A及圖9B所示，基於圖3A所示之態樣，於該第一與第二接地層71,72之各片體71a,72a之斜對角之角落處形成連接段94a,94b，以將同一層之四個片體71a,72a相接，使同一層之四個片體71a,72a之間所形成之複數溝槽911,921相互連通而於對應各該片體71a,72a之邊角處位置形成一大面積之類十字形槽孔X1,X2。換言之，將該片體71a,72a之各邊長L,W,L’,W’移除部分材質，即可形成該連接段94a,94b，且該片體71a,72a所移除之部分將形成溝槽911,921。 As shown in Figures 9A and 9B, based on the aspect shown in Figure 3A, connection sections 94a, 94b are formed at diagonally opposite corners of each piece 71a, 72a of the first and second ground layers 71, 72. , so as to connect the four sheet bodies 71a, 72a of the same layer, so that the plurality of grooves 911, 921 formed between the four sheet bodies 71a, 72a of the same layer are connected to each other and at the edges corresponding to the respective sheet bodies 71a, 72a. A large area of cross-shaped slots X1, X2 is formed at the corners. In other words, the connecting sections 94a, 94b can be formed by removing part of the material of the side lengths L, W, L', W' of the piece 71a, 72a, and the removed parts of the piece 71a, 72a will Trench 911,921 is formed.

於本實施例中，該第一接地層71之類十字形槽孔X1之中心交會處係對應重疊該第二接地層72之四個相接之連接段94b，且該第二接地層72之類十字形槽孔X2之中心交會處亦對應重疊該第一接地層71之四個相接之連接段94a， 故該第一與第二接地層71,72於重疊排設下之圖案於垂直方向上係呈現直線狀槽孔Y，如圖9C所示。 In this embodiment, the central intersection of the cross-shaped slot X1 of the first ground layer 71 corresponds to overlapping the four connecting sections 94b of the second ground layer 72, and the The central intersection of the cross-shaped slot X2 also overlaps the four connecting sections 94a of the first ground layer 71. Therefore, the pattern of the overlapping arrangement of the first and second ground layers 71 and 72 presents linear slots Y in the vertical direction, as shown in FIG. 9C .

因此，藉由該類十字形槽孔X1,X2之設計，使該第一與第二接地層71,72之溝槽911,921之延伸區域變大，以強化該第一與第二接地層71,72之撓性。 Therefore, through the design of the cross-shaped slots X1 and 72 flexibility.

再者，該第一與第二接地層71,72之間分別對應該複數片體71a,72a處亦可設置複數導電體73，如圖9D所示，使該第一與第二接地層71,72的片體71a,72a藉由該複數導電體73之至少其中一者電性連接，以縮短接地傳輸距離而減少訊號延遲，進而優化電性表現。 Furthermore, a plurality of conductors 73 can also be provided between the first and second ground layers 71 and 72 corresponding to the plurality of sheets 71a and 72a, as shown in FIG. 9D, so that the first and second ground layers 71 The sheets 71a and 72a of 72 are electrically connected through at least one of the plurality of conductors 73 to shorten the ground transmission distance and reduce signal delay, thereby optimizing the electrical performance.

於本實施例中，該溝槽911,921的總長度D5,D5’佔其對應之片體71a,72a之平行該溝槽911,921長度的邊緣的邊長L,W,L’,W’的至少60%以上(如60~95%，較佳為80~95%之間)，且該溝槽911,921的總寬度(R7+R8),(R9+R10),(R7’+R8’),(R9’+R10’)佔其對應之片體71a,72a之平行該溝槽911,921寬度的邊緣的邊長W,L,W’,L’(即寬度方向的邊長)的至少1%以上(如1~10%，較佳為5~10%之間)，而單一該片體71a,72a上之所有該開孔710,720的總面積B佔該片體71a,72a四邊輪廓之垂直投影之面積A的至少10%以上(如10~40%，較佳為10~30%之間)。舉例而言，該片體71a,72a之正方形為邊長10單位，其面積A即10*10=100平方單位，圓形開孔710,720為直徑1單位，其總面積B即20*(0.5*0.5)π=5 π平方單位，故B/A≒15.7/100≒0.16≒16%。 In this embodiment, the total length D5, D5' of the grooves 911, 921 accounts for at least 60% of the side lengths L, W, L', W' of the edges of the corresponding pieces 71a, 72a parallel to the length of the grooves 911, 921. % or more (such as 60~95%, preferably between 80~95%), and the total width of the trench 911,921 is (R7+R8), (R9+R10), (R7'+R8'), (R9 '+R10') accounts for at least 1% of the side lengths W, L, W', L' (i.e., the side lengths in the width direction) of the edges parallel to the width of the grooves 911, 921 of the corresponding pieces 71a, 72a (such as 1~10%, preferably between 5~10%), and the total area B of all the openings 710,720 on a single sheet body 71a, 72a accounts for the area A of the vertical projection of the four sides of the sheet body 71a, 72a At least 10% or more (such as 10~40%, preferably between 10~30%). For example, the square of the sheet 71a, 72a has a side length of 10 units, and its area A is 10*10=100 square units. The circular openings 710, 720 have a diameter of 1 unit, and its total area B is 20*(0.5* 0.5) π =5 π square unit, so B/A≒15.7/100≒0.16≒16%.

本發明亦提供一種電子封裝件2，係包括：一包覆層25、一第一線路結構20、一第二線路結構26、複數導電柱23、至少一電子元件21以及至少一接地層24,54(第一接地層71與第二接地層72)。 The invention also provides an electronic package 2, which includes: a coating layer 25, a first circuit structure 20, a second circuit structure 26, a plurality of conductive pillars 23, at least one electronic component 21 and at least one ground layer 24. 54 (first ground layer 71 and second ground layer 72).

所述之包覆層25係具有相對之第一表面25a與第二表面25b。 The coating layer 25 has an opposite first surface 25a and a second surface 25b.

所述之第一線路結構20係設於該包覆層25之第一表面25a上。 The first circuit structure 20 is provided on the first surface 25a of the covering layer 25.

所述之第二線路結構26係設於該包覆層25之第二表面25b上，其中，扇出型線路重佈層201,261係配置於該第一線路結構20與第二線路結構26中。 The second circuit structure 26 is disposed on the second surface 25b of the cladding layer 25, wherein the fan-out circuit redistribution layers 201, 261 are disposed in the first circuit structure 20 and the second circuit structure 26.

所述之導電柱23係嵌埋於該包覆層25中且電性連接該第一線路結構20與第二線路結構26。 The conductive pillars 23 are embedded in the cladding layer 25 and electrically connect the first circuit structure 20 and the second circuit structure 26 .

所述之電子元件21係設於該第一線路結構20上，並嵌埋於該包覆層25中且電性連接該第一線路結構20或第二線路結構26。 The electronic component 21 is disposed on the first circuit structure 20, embedded in the coating layer 25, and electrically connected to the first circuit structure 20 or the second circuit structure 26.

所述之接地層24,54(第一接地層71與第二接地層72)係設於該第一線路結構20及第二線路結構26之至少一者中，其中，該至少一接地層24,54(第一接地層71與第二接地層72)係包含複數陣列排設之片體24a,71a,72a，且每二相鄰之該片體24a,71a,72a之間設置有至少一溝槽241,441,541,641,711,721,811,821,911,921。 The ground layers 24, 54 (the first ground layer 71 and the second ground layer 72) are provided in at least one of the first circuit structure 20 and the second circuit structure 26, wherein the at least one ground layer 24 , 54 (the first ground layer 71 and the second ground layer 72) includes a plurality of sheets 24a, 71a, and 72a arranged in an array, and at least one is disposed between each two adjacent sheets 24a, 71a, and 72a. Trench 241,441,541,641,711,721,811,821,911,921.

於一實施例中，該第一線路結構20及該第二線路結構26之至少一者中係設有第一接地層71與第二接地層72，且該第一接地層71與第二接地層72的片體71a,72a之位置係上下對應，並使該第一接地層71與第二接地層72之溝槽711,721,811,821,911,921於垂直方向不重疊。進一步，還包括分別對應該複數片體71a,72a且設置於該第一接地層71與第二接地層72之間的複數導電體73，且該第一接地層71與第二接地層72的片體71a,72a藉由該複數導電體73之至少其中一者電性連接。 In one embodiment, at least one of the first circuit structure 20 and the second circuit structure 26 is provided with a first ground layer 71 and a second ground layer 72, and the first ground layer 71 and the second ground layer The positions of the pieces 71a and 72a of the ground layer 72 are corresponding up and down, so that the trenches 711, 721, 811, 821, 911, 921 of the first ground layer 71 and the second ground layer 72 do not overlap in the vertical direction. Further, it also includes a plurality of conductors 73 respectively corresponding to the plurality of sheets 71a, 72a and disposed between the first ground layer 71 and the second ground layer 72, and the first ground layer 71 and the second ground layer 72 are The pieces 71 a and 72 a are electrically connected through at least one of the plurality of conductors 73 .

於一實施例中，各該片體24a,71a,72a上形成有至少一開孔240,710,720。例如，該第一線路結構20及該第二線路結構26之至少一者中係設有 該第一接地層71與第二接地層72，且該第一接地層71與第二接地層72的片體71a,72a之位置係上下對應，並使該第一接地層71與第二接地層72之開孔710,720於垂直方向不重疊。或者，該片體24a,71a,72a上之所有該開孔240,710,720的總面積B佔該片體24a,71a,72a外邊輪廓之垂直投影之面積A的至少10%以上(如10~40%，較佳為10~30%之間)。 In one embodiment, at least one opening 240, 710, 720 is formed on each of the sheets 24a, 71a, 72a. For example, at least one of the first circuit structure 20 and the second circuit structure 26 is provided with The first ground layer 71 and the second ground layer 72, and the positions of the pieces 71a, 72a of the first ground layer 71 and the second ground layer 72 are corresponding up and down, so that the first ground layer 71 and the second ground layer 71 are in a vertical position. The openings 710, 720 of the formation 72 do not overlap in the vertical direction. Or, the total area B of all the openings 240, 710, 720 on the sheet body 24a, 71a, 72a accounts for at least 10% or more of the area A of the vertical projection of the outer contour of the sheet body 24a, 71a, 72a (such as 10~40%, Preferably between 10~30%).

於一實施例中，該至少一溝槽241,711,721係設置於其對應各該片體24a,71a,72a之邊緣的中央位置。 In one embodiment, the at least one groove 241, 711, 721 is disposed at a central position corresponding to the edge of each of the sheets 24a, 71a, 72a.

於一實施例中，該複數片體24a之相鄰兩者之間設置有複數陣列排設之溝槽441。 In one embodiment, a plurality of grooves 441 arranged in an array are provided between two adjacent pieces of the plurality of sheets 24a.

於一實施例中，該複數片體24a,71a,72a之間所形成之複數該溝槽541,911,921係相互連通而於對應各該片體24a,71a,72a之邊角處位置形成類十字形槽孔P,Z1,Z2,X1,X2。進一步，相鄰之該類十字形槽孔P之間設置有陣列排設且位置對應該片體24a之邊緣的中央位置之至少一溝槽541,641。 In one embodiment, the plurality of grooves 541, 911, 921 formed between the plurality of pieces 24a, 71a, 72a are interconnected to form cross-like grooves at the corners corresponding to the pieces 24a, 71a, 72a. Holes P, Z1, Z2, X1, X2. Furthermore, at least one groove 541, 641 arranged in an array and corresponding to the center position of the edge of the sheet body 24a is provided between adjacent cross-shaped slots P.

於一實施例中，該複數片體24a,71a,72a為矩形，且該至少一該溝槽241,441,541,641,711,721,811,821,911,921的總長度D,(D1+D2),D3,D3’,D4,D4’,D5,D5’,(L1+L2),(L1+L2+L3)佔其對應之各該片體24a,71a,72a之平行該至少一溝槽241,441,541,641,711,721,811,821,911,921長度的邊緣的邊長L,L’,W,W’的至少60%以上。 In one embodiment, the plurality of sheets 24a, 71a, 72a are rectangular, and the total length of the at least one groove 241, 441, 541, 641, 711, 721, 811, 821, 911, 921 is D, (D1+D2), D3, D3', D4, D4', D5, D5 ', (L1+L2), (L1+L2+L3) account for the side lengths L, L', W, W of the edges parallel to the length of the at least one groove 241, 441, 541, 641, 711, 721, 811, 821, 911, 921 of the corresponding pieces 24a, 71a, 72a 'At least 60% or more.

於一實施例中，該複數片體24a,71a,72a為矩形，且該至少一溝槽241,441,541,641,711,721,811,821,911,921的總寬度R,(R1+R2),(R3+R4),(R3’+R4’),(R5+R6),(R5’+R6’),(R7+R8),(R7’+R8’),(R9+R10),(R9’+R10’),W1佔其平行對應之 各該片體24a,71a,72a之平行該至少一溝槽241,441,541,641,711,721,811,821,911,921寬度的邊緣的邊長L,L’,W,W’的至少1%以上。 In one embodiment, the plurality of sheets 24a, 71a, 72a are rectangular, and the at least one groove 241, 441, 541, 641, 711, 721, 811, 821, 911, 921 has a total width of R, (R1+R2), (R3+R4), (R3'+R4'), (R5+R6), (R5'+R6'), (R7+R8), (R7'+R8'), (R9+R10), (R9'+R10'), W1 occupies its parallel corresponding The side lengths L, L’, W, W’ of the edges parallel to the width of the at least one groove 241, 71a, 72a are at least 1% or more.

綜上所述，本發明之電子封裝件及其製法，係藉由扇出型線路重佈層製作該第一線路結構與第二線路結構，以取代習知具有核心層之封裝基板，故本發明之電子封裝件能有效降低整體之封裝高度。 In summary, the electronic package and its manufacturing method of the present invention fabricate the first circuit structure and the second circuit structure through a fan-out circuit redistribution layer to replace the conventional packaging substrate with a core layer. Therefore, the electronic package and the manufacturing method thereof are The invented electronic package can effectively reduce the overall package height.

再者，藉由該接地層的片體、開孔及溝槽之設計，以提升整體線路結構的撓性，故本發明之電子封裝件可具有較佳的翹曲控制表現，以提升該封裝模組設於該第二線路結構上的結合良率。 Furthermore, through the design of the ground layer body, openings and grooves, the flexibility of the overall circuit structure is improved, so the electronic package of the present invention can have better warpage control performance, thereby improving the packaging The combination yield of the module installed on the second circuit structure.

上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above embodiments are used to illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can make modifications to the above embodiments without departing from the spirit and scope of the invention. Therefore, the scope of rights protection of the present invention should be as listed in the patent application scope described below.

2:電子封裝件 2: Electronic packages

20:第一線路結構 20: First line structure

21:電子元件 21:Electronic components

22:導電凸塊 22: Conductive bumps

23:導電柱 23:Conductive pillar

24:接地層 24: Ground layer

241:溝槽 241:Trench

25:包覆層 25: Cladding layer

25a:第一表面 25a: First surface

25b:第二表面 25b: Second surface

26:第二線路結構 26: Second line structure

262:電性接觸墊 262: Electrical contact pads

27:導電元件 27:Conductive components

29:輔助功能元件 29: Auxiliary function components

Claims (24)

一種電子封裝件，係包括： An electronic package including: 包覆層，係具有相對之第一表面與第二表面； The coating layer has a first surface and a second surface opposite to each other; 第一線路結構，係設於該包覆層之第一表面上，並配置有扇出型線路重佈層； The first circuit structure is provided on the first surface of the covering layer and is configured with a fan-out circuit redistribution layer; 第二線路結構，係設於該包覆層之第二表面上，並配置有扇出型線路重佈層； The second circuit structure is provided on the second surface of the covering layer and is configured with a fan-out circuit redistribution layer; 複數導電柱，係嵌埋於該包覆層中且電性連接該第一線路結構與該第二線路結構； A plurality of conductive pillars are embedded in the cladding layer and electrically connect the first circuit structure and the second circuit structure; 電子元件，係設於該第一線路結構上，並嵌埋於該包覆層中且電性連接該第一線路結構或該第二線路結構；以及 Electronic components are provided on the first circuit structure, embedded in the cladding layer and electrically connected to the first circuit structure or the second circuit structure; and 至少一接地層，係設於該第一線路結構及該第二線路結構之至少一者中，其中，該至少一接地層係包含複數陣列排設之片體，每二相鄰之該片體之間設置有至少一溝槽。 At least one ground layer is provided in at least one of the first circuit structure and the second circuit structure, wherein the at least one ground layer includes a plurality of sheets arranged in an array, and each two adjacent sheets There is at least one groove between them. 如請求項1所述之電子封裝件，其中，該第一線路結構及該第二線路結構之至少一者中係設有複數層該接地層，且相鄰兩層該接地層的該片體之位置係上下對應，並使相鄰兩層該接地層之該溝槽於垂直方向不重疊。 The electronic package as claimed in claim 1, wherein at least one of the first circuit structure and the second circuit structure is provided with a plurality of layers of the ground layer, and the sheet body of two adjacent layers of the ground layer The positions are corresponding up and down, so that the trenches of the two adjacent ground layers do not overlap in the vertical direction. 如請求項2所述之電子封裝件，還包括分別對應該複數片體且設置於相鄰兩層該接地層之間的複數導電體，且相鄰兩層該接地層的該片體藉由該複數導電體之至少其中一者電性連接。 The electronic package as claimed in claim 2, further comprising a plurality of conductors respectively corresponding to the plurality of sheets and disposed between two adjacent layers of the ground layer, and the sheets of the two adjacent layers of the ground layer are connected by At least one of the plurality of conductors is electrically connected. 如請求項1所述之電子封裝件，其中，每一該片體具有至少一開孔。 The electronic package of claim 1, wherein each piece has at least one opening. 如請求項4所述之電子封裝件，其中，該第一線路結構及該第二線路結構之至少一者中係設有複數層該接地層，且相鄰兩層該接地層的該片體之位置係上下對應，並使相鄰兩層該接地層之該開孔於垂直方向不重疊。 The electronic package of claim 4, wherein at least one of the first circuit structure and the second circuit structure is provided with a plurality of layers of the ground layer, and the sheet body of two adjacent layers of the ground layer The positions are corresponding up and down, so that the openings of the ground layers of two adjacent layers do not overlap in the vertical direction. 如請求項4所述之電子封裝件，其中，該至少一開孔的總面積佔各該片體外邊輪廓之垂直投影之面積的至少10%以上。 The electronic package as claimed in claim 4, wherein the total area of the at least one opening accounts for at least 10% of the area of the vertical projection of the outer contour of each chip body. 如請求項1所述之電子封裝件，其中，該至少一溝槽係設置於其對應各該片體之邊緣的中央位置。 The electronic package as claimed in claim 1, wherein the at least one groove is disposed at a central position corresponding to the edge of each of the sheets. 如請求項1所述之電子封裝件，其中，該複數片體之相鄰兩者之間設置有複數陣列排設之溝槽。 The electronic package as claimed in claim 1, wherein a plurality of trenches arranged in an array are provided between two adjacent pieces of the plurality of sheets. 如請求項1所述之電子封裝件，其中，該複數片體之間所形成之複數該溝槽係相互連通而於對應各該片體之邊角處位置形成類十字形槽孔。 The electronic package as claimed in claim 1, wherein the plurality of grooves formed between the plurality of sheets are interconnected to form quasi-cross-shaped slots at corresponding corners of the sheets. 如請求項9所述之電子封裝件，其中，相鄰之該類十字形槽孔之間設置有陣列排設且位置對應該片體之邊緣的中央位置之複數溝槽。 The electronic package as claimed in claim 9, wherein a plurality of grooves arranged in an array and corresponding to the center position of the edge of the sheet are provided between adjacent cross-shaped slots. 如請求項1所述之電子封裝件，其中，該複數片體為矩形，且該至少一溝槽的總長度佔其對應之各該片體之平行該至少一溝槽長度的邊緣的邊長的至少60%以上。 The electronic package of claim 1, wherein the plurality of sheets are rectangular, and the total length of the at least one groove accounts for the side length of the edge of the corresponding sheet that is parallel to the length of the at least one groove. of at least 60%. 如請求項1所述之電子封裝件，其中，該複數片體為矩形，且該至少一溝槽的總寬度佔其對應之各該片體之平行該至少一溝槽寬度的邊緣的邊長的至少1%以上。 The electronic package of claim 1, wherein the plurality of sheets are rectangular, and the total width of the at least one groove accounts for the side length of the edge of the corresponding sheet that is parallel to the width of the at least one trench. of at least 1%. 一種電子封裝件之製法，係包括： A method for manufacturing electronic packages includes: 於第一線路結構上形成複數導電柱及設置電子元件； Forming a plurality of conductive pillars and disposing electronic components on the first circuit structure; 形成包覆層於該第一線路結構上以包覆該複數導電柱及該電子元件；以及 Forming a coating layer on the first circuit structure to cover the plurality of conductive pillars and the electronic component; and 形成一第二線路結構於該包覆層上，以令該複數導電柱電性連接該第一線路結構與該第二線路結構，且令該電子元件電性連接該第一線路結構或該第二線路結構，其中，於該第一線路結構與第二線路結構中配置有扇出型線路重佈層，且於該第一線路結構及該第二線路結構之至少一者中設置有至少一接地層，該至少一接地層係包含複數陣列排設之片體，且每二相鄰之該片體之間設置有至少一溝槽。 A second circuit structure is formed on the cladding layer, so that the plurality of conductive pillars are electrically connected to the first circuit structure and the second circuit structure, and the electronic component is electrically connected to the first circuit structure or the third circuit structure. Two line structures, wherein a fan-out line redistribution layer is configured in the first line structure and the second line structure, and at least one of the first line structure and the second line structure is provided with The at least one ground layer includes a plurality of sheets arranged in an array, and at least one trench is provided between every two adjacent sheets. 如請求項13所述之電子封裝件之製法，其中，該第一線路結構及該第二線路結構之至少一者中係設有複數層該接地層，且相鄰兩層該接地層的該片體之位置係上下對應，並使相鄰兩層該接地層之該溝槽於垂直方向不重疊。 The method for manufacturing an electronic package as claimed in claim 13, wherein at least one of the first circuit structure and the second circuit structure is provided with a plurality of layers of the ground layer, and the two adjacent layers of the ground layer are The positions of the pieces are corresponding up and down, so that the grooves of the ground layers of two adjacent layers do not overlap in the vertical direction. 如請求項14所述之電子封裝件之製法，還包括分別對應該複數片體且設置於相鄰兩層該接地層之間的複數導電體，且相鄰兩層該接地層的該片體藉由該複數導電體之至少其中一者電性連接。 The method for manufacturing an electronic package as claimed in claim 14, further comprising a plurality of conductors respectively corresponding to the plurality of sheets and disposed between two adjacent layers of the ground layer, and the sheets of the two adjacent layers of the ground layer They are electrically connected through at least one of the plurality of conductors. 如請求項13所述之電子封裝件之製法，其中，每一該片體具有至少一開孔。 The method of manufacturing an electronic package as claimed in claim 13, wherein each piece has at least one opening. 如請求項16所述之電子封裝件之製法，其中，該第一線路結構及該第二線路結構之至少一者中係設有複數層該接地層，且相鄰兩層該接地層的該片體之位置係上下對應，並使相鄰兩層該接地層之該開孔於垂直方向不重疊。 The method for manufacturing an electronic package as claimed in claim 16, wherein at least one of the first circuit structure and the second circuit structure is provided with a plurality of layers of the ground layer, and the two adjacent layers of the ground layer are The positions of the pieces are corresponding up and down, so that the openings of the ground layers of two adjacent layers do not overlap in the vertical direction. 如請求項16所述之電子封裝件之製法，其中，各該片體上之所有該開孔的總面積佔該各片體外邊輪廓之垂直投影之面積的至少10%以上。 The method for manufacturing an electronic package as claimed in claim 16, wherein the total area of all the openings on each sheet body accounts for at least 10% of the area of the vertical projection of the outer contour of each sheet body. 如請求項13所述之電子封裝件之製法，其中，該至少一溝槽係設置於其對應各該片體之邊緣的中央位置。 The method of manufacturing an electronic package as claimed in claim 13, wherein the at least one groove is disposed at a central position corresponding to the edge of each of the sheets. 如請求項13所述之電子封裝件之製法，其中，該複數片體之相鄰兩者之間設置有複數陣列排設之溝槽。 The method for manufacturing an electronic package as claimed in claim 13, wherein a plurality of trenches arranged in an array are provided between two adjacent pieces of the plurality of sheets. 如請求項13所述之電子封裝件之製法，其中，該複數片體之間所形成之複數該溝槽係相互連通而於對應各該片體之邊角處位置形成類十字形槽孔。 The manufacturing method of an electronic package as claimed in claim 13, wherein the plurality of grooves formed between the plurality of pieces are interconnected to form quasi-cross-shaped slots at corresponding corners of the pieces. 如請求項21所述之電子封裝件之製法，其中，相鄰之該類十字形槽孔之間設置有陣列排設且位置對應該片體之邊緣的中央位置之複數溝槽。 The method for manufacturing an electronic package as claimed in claim 21, wherein a plurality of grooves arranged in an array and corresponding to the center position of the edge of the sheet are provided between adjacent cross-shaped slots. 如請求項13所述之電子封裝件之製法，其中，該複數片體為矩形，且該至少一溝槽的總長度佔其對應之各該片體之平行該至少一溝槽長度的邊緣的邊長的至少60%以上。 The method for manufacturing an electronic package as claimed in claim 13, wherein the plurality of sheets are rectangular, and the total length of the at least one groove accounts for 30% of the corresponding edge of the sheet that is parallel to the length of the at least one groove. At least 60% of the side length. 如請求項13所述之電子封裝件之製法，其中，該複數片體為矩形，且該至少一溝槽的總寬度佔其對應之各該片體之平行該至少一溝槽寬度的邊緣的邊長的至少1%以上。 The method for manufacturing an electronic package as claimed in claim 13, wherein the plurality of sheets are rectangular, and the total width of the at least one groove accounts for 30% of the corresponding edge of the sheet that is parallel to the width of the at least one trench. At least 1% of the side length.
TW111111159A 2022-03-24 2022-03-24 Electronic packaging and manufacturing method thereof TWI796180B (en)

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Application Number Priority Date Filing Date Title
TW111111159A TWI796180B (en) 2022-03-24 2022-03-24 Electronic packaging and manufacturing method thereof
CN202210355197.5A CN116845050A (en) 2022-03-24 2022-04-06 Electronic package and method for manufacturing the same
US17/748,920 US20230307339A1 (en) 2022-03-24 2022-05-19 Electronic package and manufacturing method thereof

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