TW202339121A - Memory device having word line with dual conductive materials - Google Patents

Memory device having word line with dual conductive materials Download PDF

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TW202339121A
TW202339121A TW111119176A TW111119176A TW202339121A TW 202339121 A TW202339121 A TW 202339121A TW 111119176 A TW111119176 A TW 111119176A TW 111119176 A TW111119176 A TW 111119176A TW 202339121 A TW202339121 A TW 202339121A
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conductive component
isolation layer
recess
memory device
semiconductor substrate
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TW111119176A
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TWI825735B (en
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陳昱頻
蔡鎮宇
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南亞科技股份有限公司
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Abstract

The present application provides a memory device having a word line (WL) with dual conductive materials. The memory device includes a semiconductor substrate with an active area defined adjacent to a surface of the semiconductor substrate, wherein the semiconductor substrate includes a recess extending from the surface into the semiconductor substrate; and a word line disposed within the recess, wherein the word line includes a first insulating layer disposed within and conformal to the recess, a first conductive member surrounded by the first insulating layer and disposed within the recess, a second insulating layer disposed conformal to the first insulating layer and the first conductive member, and a second conductive member disposed adjacent to the first conductive member and surrounded by the second insulating layer.

Description

具有雙導電材料之字元線的記憶體元件Memory device with character lines of dual conductive materials

本申請案主張美國第17/695,972及17/696,058號專利申請案之優先權(即優先權日為「2022年3月16日」),其內容以全文引用之方式併入本文中。This application claims priority to U.S. Patent Application Nos. 17/695,972 and 17/696,058 (that is, the priority date is "March 16, 2022"), the contents of which are incorporated herein by reference in their entirety.

本揭露關於一種記憶體元件。特別是有關於一種具有雙導電材料之一字元線的記憶體元件。The present disclosure relates to a memory device. In particular, it relates to a memory device having one word line of dual conductive material.

動態隨機存取記憶體(DRAM)是一種半導體配置,用於將資料的多個位元儲存在一積體電路(IC)內的單獨電容器中。DRAMs通常形成為溝槽電容器DRAM單元。一種製造埋入式閘極的先進方法包含在包括一淺溝隔離(STI)結構之一主動區(AA)中的一溝槽中建立一電晶體的一閘極電極以及一字元線。Dynamic random access memory (DRAM) is a semiconductor device used to store multiple bits of data in individual capacitors within an integrated circuit (IC). DRAMs are typically formed as trench capacitor DRAM cells. An advanced method of fabricating a buried gate involves building a gate electrode of a transistor and a word line in a trench in an active area (AA) of a shallow trench isolation (STI) structure.

在過去的幾十年裡,隨著半導體製造技術的不斷改進,電子元件的尺寸也相應地減小。隨著一單元電晶體的尺寸減小到數奈米的長度,可能會發生漏電流。漏電流可能導致該等單元電晶體的效能顯著地下降。因此,希望開發解決相關製造挑戰的改進。As semiconductor manufacturing technology has improved over the past few decades, the size of electronic components has decreased accordingly. As the size of a cell transistor decreases to several nanometers in length, leakage current may occur. Leakage current may significantly reduce the performance of these unit transistors. Therefore, it is desirable to develop improvements that address related manufacturing challenges.

本揭露之一實施例提供一種記憶體元件。該記憶體元件包括一半導體基底,具有鄰近該半導體基底之一表面處所界定的一主動區,其中該半導體基底具有一凹陷,從該表面延伸進入該半導體基底中;以及一字元線,設置在該凹陷內;其中該字元線具有一第一隔離層、一第一導電組件、一第二隔離層以及一第二導電組件,該第一隔離層設置在該凹陷內且共形於該凹陷,該第一導電組件被該第一隔離層所圍繞並設置在該凹陷內,該第二隔離層共形於該第一隔離層與該第一導電組件設置,該第二導電組件鄰近該第一導電組件設置且被該第二隔離層所圍繞。An embodiment of the present disclosure provides a memory device. The memory device includes a semiconductor substrate having an active region defined adjacent a surface of the semiconductor substrate, wherein the semiconductor substrate has a recess extending from the surface into the semiconductor substrate; and a word line disposed on Within the recess; wherein the word line has a first isolation layer, a first conductive component, a second isolation layer and a second conductive component, the first isolation layer is disposed in the recess and conforms to the recess , the first conductive component is surrounded by the first isolation layer and is disposed in the recess, the second isolation layer is disposed conformally to the first isolation layer and the first conductive component, and the second conductive component is adjacent to the first conductive component. A conductive component is disposed and surrounded by the second isolation layer.

在一些實施例中,該第一導電組件的一第一功函數大致不同於該第二導電組件的一第二功函數。In some embodiments, a first work function of the first conductive component is substantially different from a second work function of the second conductive component.

在一些實施例中,該第一導電組件的該第一功函數大致大於該第二導電組件的該第二功函數。In some embodiments, the first work function of the first conductive component is substantially greater than the second work function of the second conductive component.

在一些實施例中,該第一導電組件與該第二導電組件包括一相同材料。In some embodiments, the first conductive component and the second conductive component include the same material.

在一些實施例中,該第一導電組件與該第二導電組件包括鎢(W)或氮化鈦(TiN)。In some embodiments, the first conductive component and the second conductive component include tungsten (W) or titanium nitride (TiN).

在一些實施例中,該第一隔離層與該第二隔離層包括氧化物。In some embodiments, the first isolation layer and the second isolation layer include oxide.

在一些實施例中,該第一導電組件被該第一隔離層與該第二隔離層所包圍。In some embodiments, the first conductive component is surrounded by the first isolation layer and the second isolation layer.

在一些實施例中,該第一導電組件與該第二導電組件藉由該第二隔離層而分隔開。In some embodiments, the first conductive component and the second conductive component are separated by the second isolation layer.

在一些實施例中,該第一導電組件的一上表面大致低於該第二導電組件的一上表面。In some embodiments, an upper surface of the first conductive component is substantially lower than an upper surface of the second conductive component.

在一些實施例中,該第一導電組件的該上表面與該第二導電組件的該上表面被該半導體基底的該主動區所圍繞。In some embodiments, the upper surface of the first conductive component and the upper surface of the second conductive component are surrounded by the active region of the semiconductor substrate.

在一些實施例中,該第一導電組件之該上表面的一寬度大致大於或等於該第二導電組件之該上表面的一寬度。In some embodiments, a width of the upper surface of the first conductive component is substantially greater than or equal to a width of the upper surface of the second conductive component.

在一些實施例中,該記憶體元件還包括一介電層,設置在該第一導電組件、該第二導電組件以及該第二隔離層上。In some embodiments, the memory device further includes a dielectric layer disposed on the first conductive component, the second conductive component and the second isolation layer.

在一些實施例中,該介電層接觸該第二導電組件的該上表面。In some embodiments, the dielectric layer contacts the upper surface of the second conductive component.

在一些實施例中,該記憶體元件還包括一導電栓塞,延伸經過該介電層並連接到該半導體基底的該主動區。In some embodiments, the memory device further includes a conductive plug extending through the dielectric layer and connected to the active region of the semiconductor substrate.

在一些實施例中,該第二隔離層的至少一部分設置在該介電層與該第一導電組件的一上表面之間。In some embodiments, at least a portion of the second isolation layer is disposed between the dielectric layer and an upper surface of the first conductive component.

在一些實施例中,該介電層包括氮化物。In some embodiments, the dielectric layer includes nitride.

在一些實施例中,該第一導電組件的一高度大致小於或等於該第二導電組件的一高度。In some embodiments, a height of the first conductive component is substantially less than or equal to a height of the second conductive component.

本揭露之另一實施例提供一種記憶體元件。該記憶體元件包括一半導體基底,具有鄰近該半導體基底之一表面處的一主動區,其中該半導體基底具有一第一凹陷,從該表面延伸進入該半導體基底中;以及一字元線,設置在該第一凹陷內;其中該字元線具有一第一隔離層、一第一導電組件、一第二隔離層以及一第二導電組件,該第一隔離層共形於該第一凹陷設置並具有一第二凹陷在該第一凹陷內,該第一導電組件被該第一隔離層所圍繞並設置在該第二凹陷內,該第二隔離層共形於該第二凹陷與該第二導電組件設置並具有一第三凹陷在該第二凹陷內,該第二導電組件設置在該第三凹陷內。Another embodiment of the present disclosure provides a memory device. The memory device includes a semiconductor substrate having an active region adjacent a surface of the semiconductor substrate, wherein the semiconductor substrate has a first recess extending from the surface into the semiconductor substrate; and a word line disposed In the first recess; wherein the word line has a first isolation layer, a first conductive component, a second isolation layer and a second conductive component, the first isolation layer is conformally disposed in the first recess and has a second recess in the first recess, the first conductive component is surrounded by the first isolation layer and is disposed in the second recess, and the second isolation layer is conformal to the second recess and the third recess. Two conductive components are disposed and have a third recess in the second recess, and the second conductive component is disposed in the third recess.

在一些實施例中,該三凹陷具有一第一寬度以及一第二寬度,該第一寬度位在鄰近該第一導電組件的一位置處,該第二寬度位在該第一導電組件的一位置上以及在具有該第一寬度的該位置上。In some embodiments, the three recesses have a first width and a second width, the first width is located at a position adjacent to the first conductive component, and the second width is located at a position of the first conductive component. position and at the position with the first width.

在一些實施例中,該第二寬度大致不同於該第一寬度。In some embodiments, the second width is substantially different than the first width.

在一些實施例中,該第二寬度大致大於該第一寬度。In some embodiments, the second width is substantially greater than the first width.

在一些實施例中,該第一導電組件的一第一功函數大致大於該第二導電組件的一第二功函數。In some embodiments, a first work function of the first conductive component is substantially greater than a second work function of the second conductive component.

在一些實施例中,該第一導電組件的該第一功函數大致大於4eV,且該第二導電組件的該第二功函數大致小於4eV。In some embodiments, the first work function of the first conductive component is approximately greater than 4 eV, and the second work function of the second conductive component is approximately less than 4 eV.

在一些實施例中,該第一功函數與該第二功函數之間的一差值大致大於0.5eV。In some embodiments, a difference between the first work function and the second work function is approximately greater than 0.5 eV.

本揭露之另一實施例提供一種記憶體元件的製備方法。該製備方法包括提供一半導體基底,該半導體基底具有鄰近該半導體基底之一表面處所界定的一主動區;形成一凹陷以從該表面延伸進入該半導體基底中;設置一第一隔離層以共形於該凹陷;設置一第一導電材料在該凹陷內並被該地一隔離層所圍繞;移除該第一導電材料的一部分以形成一第一導電組件;設置一第二隔離層在該凹陷內且共形於該第一隔離層與該第一導電組件;以及設置一第二導電材料在該凹陷內並被該第二隔離層所圍繞,以形成鄰近該第一導電組件的一第二導電組件。Another embodiment of the present disclosure provides a method of manufacturing a memory device. The preparation method includes providing a semiconductor substrate having an active region defined adjacent to a surface of the semiconductor substrate; forming a recess to extend from the surface into the semiconductor substrate; and providing a first isolation layer to conformally in the recess; disposing a first conductive material in the recess and surrounded by an isolation layer; removing a portion of the first conductive material to form a first conductive component; disposing a second isolation layer in the recess within and conformable to the first isolation layer and the first conductive component; and disposing a second conductive material in the recess and surrounded by the second isolation layer to form a second conductive component adjacent to the first conductive component. Conductive components.

在一些實施例中,該第一導電組件的一第一功函數大致不同於該第二導電組件的一第二功函數。In some embodiments, a first work function of the first conductive component is substantially different from a second work function of the second conductive component.

在一些實施例中,該第一導電組件的該第一功函數大致大於該第二導電組件的該第二功函數。In some embodiments, the first work function of the first conductive component is substantially greater than the second work function of the second conductive component.

在一些實施例中,該第一導電材料相同於該第二導電材料。In some embodiments, the first conductive material is the same as the second conductive material.

在一些實施例中,該製備方法還包括設置一圖案化光阻在該第一隔離層與該第一導電材料上,其中移除該第一導電組件經由該圖案化光阻而暴露的該部分。In some embodiments, the preparation method further includes disposing a patterned photoresist on the first isolation layer and the first conductive material, wherein removing the portion of the first conductive component exposed through the patterned photoresist .

在一些實施例中,該製備方法還包括在該第一導電組件形成之後,移除該圖案化光阻。In some embodiments, the preparation method further includes removing the patterned photoresist after the first conductive component is formed.

在一些實施例中,移除該第二導電組件設置在該第一導電組件上的一部分,以形成該第二導電組件。In some embodiments, a portion of the second conductive component disposed on the first conductive component is removed to form the second conductive component.

在一些實施例中,該製備方法還包括:設置一介電層在該第一導電組件、該第二導電組件以及該第二隔離層上;以及形成一導電栓塞以延伸經過該介電層並連接到該半導體基底的該主動區。In some embodiments, the preparation method further includes: disposing a dielectric layer on the first conductive component, the second conductive component and the second isolation layer; and forming a conductive plug to extend through the dielectric layer and connected to the active region of the semiconductor substrate.

在一些實施例中,在設置該第二導電材料之前,執行該第二隔離層的設置。In some embodiments, the second isolation layer is provided before the second conductive material is provided.

在一些實施例中,在設置該第二導電材料之前,執行該第一導電材料的設置。In some embodiments, the provision of the first conductive material is performed before the second conductive material is provided.

在一些實施例中,該第一導電材料的設置以及該第二導電材料的設置是各別執行。In some embodiments, the placement of the first conductive material and the placement of the second conductive material are performed separately.

總之,因為一字元線包括具有不同功函數的雙導電材料,所以這種差異可抑制或避免一閘極誘導汲極洩漏(GIDL)。在一些實施例中,因為該字元線包括具有一高功函數的一第一導電材料以及具有一低功函數的一第二導電材料,所以此配置可減少GIDL問題。因此,改善該記憶體元件的效能以及製造該記憶體元件的一製程。In summary, because a word line includes dual conductive materials with different work functions, this difference can suppress or avoid a gate-induced drain leakage (GIDL). In some embodiments, this configuration may reduce GIDL problems because the word line includes a first conductive material with a high work function and a second conductive material with a low work function. Therefore, the performance of the memory device and a process for manufacturing the memory device are improved.

上文已相當廣泛地概述本揭露之技術特徵及優點,俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解,可相當容易地利用下文揭示之概念與特定實施例可作為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解,這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

以下描述了組件和配置的具體範例,以簡化本揭露之實施例。當然,這些實施例僅用以例示,並非意圖限制本揭露之範圍。舉例而言,在敘述中第一部件形成於第二部件之上,可能包含形成第一和第二部件直接接觸的實施例,也可能包含額外的部件形成於第一和第二部件之間,使得第一和第二部件不會直接接觸的實施例。另外,本揭露之實施例可能在許多範例中重複參照標號及/或字母。這些重複的目的是為了簡化和清楚,除非內文中特別說明,其本身並非代表各種實施例及/或所討論的配置之間有特定的關係。Specific examples of components and configurations are described below to simplify embodiments of the present disclosure. Of course, these embodiments are only for illustration and are not intended to limit the scope of the present disclosure. For example, in the description, the first component is formed on the second component, which may include an embodiment in which the first and second components are in direct contact, or may include an additional component formed between the first and second components. An embodiment such that the first and second components are not in direct contact. In addition, embodiments of the present disclosure may repeat reference numbers and/or letters in many examples. These repetitions are for simplicity and clarity and do not in themselves represent a specific relationship between the various embodiments and/or configurations discussed unless otherwise specified herein.

此外,本揭露可在各種例子中重複元件編號及/或字母。這種重複是為了簡單以及清楚的目的,且其本身並未規定所討論的各種實施例及/或配置之間的關係。Additionally, this disclosure may repeat element numbers and/or letters in various examples. This repetition is for simplicity and clarity and does not by itself define the relationship between the various embodiments and/or configurations discussed.

再者,為易於說明,本文中可能使用例如「之下(beneath)」、「下面(below)」、「下部的(lower)」、「上方(above)」、「上部的(upper)」等空間相對關係用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對關係 用語旨在除圖中所繪示的取向外亦囊括元件在使用或操作中的不同取向。所述裝置可具有其他取向(旋轉90度或處於其他取向)且本文中所用的空間相對關係描述語可同樣相應地進行解釋。Furthermore, for ease of explanation, terms such as "beneath", "below", "lower", "above", "upper", etc. may be used in this article. Spatially relative terms are used to describe the relationship of one element or feature to another (other) element or feature shown in the figures. These spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

圖1是剖視示意圖,例示本揭露一實施例之記憶體元件。在一些實施例中,記憶體元件100包括多個單元胞,呈行列配置。FIG. 1 is a schematic cross-sectional view illustrating a memory device according to an embodiment of the present disclosure. In some embodiments, the memory device 100 includes a plurality of unit cells arranged in rows and columns.

在一些實施例中,記憶體元件100包括一半導體基底101。在一些實施例中,半導體基底101包括半導體材料,例如矽、鍺、砷化鎵或其組合。在一些實施例中,半導體基底101包括塊狀(bulk)半導體材料。在一些實施例中,半導體基底101是一半導體晶圓(例如一矽晶圓)或一絕緣體上覆半導體(SOI)晶圓(例如一絕緣體上覆矽晶圓)。在一些實施例中,半導體基底101是一矽基底。在一些實施例中,半導體基底101包括輕度摻雜單晶矽。在一些實施例中,半導體基底101是一p型基底。In some embodiments, memory device 100 includes a semiconductor substrate 101 . In some embodiments, semiconductor substrate 101 includes a semiconductor material such as silicon, germanium, gallium arsenide, or combinations thereof. In some embodiments, semiconductor substrate 101 includes bulk semiconductor material. In some embodiments, the semiconductor substrate 101 is a semiconductor wafer (eg, a silicon wafer) or a semiconductor-on-insulator (SOI) wafer (eg, a silicon-on-insulator wafer). In some embodiments, semiconductor substrate 101 is a silicon substrate. In some embodiments, semiconductor substrate 101 includes lightly doped single crystal silicon. In some embodiments, semiconductor substrate 101 is a p-type substrate.

在一些實施例中,半導體基底101包括多個主動區(AA)101a。主動區101a是在半導體基底101中的一摻雜區。在一些實施例中,主動區101a在半導體基底101之一上表面的上方或正上方水平延伸。在一些實施例中,主動區101a鄰近半導體基底101的上表面設置。在一些實施例中,每一個主動區101a包括一相同類型的摻雜物。在一些實施例中,每一個主動區101a包括一類型的摻雜物,其不同於包括在其他主動區101a中之類型的摻雜物。在一些實施例中,每一個主動區101a具有一相同導電類型。在一些實施例中,主動區101a包括n型摻雜物。In some embodiments, the semiconductor substrate 101 includes a plurality of active areas (AA) 101a. The active region 101a is a doped region in the semiconductor substrate 101. In some embodiments, active region 101 a extends horizontally above or directly above one of the upper surfaces of semiconductor substrate 101 . In some embodiments, the active region 101 a is disposed adjacent the upper surface of the semiconductor substrate 101 . In some embodiments, each active region 101a includes a same type of dopant. In some embodiments, each active region 101a includes a type of dopant that is different from the type of dopant included in other active regions 101a. In some embodiments, each active region 101a has a same conductivity type. In some embodiments, active region 101a includes n-type dopants.

在一些實施例中,半導體基底101包括一第一表面101b以及一第二表面101c,而第二表面101c相對第一表面101b設置。在一些實施例中,第一表面101b是半導體基底101的一前側,其中多個電子元件或部件依序地形成在第一表面101b上且經配置以電性連接到一外部電路。在一些實施例中,主動區101a鄰近第一表面101b設置或設置在第一表面101b下方。在一些實施例中,第二表面101c是半導體基底101的一後側,其沒有電子元件或部件。In some embodiments, the semiconductor substrate 101 includes a first surface 101b and a second surface 101c, and the second surface 101c is disposed opposite to the first surface 101b. In some embodiments, the first surface 101b is a front side of the semiconductor substrate 101, where a plurality of electronic components or components are sequentially formed on the first surface 101b and configured to be electrically connected to an external circuit. In some embodiments, active region 101a is disposed adjacent to or below first surface 101b. In some embodiments, second surface 101c is a backside of semiconductor substrate 101 that is free of electronic components or components.

在一些實施例中,半導體基底101包括一凹陷102,延伸進入半導體基底101。在一些實施例中,凹陷102從第一表面101b朝向半導體基底101的第二表面101c延伸。在一些實施例中,凹陷102從第一表面101b朝向半導體基底101的第二表面101c而逐漸變細。在一些實施例中,凹陷102的一深度大致大於主動區101a的一深度。In some embodiments, the semiconductor substrate 101 includes a recess 102 extending into the semiconductor substrate 101 . In some embodiments, recess 102 extends from first surface 101 b toward second surface 101 c of semiconductor substrate 101 . In some embodiments, recess 102 tapers from first surface 101 b toward second surface 101 c of semiconductor substrate 101 . In some embodiments, recess 102 has a depth that is substantially greater than a depth of active region 101a.

在一些實施例中,記憶體元件100包括一字元線103,設置在凹陷102內。在一些實施例中,字元線103包括一第一隔離層103a、一第一導電組件103b、一第二隔離層103c以及一第二導電組件103d。In some embodiments, memory device 100 includes a word line 103 disposed within recess 102 . In some embodiments, the word line 103 includes a first isolation layer 103a, a first conductive component 103b, a second isolation layer 103c and a second conductive component 103d.

在一些實施例中,第一隔離層103a設置在凹陷102中且共形於凹陷102。在一些實施例中,第一隔離層103a的至少一部分被主動區101a所圍繞。在一些實施例中,第一隔離層103a覆蓋凹陷102的一整個側壁。在一些實施例中,第一隔離層103a的一部分設置在半導體基底101的第一表面101b上。在一些實施例中,第一隔離層103a具有一第二凹陷104,設置在凹陷102內。In some embodiments, the first isolation layer 103a is disposed in the recess 102 and conforms to the recess 102 . In some embodiments, at least a portion of first isolation layer 103a is surrounded by active region 101a. In some embodiments, the first isolation layer 103a covers an entire sidewall of the recess 102. In some embodiments, a portion of the first isolation layer 103a is disposed on the first surface 101b of the semiconductor substrate 101. In some embodiments, the first isolation layer 103a has a second recess 104 disposed in the recess 102.

在一些實施例中,第一隔離層103a包括介電材料,例如氧化物。在一些實施例中,第一隔離層103a包含一隔離材料,例如氧化矽、氮化矽、氮氧化矽、類似物或其組合。在一些實施例中,第一隔離層103a包括具有一低介電常數(低k值)的介電材料。In some embodiments, first isolation layer 103a includes a dielectric material, such as an oxide. In some embodiments, the first isolation layer 103a includes an isolation material, such as silicon oxide, silicon nitride, silicon oxynitride, the like, or combinations thereof. In some embodiments, the first isolation layer 103a includes a dielectric material with a low dielectric constant (low k value).

在一些實施例中,第一導電組件103b被第一隔離層103a所圍繞且設置在凹陷102內。在一些實施例中,第一導電組件103b在第一隔離層103a內從第一表面101b朝向半導體基底101的第二表面101c延伸。在一些實施例中,第一導電組件103b沿著第一隔離層103a的一側壁延伸。在一些實施例中,第一導電組件103b設置在第二凹陷104內。In some embodiments, the first conductive component 103b is surrounded by the first isolation layer 103a and is disposed within the recess 102. In some embodiments, the first conductive component 103b extends from the first surface 101b toward the second surface 101c of the semiconductor substrate 101 within the first isolation layer 103a. In some embodiments, the first conductive component 103b extends along a side wall of the first isolation layer 103a. In some embodiments, the first conductive component 103b is disposed within the second recess 104.

在一些實施例中,第一導電組件103b包括具有一第一功函數的一第一導電材料。在一些實施例中,第一導電組件103b的第一功函數大致大於4eV。在一些實施例中,第一導電組件103b的第一功函數是在大約1eV到大約8eV之間的範圍。在一些實施例中,第一導電組件103b包括導電材料,例如氮化鈦(TiN)、鎢(W)或類似物。In some embodiments, the first conductive component 103b includes a first conductive material having a first work function. In some embodiments, the first work function of the first conductive component 103b is approximately greater than 4 eV. In some embodiments, the first work function of the first conductive component 103b ranges between approximately 1 eV and approximately 8 eV. In some embodiments, the first conductive component 103b includes a conductive material such as titanium nitride (TiN), tungsten (W), or the like.

在一些實施例中,第二隔離層103c共形於第一隔離層103a與第二導電組件103b設置。在一些實施例中,第二隔離層103c共形於第二凹陷104的一部分設置。在一些實施例中,第二隔離層103c的至少部分被主動區101a所圍繞。在一些實施例中,第二隔離層103c與第一隔離層103a包圍第一導電組件103b。在一些實施例中,第二隔離層103c覆蓋第一導電組件103b。In some embodiments, the second isolation layer 103c is disposed conformally to the first isolation layer 103a and the second conductive component 103b. In some embodiments, the second isolation layer 103c is disposed conformally to a portion of the second recess 104. In some embodiments, at least part of the second isolation layer 103c is surrounded by the active region 101a. In some embodiments, the second isolation layer 103c and the first isolation layer 103a surround the first conductive component 103b. In some embodiments, the second isolation layer 103c covers the first conductive component 103b.

在一些實施例中,第二隔離層103c沿著第一隔離層103a之一側壁的一部分、第一隔離層103a之一下表面的一部分、第一導電組件103b之一側壁的一部分以及第一導電組件103b的一上表面103e延伸。在一些實施例中,第二隔離層103c的一部分設置在半導體基底101的第一表面101b上。In some embodiments, the second isolation layer 103c is formed along a portion of a sidewall of the first isolation layer 103a, a portion of a lower surface of the first isolation layer 103a, a portion of a sidewall of the first conductive component 103b, and the first conductive component An upper surface 103e of 103b extends. In some embodiments, a portion of the second isolation layer 103c is disposed on the first surface 101b of the semiconductor substrate 101.

在一些實施例中,第二隔離層103c具有一第三凹陷105,設置在第二凹陷104內。在一些實施例中,第三凹陷105具有一第一寬度W3以及一第二寬度W4,第一寬度W3位在鄰近第一導電組件103b的一位置處,第二寬度W4位在第一導電組件103b上的一位置處以及在具有第一寬度W3的該位置上。在一些實施例中,第二寬度W4大致不同於第一寬度W3。在一些實施例中,第二寬度W4大致大於第一寬度W3。In some embodiments, the second isolation layer 103c has a third recess 105 disposed in the second recess 104. In some embodiments, the third recess 105 has a first width W3 and a second width W4. The first width W3 is located at a position adjacent to the first conductive component 103b, and the second width W4 is located at a position adjacent to the first conductive component 103b. 103b and at the position having the first width W3. In some embodiments, the second width W4 is substantially different than the first width W3. In some embodiments, the second width W4 is substantially greater than the first width W3.

在一些實施例中,第二隔離層103c包括不同於第一隔離層103a的一材料。在一些實施例中,第二隔離層103c包括與第一隔離層103a相同的一材料。在一些實施例中,第二隔離層103c包括介電材料,例如氧化物。在一些實施例中,第二隔離層103c包含一隔離材料,例如氧化矽、氮化矽、氮氧化矽、類似物或其組合。在一些實施例中,第二隔離層103c包括具有一低介電常數(低k值)的介電材料。In some embodiments, the second isolation layer 103c includes a different material than the first isolation layer 103a. In some embodiments, the second isolation layer 103c includes the same material as the first isolation layer 103a. In some embodiments, second isolation layer 103c includes a dielectric material, such as an oxide. In some embodiments, the second isolation layer 103c includes an isolation material, such as silicon oxide, silicon nitride, silicon oxynitride, the like, or combinations thereof. In some embodiments, the second isolation layer 103c includes a dielectric material with a low dielectric constant (low k value).

在一些實施例中,第二導電組件103d鄰近第一導電組件103b設置且被第二隔離層103c所圍繞。在一些實施例中,第二導電組件103d在第二隔離層103c內從第一表面101b朝向半導體基底101的第二表面101c延伸。In some embodiments, the second conductive component 103d is disposed adjacent to the first conductive component 103b and is surrounded by the second isolation layer 103c. In some embodiments, the second conductive component 103d extends from the first surface 101b toward the second surface 101c of the semiconductor substrate 101 within the second isolation layer 103c.

在一些實施例中,第二導電組件103d大致平行於第一導電組件103b延伸。第二導電組件103d與第一導電組件103b藉由第二隔離層103c而分隔開。在一些實施例中,第二導電組件103d設置在第三凹陷105內。在一些實施例中,第一導電組件103b與第二導電組件103d當成一閘極電極。In some embodiments, the second conductive component 103d extends generally parallel to the first conductive component 103b. The second conductive component 103d and the first conductive component 103b are separated by a second isolation layer 103c. In some embodiments, the second conductive component 103d is disposed within the third recess 105. In some embodiments, the first conductive component 103b and the second conductive component 103d serve as a gate electrode.

在一些實施例中,第一導電組件103b的上表面103e大致低於第二導電組件103d的一上表面103f。在一些實施例中,第一導電組件103b的上表面103e與第二導電組件103d的上表面103f被半導體基底101的主動區101a所圍繞。在一些實施例中,第二導電組件103d的上表面103f大致與第二隔離層103c的一水平表面呈共面。In some embodiments, the upper surface 103e of the first conductive component 103b is substantially lower than an upper surface 103f of the second conductive component 103d. In some embodiments, the upper surface 103e of the first conductive component 103b and the upper surface 103f of the second conductive component 103d are surrounded by the active region 101a of the semiconductor substrate 101. In some embodiments, the upper surface 103f of the second conductive component 103d is substantially coplanar with a horizontal surface of the second isolation layer 103c.

在一些實施例中,第一導電組件103b之上表面103e的一寬度W1大致大於或等於第二導電組件103d之上表面103f的一寬度W2。在一些實施例中,第一導電組件103b的一高度H1大致小於或等於第二導電組件103d的一高度H2。In some embodiments, a width W1 of the upper surface 103e of the first conductive component 103b is substantially greater than or equal to a width W2 of the upper surface 103f of the second conductive component 103d. In some embodiments, a height H1 of the first conductive component 103b is substantially less than or equal to a height H2 of the second conductive component 103d.

在一些實施例中,第二導電組件103d包括具有一第二功函數的一第二導電材料。在一些實施例中,第一導電材料103b的第一功函數大致不同於第二導電組件103d的第二功函數。在一些實施例中,第一導電材料103b的第一功函數大致大於第二導電組件103d的第二功函數。In some embodiments, the second conductive component 103d includes a second conductive material having a second work function. In some embodiments, the first work function of the first conductive material 103b is substantially different than the second work function of the second conductive component 103d. In some embodiments, the first work function of the first conductive material 103b is substantially greater than the second work function of the second conductive component 103d.

在一些實施例中,第二導電組件103d的第二功函數大致小於4eV。在一些實施例中,第二導電組件103d的第二功函數在大約0.1eV到大約1eV的範圍之間。在一些實施例中,第一導電材料103b的第一功函數大致與第二導電組件103d的第二功函數之間的一差值大致大於0.5eV。在一些實施例中,第二導電組件103d包括導電材料,例如氮化鈦(TiN)、鎢(W)或類似物。在一些實施例中,第二導電組件103d包括與第一導電組件103b相同的一材料。In some embodiments, the second work function of the second conductive component 103d is approximately less than 4 eV. In some embodiments, the second work function of the second conductive component 103d is in the range of about 0.1 eV to about 1 eV. In some embodiments, a difference between the first work function of the first conductive material 103b and the second work function of the second conductive component 103d is approximately greater than 0.5 eV. In some embodiments, the second conductive component 103d includes a conductive material such as titanium nitride (TiN), tungsten (W), or the like. In some embodiments, the second conductive component 103d includes the same material as the first conductive component 103b.

在一些實施例中,記憶體元件100還包括一絕緣結構106,鄰近字元線103設置。在一些實施例中,絕緣結構106從第一表面101b朝向半導體基底101的第二表面101c而延伸進入半導體基底101中。In some embodiments, the memory device 100 further includes an insulating structure 106 disposed adjacent the word line 103 . In some embodiments, the insulating structure 106 extends into the semiconductor substrate 101 from the first surface 101 b toward the second surface 101 c of the semiconductor substrate 101 .

在一些實施例中,絕緣結構106是一淺溝隔離(STI)。在一些實施例中,絕緣結構106界定主動區101a的一邊界。在一些實施例中,絕緣結構106包括介電材料,例如氧化物。在一些實施例中,絕緣結構106包含一隔離材料,例如氧化矽、氮化矽、氮氧化矽、類似舞或其組合。In some embodiments, isolation structure 106 is a shallow trench isolation (STI). In some embodiments, insulating structure 106 defines a boundary of active region 101a. In some embodiments, insulating structure 106 includes a dielectric material, such as an oxide. In some embodiments, the insulating structure 106 includes an isolation material such as silicon oxide, silicon nitride, silicon oxynitride, the like, or combinations thereof.

在一些實施例中,一第三導電組件107被絕緣結構106所圍繞。在一些實施例中,第三導電組件107具有一第三功函數,大致等於第一導電組件103b的第一功函數。在一些實施例中,第三導電組件107的第三功函數大致大於4eV。在一些實施例中,第三導電組件107包括導電材料,例如氮化鈦(TiN)、鎢(W)或類似物。In some embodiments, a third conductive component 107 is surrounded by an insulating structure 106 . In some embodiments, the third conductive component 107 has a third work function that is substantially equal to the first work function of the first conductive component 103b. In some embodiments, the third work function of the third conductive component 107 is approximately greater than 4 eV. In some embodiments, the third conductive component 107 includes a conductive material such as titanium nitride (TiN), tungsten (W), or the like.

在一些實施例中,一第三隔離層108設置在第三導電組件107與絕緣結構106上。在一些實施例中,第三隔離層108包括與第二隔離層103c相同的一材料。在一些實施例中,第三隔離層108包括介電材料,例如氧化物。在一些實施例中,第三隔離層108包含一隔離材料,例如氧化矽、氮化矽、氮氧化矽、類似物或其組合。In some embodiments, a third isolation layer 108 is disposed on the third conductive component 107 and the insulating structure 106 . In some embodiments, the third isolation layer 108 includes the same material as the second isolation layer 103c. In some embodiments, third isolation layer 108 includes a dielectric material, such as an oxide. In some embodiments, the third isolation layer 108 includes an isolation material such as silicon oxide, silicon nitride, silicon oxynitride, the like, or combinations thereof.

在一些實施例中,記憶體元件100還包括一介電層109,設置在第一導電組件103b、第二導電組件103d、第二隔離層103c、第三導電組件107以及第三隔離層108上。在一些實施例中,介電層109接觸第二隔離層103c、第三隔離層108以及第二導電組件103d的上表面103f。In some embodiments, the memory device 100 further includes a dielectric layer 109 disposed on the first conductive component 103b, the second conductive component 103d, the second isolation layer 103c, the third conductive component 107 and the third isolation layer 108 . In some embodiments, the dielectric layer 109 contacts the second isolation layer 103c, the third isolation layer 108, and the upper surface 103f of the second conductive component 103d.

在一些實施例中,第二隔離層103c的至少一部分設置在介電層109與第一導電組件103b的上表面103e之間。在一些實施例中,介電層109包括介電材料,例如氮化物。在一些實施例中,介電層109當作一閘極介電質。In some embodiments, at least a portion of the second isolation layer 103c is disposed between the dielectric layer 109 and the upper surface 103e of the first conductive component 103b. In some embodiments, dielectric layer 109 includes a dielectric material, such as nitride. In some embodiments, dielectric layer 109 acts as a gate dielectric.

在一些實施例中,記憶體元件100還包括一導電栓塞110,延伸經過介電層109並連接到半導體基底101的主動區101a。在一些實例中,導電栓塞110延伸經過第一隔離層103a與第二隔離層103c。在一些實施例中,導電栓塞110的一部分突伸進入半導體基底101中或是半導體基底101的主動區101a中,以使導電栓塞110的該部分被半導體基底101或是半導體基底101的主動區101a所圍繞。在一些實施例中,導電栓塞110包括導電材料,例如金屬。在一些實施例中,導電栓塞110包括銅、金、銀或類似物。In some embodiments, the memory device 100 further includes a conductive plug 110 extending through the dielectric layer 109 and connected to the active region 101 a of the semiconductor substrate 101 . In some examples, the conductive plug 110 extends through the first isolation layer 103a and the second isolation layer 103c. In some embodiments, a portion of the conductive plug 110 protrudes into the semiconductor substrate 101 or the active region 101a of the semiconductor substrate 101, so that the portion of the conductive plug 110 is covered by the semiconductor substrate 101 or the active region 101a of the semiconductor substrate 101. surrounded by. In some embodiments, conductive plug 110 includes a conductive material, such as metal. In some embodiments, conductive plug 110 includes copper, gold, silver, or the like.

由於字元線103包括具有不同功函數的雙導電材料,此差異可抑制或避免一閘極誘導汲極洩漏(GIDL)。在一些實施例中,因為字元線103包括具有該高功函數的第一導電組件103b以及具有該低功函數的第二導電組件103d,所以此配置可減少GIDL問題。因此,可改善記憶體元件100的效能。Since word line 103 includes dual conductive materials with different work functions, this difference can suppress or avoid a gate-induced drain leakage (GIDL). In some embodiments, this configuration may reduce GIDL problems because word line 103 includes a first conductive component 103b having the high work function and a second conductive component 103d having the low work function. Therefore, the performance of the memory device 100 can be improved.

圖2是流程示意圖,例示本揭露一實施例之記憶體元件100的製備方法S200。圖3到圖20是剖視示意圖,例示本揭露一實施例製備記憶體元件100的各中間階段。FIG. 2 is a schematic flowchart illustrating a method S200 for manufacturing the memory device 100 according to an embodiment of the present disclosure. 3 to 20 are schematic cross-sectional views illustrating various intermediate stages of preparing the memory device 100 according to an embodiment of the present disclosure.

圖3到圖20所示的各階段亦在圖2的流程圖中示意地顯示。在以下討論中,參考圖2中所示的製程步驟討論圖3到圖20中所示的各製造階段。製備方法S200包括多個步驟,描述以及說明並不視為對步驟之順序的限制。製備方法S200包括許多步驟(S201、S202、S203、S204、S205、S206以及S207)。The stages shown in Figures 3 to 20 are also schematically shown in the flow chart of Figure 2 . In the following discussion, the various manufacturing stages shown in FIGS. 3 through 20 are discussed with reference to the process steps shown in FIG. 2 . The preparation method S200 includes multiple steps, and the description and explanation are not considered to limit the order of the steps. The preparation method S200 includes many steps (S201, S202, S203, S204, S205, S206 and S207).

請參考圖3到圖5,依據圖2中的步驟S201,提供一半導體基底101,半導體基底101具有鄰近半導體基底101之一第一表面101b所界定的一主動區101a。在一些實施例中,如圖3所示,提供具有第一表面101b與第二表面101c的半導體基底101,而第二表面101c對第一表面101b設置。在一些實施例中,如圖4所示,形成一溝槽111,溝槽111從第一表面101b朝向第二表面101c延伸。溝槽111的製作技術包含移除半導體基底101的一些部分。Please refer to FIGS. 3 to 5 . According to step S201 in FIG. 2 , a semiconductor substrate 101 is provided. The semiconductor substrate 101 has an active region 101 a defined adjacent to a first surface 101 b of the semiconductor substrate 101 . In some embodiments, as shown in FIG. 3 , a semiconductor substrate 101 having a first surface 101 b and a second surface 101 c is provided, and the second surface 101 c is disposed opposite the first surface 101 b. In some embodiments, as shown in FIG. 4 , a groove 111 is formed, and the groove 111 extends from the first surface 101 b toward the second surface 101 c. The fabrication technique of trench 111 involves removing portions of semiconductor substrate 101 .

在一些實施例中,半導體基底101包括一絕緣結構106,圍繞主動區101a設置。在一些實施例中,絕緣結構106從第一表面101b朝向半導體基底101的第二表面101c延伸。在一些實施例中,絕緣結構106包括介電材料,例如氧化物或類似物。在一些實施例中,如圖5所示,絕緣結構106的製作技術包含設置一絕緣材料進入溝槽111中。In some embodiments, the semiconductor substrate 101 includes an insulating structure 106 disposed around the active region 101a. In some embodiments, the insulating structure 106 extends from the first surface 101 b toward the second surface 101 c of the semiconductor substrate 101 . In some embodiments, insulating structure 106 includes a dielectric material such as an oxide or the like. In some embodiments, as shown in FIG. 5 , the manufacturing technique of the insulating structure 106 includes disposing an insulating material into the trench 111 .

請參考圖6,依據圖2中的步驟S202,形成一凹陷102,凹陷102從第一表面101b延伸進入半導體基底101中。在一些實施例中,凹陷102的製作技術包含移除半導體基底101的一些部分。在一些實施例中,半導體基底101的該等部分藉由蝕刻或任何其他適合的製程而進行移除。在一些實施例中,凹陷102至少部分被半導體基底101的主動區101a所圍繞。在一些實施例中,移除絕緣結構106的一部分。Referring to FIG. 6 , according to step S202 in FIG. 2 , a recess 102 is formed, and the recess 102 extends from the first surface 101 b into the semiconductor substrate 101 . In some embodiments, the fabrication technique of recess 102 includes removing portions of semiconductor substrate 101 . In some embodiments, these portions of semiconductor substrate 101 are removed by etching or any other suitable process. In some embodiments, recess 102 is at least partially surrounded by active region 101 a of semiconductor substrate 101 . In some embodiments, a portion of the insulating structure 106 is removed.

請參考圖7,依據圖2中的步驟S203,一第一隔離層103a共形於凹陷102設置。在一些實施例中,第一隔離層103a設置在半導體基底101的 第一表面101b上。在一些實施例中,第一隔離層103a覆蓋凹陷102的一整個側壁。在一些實施例中,第一隔離層103a包括介電材料,例如氧化物。在一些實施例中,第一隔離層103a與絕緣結構106包括一相同材料。在一些實施例中,第一隔離層103a的製作技術包含沉積、氧化或任何其他適合的製程。Please refer to FIG. 7 . According to step S203 in FIG. 2 , a first isolation layer 103 a is disposed conformally to the recess 102 . In some embodiments, the first isolation layer 103a is disposed on the first surface 101b of the semiconductor substrate 101. In some embodiments, the first isolation layer 103a covers an entire sidewall of the recess 102. In some embodiments, first isolation layer 103a includes a dielectric material, such as an oxide. In some embodiments, the first isolation layer 103a and the insulating structure 106 include the same material. In some embodiments, the manufacturing technology of the first isolation layer 103a includes deposition, oxidation or any other suitable process.

請參考圖8,依據圖2中的步驟S204,設置一第一導電材料112。在一些實施例中,第一導電材料112設置在凹陷102內並被第一隔離層103a所圍繞。在一些實施例中,第一導電材料112亦設置在溝槽111內並被絕緣結構106所圍繞。在一些實施例中,第一導電材料112的至少一部分被半導體基底101的主動區101a所圍繞。在一些實施例中,第一導電材料112的製作技術包含沉積、化學氣相沉積(CVD)或任何其他適合的製程。Referring to FIG. 8 , according to step S204 in FIG. 2 , a first conductive material 112 is provided. In some embodiments, first conductive material 112 is disposed within recess 102 and is surrounded by first isolation layer 103a. In some embodiments, the first conductive material 112 is also disposed in the trench 111 and surrounded by the insulating structure 106 . In some embodiments, at least a portion of the first conductive material 112 is surrounded by the active region 101 a of the semiconductor substrate 101 . In some embodiments, the manufacturing technology of the first conductive material 112 includes deposition, chemical vapor deposition (CVD), or any other suitable process.

在一些實施例中,第一導電材料112具有一第一功函數,大致大於4eV。在一些實施例中,第一導電材料112是氮化鈦](TiN)、鎢(W)或類似物。In some embodiments, the first conductive material 112 has a first work function that is approximately greater than 4 eV. In some embodiments, the first conductive material 112 is titanium nitride (TiN), tungsten (W), or the like.

請參考圖9到圖12,依據圖2中的步驟S205,移除第一導電材料112的一部分以形成一第一導電組件103b。在一些實施例中,如圖9所示,一光阻114’設置在第一導電材料112、第一隔離層103a以及絕緣結構106上。在一些實施例中,光阻114’的製作技術包含旋轉塗佈或任何其他適合的製程。Referring to FIGS. 9 to 12 , according to step S205 in FIG. 2 , a portion of the first conductive material 112 is removed to form a first conductive component 103b. In some embodiments, as shown in Figure 9, a photoresist 114' is disposed on the first conductive material 112, the first isolation layer 103a and the insulating structure 106. In some embodiments, the manufacturing technique of the photoresist 114' includes spin coating or any other suitable process.

在一些實施例中,如圖10所示,在設置光阻114’之後,移除光阻114’的一部分以形成一圖案化光阻114。在一些實施例中,第一導電材料112的一部分經由圖案化光阻114而暴露。在一些實施例中,第一導電材料112的該部分設置在凹陷102內且被第一隔離層103a所圍繞。In some embodiments, as shown in Figure 10, after disposing the photoresist 114', a portion of the photoresist 114' is removed to form a patterned photoresist 114. In some embodiments, a portion of first conductive material 112 is exposed via patterned photoresist 114 . In some embodiments, the portion of first conductive material 112 is disposed within recess 102 and is surrounded by first isolation layer 103a.

在一些實施例中,如圖11所示,移除第一導電材料112經由圖案化光阻114所暴露的該部分。在一些實施例中,藉由蝕刻或任何其他適合的製程而移除第一導電材料112經由圖案化光阻114所暴露的該部分。In some embodiments, as shown in FIG. 11 , the portion of the first conductive material 112 exposed through the patterned photoresist 114 is removed. In some embodiments, the portion of first conductive material 112 exposed through patterned photoresist 114 is removed by etching or any other suitable process.

在一些實施例中,如圖12所示,在移除第一導電材料112經由圖案化光阻114所暴露的該部分之後,移除圖案化光阻114並形成第一導電組件103b。在一些實施例中,形成第一導電組件103b的一上表面103e。在一些實施例中,藉由蝕刻、剝除(stripping)或任何其他適合的製程而移除圖案化光阻114。In some embodiments, as shown in FIG. 12 , after removing the portion of the first conductive material 112 exposed through the patterned photoresist 114 , the patterned photoresist 114 is removed and the first conductive component 103 b is formed. In some embodiments, an upper surface 103e of the first conductive component 103b is formed. In some embodiments, patterned photoresist 114 is removed by etching, stripping, or any other suitable process.

在一些實施例中,一第三導電組件107亦形成在溝槽111內並被絕緣結構106所圍繞。在一些實施例中,第一導電組件103b與第三導電組件107是同時或各別形成的。In some embodiments, a third conductive component 107 is also formed in the trench 111 and surrounded by the insulating structure 106 . In some embodiments, the first conductive component 103b and the third conductive component 107 are formed simultaneously or separately.

請參考圖13,依據圖2中的步驟S206,一第二隔離層103c設置在凹陷102內且共形於第一隔離層103a與第一導電組件103b設置。在一些實施例中,第二隔離層103c覆蓋第一導電組件103b與第三導電組件107。在一些實施例中,第二隔離層103c亦設置在半導體基底101的第一表面101b上。Please refer to FIG. 13. According to step S206 in FIG. 2, a second isolation layer 103c is disposed in the recess 102 and conforms to the first isolation layer 103a and the first conductive component 103b. In some embodiments, the second isolation layer 103c covers the first conductive component 103b and the third conductive component 107. In some embodiments, the second isolation layer 103c is also disposed on the first surface 101b of the semiconductor substrate 101.

在一些實施例中,第一導電組件103b被第二隔離層103c與第一隔離層103a所包圍。在一些實施例中,第二隔離層103c包括介電材料,例如氧化物。在一些實施例中,第二隔離層103c的製作技術包含沉積、原子層沉積(ALD)或任何其他適合的製程。In some embodiments, the first conductive component 103b is surrounded by the second isolation layer 103c and the first isolation layer 103a. In some embodiments, second isolation layer 103c includes a dielectric material, such as an oxide. In some embodiments, the manufacturing technology of the second isolation layer 103c includes deposition, atomic layer deposition (ALD), or any other suitable process.

請參考圖14及圖15,依據圖2中的步驟S207,一第二導電材料113設置在凹陷102內並被第二隔離層103c所圍繞,以形成鄰近第一導電組件103b的一第二導電組件103d。在一些實施例中,如圖14所示,第二導電材料113設置在第二隔離層103c上。在一些實施例中,第二導電材料113的製作技術包含沉積、化學氣相沉積(CVD)或任何其他適合的製程。Please refer to Figures 14 and 15. According to step S207 in Figure 2, a second conductive material 113 is disposed in the recess 102 and surrounded by the second isolation layer 103c to form a second conductive element adjacent to the first conductive component 103b. Component 103d. In some embodiments, as shown in Figure 14, the second conductive material 113 is disposed on the second isolation layer 103c. In some embodiments, the manufacturing technology of the second conductive material 113 includes deposition, chemical vapor deposition (CVD), or any other suitable process.

在一些實施例中,在設置第二導電材料113之前,執行第二隔離層103c的設置。在一些實施例中,在設置第二導電材料113之前,執行第一導電材料112的設置。在一些實施例中,第一導電材料112的設置以及第二導電材料113的設置是各別執行的。In some embodiments, the placement of the second isolation layer 103c is performed before the second conductive material 113 is placed. In some embodiments, the provision of the first conductive material 112 is performed before the second conductive material 113 is provided. In some embodiments, the placement of the first conductive material 112 and the placement of the second conductive material 113 are performed separately.

在一些實施例中,如圖15所示,移除第二導電材料113的一些部分以形成第二導電組件103s。在一些實施例中,藉由蝕刻或任何其他適合的製程而移除第二導電材料113的一些部分。在一些實施例中,移除第二導電材料113設置在第一導電組件103b上的一部分,以形成第二導電組件103d。In some embodiments, as shown in Figure 15, some portions of the second conductive material 113 are removed to form the second conductive component 103s. In some embodiments, portions of the second conductive material 113 are removed by etching or any other suitable process. In some embodiments, a portion of the second conductive material 113 disposed on the first conductive component 103b is removed to form the second conductive component 103d.

在一些實施例中,移除第二導電材料113在第三導電組件107上的一部分。在一些實施例中,移除第二導電材料113的一部分,直到第二導電組件103d的一上表面103f與第二隔離層103c之一水平部的一表面呈共面為止。In some embodiments, a portion of the second conductive material 113 on the third conductive component 107 is removed. In some embodiments, a portion of the second conductive material 113 is removed until an upper surface 103f of the second conductive component 103d is coplanar with a surface of a horizontal portion of the second isolation layer 103c.

在一些實施例中,第一導電組件103b的上表面103e大致低於第二導電組件103d的上表面103f。在一些實施例中,第一導電組件103b的上表面103e與第二導電組件103d的上表面103f被半導體基底101的主動區101a所圍繞。In some embodiments, the upper surface 103e of the first conductive component 103b is substantially lower than the upper surface 103f of the second conductive component 103d. In some embodiments, the upper surface 103e of the first conductive component 103b and the upper surface 103f of the second conductive component 103d are surrounded by the active region 101a of the semiconductor substrate 101.

在一些實施例中,第二導電材料113具有一第二功函數,其大致不同於第一導電材料112的第一功函數。在一些實施例中,第一導電材料113的第一功函數大致大於第二導電材料113的第二功函數。在一些實施例中,第二導電材料113的第二功函數大致小於4eV。In some embodiments, the second conductive material 113 has a second work function that is substantially different from the first work function of the first conductive material 112 . In some embodiments, the first work function of the first conductive material 113 is substantially greater than the second work function of the second conductive material 113 . In some embodiments, the second work function of the second conductive material 113 is approximately less than 4 eV.

在一些實施例中,第一導電材料112的第一功函數與第二導電材料113的第二功函數之間一差值大致大於0.5eV。在一些實施例中,第二導電材料113是氮化鈦(TiN)、鎢(W)或類似物。在一些實施例中,第二導電材料113包括與第一導電材料112相同的一材料。In some embodiments, a difference between the first work function of the first conductive material 112 and the second work function of the second conductive material 113 is approximately greater than 0.5 eV. In some embodiments, the second conductive material 113 is titanium nitride (TiN), tungsten (W), or the like. In some embodiments, the second conductive material 113 includes the same material as the first conductive material 112 .

在一些實施例中,如圖16所示,在形成第二導電組件103d之後,一介電材料109’設置在第二隔離層103c與第二導電組件103d上。在一些實施例中,介電材料109’的製作技術包含沉積、CVD或任何其他適合的製程。在一些實施例中,介電材料109’是氮化物或類似物。In some embodiments, as shown in Figure 16, after forming the second conductive component 103d, a dielectric material 109' is disposed on the second isolation layer 103c and the second conductive component 103d. In some embodiments, the fabrication technique of dielectric material 109' includes deposition, CVD, or any other suitable process. In some embodiments, dielectric material 109' is nitride or the like.

在一些實施例中,如圖17所示,在設置介電材料109’之後,移除介電材料109’的一部分以形成一介電層109。在一些實施例中,藉由蝕刻或任何其他適合的製程而移除移除介電材料109’的該部分。在一些實施例中,第二隔離層103c的一部分經由介電層109而暴露。In some embodiments, as shown in Figure 17, after the dielectric material 109' is provided, a portion of the dielectric material 109' is removed to form a dielectric layer 109. In some embodiments, the portion of dielectric material 109' is removed by etching or any other suitable process. In some embodiments, a portion of second isolation layer 103c is exposed via dielectric layer 109.

在一些實施例中,如圖18所示,移除第二隔離層103c經由介電層109而暴露的該部分。在一些實施例中,亦移除第一隔離層103a經由介電層109而暴露的一部分。藉由蝕刻或任何其他適合的製程而實現第二隔離層103c經由介電層109而暴露之該部分的移除以及第一隔離層103a經由介電層109而暴露之該部分的移除。在一些實施例中,如圖19所示,還移除半導體基底101經由介電層109而暴露的一部分。In some embodiments, as shown in FIG. 18 , the portion of the second isolation layer 103c exposed through the dielectric layer 109 is removed. In some embodiments, a portion of the first isolation layer 103a exposed through the dielectric layer 109 is also removed. The removal of the portion of the second isolation layer 103c exposed through the dielectric layer 109 and the removal of the portion of the first isolation layer 103a exposed through the dielectric layer 109 are accomplished by etching or any other suitable process. In some embodiments, as shown in FIG. 19 , a portion of the semiconductor substrate 101 exposed through the dielectric layer 109 is also removed.

在一些實施例中,如圖20所示,在移除第一隔離層103a經由介電層109而暴露之該部分以及移除第二隔離層103c經由介電層109而暴露之該部分之後,一導電栓塞110形成在半導體基底101的主動區101a上。在一些實施例中,導電栓塞110的製作技術包含設置一導電材料。在一些實施例中,導電材料的製作技術包含電鍍或任何其他適合的製程。In some embodiments, as shown in FIG. 20 , after removing the portion of the first isolation layer 103 a exposed through the dielectric layer 109 and removing the portion of the second isolation layer 103 c exposed through the dielectric layer 109 , A conductive plug 110 is formed on the active region 101a of the semiconductor substrate 101. In some embodiments, the manufacturing technique of the conductive plug 110 includes disposing a conductive material. In some embodiments, the manufacturing technology of the conductive material includes electroplating or any other suitable process.

在一些實施例中,導電栓塞110延伸經過介電層109且連接到半導體基底101的主動區101a。在一些實施例中,導電栓塞110經由半導體基底101的主動區101a而電性連接到字元線103。在一些實施例中,如圖20所示,形成圖1的記憶體元件100。In some embodiments, conductive plug 110 extends through dielectric layer 109 and connects to active region 101 a of semiconductor substrate 101 . In some embodiments, the conductive plug 110 is electrically connected to the word line 103 via the active region 101 a of the semiconductor substrate 101 . In some embodiments, as shown in Figure 20, the memory device 100 of Figure 1 is formed.

本揭露之一實施例提供一種記憶體元件。該記憶體元件包括一半導體基底,具有鄰近該半導體基底之一表面處所界定的一主動區,其中該半導體基底具有一凹陷,從該表面延伸進入該半導體基底中;以及一字元線,設置在該凹陷內;其中該字元線具有一第一隔離層、一第一導電組件、一第二隔離層以及一第二導電組件,該第一隔離層設置在該凹陷內且共形於該凹陷,該第一導電組件被該第一隔離層所圍繞並設置在該凹陷內,該第二隔離層共形於該第一隔離層與該第一導電組件設置,該第二導電組件鄰近該第一導電組件設置且被該第二隔離層所圍繞。An embodiment of the present disclosure provides a memory device. The memory device includes a semiconductor substrate having an active region defined adjacent a surface of the semiconductor substrate, wherein the semiconductor substrate has a recess extending from the surface into the semiconductor substrate; and a word line disposed on Within the recess; wherein the word line has a first isolation layer, a first conductive component, a second isolation layer and a second conductive component, the first isolation layer is disposed in the recess and conforms to the recess , the first conductive component is surrounded by the first isolation layer and is disposed in the recess, the second isolation layer is disposed conformally to the first isolation layer and the first conductive component, and the second conductive component is adjacent to the first conductive component. A conductive component is disposed and surrounded by the second isolation layer.

本揭露之另一實施例提供一種記憶體元件。該記憶體元件包括一半導體基底,具有鄰近該半導體基底之一表面處的一主動區,其中該半導體基底具有一第一凹陷,從該表面延伸進入該半導體基底中;以及一字元線,設置在該第一凹陷內;其中該字元線具有一第一隔離層、一第一導電組件、一第二隔離層以及一第二導電組件,該第一隔離層共形於該第一凹陷設置並具有一第二凹陷在該第一凹陷內,該第一導電組件被該第一隔離層所圍繞並設置在該第二凹陷內,該第二隔離層共形於該第二凹陷與該第二導電組件設置並具有一第三凹陷在該第二凹陷內,該第二導電組件設置在該第三凹陷內。Another embodiment of the present disclosure provides a memory device. The memory device includes a semiconductor substrate having an active region adjacent a surface of the semiconductor substrate, wherein the semiconductor substrate has a first recess extending from the surface into the semiconductor substrate; and a word line disposed In the first recess; wherein the word line has a first isolation layer, a first conductive component, a second isolation layer and a second conductive component, the first isolation layer is conformally disposed in the first recess and has a second recess in the first recess, the first conductive component is surrounded by the first isolation layer and is disposed in the second recess, and the second isolation layer is conformal to the second recess and the third recess. Two conductive components are disposed and have a third recess in the second recess, and the second conductive component is disposed in the third recess.

本揭露之另一實施例提供一種記憶體元件的製備方法。該製備方法包括提供一半導體基底,該半導體基底具有鄰近該半導體基底之一表面處所界定的一主動區;形成一凹陷以從該表面延伸進入該半導體基底中;設置一第一隔離層以共形於該凹陷;設置一第一導電材料在該凹陷內並被該地一隔離層所圍繞;移除該第一導電材料的一部分以形成一第一導電組件;設置一第二隔離層在該凹陷內且共形於該第一隔離層與該第一導電組件;以及設置一第二導電材料在該凹陷內並被該第二隔離層所圍繞,以形成鄰近該第一導電組件的一第二導電組件。Another embodiment of the present disclosure provides a method of manufacturing a memory device. The preparation method includes providing a semiconductor substrate having an active region defined adjacent to a surface of the semiconductor substrate; forming a recess to extend from the surface into the semiconductor substrate; and providing a first isolation layer to conformally in the recess; disposing a first conductive material in the recess and surrounded by an isolation layer; removing a portion of the first conductive material to form a first conductive component; disposing a second isolation layer in the recess within and conformable to the first isolation layer and the first conductive component; and disposing a second conductive material in the recess and surrounded by the second isolation layer to form a second conductive component adjacent to the first conductive component. Conductive components.

總之,因為一字元線包括具有不同功函數的雙導電材料,所以這種差異可抑制或避免一閘極誘導汲極洩漏(GIDL)。在一些實施例中,因為該字元線包括具有一高功函數的一第一導電材料以及具有一低功函數的一第二導電材料,所以此配置可減少GIDL問題。因此,改善該記憶體元件的效能以及製造該記憶體元件的一製程。In summary, because a word line includes dual conductive materials with different work functions, this difference can suppress or avoid a gate-induced drain leakage (GIDL). In some embodiments, this configuration may reduce GIDL problems because the word line includes a first conductive material with a high work function and a second conductive material with a low work function. Therefore, the performance of the memory device and a process for manufacturing the memory device are improved.

雖然已詳述本揭露及其優點,然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如,可用不同的方法實施上述的許多製程,並且以其他製程或其組合替代上述的許多製程。Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the claimed claims. For example, many of the processes described above may be implemented in different ways and replaced with other processes or combinations thereof.

再者,本申請案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質上相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此,此等製程、機械、製造、物質組成物、手段、方法、或步驟包含於本申請案之申請專利範圍內。Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, etc. that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patent scope of this application.

100:記憶體元件 101:半導體基底 101a:主動區 101b:第一表面 101c:第二表面 102:凹陷 103:字元線 103a:第一隔離層 103b:第一導電組件 103c:第二隔離層 103d:第二導電組件 103e:上表面 103f:上表面 104:第二凹陷 105:第三凹陷 106:絕緣結構 107:第三導電組件 108:第三隔離層 109:介電層 109’:介電材料 110:導電栓塞 111:溝槽 112:第一導電材料 113:第二導電材料 114:圖案化光阻 114’:光阻 H1:高度 H2:高度 S200:製備方法 S201:步驟 S202:步驟 S203:步驟 S204:步驟 S205:步驟 S206:步驟 S207:步驟 W1:寬度 W2:寬度 W3:第一寬度 W4:第二寬度 100:Memory components 101:Semiconductor substrate 101a: Active area 101b: First surface 101c: Second surface 102:dent 103: character line 103a: First isolation layer 103b: First conductive component 103c: Second isolation layer 103d: Second conductive component 103e: Upper surface 103f: Upper surface 104:Second depression 105:Third depression 106:Insulation structure 107:Third conductive component 108:Third isolation layer 109: Dielectric layer 109’: Dielectric material 110: Conductive plug 111:Trench 112: First conductive material 113: Second conductive material 114:Patterned photoresist 114’: Photoresist H1: height H2: height S200: Preparation method S201: Steps S202: Step S203: Step S204: Step S205: Step S206: Step S207: Step W1: Width W2: Width W3: first width W4: Second width

當結合圖式一起閱讀時,從以下詳細描述中可以最好地理解本揭露的各方面。值得注意的是,依據產業的標準慣例,各種特徵並未按比例繪製。事實上,為了討論的清晰,可以任意增加或減少各種特徵的尺寸。 圖1是剖視示意圖,例示本揭露一實施例之記憶體元件。 圖2是流程示意圖,例示本揭露一實施例之記憶體元件的製備方法。 圖3到圖20是剖視示意圖,例示本揭露一實施例製備記憶體元件的各中間階段。 Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the drawings. Note that, consistent with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 is a schematic cross-sectional view illustrating a memory device according to an embodiment of the present disclosure. FIG. 2 is a schematic flowchart illustrating a method for manufacturing a memory device according to an embodiment of the present disclosure. 3 to 20 are schematic cross-sectional views illustrating various intermediate stages of preparing a memory device according to an embodiment of the present disclosure.

100:記憶體元件 100:Memory components

101:半導體基底 101:Semiconductor substrate

101a:主動區 101a: Active area

101b:第一表面 101b: First surface

101c:第二表面 101c: Second surface

102:凹陷 102:dent

103:字元線 103: character line

103a:第一隔離層 103a: First isolation layer

103b:第一導電組件 103b: First conductive component

103c:第二隔離層 103c: Second isolation layer

103d:第二導電組件 103d: Second conductive component

103e:上表面 103e: Upper surface

103f:上表面 103f: Upper surface

104:第二凹陷 104:Second depression

105:第三凹陷 105:Third depression

106:絕緣結構 106:Insulation structure

107:第三導電組件 107:Third conductive component

108:第三隔離層 108:Third isolation layer

109:介電層 109: Dielectric layer

110:導電栓塞 110: Conductive plug

H1:高度 H1: height

H2:高度 H2: height

W1:寬度 W1: Width

W2:寬度 W2: Width

W3:第一寬度 W3: first width

W4:第二寬度 W4: Second width

Claims (20)

一種記憶體元件,包括: 一半導體基底,具有鄰近該半導體基底之一表面處所界定的一主動區,其中該半導體基底具有一凹陷,從該表面延伸進入該半導體基底中;以及 一字元線,設置在該凹陷內; 其中該字元線具有一第一隔離層、一第一導電組件、一第二隔離層以及一第二導電組件,該第一隔離層設置在該凹陷內且共形於該凹陷,該第一導電組件被該第一隔離層所圍繞並設置在該凹陷內,該第二隔離層共形於該第一隔離層與該第一導電組件設置,該第二導電組件鄰近該第一導電組件設置且被該第二隔離層所圍繞。 A memory component including: a semiconductor substrate having an active region defined adjacent a surface of the semiconductor substrate, wherein the semiconductor substrate has a recess extending from the surface into the semiconductor substrate; and A character line is arranged in the depression; The word line has a first isolation layer, a first conductive component, a second isolation layer and a second conductive component. The first isolation layer is disposed in the recess and conforms to the recess. The first isolation layer The conductive component is surrounded by the first isolation layer and is disposed in the recess. The second isolation layer is disposed conformally to the first isolation layer and the first conductive component. The second conductive component is disposed adjacent to the first conductive component. and surrounded by the second isolation layer. 如請求項1所述之記憶體元件,其中該第一導電組件的一第一功函數大致不同於該第二導電組件的一第二功函數。The memory device of claim 1, wherein a first work function of the first conductive component is substantially different from a second work function of the second conductive component. 如請求項2所述之記憶體元件,其中該第一導電組件的該第一功函數大致大於該第二導電組件的該第二功函數。The memory device of claim 2, wherein the first work function of the first conductive component is substantially greater than the second work function of the second conductive component. 如請求項1所述之記憶體元件,其中該第一導電組件與該第二導電組件包括一相同材料。The memory device of claim 1, wherein the first conductive component and the second conductive component include the same material. 如請求項1所述之記憶體元件,其中該第一導電組件與該第二導電組件包括鎢或氮化鈦。The memory device of claim 1, wherein the first conductive component and the second conductive component include tungsten or titanium nitride. 如請求項1所述之記憶體元件,其中該第一隔離層與該第二隔離層包括氧化物。The memory device of claim 1, wherein the first isolation layer and the second isolation layer include oxide. 如請求項1所述之記憶體元件,其中該第一導電組件被該第一隔離層與該第二隔離層所包圍。The memory device of claim 1, wherein the first conductive component is surrounded by the first isolation layer and the second isolation layer. 如請求項1所述之記憶體元件,其中該第一導電組件與該第二導電組件藉由該第二隔離層而分隔開。The memory device of claim 1, wherein the first conductive component and the second conductive component are separated by the second isolation layer. 如請求項1所述之記憶體元件,其中該第一導電組件的一上表面大致低於該第二導電組件的一上表面。The memory device of claim 1, wherein an upper surface of the first conductive component is substantially lower than an upper surface of the second conductive component. 如請求項9所述之記憶體元件,其中該第一導電組件的該上表面與該第二導電組件的該上表面被該半導體基底的該主動區所圍繞。The memory device of claim 9, wherein the upper surface of the first conductive component and the upper surface of the second conductive component are surrounded by the active region of the semiconductor substrate. 如請求項9所述之記憶體元件,其中該第一導電組件之該上表面的一寬度大致大於或等於該第二導電組件之該上表面的一寬度。The memory device of claim 9, wherein a width of the upper surface of the first conductive component is substantially greater than or equal to a width of the upper surface of the second conductive component. 如請求項1所述之記憶體元件,還包括一介電層,設置在該第一導電組件、該第二導電組件以及該第二隔離層上,其中該介電層接觸該第二導電組件的該上表面。The memory device of claim 1, further comprising a dielectric layer disposed on the first conductive component, the second conductive component and the second isolation layer, wherein the dielectric layer contacts the second conductive component of the upper surface. 如請求項12所述之記憶體元件,還包括一導電栓塞,延伸經過該介電層並連接到該半導體基底的該主動區,其中該第二隔離層的至少一部分設置在該介電層與該第一導電組件的一上表面之間。The memory device of claim 12, further comprising a conductive plug extending through the dielectric layer and connected to the active region of the semiconductor substrate, wherein at least a portion of the second isolation layer is disposed between the dielectric layer and between an upper surface of the first conductive component. 如請求項1所述之記憶體元件,其中該第一導電組件的一高度大致小於或等於該第二導電組件的一高度。The memory device of claim 1, wherein a height of the first conductive component is substantially less than or equal to a height of the second conductive component. 一種記憶體元件,包括: 一半導體基底,具有鄰近該半導體基底之一表面處的一主動區,其中該半導體基底具有一第一凹陷,從該表面延伸進入該半導體基底中;以及 一字元線,設置在該第一凹陷內; 其中該字元線具有一第一隔離層、一第一導電組件、一第二隔離層以及一第二導電組件,該第一隔離層共形於該第一凹陷設置並具有一第二凹陷在該第一凹陷內,該第一導電組件被該第一隔離層所圍繞並設置在該第二凹陷內,該第二隔離層共形於該第二凹陷與該第二導電組件設置並具有一第三凹陷在該第二凹陷內,該第二導電組件設置在該第三凹陷內。 A memory component including: a semiconductor substrate having an active region adjacent a surface of the semiconductor substrate, wherein the semiconductor substrate has a first recess extending from the surface into the semiconductor substrate; and A character line is provided in the first depression; The word line has a first isolation layer, a first conductive component, a second isolation layer and a second conductive component. The first isolation layer is conformally disposed in the first recess and has a second recess in In the first recess, the first conductive component is surrounded by the first isolation layer and is disposed in the second recess. The second isolation layer is conformally arranged in the second recess and the second conductive component and has a The third recess is in the second recess, and the second conductive component is disposed in the third recess. 如請求項15所述之記憶體元件,其中該三凹陷具有一第一寬度以及一第二寬度,該第一寬度鄰近該第一導電組件,該第二寬度位在該第一導電組件上,且該第二寬度大致不同於該第一寬度。The memory device of claim 15, wherein the three recesses have a first width and a second width, the first width is adjacent to the first conductive component, and the second width is located on the first conductive component, And the second width is substantially different from the first width. 如請求項16所述之記憶體元件,其中該第二寬度大致大於該第一寬度。The memory device of claim 16, wherein the second width is substantially larger than the first width. 如請求項15所述之記憶體元件,其中該第一導電組件的一第一功函數大致大於該第二導電組件的一第二功函數。The memory device of claim 15, wherein a first work function of the first conductive component is substantially greater than a second work function of the second conductive component. 如請求項18所述之記憶體元件,其中該第一導電組件的該第一功函數大致大於4eV,且該第二導電組件的該第二功函數大致小於4eV。The memory device of claim 18, wherein the first work function of the first conductive component is approximately greater than 4 eV, and the second work function of the second conductive component is approximately less than 4 eV. 如請求項18所述之記憶體元件,其中該第一功函數與該第二功函數之間的一差值大致大於0.5eV。The memory device of claim 18, wherein a difference between the first work function and the second work function is approximately greater than 0.5 eV.
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