TW202337139A - Delay-locked loop device - Google Patents

Abstract

A delay-locked loop (DLL) device is provided. The DLL device includes a delay line, a replica circuit, an internal clock generator, a phase detector and a delay controller. The delay line delays the input clock to generate a delay clock in response to the delay signal. The replica circuit generates a replica clock according to the delay clock. The internal clock generator generates a leading clock and a lagging clock according to the replica clock. The phase detector provides an update trigger signal based on a shift phase difference between the replica clock and the input clock, a leading phase difference between the leading clock and the input clock, and a lagging phase difference between the lagging clock and the input clock. The delay controller provides a delay controlling signal, and updates the delay controlling signal in response to the update trigger signal.

Description

delay locked loop device

The present invention relates to a delay locked loop device, and in particular to a delay locked loop device with low power consumption.

Generally, a delay-locked loop (DLL) device is set to an update period to adjust the received input clock to a desired delay clock.

However, in the case of a short update cycle, the DLL device will frequently update the delay control signal used to control the delay line, thereby increasing power consumption. In the case of a long update cycle, once the delayed clock generated by the DLL device has a significant phase shift, the DLL device will be unable to adjust the delayed clock in time. Therefore, how to provide a delay locked loop device that has low power consumption and can delay the clock in a timely manner is one of the research focuses of those skilled in the art.

The present invention provides a delay-locked loop (DLL) device with low power consumption and capable of adjusting a delay clock in time.

The DLL device of the present invention includes a delay line, a replica circuit, an internal clock generator, a phase detector and a delay controller. The delay line receives the input clock and responds to the delay control signal to delay the input clock to generate a delay clock. The replica circuit is coupled to the delay line. The replica circuit receives the delay clock and generates a replica clock based on the delay clock. The internal clock generator is coupled to the replica circuit. The internal clock generator generates a leading clock and a lagging clock based on the replica clock and provides the replica clock. The phase detector is coupled to the internal clock generator. The phase detector provides an update trigger signal based on the translational phase difference between the replica clock and the input clock, the leading phase difference between the leading clock and the input clock, and the lagging phase difference between the lagging clock and the input clock. . The delay controller is coupled to the phase detector and the delay line. The delay controller provides a delay control signal and updates the delay control signal in response to the update trigger signal.

Based on the above, the phase detector will provide an update trigger signal based on the translation phase difference, the leading phase difference and the lagging phase difference, and the delay controller will update the delay control signal in response to the update trigger signal. In this way, when the phase of the delayed clock deviates significantly, the DLL device can adjust the delayed clock in time. When the phase of the delayed clock does not shift significantly, the DLL device does not adjust the delayed clock. In this way, the power consumption of the DLL device can be reduced.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings.

Some embodiments of the present invention will be described in detail with reference to the accompanying drawings. The component symbols cited in the following description will be regarded as the same or similar components when the same component symbols appear in different drawings. These embodiments are only part of the present invention and do not disclose all possible implementations of the present invention. Rather, these embodiments are only examples within the scope of the patent application of the invention.

Please refer to FIG. 1 , which is a schematic diagram of a delay locked loop device according to a first embodiment of the present invention. In this embodiment, the DLL device 100 includes a delay line 110 , a replica circuit 120 , an internal clock generator 130 , a phase detector 140 and a delay controller 150 . The delay line 110 receives the input clock ICLK and delays the input clock ICLK in response to the delay control signal SDL to generate the delayed clock DCLK. The replica circuit is coupled to delay line 110 . The replica circuit 120 receives the delayed clock DCLK and generates the replica clock RCLK according to the delayed clock DCLK. The internal clock generator 130 is coupled to the replica circuit 120 . The internal clock generator 130 generates the leading clock RCLK_lead and the lagging clock RCLK_lag according to the replica clock RCLK. In this embodiment, the periods of the input clock ICLK, the delayed clock DCLK, the replica clock RCLK, the leading clock RCLK_lead and the lagging clock RCLK_lag are the same as each other.

In this embodiment, the phase detector 140 is coupled to the internal clock generator 130 . The phase detector 140 is based on the translation phase difference PD between the replica clock RCLK and the input clock ICLK, the leading phase difference PD_lead between the leading clock RCLK_lead and the input clock ICLK, and the difference between the lagging clock RCLK_lag and the input clock ICLK. The lagging phase difference PD_lag is used to provide the update trigger signal SU.

In this embodiment, the phase detector 140 receives the input clock ICLK, the replica clock RCLK, the leading clock RCLK_lead, and the lagging clock RCLK_lag. The phase detector 140 obtains the translation phase difference PD between the replica clock RCLK and the input clock ICLK. The phase detector 140 obtains the leading phase difference PD_lead between the leading clock RCLK_lead and the input clock ICLK. The phase detector 140 obtains the lagging phase difference PD_lag between the lagging clock RCLK_lag and the input clock ICLK. Next, the phase detector 140 provides an update trigger signal SU according to the translation phase difference PD, the leading phase difference PD_lead, and the lagging phase difference PD_lag.

In this embodiment, the delay controller 150 is coupled to the phase detector 140 and the delay line 110 . The delay controller 150 provides the delay control signal SDL. When receiving the update trigger signal SU, the delay controller 150 updates the delay control signal SDL in response to the update trigger signal SU. In this embodiment, the delay controller 150 is triggered in response to the update trigger signal SU, and updates the digital code of the delay control signal SDL based on the translation phase difference PD. On the other hand, when the update trigger signal SU is not received, the delay controller 150 does not update the delay control signal SDL.

It is worth mentioning here that the phase detector 140 provides the update trigger signal SU based on the translation phase difference PD, the leading phase difference PD_lead, and the lagging phase difference PD_lag. The delay controller 150 updates the delay control signal SDL in response to the update trigger signal SU. In this way, when the phase of the delayed clock DCLK deviates significantly, the DLL device 100 can adjust the delayed clock DCLK in time. When the phase of the delayed clock DCLK does not shift significantly, the DLL device 100 does not adjust the delayed clock DCLK. In this way, the power consumption of the DLL device 100 can be reduced.

Furthermore, in this embodiment, the phase detector 140 determines the translation phase difference PD, the leading phase difference PD_lead, and the lagging phase difference PD_lag. When the translation phase difference PD is greater than one of the leading phase difference PD_lead and the lagging phase difference PD_lag, it means that the phase of the delayed clock DCLK has significantly shifted. Therefore, the phase detector 140 provides the update trigger signal SU. The delay controller 150 is triggered in response to the update trigger signal SU, and updates the delay control signal SDL based on the translation phase difference PD. Therefore, the DLL device 100 enters the update period.

On the other hand, when the translation phase difference PD is less than or equal to the leading phase difference PD_lead and the lagging phase difference PD_lag, it means that the phase of the delayed clock DCLK has not shifted significantly. Therefore, the phase detector stops providing the update trigger signal SU. The delay controller 150 does not update the delay control signal SDL. Therefore, the DLL device 100 enters a non-update period.

Please refer to FIG. 1 and FIG. 2 simultaneously. FIG. 2 is a schematic diagram of an internal clock generator according to an embodiment of the present invention. The internal clock generator 230 may be adapted to the internal clock generator 130 shown in FIG. 1 . In this embodiment, the internal clock generator 230 includes delay circuits DL1˜DL3. The delay circuit DL1 is coupled to the replica circuit 120 . The delay circuit DL1 delays the replica clock RCLK from the replica circuit 120 to generate the leading clock RCLK_lead. Delay circuit DL2 is coupled to delay circuit DL1. The delay circuit DL2 delays the leading clock RCLK_lead to generate a replica clock RCLK that is one cycle behind. Delay circuit DL3 is coupled to delay circuit DL2. The delay circuit DL3 delays the replica clock RCLK which is lagging behind by a single cycle to generate a lagging clock RCLK_lag.

For example, the delay circuit DL1 may generate a first delay time length. Delay circuit DL2 may generate a second delay time length. Delay circuit DL3 may generate a third delay time length. Therefore, the sum of the delay time lengths of the first delay time length and the second delay time length is equal to a single cycle of the replica clock RCLK. The replica clock RCLK provided by the delay circuit DL2 has a delay of a second delay time length compared with the leading clock RCLK_lead. The lagging clock RCLK_lag has a delay of a third delay time length compared to the replica clock RCLK provided by the delay circuit DL2. For example, the second delay time length and the third delay time length are 10 to 20 picoseconds (pico-second, psec) respectively, and the present invention is not limited thereto. For example, the delay circuits DL1 to DL3 are implemented by including a plurality of buffers coupled in series. The number of buffers in series will determine the delay generated by delay circuits DL1~DL3. Therefore, the second delay time length and the third delay time length may be determined by the series number of buffers in the delay circuits DL2 and DL3.

Please refer to FIG. 1 and FIG. 3 simultaneously. FIG. 3 is a schematic diagram of an internal clock generator according to another embodiment of the present invention. The internal clock generator 330 may be adapted to the internal clock generator 130 shown in FIG. 1 . In this embodiment, the internal clock generator 330 includes delay circuits DL1˜DL3. The delay circuit DL1 is coupled to the replica circuit 120 . The delay circuit DL1 delays the replica clock RCLK to generate the leading clock RCLK_lead. Delay circuit DL2 is coupled to replica circuit 120 . The delay circuit DL2 delays the replica clock RCLK to generate a replica clock RCLK that is one cycle behind. In other words, the delay circuit DL2 delays the replica clock RCLK by a single cycle. The delay circuit DL3 is coupled to the replica circuit 120 . The delay circuit DL3 delays the replica clock RCLK to generate a lagging clock RCLK_lag.

In this embodiment, the delay circuit DL1 has a first time constant. Delay circuit DL2 has a second time constant. Delay circuit DL3 has a third time constant. The second time constant is greater than the first time constant. The third time constant is greater than the second time constant. Therefore, the phase of the leading clock RCLK_lead will lead the phase of the replica clock RCLK generated by the delay circuit DL2. The phase of the lagging clock RCLK_lag will lag behind the phase of the replica clock RCLK generated by the delay circuit DL2.

In this embodiment, the delay circuit DL1 includes a capacitor C_lead. The first time constant is determined by the capacitance value of capacitor C_lead. Delay circuit DL2 includes capacitor C. The second time constant is determined by the capacitance value of capacitor C. Delay circuit DL3 includes capacitor C_lag. The third time constant is determined by the capacitance value of the capacitor C_lag.

In addition, the delay circuit DL1 also includes buffers B1 and B2. The input terminal of the buffer B1 is coupled to the replica circuit 120 . The input terminal of buffer B1 is used to receive the replica clock RCLK. The output terminal of the buffer B1 is coupled to the first terminal of the capacitor C_lead. The second terminal of the capacitor C_lead is coupled to the reference low voltage (eg, ground). The input terminal of buffer B2 is coupled to the output terminal of buffer B1. The output terminal of buffer B2 is used to output the leading clock RCLK_lead. Delay circuit DL2 also includes buffers B3, B4. The input terminal of the buffer B3 is coupled to the replica circuit 120 . The input terminal of buffer B3 is used to receive the replica clock RCLK. The output terminal of the buffer B3 is coupled to the first terminal of the capacitor C. The second terminal of the capacitor C is coupled to the reference low voltage. The input terminal of buffer B4 is coupled to the output terminal of buffer B3. The output terminal of the buffer B4 is used to output the replica clock RCLK that is one cycle behind. Delay circuit DL3 also includes buffers B5, B6. The input terminal of the buffer B5 is coupled to the replica circuit 120 . The input terminal of buffer B5 is used to receive the replica clock RCLK. The output terminal of the buffer B5 is coupled to the first terminal of the capacitor C_lag. The second terminal of the capacitor C_lag is coupled to the reference low voltage. The input terminal of buffer B6 is coupled to the output terminal of buffer B5. The output terminal of the buffer B6 is used to output the lagging clock RCLK_lag.

In this embodiment, the buffers B1 to B6 can be used to maintain the waveform of the replica clock RCLK during the delay process. Buffers B1~B6 can also be used to extend the delay time length. In some embodiments, a buffer (not shown) may be disposed between the replica circuit 120 and the internal clock generator 330 to jointly extend the delay time length.

Please refer to both Figure 3 and Figure 4. FIG. 4 is a timing diagram based on the replica clock, leading clock and lagging clock shown in FIG. 3 . In this embodiment, FIG. 4 shows timing diagrams C1 and C2. The timing diagram C1 shows the timing of the replica clock RCLK, the leading clock RCLK_lead, and the lagging clock RCLK_lag under the condition that there is a large difference between the capacitance values of the capacitors C_lead, C, and C_lag. The timing diagram C2 shows the timing of the replica clock RCLK, the leading clock RCLK_lead, and the lagging clock RCLK_lag under the condition that there is a small difference between the capacitance values of the capacitors C_lead, C, and C_lag. There is a time difference td1 between the rising edge of the replica clock RCLK and the rising edge of the leading clock RCLK_lead. There is a time difference td2 between the rising edge of the replica clock RCLK and the rising edge of the lagging clock RCLK_lag. Under the condition that there is a large difference between the capacitance values of the capacitors C_lead, C, and C_lag, the time differences td1 and td2 will be large. Under the condition that there is a small difference between the capacitance values of the capacitors C_lead, C, and C_lag, the time differences td1 and td2 will be small.

In this embodiment, the rising edge of the leading clock RCLK_lead and the rising edge of the lagging clock RCLK_lag will be used as an important basis for judging whether the phase of the delayed clock DCLK is significantly shifted. For example, when the phase of the delayed clock DCLK shifts (eg, leads or lags), the replica clock RCLK, the leading clock RCLK_lead, and the lagging clock RCLK_lag will also shift in the same direction. When the rising edge of the input clock leads the rising edge of the leading clock RCLK_lead or when the rising edge of the input clock lags behind the rising edge of the lagging clock RCLK_lag, the phase of the delayed clock DCLK will be judged to be significantly offset.

Therefore, under the condition that there is a large difference between the capacitance values of the capacitors C_lead, C, and C_lag, the update sensitivity of the phase detector 140 will be low. Under the condition that there is a small difference between the capacitance values of the capacitors C_lead, C, and C_lag, the update sensitivity of the phase detector will be higher. That is, the capacitance values of the capacitors C_lead, C, C_lag can be designed to determine the update sensitivity of the phase detector 140 .

Please refer to FIG. 5 , which is a schematic diagram of a delay locked loop device according to a second embodiment of the present invention. In this embodiment, the DLL device 400 includes a delay line 110, a replica circuit 120, an internal clock generator 130, a phase detector 440 and a delay controller 150. The implementation details of the delay line 110, the replica circuit 120, the internal clock generator 130 and the delay controller 150 can be sufficiently taught in the various embodiments of FIGS. 1 to 4 and will not be repeated here.

In this embodiment, the phase detector 440 includes phase difference determiners PDD1 to PDD3 and an update trigger signal generator 441. The phase difference determiner PDD1 is coupled to the delay controller 150 . The phase difference determiner PDD1 receives the replica clock RCLK and the input clock ICLK. The phase difference determiner PDD1 obtains the translation phase difference PD according to the rising edge of the replica clock RCLK and the rising edge of the input clock ICLK. The phase difference determiner PDD1 provides the translation phase difference PD to the delay controller 150 .

In this embodiment, the phase difference determiner PDD2 receives the leading clock RCLK_lead and the input clock ICLK. The phase difference determiner PDD2 compares the rising edge of the leading clock RCLK_lead with the rising edge of the input clock ICLK. When the rising edge of the leading clock RCLK_lead lags behind the rising edge of the input clock ICLK, the phase difference determiner PDD2 provides the first error signal SE1 according to the leading clock RCLK_lead. The phase difference determiner PDD3 receives the lagging clock RCLK_lag and the input clock ICLK. The phase difference determiner PDD3 will lag behind the rising edge of the clock RCLK_lag and the rising edge of the input clock ICLK. When the rising edge of the lagging clock RCLK_lag leads the rising edge of the input clock ICLK, the phase difference determiner PDD3 provides the second error signal SE2 according to the lagging clock RCLK_lag.

In this embodiment, the update trigger signal generator 441 is coupled to the phase difference determiners PDD2, PDD3 and the delay controller 150. The update trigger signal generator 441 provides the update trigger signal SU according to the first error signal SE1 and the second error signal SE2.

In this embodiment, the update trigger signal generator 441 includes a logic circuit LOC. The logic circuit LOC responds to one of the first error signal SE1 and the second error signal SE2 to output the update trigger signal SU. Furthermore, the logic circuit LOC performs logical operations on the first error signal SE1 and the second error signal SE2 to output the update trigger signal SU. Taking this embodiment as an example, the first error signal SE1 and the second error signal SE2 are signals with high logic levels respectively (the invention is not limited thereto). The logic circuit LOC can be implemented by an OR logic gate. Therefore, the logic circuit LOC can output the update trigger signal SU with a high logic level according to one of the first error signal SE1 and the second error signal SE2. In some embodiments, the logic circuit LOC may be implemented as an exclusive OR (XOR) logic gate.

Please refer to FIG. 5 and FIG. 6A at the same time. FIG. 6A is a first timing diagram based on FIG. 5 . In this embodiment, the translation phase difference PD between the replica clock RCLK and the input clock ICLK is less than or equal to the leading phase difference PD_lead and the lagging phase difference PD_lag. That is, the rising edge of the input clock ICLK lags the rising edge of the leading clock RCLK_lead and leads the rising edge of the lagging clock RCLK_lag. The phase difference determiner PDD2 provides the first error signal SE1 with a low logic level. The phase difference determiner PDD3 provides the second error signal SE2 with a low logic level. Therefore, the update trigger signal generator 441 provides a signal with a low logic level instead of the update trigger signal SU with a high logic level. The delay controller 150 does not update the delay control signal SDL.

Please refer to FIG. 5 and FIG. 6B at the same time. FIG. 6B is a second timing diagram based on FIG. 5 . In this embodiment, the translation phase difference PD between the replica clock RCLK and the input clock ICLK is greater than the leading phase difference PD_lead. That is, the rising edge of the input clock ICLK leads the rising edge of the leading clock RCLK_lead and leads the rising edge of the lagging clock RCLK_lag. The phase difference determiner PDD2 provides the first error signal SE1 with a high logic level. The phase difference determiner PDD3 provides the second error signal SE2 with a low logic level. Therefore, the update trigger signal generator 441 provides the update trigger signal SU with a high logic level. The delay controller 150 updates the delay control signal SDL in response to the update trigger signal SU having a high logic level.

Furthermore, in this embodiment, when the rising edge of the leading clock RCLK_lead is determined to lag behind the rising edge of the input clock ICLK, the first error signal SE1 is equal to the leading clock RCLK_lead. Taking this embodiment as an example, the phase difference determiner PDD2 determines the rising edge of the leading clock RCLK_lead and the rising edge of the input clock ICLK. When the rising edge of the input clock ICLK is generated and the rising edge of the leading clock RCLK_lead has not yet been generated, the phase difference determiner PDD2 will determine that the phase of the delayed clock DCLK is significantly ahead of the phase of the input clock ICLK. Therefore, when the rising edge of the leading clock RCLK_lead is subsequently generated, the phase difference determiner PDD2 can use the leading clock RCLK_lead as the first error signal SE1.

Please refer to FIG. 5 and FIG. 6C at the same time. FIG. 6C is a third timing diagram based on FIG. 5 . In this embodiment, the translation phase difference PD between the replica clock RCLK and the input clock ICLK is greater than the lagging phase difference PD_lag. That is, the rising edge of the input clock ICLK lags the rising edge of the leading clock RCLK_lead and lags the rising edge of the lagging clock RCLK_lag. The phase difference determiner PDD2 provides the first error signal SE1 with a low logic level. The phase difference determiner PDD3 provides the second error signal SE2 with a high logic level. Therefore, the update trigger signal generator 441 provides the update trigger signal SU with a high logic level. The delay controller 150 updates the delay control signal SDL in response to the update trigger signal SU having a high logic level.

Furthermore, in this embodiment, when the rising edge of the lagging clock RCLK_lag is determined to be ahead of the rising edge of the input clock ICLK, the second error signal SE2 is equal to the lagging clock RCLK_lag. Taking this embodiment as an example, the phase difference determiner PDD3 determines the rising edge of the lagging clock RCLK_lag and the rising edge of the input clock ICLK. When the rising edge of the lagging clock RCLK_lag is generated and the rising edge of the input clock ICLK has not yet been generated, the phase difference determiner PDD2 determines that the phase of the delayed clock DCLK is significantly behind the phase of the subsequent input clock ICLK. Therefore, when the rising edge of the lagging clock RCLK_lag is generated and the rising edge of the input clock ICLK has not been generated, the phase difference determiner PDD3 may use the lagging clock RCLK_lag as the second error signal SE2.

Please refer to FIG. 7 , which is a schematic diagram of a phase detector according to an embodiment of the present invention. In this embodiment, the phase detector 540 includes phase difference determiners PDD1 to PDD3 and an update trigger signal generator 541. The implementation details of the phase difference determiners PDD1 to PDD3 can be sufficiently taught in the multiple embodiments of FIG. 5 and FIGS. 6A to 6C and will not be repeated here.

In this embodiment, the update trigger signal generator 541 includes counters CNT1, CNT2 and a logic circuit LOC. The counter CNT1 is coupled to the phase difference determiner PDD2. The counter CNT1 counts the occurrence times of the first error signal SE1 to generate a count value CV1. When the count value CV1 reaches the first preset value, the counter CNT1 provides the trigger signal STR1. The counter CNT2 is coupled to the phase difference determiner PDD3. The counter CNT2 counts the occurrence times of the second error signal SE2 to generate a count value CV2. When the count value CV2 reaches the second preset value, the counter CNT2 provides the trigger signal STR2. In this embodiment, the first preset value and the second preset value may be the same numerical value or different numerical values.

The logic circuit LOC is coupled to the counters CNT1, CNT2 and the delay controller. The logic circuit LOC outputs the update trigger signal SU according to one of the trigger signals STR1 and STR2. Furthermore, the logic circuit LOC performs logical operations on the trigger signals STR1 and STR2 to output the update trigger signal SU. Taking this embodiment as an example, the trigger signals STR1 and STR2 are signals with high logic levels respectively (the invention is not limited thereto). The logic circuit LOC can be implemented by an OR logic gate. Therefore, the logic circuit LOC can output the update trigger signal SU with a high logic level according to one of the trigger signals STR1 and STR2. In some embodiments, the logic circuit LOC may be implemented as an exclusive OR (XOR) logic gate.

It is worth mentioning here that in this embodiment, the logic circuit LOC will output the update trigger signal SU only when the count value CV1 reaches the first preset value or when the count value CV2 reaches the second preset value. The DLL device does not frequently update the delay control signal SDL. In this way, the power consumption of the DLL device can be further reduced.

Please refer to FIG. 8 , which is a schematic diagram of a delay locked loop device according to a third embodiment of the present invention. In this embodiment, the DLL device 600 includes a delay line 110, a replica circuit 120, an internal clock generator 130, a phase detector 140, a delay controller 150 and a timer circuit 160. The implementation details of the delay line 110, the replica circuit 120, the internal clock generator 130, the phase detector 140 and the delay controller 150 can be sufficiently taught in the various embodiments of FIGS. 1 to 7 and will not be repeated here. narrate.

In this embodiment, the timer circuit 160 controls the internal clock generator 130 to generate the leading clock RCLK_lead and the lagging clock RCLK_lag based on the operation cycle. In this embodiment, the timer circuit 160 is coupled to the delay line 110 and the replica circuit 120 . The timer circuit 160 affects the replica circuit 120 to receive the delayed clock DCLK. Taking this embodiment as an example, the timer circuit 160 includes an AND logic gate AG and a timer 161 . The timer 161 provides the control signal SC having a first logic level (ie, a high logic level) based on the operation cycle. And the first input terminal of the logic gate AG is used to receive the delayed clock DCLK. And the second input end of the logic gate AG is used to receive the control signal SC. And the output terminal of the logic gate AG is coupled to the replica circuit 120 . Therefore, the timer circuit 160 controls the replica circuit 120 to intermittently receive the delayed clock DCLK based on the operating cycle. The internal clock generator 130 intermittently generates the leading clock RCLK_lead and the lagging clock RCLK_lag. In this way, the power consumption of the internal clock generator 130 and the phase detector 140 can be further reduced.

In addition, the delay controller 150 of this embodiment does not frequently update the delay control signal SDL. In this way, the power consumption of the delay controller 150 of this embodiment can be further reduced.

In some embodiments, the timer circuit 160 is coupled to the replica circuit 120 and the internal clock generator 130 . The timer circuit 160 affects the internal clock generator 130 to receive the replica clock RCLK. Therefore, the timer circuit 160 can control the internal clock generator 130 to intermittently receive the replica clock RCLK and intermittently generate the leading clock RCLK_lead and the lagging clock RCLK_lag based on the operation cycle. In this way, the power consumption of the internal clock generator 130, the phase detector 140 and the delay controller 150 can be reduced.

Please refer to FIG. 1 and FIG. 9 at the same time. FIG. 9 is a comparison diagram of eye diagrams and power consumption according to an embodiment of the present invention. In this embodiment, FIG. 9 shows the eye diagrams E1, E2, and E3 of the clock and the comparison diagram. Eye diagram E1 is an eye diagram generated by the DLL device continuously updating the delay control signal SDL. Eye diagram E2 is an eye diagram generated by the DLL device continuing not to update the delay control signal SDL. The eye diagram E3 is an eye diagram generated by the DLL device 100 updating the delay control signal SDL in response to the update trigger signal SU.

The comparison diagram shows the operating point P(E1) of the eye diagram E1, the operating point P(E2) of the eye diagram E2, and the operating point P(E3) of the eye diagram E3. In the comparison diagram, the eye width W1 of eye diagram E1 is the largest. Since the DLL device continues to update the delay control signal SDL, the power consumption corresponding to the eye diagram E1 will be very large. In the case where the DLL device continues not to update the delay control signal SDL, the power consumption corresponding to the eye diagram E2 will be very small. However, the eye width W2 of eye diagram E1 will also be significantly smaller.

In this embodiment, based on the implementation of the DLL device 100, when the translation phase difference PD is greater than one of the leading phase difference PD_lead and the lagging phase difference PD_lag, the DLL device 100 updates the delay control signal SDL. Therefore, the eye width W3 of eye diagram E3 is only slightly smaller than the eye width W1. The power consumption corresponding to eye diagram E3 is only slightly greater than the power consumption corresponding to eye diagram E2.

In this embodiment, for example, the teachings of multiple embodiments are based on FIG. 4 , FIG. 7 , and FIG. 8 . The frequency and/or update sensitivity of the DLL device 100 in updating the delay control signal SDL may be adjusted. Therefore, the eye width W3 and the power consumption of the eye diagram E3 can be adjusted to be close to one of the eye widths W1 and W2.

In summary, the phase detector of the DLL device will provide an update trigger signal based on the translation phase difference, the leading phase difference, and the lagging phase difference, and the delay controller of the DLL device will update the delay control signal in response to the update trigger signal. In this way, when the phase of the delayed clock deviates significantly, the DLL device can adjust the delayed clock in time. When the phase of the delayed clock does not shift significantly, the DLL device does not adjust the delayed clock. In this way, the power consumption of the DLL device can be reduced.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

100, 400, 600: DLL device 110: Delay line 120:Copy circuit 130, 230, 330: Internal clock generator 140, 440, 540: Phase detector 150:Delay controller 160: Timer circuit 161: timer 441, 541: Update trigger signal generator AG: and logic gate B1~B6: buffer C, C_C_lag, C_lead: capacitor C1, C2: Timing diagram CNT1, CNT2: counter CV1, CV: count value DCLK: delayed clock DL1, DL2, DL3: delay circuit E1, E2, E3: eye diagram ICLK: input clock LOC: logic circuit PD: translational phase difference PDD1, PDD2, PDD3: phase difference judger P(E1), P(E2), P(E3): operating point PD_lag: lagging phase difference PD_lead: leading phase difference RCLK: replica clock RCLK_lead: leading clock RCLK_lag: lagging clock SC: control signal SDL: delay control signal SE1: first error signal SE2: second error signal SU: update trigger signal td1, td2: time difference W1, W2, W3: Eye width

FIG. 1 is a schematic diagram of a delay locked loop device according to a first embodiment of the present invention. FIG. 2 is a schematic diagram of an internal clock generator according to an embodiment of the invention. FIG. 3 is a schematic diagram of an internal clock generator according to another embodiment of the invention. FIG. 4 is a timing diagram based on the replica clock, leading clock and lagging clock shown in FIG. 3 . FIG. 5 is a schematic diagram of a delay locked loop device according to a second embodiment of the present invention. FIG. 6A is a first timing diagram shown in FIG. 5 . FIG. 6B is a second timing diagram shown in FIG. 5 . FIG. 6C is a third timing diagram shown in FIG. 5 . FIG. 7 is a schematic diagram of a phase detector according to an embodiment of the present invention. FIG. 8 is a schematic diagram of a delay locked loop device according to a third embodiment of the present invention. FIG. 9 is a comparison diagram of eye diagrams and power consumption according to an embodiment of the present invention.

100:DLL device

110: Delay line

120:Copy circuit

130: Internal clock generator

140: Phase detector

150:Delay controller

DCLK: delayed clock

ICLK: input clock

PD: translational phase difference

PD_lag: lagging phase difference

PD_lead: leading phase difference

RCLK: replica clock

RCLK_lag: lagging clock

RCLK_lead: leading clock

SDL: delay control signal

SU: update trigger signal

Claims (13)

A delay locked loop device, including: a delay line configured to receive an input clock and to delay the input clock in response to a delay control signal to generate a delay clock; a replica circuit coupled to the delay line and configured to receive the delay clock and generate a replica clock based on the delay clock; an internal clock generator coupled to the replica circuit and configured to generate a leading clock and a lagging clock based on the replica clock and provide the replica clock; a phase detector coupled to the internal clock generator configured to depend on a translation phase difference between the replica clock and the input clock, a lead between the leading clock and the input clock The phase difference and a lagging phase difference between the lagging clock and the input clock provide an update trigger signal; and A delay controller coupled to the phase detector and the delay line is configured to provide the delay control signal and to update the delay control signal in response to the update trigger signal. The delay locked loop device as claimed in claim 1, wherein when the translation phase difference is greater than one of the leading phase difference and the lagging phase difference, the phase detector provides the update trigger signal. The delay locked loop device of claim 1, wherein when the translation phase difference is less than or equal to the leading phase difference and the lagging phase difference, the phase detector stops providing the update trigger signal. The delay locked loop device as claimed in claim 1, wherein the internal clock generator includes: a first delay circuit coupled to the replica circuit and configured to delay the replica clock from the replica circuit to generate the leading clock; a second delay circuit coupled to the first delay circuit configured to delay the leading clock to generate the replica clock lagging behind by a single period; and A third delay circuit, coupled to the second delay circuit, is configured to delay the replica clock that is lagging behind by a single period to generate the lagging clock. The delay locked loop device as claimed in claim 1, wherein the internal clock generator includes: a first delay circuit coupled to the replica circuit and configured to delay the replica clock to generate the leading clock; a second delay circuit coupled to the replica circuit and configured to delay the replica clock to generate the replica clock lagging behind by a single period; and A third delay circuit, coupled to the replica circuit, is configured to delay the replica clock to generate the lagging clock. The delay locked loop device as claimed in claim 5, wherein: The first delay circuit has a first time constant, The second delay circuit has a second time constant, The third delay circuit has a third time constant, The second time constant is greater than the first time constant, and The third time constant is greater than the second time constant. The delay locked loop device as claimed in claim 6, wherein: The first delay circuit includes: a first capacitor, wherein the first time constant is determined by the capacitance value of the first capacitor, The second delay circuit includes: a second capacitor, wherein the second time constant is determined by the capacitance value of the second capacitor, and The third delay circuit includes: a third capacitor, wherein the third time constant is determined by the capacitance value of the third capacitor. The delay locked loop device as claimed in claim 7, wherein a first difference between the capacitance value of the second capacitor and the capacitance value of the first capacitor and a capacitance value of the third capacitor and the second capacitor A second difference between the capacitance values is used to determine the update sensitivity of the phase detector. The delay locked loop device as claimed in claim 1, wherein the phase detector includes: a first phase difference determiner, coupled to the delay controller, configured to obtain the translation phase difference based on the rising edge of the replica clock and the rising edge of the input clock; a second phase difference determiner configured to provide a first error signal based on the leading clock when the rising edge of the leading clock lags behind the rising edge of the input clock; a third phase difference determiner configured to provide a second error signal based on the lagging clock when the rising edge of the lagging clock leads the rising edge of the input clock; and An update trigger signal generator coupled to the second phase difference determiner, the third phase difference determiner and the delay controller, configured to provide the update based on the first error signal and the second error signal Trigger signal. The delay locked loop device as claimed in claim 9, wherein the update trigger signal generator includes: A logic circuit configured to respond to one of the first error signal and the second error signal to output the update trigger signal. The delay locked loop device as claimed in claim 10, wherein: When the rising edge of the leading clock is determined to lag behind the rising edge of the input clock, the first error signal is equal to the leading clock, and When the rising edge of the lagging clock is determined to be ahead of the rising edge of the input clock, the second error signal is equal to the lagging clock. The delay locked loop device as claimed in claim 9, wherein the update trigger signal generator includes: A first counter, coupled to the second phase difference judger, configured to count the number of occurrences of the first error signal to generate a first count value, and when the first count value reaches a first predetermined When setting, provide a first trigger signal; A second counter, coupled to the third phase difference judger, configured to count the number of occurrences of the second error signal to generate a second count value, and when the second count value reaches a second predetermined When setting, provide the second trigger signal; and A logic circuit, coupled to the first counter, the second counter and the delay controller, is configured to output the update trigger signal according to one of the first trigger signal and the second trigger signal. The delay locked loop device as described in claim 1 also includes: A timer circuit configured to control the internal clock generator to generate the leading clock and the lagging clock based on an operating cycle.

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