TW202337013A - Semiconductor structure - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 102
- 230000002093 peripheral effect Effects 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000004020 conductor Substances 0.000 claims description 58
- 229920005591 polysilicon Polymers 0.000 claims description 22
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 29
- 238000000034 method Methods 0.000 description 16
- 239000000463 material Substances 0.000 description 10
- 238000003860 storage Methods 0.000 description 9
- 238000000151 deposition Methods 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 7
- 239000003989 dielectric material Substances 0.000 description 6
- 238000001039 wet etching Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000000460 chlorine Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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Abstract
Description
本揭露是關於一種半導體結構。The present disclosure relates to a semiconductor structure.
近年來,半導體裝置的結構不斷改變,且半導體裝置的儲存容量不斷增加。記憶體裝置被應用於許多產品(例如數位相機、手機及電腦等)的儲存元件中。隨著這些應用的增加,記憶體裝置的需求集中在小尺寸與大儲存容量上。為了滿足此條件,需要具有高元件密度與小尺寸的記憶體裝置及其製造方法。In recent years, the structure of semiconductor devices has been continuously changed, and the storage capacity of semiconductor devices has been continuously increased. Memory devices are used in storage components of many products, such as digital cameras, mobile phones, and computers. As these applications increase, the demand for memory devices focuses on small size and large storage capacity. In order to meet this condition, memory devices with high device density and small size and manufacturing methods thereof are required.
因此,期望開發出具有更多數量之多個堆疊平面的三維(three-dimensional,3D)記憶體裝置,以達到更大的儲存容量、改善品質並同時保持記憶體裝置的小尺寸。Therefore, it is desirable to develop three-dimensional (3D) memory devices with a larger number of stacking planes to achieve greater storage capacity and improve quality while maintaining a small size of the memory device.
根據本揭露的一實施方式,提供一種半導體結構,包含具有相鄰的陣列區與周邊區的基板、階梯狀地設置在周邊區上的複數個堆疊,其中各堆疊包含絕緣層以及設置在絕緣層上的導體層。半導體結構更包含分別設置在導體層上的多晶矽層、分別設置於多晶矽層上的氧化物層、設置在堆疊、多晶矽層與氧化物層上的介電層,以及多個接觸柱。位在導體層中的同一層上的絕緣層與多晶矽層之間相隔一距離。接觸柱分別穿過介電層與氧化物層,以與對應的多晶矽層連接。According to an embodiment of the present disclosure, a semiconductor structure is provided, including a substrate having adjacent array regions and peripheral regions, and a plurality of stacks disposed on the peripheral regions in a stepped manner, wherein each stack includes an insulating layer and is disposed on the insulating layer. conductor layer on. The semiconductor structure further includes a polysilicon layer respectively disposed on the conductor layer, an oxide layer respectively disposed on the polysilicon layer, a dielectric layer disposed on the stack, the polysilicon layer and the oxide layer, and a plurality of contact pillars. The insulating layer and the polycrystalline silicon layer located on the same layer in the conductor layer are separated by a distance. The contact pillars pass through the dielectric layer and the oxide layer respectively to connect with the corresponding polycrystalline silicon layer.
在一些實施例中,多晶矽層為經摻雜的多晶矽。In some embodiments, the polycrystalline silicon layer is doped polycrystalline silicon.
在一些實施例中,位在導體層的同一層上的絕緣層與多晶矽層之間由介電層所隔開。In some embodiments, the insulating layer and the polysilicon layer on the same layer as the conductor layer are separated by a dielectric layer.
在一些實施例中,多晶矽層由對應的氧化物層內縮。In some embodiments, the polysilicon layer is set back from the corresponding oxide layer.
在一些實施例中,氧化物層由對應的導體層橫向凸出。In some embodiments, the oxide layer protrudes laterally from the corresponding conductor layer.
在一些實施例中,對應的絕緣層與多晶矽層之間的距離約為10nm至70nm。In some embodiments, the distance between the corresponding insulating layer and the polysilicon layer is approximately 10 nm to 70 nm.
在一些實施例中,氧化物層的厚度約為50Å至175Å。In some embodiments, the oxide layer has a thickness of approximately 50Å to 175Å.
在一些實施例中,多晶矽層的厚度約為10nm至70nm。In some embodiments, the polycrystalline silicon layer has a thickness of approximately 10 nm to 70 nm.
在一些實施例中,接觸柱更分別穿過多晶矽層,以與對應的導體層連接。In some embodiments, the contact pillars further pass through the polysilicon layer to connect with the corresponding conductor layer.
在一些實施例中,堆疊更延伸進入陣列區,使導體層作為記憶體單元的閘極結構。In some embodiments, the stack further extends into the array area, allowing the conductor layer to serve as a gate structure for the memory cell.
本揭露的一些實施方式所提供的半導體結構透過在階梯狀的導體層的表面上設置多晶矽層,以讓接觸通孔所對應的導體層處被多晶矽層所保護,如此一來,便可以解決因導體層厚度太薄且不同位置的接觸通孔的蝕刻深度差異過大而導致的開孔失敗的問題。The semiconductor structure provided by some embodiments of the present disclosure disposes a polycrystalline silicon layer on the surface of the stepped conductor layer, so that the conductor layer corresponding to the contact via hole is protected by the polycrystalline silicon layer. In this way, the problem can be solved. The problem of hole opening failure is caused by the thickness of the conductor layer being too thin and the etching depth of the contact via holes at different locations being too different.
以下將以圖式及詳細說明清楚說明本揭露之精神,任何所屬技術領域中具有通常知識者在瞭解本揭露之較佳實施例後,當可由本揭露所教示之技術,加以改變及修飾,其並不脫離本揭露之精神與範圍。The spirit of the present disclosure will be clearly explained in the following drawings and detailed descriptions. Anyone with ordinary knowledge in the art, after understanding the preferred embodiments of the present disclosure, can make changes and modifications based on the techniques taught in the present disclosure. It does not depart from the spirit and scope of this disclosure.
參照第1圖,其為本揭露的半導體結構的一實施例的剖面圖。半導體結構100包含基板110、堆疊在基板110上的複數個絕緣層120及複數個導體層130、穿過絕緣層120與導體層130的多個記憶體單元140,以及多個接觸柱150。絕緣層120與導體層130為交替地堆疊設置在基板110上。Referring to FIG. 1 , which is a cross-sectional view of an embodiment of the semiconductor structure of the present disclosure. The semiconductor structure 100 includes a substrate 110 , a plurality of insulating layers 120 and a plurality of conductor layers 130 stacked on the substrate 110 , a plurality of memory cells 140 passing through the insulating layers 120 and the conductor layers 130 , and a plurality of contact pillars 150 . The insulating layer 120 and the conductor layer 130 are alternately stacked on the substrate 110 .
基板110具有相鄰的陣列區112(array region)與周邊區114(peripheral region),其中每一個導體層130具有相連的第一區段132及第二區段134,第一區段132設置在陣列區112上,且第二區段134設置在周邊區114上。換句話說,每個導體層130延伸通過陣列區112及周邊區114。此外,每一個導體層130中的第一區段132的長度L1可相同,且每一個導體層130中第二區段134的長度L2可相異。舉例來說,第二區段134的長度L2可由最底部的導體層130的第二區段134至最頂部的導體層130的第二區段134逐漸減小,使得位於周邊區114上之導體層130的第二區段134為階梯狀配置。絕緣層120為配置在導體層130之間,也因此,位於周邊區114上的絕緣層120為同樣的階梯狀配置。介電層220則覆蓋在絕緣層120與導體層130上。The substrate 110 has adjacent array regions 112 and peripheral regions 114. Each conductor layer 130 has a connected first section 132 and a second section 134. The first section 132 is disposed on on the array area 112 , and the second section 134 is disposed on the peripheral area 114 . In other words, each conductor layer 130 extends through the array region 112 and the peripheral region 114 . In addition, the length L1 of the first section 132 in each conductor layer 130 may be the same, and the length L2 of the second section 134 in each conductor layer 130 may be different. For example, the length L2 of the second section 134 may gradually decrease from the second section 134 of the bottommost conductor layer 130 to the second section 134 of the topmost conductor layer 130 such that the conductor located on the peripheral area 114 The second section 134 of the layer 130 is configured in a stepped manner. The insulating layer 120 is disposed between the conductor layers 130. Therefore, the insulating layer 120 located on the peripheral area 114 is disposed in the same stepped manner. The dielectric layer 220 covers the insulating layer 120 and the conductive layer 130 .
記憶體單元140為穿過介電層220設置的垂直式的記憶體單元,導體層130則是圍繞於記憶體單元140設置,以作為記憶體單元140的閘極結構,又稱字元線(word line,WL)。在一些實施例中,記憶體單元140包含有ONO儲存層、通道層等結構。The memory unit 140 is a vertical memory unit disposed through the dielectric layer 220. The conductor layer 130 is disposed around the memory unit 140 as a gate structure of the memory unit 140, also known as a word line ( word line, WL). In some embodiments, the memory unit 140 includes an ONO storage layer, a channel layer and other structures.
在一些實施例中,設置在陣列區112的記憶體單元140為穿過絕緣層120與導體層130而後與基板110中對應的訊號線,例如對應的源極線電性連接,而設置在周邊區114的記憶體單元140則是穿過絕緣層120與導體層130,但是與基板110絕緣。換言之,設置在周邊區114的記憶體單元140可以視為虛設(dummy)的記憶體單元,其作用在於平衡製程中的負載(loading)。在一些實施例中,在陣列區112的記憶體單元140的分布密度大於在周邊區114的記憶體單元140的分布密度。In some embodiments, the memory unit 140 disposed in the array area 112 passes through the insulating layer 120 and the conductor layer 130 and is electrically connected to the corresponding signal line in the substrate 110, such as the corresponding source line, and is disposed in the periphery. The memory unit 140 in the region 114 passes through the insulating layer 120 and the conductive layer 130 but is insulated from the substrate 110 . In other words, the memory unit 140 disposed in the peripheral area 114 can be regarded as a dummy memory unit, whose role is to balance the load in the process. In some embodiments, the distribution density of the memory cells 140 in the array area 112 is greater than the distribution density of the memory cells 140 in the peripheral area 114 .
由於在周邊區114中,導體層130的第二區段134為階梯狀配置,因此周邊區114中的每一個記憶體單元140可穿過不同數量的導體層130。詳細來說,較靠近陣列區112的記憶體單元140可穿過較多的導體層130,而較遠離陣列區112的記憶體單元140可穿過較少的導體層130。Since the second section 134 of the conductor layer 130 in the peripheral area 114 is configured in a stepped manner, each memory unit 140 in the peripheral area 114 can pass through a different number of conductor layers 130 . Specifically, the memory cells 140 closer to the array area 112 can pass through more conductor layers 130 , while the memory cells 140 farther away from the array area 112 can pass through fewer conductor layers 130 .
接觸柱150設置在周邊區114上,穿過介電層220且接觸導體層130其中一者的第二區段134。換言之,當導體層130作為字元線的時候,接觸柱150作為字元線接觸(word line contact)使用。Contact posts 150 are disposed on the peripheral region 114 , passing through the dielectric layer 220 and contacting the second section 134 of one of the conductor layers 130 . In other words, when the conductor layer 130 serves as a word line, the contact pillar 150 serves as a word line contact.
而隨著記憶體密度越來越高,絕緣層120與導體層130的疊層數量也越來越多,較靠近陣列區112的接觸柱150與較遠離陣列區112的接觸柱150之間的深度差也越來越大,因此,蝕刻介電層220製作接觸通孔的控制精度的難度也隨之提升。本揭露便提供了一種半導體結構,其進一步在階梯狀配置的導體層130的上表面設置有多晶矽層180,以在蝕刻接觸通孔時藉由多晶矽層180作為緩衝,藉以解決在階梯狀配置中因接觸通孔的蝕刻深度差過大,而導致開孔失敗的問題。As the memory density becomes higher and higher, the number of stacks of the insulating layer 120 and the conductor layer 130 is also increasing, and the gap between the contact pillars 150 closer to the array area 112 and the contact pillars 150 farther away from the array area 112 The depth difference is also getting larger and larger. Therefore, it is more difficult to control the accuracy of etching the dielectric layer 220 to produce contact vias. The present disclosure provides a semiconductor structure, which further provides a polycrystalline silicon layer 180 on the upper surface of the conductor layer 130 arranged in a stepped manner, so that the polycrystalline silicon layer 180 can be used as a buffer when etching contact vias, thereby solving the problem in the stepped configuration. The problem of hole opening failure due to the excessive difference in etching depth of contact via holes.
參照第2圖至第11圖,其為製作本揭露之半導體結構的一實施例,於不同製作階段的剖面圖。須注意的是,為了清楚表現本揭露的半導體結構的一實施例的特徵,第2圖至第11圖中僅繪示第1圖中的周邊區,並且省略了第1圖中的記憶體單元。Referring to FIGS. 2 to 11 , which are cross-sectional views at different manufacturing stages of an embodiment of the semiconductor structure of the present disclosure. It should be noted that in order to clearly express the characteristics of an embodiment of the semiconductor structure of the present disclosure, only the peripheral area in Figure 1 is shown in Figures 2 to 11, and the memory unit in Figure 1 is omitted. .
首先,在第2圖中,在基板110上形成交替堆疊的多個絕緣層120及多個犧牲層170至基板110上,其中最底層的絕緣層120設置於基板110上。絕緣層120的材料不同於犧牲層170的材料。舉例而言,絕緣層120的材料可由包含氧化矽或其他介電質的材料所製成,而犧牲層170可由包含氮化矽的材料所製成,但並不用以限制本揭露。在一些實施例中,犧牲層170的厚度可以相同或是相異,也就是說,每一個絕緣層120之間的距離可相同或是相異。犧牲層170的厚度可以相同或是相異於絕緣層120的厚度。舉例而言,在一些實施例中,絕緣層120的厚度約為10nm至50nm,犧牲層170的厚度約為10nm至70nm。First, in FIG. 2 , a plurality of alternately stacked insulating layers 120 and a plurality of sacrificial layers 170 are formed on the substrate 110 , in which the bottom insulating layer 120 is disposed on the substrate 110 . The material of the insulating layer 120 is different from the material of the sacrificial layer 170 . For example, the material of the insulating layer 120 may be made of materials including silicon oxide or other dielectrics, and the sacrificial layer 170 may be made of materials including silicon nitride, but this disclosure is not limited. In some embodiments, the thickness of the sacrificial layer 170 may be the same or different, that is, the distance between each insulating layer 120 may be the same or different. The thickness of the sacrificial layer 170 may be the same as or different from the thickness of the insulating layer 120 . For example, in some embodiments, the thickness of the insulating layer 120 is approximately 10 nm to 50 nm, and the thickness of the sacrificial layer 170 is approximately 10 nm to 70 nm.
在製作多個絕緣層120及多個犧牲層170的堆疊的時候,成對的絕緣層120與犧牲層170以不同的程度(例如,長度)被移除。舉例來說,以較大的程度移除絕緣層120的最頂層及犧牲層170的最頂層,並以較小的程度移除絕緣層120的最底層及犧牲層170的最底層,並且使得剩餘的絕緣層120及剩餘的犧牲層170形成階梯狀配置。更具體地說,成對的絕緣層120與犧牲層170是指犧牲層170在絕緣層120上的組合,且成對的絕緣層120與犧牲層170具有大致上相同的長度,而在較下層的成對的絕緣層120與犧牲層170會橫向地從較上層的成對的絕緣層120與犧牲層170凸出。一個較厚的絕緣層120設置在成對的絕緣層120及犧牲層170的多個堆疊的頂表面上。When fabricating a stack of multiple insulating layers 120 and multiple sacrificial layers 170 , the pairs of insulating layers 120 and sacrificial layers 170 are removed to different extents (eg, lengths). For example, remove the topmost layer of the insulating layer 120 and the topmost layer of the sacrificial layer 170 to a greater extent, and remove the bottommost layer of the insulating layer 120 and the bottommost layer of the sacrificial layer 170 to a smaller extent, and leave the remaining The insulating layer 120 and the remaining sacrificial layer 170 form a stepped configuration. More specifically, the paired insulating layer 120 and the sacrificial layer 170 refers to the combination of the sacrificial layer 170 on the insulating layer 120, and the paired insulating layer 120 and the sacrificial layer 170 have substantially the same length, and the lower layer The pair of insulating layer 120 and sacrificial layer 170 will laterally protrude from the upper pair of insulating layer 120 and sacrificial layer 170 . A thicker insulating layer 120 is disposed on the top surfaces of the stacks of pairs of insulating layers 120 and sacrificial layers 170 .
參閱第3圖,接著沉積多晶矽層180在前述的結構上,其中多晶矽層180為沉積在露出來的犧牲層170的上表面與側表面以及沉積在絕緣層120的側表面。在一些實施例中,多晶矽層180為未經摻雜的多晶矽材料。在一些實施例中,由於沉積的條件不同,多晶矽層180可能是共形地沉積在露出來的犧牲層170的上表面與側表面以及絕緣層120的側表面,亦即,多晶矽層180在犧牲層170的上表面的厚度t1與多晶矽層180在犧牲層170的側表面以及絕緣層120的側表面的厚度t2大致相同。或者,多晶矽層180可能是非共形地沉積在露出來的犧牲層170的上表面與側表面以及絕緣層120的側表面,亦即,多晶矽層180在犧牲層170的上表面的厚度t1可能會大於多晶矽層180在犧牲層170的側表面以及絕緣層120的側表面的厚度t2。Referring to FIG. 3 , a polycrystalline silicon layer 180 is then deposited on the aforementioned structure, wherein the polycrystalline silicon layer 180 is deposited on the upper surface and side surfaces of the exposed sacrificial layer 170 and on the side surfaces of the insulating layer 120 . In some embodiments, polycrystalline silicon layer 180 is undoped polycrystalline silicon material. In some embodiments, due to different deposition conditions, the polycrystalline silicon layer 180 may be conformally deposited on the exposed upper and side surfaces of the sacrificial layer 170 and the side surfaces of the insulating layer 120 , that is, the polycrystalline silicon layer 180 is deposited on the exposed sacrificial layer 170 . The thickness t1 of the upper surface of the layer 170 is substantially the same as the thickness t2 of the polycrystalline silicon layer 180 on the side surfaces of the sacrificial layer 170 and the side surfaces of the insulating layer 120 . Alternatively, the polycrystalline silicon layer 180 may be non-conformally deposited on the exposed upper and side surfaces of the sacrificial layer 170 and the side surfaces of the insulating layer 120 . That is, the thickness t1 of the polycrystalline silicon layer 180 on the upper surface of the sacrificial layer 170 may be It is greater than the thickness t2 of the polycrystalline silicon layer 180 on the side surface of the sacrificial layer 170 and the side surface of the insulating layer 120 .
參照第4圖,進行離子佈植,其中離子佈植為具有方向性的。具體而言,離子佈植的方向為垂直地從上而下進行,即離子佈植的方向大致平行於基板110的法線方向,而讓多晶矽層180的上表面的離子佈質濃度遠大於多晶矽層180的側表面的離子佈質濃度。在一些實施例中,多晶矽層180的側表面的離子佈質濃度極低,甚至可以視為未摻雜的多晶矽。在一些實施例中,離子佈植是N型的離子佈植,如砷或是磷的離子佈植。Referring to Figure 4, ion implantation is performed, wherein the ion implantation is directional. Specifically, the direction of ion implantation is vertical from top to bottom, that is, the direction of ion implantation is approximately parallel to the normal direction of the substrate 110, so that the ion density on the upper surface of the polycrystalline silicon layer 180 is much greater than that of the polycrystalline silicon. The ion texture concentration of the side surface of layer 180. In some embodiments, the ion texture concentration on the side surface of the polycrystalline silicon layer 180 is extremely low and can even be regarded as undoped polycrystalline silicon. In some embodiments, the ion implantation is an N-type ion implantation, such as arsenic or phosphorus ion implantation.
參照第5圖,接著進行氧化製程,以在多晶矽層180的表面上形成氧化物層190。由於多晶矽層180的表面的離子佈質濃度不同,形成氧化物的速率也隨之出現差異。舉例而言,多晶矽層180在N型的離子佈質濃度較高的地方,如多晶矽層180的上表面處,其形成氧化物的速率會明顯大於多晶矽層180在N型的離子佈質濃度較低的地方,如多晶矽層180的側表面處,而讓氧化物層190在多晶矽層180的上表面上的厚度t3明顯大於氧化物層190在多晶矽層180的側表面上的厚度t4。在一些實施例中,氧化物層190在多晶矽層180的上表面上的厚度t3約為氧化物層190在多晶矽層180的側表面上的厚度t4的兩倍至六倍。在一些實施例中,氧化物層190在多晶矽層180的上表面上的厚度t3約為100Å至200Å,氧化物層190在多晶矽層180的側表面上的厚度t4約為25Å至50Å。Referring to FIG. 5 , an oxidation process is then performed to form an oxide layer 190 on the surface of the polycrystalline silicon layer 180 . Due to the different concentration of ion texture on the surface of the polycrystalline silicon layer 180, the rate of oxide formation is also different. For example, where the polycrystalline silicon layer 180 has a higher N-type ion texture concentration, such as the upper surface of the polycrystalline silicon layer 180 , the rate of oxide formation will be significantly greater than where the N-type ion texture concentration of the polycrystalline silicon layer 180 is higher. The thickness t3 of the oxide layer 190 on the upper surface of the polycrystalline silicon layer 180 is significantly greater than the thickness t4 of the oxide layer 190 on the side surface of the polycrystalline silicon layer 180 . In some embodiments, the thickness t3 of the oxide layer 190 on the upper surface of the polysilicon layer 180 is about two to six times the thickness t4 of the oxide layer 190 on the side surfaces of the polysilicon layer 180 . In some embodiments, the thickness t3 of the oxide layer 190 on the upper surface of the polycrystalline silicon layer 180 is about 100 Å to 200 Å, and the thickness t4 of the oxide layer 190 on the side surfaces of the polycrystalline silicon layer 180 is about 25 Å to 50 Å.
參照第6圖,接著進行濕式蝕刻製程,包含將如第5圖所示的結構浸泡於蝕刻液中。由於濕式蝕刻為等向性的蝕刻,因此,可以在移除多晶矽層180的側表面上的氧化物層190之後,多晶矽層180的上表面上的氧化物層190變薄而仍然保留在多晶矽層180的上表面上。經薄化的氧化物層190在多晶矽層180的上表面上的厚度t3’約為50Å至175Å。Referring to Figure 6, a wet etching process is then performed, including immersing the structure shown in Figure 5 in an etching liquid. Since wet etching is isotropic etching, after the oxide layer 190 on the side surface of the polycrystalline silicon layer 180 is removed, the oxide layer 190 on the upper surface of the polycrystalline silicon layer 180 can be thinned while still remaining in the polycrystalline silicon layer. on the upper surface of layer 180. The thickness t3' of the thinned oxide layer 190 on the upper surface of the polycrystalline silicon layer 180 is approximately 50Å to 175Å.
在一些實施例中,濕式蝕刻製程所使用的蝕刻液可以為緩衝氧化物蝕刻液(buffered oxide etchant, BOE)或是稀釋的氫氟酸(dilute hydrofluoric acid, dHF)等對氧化物具有較高蝕刻速率的蝕刻液。In some embodiments, the etching liquid used in the wet etching process may be a buffered oxide etchant (BOE) or dilute hydrofluoric acid (dHF), which has a high affinity for oxides. Etching rate of etching solution.
更具體地說,在第6圖的結構中,多晶矽層180連續地覆蓋在呈階梯狀配置的絕緣層120與犧牲層170上,其中氧化物層190覆蓋在多晶矽層180的上表面上,而多晶矽層180的側表面從氧化物層190露出。More specifically, in the structure of FIG. 6 , the polycrystalline silicon layer 180 continuously covers the insulating layer 120 and the sacrificial layer 170 arranged in a ladder shape, wherein the oxide layer 190 covers the upper surface of the polycrystalline silicon layer 180 , and Side surfaces of the polycrystalline silicon layer 180 are exposed from the oxide layer 190 .
接著參照第7圖,進行另一蝕刻製程,以部分地移除多晶矽層180,此蝕刻製程中所選用的蝕刻劑為對多晶矽層180具有較快蝕刻速率,而對氧化物層190、絕緣層120以及犧牲層170具有較低蝕刻速率的蝕刻劑,使得在經過蝕刻製程之後,讓多晶矽層180相對於氧化物層190內縮且露出絕緣層120以及犧牲層170的側表面。Next, referring to FIG. 7 , another etching process is performed to partially remove the polycrystalline silicon layer 180 . The etchant selected in this etching process has a faster etching rate for the polycrystalline silicon layer 180 and has a faster etching rate for the oxide layer 190 and the insulating layer. 120 and the sacrificial layer 170 have an etchant with a lower etching rate, so that after the etching process, the polycrystalline silicon layer 180 is retracted relative to the oxide layer 190 and the side surfaces of the insulating layer 120 and the sacrificial layer 170 are exposed.
第7圖中的蝕刻製程較佳地為等向性蝕刻,其可以為濕式蝕刻或是乾式蝕刻。若是第7圖中的蝕刻製程為濕式蝕刻,則可以選用氢氧化四甲铵(tetramethylammonium hydroxide;TMAH)或是由NH 4OH、H 2O 2和H 2O之混合物所組成之標準潔淨1溶液(SC1溶液)作為蝕刻劑,將結構浸泡在蝕刻劑中進行蝕刻製程。若是第7圖中的蝕刻製程為乾式蝕刻,則可以選用含氯的氣體,如含有Cl 2、CCl 2F 2等化學氣體作為蝕刻劑,將含氯的氣體通入腔室中進行蝕刻反應。 The etching process in Figure 7 is preferably isotropic etching, which can be wet etching or dry etching. If the etching process in Figure 7 is wet etching, you can use tetramethylammonium hydroxide (TMAH) or standard clean 1 composed of a mixture of NH 4 OH, H 2 O 2 and H 2 O. The solution (SC1 solution) is used as an etchant, and the structure is immersed in the etchant to perform the etching process. If the etching process in Figure 7 is dry etching, you can use chlorine-containing gas, such as Cl 2 , CCl 2 F 2 and other chemical gases as the etchant, and pass the chlorine-containing gas into the chamber to perform the etching reaction.
由於第7圖中的蝕刻製程為等向性蝕刻,因此可以從未被氧化物層190所覆蓋的多晶矽層180的側表面開始進行蝕刻反應,接著繼續蝕刻多晶矽層180,直至絕緣層120以及犧牲層170的側表面露出為止。如前所述,由於多晶矽層180為經過具有方向性(垂直方向)的離子佈植,且多晶矽層180是從側表面開始被蝕刻,因此,所殘留的多晶矽層180可以視為經摻雜的多晶矽層。Since the etching process in FIG. 7 is isotropic etching, the etching reaction can start from the side surface of the polycrystalline silicon layer 180 that is not covered by the oxide layer 190, and then continue to etch the polycrystalline silicon layer 180 until the insulating layer 120 and the sacrificial layer 120. until the side surface of layer 170 is exposed. As mentioned above, since the polycrystalline silicon layer 180 is implanted with directional (vertical direction) ions, and the polycrystalline silicon layer 180 is etched from the side surface, the remaining polycrystalline silicon layer 180 can be regarded as doped. Polycrystalline silicon layer.
而在進行完蝕刻製程之後,在殘留的多晶矽層180的第一端180A與絕緣層120之間會形成空腔200,而在殘留的多晶矽層180的第二端180B處則具有內凹於氧化物層190的凹口210。換言之,殘留的多晶矽層180的第一端180A與第二端180B分別由多晶矽層180上方的氧化物層190內縮。After the etching process is completed, a cavity 200 will be formed between the first end 180A of the remaining polycrystalline silicon layer 180 and the insulating layer 120 , and a cavity 200 will be formed at the second end 180B of the remaining polycrystalline silicon layer 180 . Notch 210 of object layer 190 . In other words, the first end 180A and the second end 180B of the remaining polycrystalline silicon layer 180 are respectively retracted by the oxide layer 190 above the polycrystalline silicon layer 180 .
接著參照第8圖,形成介電層220填補第7圖的結構中的空腔200與凹口210,介電層220更沉積在絕緣層120以及犧牲層170的疊層上。在一些實施例中,介電層220的材料不同於犧牲層170的材料。舉例而言, 犧牲層170的材料可以為氮化物,而介電層220的材料可以為氧化物。Next, referring to FIG. 8 , a dielectric layer 220 is formed to fill the cavity 200 and the recess 210 in the structure of FIG. 7 , and the dielectric layer 220 is further deposited on the stack of the insulating layer 120 and the sacrificial layer 170 . In some embodiments, the material of dielectric layer 220 is different from the material of sacrificial layer 170 . For example, the sacrificial layer 170 may be made of nitride, and the dielectric layer 220 may be made of oxide.
在一些實施例中,沉積介電材料以形成介電層220的步驟包含先共形(conformal)沉積,如透過原子層沉積(atomic layer deposition,ALD)的方式沉積介電材料在第7圖的結構上,以填補第7圖中的空腔200與凹口210。在一些實施例中,共形地沉積約50Å至200Å的介電材料即可填補第7圖中的空腔200與凹口210。In some embodiments, the step of depositing dielectric material to form dielectric layer 220 includes first conformal deposition, such as depositing the dielectric material by atomic layer deposition (ALD) in FIG. 7 Structurally, to fill the cavity 200 and the notch 210 in Figure 7 . In some embodiments, conformally depositing approximately 50 Å to 200 Å of dielectric material can fill the cavity 200 and recess 210 in FIG. 7 .
而後,再使用共形或是非共形的沉積方式將介電材料沉積在絕緣層120以及犧牲層170的疊層上,接著進行平坦化製程,讓最上層的多晶矽層180被露出來,以及讓最上層的多晶矽層180的上表面與介電層220的上表面共平面。Then, the dielectric material is deposited on the stack of the insulating layer 120 and the sacrificial layer 170 using a conformal or non-conformal deposition method, and then a planarization process is performed to expose the uppermost polycrystalline silicon layer 180 and allow The upper surface of the uppermost polysilicon layer 180 is coplanar with the upper surface of the dielectric layer 220 .
在一些實施例中,雖然介電層220與氧化物層190的材料皆是氧化物,如二氧化矽,但是由於製程的差異,兩者仍在材料特性上有些許不同。舉例而言,由於氧化物層190是將多晶矽材料表面氧化得到,而介電層220是透過沉積的方式得到,因此,氧化物層190的密度會大於介電層220的密度。In some embodiments, although the materials of the dielectric layer 220 and the oxide layer 190 are both oxides, such as silicon dioxide, due to differences in manufacturing processes, they still have slightly different material properties. For example, since the oxide layer 190 is obtained by oxidizing the surface of polycrystalline silicon material, and the dielectric layer 220 is obtained by deposition, the density of the oxide layer 190 will be greater than the density of the dielectric layer 220 .
參照第9圖,移除第8圖中的最上層的多晶矽層180,接著再繼續沉積介電材料並再次進行平坦化,以增加介電層220的厚度,使其完全覆蓋底下的階梯狀的絕緣層120以及犧牲層170的疊層,其中最頂層的絕緣層120的上表面高於最頂層的氧化物層190的上表面。Referring to Figure 9, the uppermost polycrystalline silicon layer 180 in Figure 8 is removed, and then the dielectric material is continued to be deposited and planarized again to increase the thickness of the dielectric layer 220 so that it completely covers the underlying stepped layer. A stack of insulating layers 120 and sacrificial layers 170, wherein the upper surface of the topmost insulating layer 120 is higher than the upper surface of the topmost oxide layer 190.
參照第10圖,進行閘極替換製程,以將第9圖中的犧牲層170替換為導體層130,以作為記憶體單元的閘極結構。在一些實施例中,導體層130的材料包含氮化鈦或是鎢。在一些實施例中,多晶矽層180由氧化物層190內縮,而氧化物層190的兩端由多晶矽層180的兩端橫向凸出。在一些實施例中,氧化物層190橫向凸出於其所在的對應導體層130的側表面。Referring to FIG. 10 , a gate replacement process is performed to replace the sacrificial layer 170 in FIG. 9 with a conductor layer 130 as the gate structure of the memory cell. In some embodiments, the material of the conductor layer 130 includes titanium nitride or tungsten. In some embodiments, the polycrystalline silicon layer 180 is retracted from the oxide layer 190 , and both ends of the oxide layer 190 are laterally protruded from both ends of the polycrystalline silicon layer 180 . In some embodiments, the oxide layer 190 laterally protrudes from the side surface of the corresponding conductor layer 130 where it is located.
在一些實施例中,同層的絕緣層120與多晶矽層180,即位在同一導體層130上的絕緣層120與多晶矽層180之間是被介電層220所隔開,而位在同一導體層130上的絕緣層120與多晶矽層180之間的距離d約為10nm至70nm,多晶矽層180的厚度T約為10nm至70nm,氧化物層190的厚度t3’約為50Å至175Å。在一些實施例中,多晶矽層180的厚度T可以等於或是相異於絕緣層120的厚度,但是多晶矽層180的厚度T不得大於成對的絕緣層120與導體層130的厚度和。In some embodiments, the insulating layer 120 and the polysilicon layer 180 of the same layer, that is, the insulating layer 120 and the polysilicon layer 180 located on the same conductor layer 130 are separated by the dielectric layer 220 and are located on the same conductor layer. The distance d between the insulating layer 120 and the polycrystalline silicon layer 180 on 130 is about 10 nm to 70 nm, the thickness T of the polycrystalline silicon layer 180 is about 10 nm to 70 nm, and the thickness t3' of the oxide layer 190 is about 50 Å to 175 Å. In some embodiments, the thickness T of the polysilicon layer 180 may be equal to or different from the thickness of the insulating layer 120 , but the thickness T of the polysilicon layer 180 shall not be greater than the sum of the thicknesses of the paired insulating layer 120 and the conductor layer 130 .
參照第11圖,接著在第10圖的結構中形成多個接觸通孔,接著在接觸通孔中填入金屬作為接觸柱150,其中接觸柱150可以穿過氧化物層190而著陸在多晶矽層180上或是伸入多晶矽層180中而與多晶矽層180連接。由於多晶矽層180為經摻雜的,因此,接觸柱150可以透過多晶矽層180與對應的導體層130電性連接,以作為閘極結構的接觸柱。由於接觸通孔對應的導體層130處被多晶矽層180以及氧化物層190所保護住,因此,可以讓形成接觸通孔時的蝕刻步驟不至於直接打穿導體層130。Referring to Figure 11, a plurality of contact via holes are then formed in the structure of Figure 10, and then metal is filled into the contact via holes as contact pillars 150, wherein the contact pillars 150 can pass through the oxide layer 190 and land on the polycrystalline silicon layer. 180 or extends into the polycrystalline silicon layer 180 to be connected with the polycrystalline silicon layer 180 . Since the polysilicon layer 180 is doped, the contact pillars 150 can be electrically connected to the corresponding conductor layer 130 through the polysilicon layer 180 to serve as contact pillars of the gate structure. Since the conductor layer 130 corresponding to the contact via hole is protected by the polysilicon layer 180 and the oxide layer 190, the etching step when forming the contact via hole can not directly penetrate the conductor layer 130.
或者,如第12圖所示,在其他的一些實施例中,在形成如第10圖所示的結構之後,先進行第一次蝕刻,讓接觸通孔先穿過氧化物層190並停在多晶矽層180,接著再進行第二次蝕刻,讓接觸通孔可以進一步穿過多晶矽層180,並停在導體層130的表面或是伸入導體層130中,而後在接觸通孔中填入金屬作為接觸柱150,其中接觸柱150可以著陸在導體層130上或是伸入導體層130中,以作為閘極結構的接觸柱。由於形成接觸柱150的接觸通孔是經過兩次的蝕刻,因此更能有效地控制接觸通孔的蝕刻深度,有效避免因導體層130厚度太薄而難以將接觸柱150定位在導體層130上的問題。Or, as shown in Figure 12, in some other embodiments, after forming the structure as shown in Figure 10, the first etching is performed first, so that the contact via hole first passes through the oxide layer 190 and stops at The polycrystalline silicon layer 180 is then etched a second time, so that the contact via hole can further penetrate the polycrystalline silicon layer 180 and stop on the surface of the conductor layer 130 or extend into the conductor layer 130, and then fill the contact via hole with metal. As the contact pillar 150, the contact pillar 150 can land on the conductor layer 130 or extend into the conductor layer 130 to serve as a contact pillar of the gate structure. Since the contact via hole forming the contact post 150 is etched twice, the etching depth of the contact via hole can be more effectively controlled, effectively avoiding the difficulty in positioning the contact post 150 on the conductor layer 130 due to the thickness of the conductor layer 130 being too thin. problem.
本揭露的一些實施方式所提供的半導體結構透過在階梯狀的導體層的表面上設置多晶矽層,以讓接觸通孔所對應的導體層處被多晶矽層所保護,如此一來,便可以解決因導體層厚度太薄且不同位置的接觸通孔的蝕刻深度差異過大而導致的開孔失敗的問題。The semiconductor structure provided by some embodiments of the present disclosure disposes a polycrystalline silicon layer on the surface of the stepped conductor layer, so that the conductor layer corresponding to the contact via hole is protected by the polycrystalline silicon layer. In this way, the problem can be solved. The problem of hole opening failure is caused by the thickness of the conductor layer being too thin and the etching depth of the contact via holes at different locations being too different.
雖然本揭露已以實施例揭露如上,然其並非用以限定本揭露,任何熟習此技藝者,在不脫離本揭露之精神和範圍內,當可作各種之更動與潤飾,因此本揭露之保護範圍當視後附之申請專利範圍所界定者為準。Although the present disclosure has been disclosed above in terms of embodiments, they are not intended to limit the disclosure. Anyone skilled in the art can make various modifications and modifications without departing from the spirit and scope of the disclosure. Therefore, the protection of the disclosure is The scope shall be determined by the appended patent application scope.
100:半導體結構 110:基板 112:陣列區 114:周邊區 120:絕緣層 130:導體層 132:第一區段 134:第二區段 140:記憶體單元 150:接觸柱 170:犧牲層 180:多晶矽層 180A:第一端 180B:第二端 190:氧化物層 200:空腔 210:凹口 220:介電層 L1,L2:長度 t1,t2,t3,t3’,t4,T:厚度 d:距離 100:Semiconductor Structure 110:Substrate 112:Array area 114: Surrounding area 120:Insulation layer 130: Conductor layer 132:First section 134:Second section 140:Memory unit 150: Contact post 170:Sacrificial layer 180:Polycrystalline silicon layer 180A: first end 180B:Second end 190:Oxide layer 200:Cavity 210: Notch 220: Dielectric layer L1, L2: length t1,t2,t3,t3’,t4,T: Thickness d: distance
為讓本揭露之目的、特徵、優點與實施例能更明顯易懂,所附圖式之詳細說明如下: 第1圖為本揭露的半導體結構的一實施例的剖面圖。 第2圖至第11圖為製作本揭露之半導體結構的一實施例於不同製作階段的剖面圖。 第12圖為本揭露之半導體結構的另一實施例的剖面圖。 In order to make the purpose, features, advantages and embodiments of the present disclosure more obvious and understandable, the detailed description of the attached drawings is as follows: Figure 1 is a cross-sectional view of an embodiment of the semiconductor structure of the present disclosure. 2 to 11 are cross-sectional views of an embodiment of the disclosed semiconductor structure at different manufacturing stages. FIG. 12 is a cross-sectional view of another embodiment of the semiconductor structure of the present disclosure.
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無 Domestic storage information (please note in order of storage institution, date and number) without Overseas storage information (please note in order of storage country, institution, date, and number) without
110:基板 110:Substrate
114:周邊區 114: Surrounding area
120:絕緣層 120:Insulation layer
130:導體層 130: Conductor layer
150:接觸柱 150: Contact post
180:多晶矽層 180:Polycrystalline silicon layer
190:氧化物層 190:Oxide layer
220:介電層 220: Dielectric layer
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