TW202336959A - Method for manufacturing a semiconductor memory - Google Patents

Abstract

A method of manufacturing a semiconductor memory is provided. The method includes steps of forming a data storage device; forming a contact element electrically connected to the data storage device; and forming a data processing device over the data storage device and electrically connected to the contact element.

Description

Preparation method of semiconductor memory

This application claims priority to U.S. Patent Application Nos. 17/684,526 and 17/684,650 (that is, the priority date is "March 2, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a method of manufacturing a semiconductor memory. In particular, it relates to a method of manufacturing a semiconductor memory, which has a contact element between a data storage element and a data processing element.

As computer processing units (CPUs) and graphics processing units (GPUs) or other types of processing units become faster and more powerful, more data must be transferred between these computing units and the semiconductor memory. The requirements for how fast and how much data are available are becoming more and more stringent. Some requirements focus on increasing off-chip bandwidth. However, the ever-shrinking power constraints of these processing units have restricted their development.

The above description of "prior art" is only to provide background technology, and does not admit that the above description of "prior art" reveals the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and any description of the above "prior art" None should form any part of this case.

An embodiment of the present disclosure provides a semiconductor memory. The semiconductor memory includes a data storage element, a data processing element and a contact element. The data processing component is disposed on the data storage component. The contact element is disposed between the data storage element and the data processing element. The contact element electrically connects the data storage element and the data processing element.

An embodiment of the present disclosure provides a method for manufacturing a semiconductor memory, including forming a data storage element; forming a contact element to electrically connect to the data storage element; and forming a data processing element on the data storage element and electrically electrically connected to the contact element.

The semiconductor memory of the present disclosure includes the data storage element and the data processing element. The data processing element is disposed on the data storage element and is electrically connected to the data storage element through the contact element. The data processing element may receive or transmit multiple command signals, multiple bits from an external circuit (such as a semiconductor memory controller or a host device) before multiple signals are received through the data storage element. address signal or multiple data signals. The data storage component can transmit the data signals to the data processing component in response to the commands. The data processing device may be configured to process the data signals from the data storage device via, for example, multiplexing or other functions, and between the semiconductor memory (or the data storage device) and the external device Provides higher processing bandwidth. Therefore, bandwidth is increased without sacrificing low power performance.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

Specific language will now be used to describe the embodiments or examples of the present disclosure illustrated in the drawings. It should be understood that the scope of the present disclosure is not intended to be limited thereby. Any modifications or improvements to the described embodiments, as well as any further applications of the principles described in this document, are within the realm of ordinary skill in the art. Element numbers may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment apply to another embodiment even if they share the same element number.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, These elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, a "first element", "component", "region", "layer" or "section" discussed below may be referred to as a second device , component, region, layer or portion without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and/or "comprising" are used in this specification, these terms specify the stated features, integers, steps, operations, elements, and/or components. exists, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups of the above.

FIG. 1 is a block diagram illustrating a semiconductor memory 1 and a semiconductor memory controller 50 according to some embodiments of the present disclosure. The semiconductor memory controller 50 can be connected to the semiconductor memory 1 via a plurality of buses. The semiconductor memory controller 50 may be configured to control the semiconductor memory 1 . The semiconductor memory 1 may include a data storage device 10 and a data processing device 20 . The semiconductor memory 1 may be configured to receive multiple address signals, multiple data signals or multiple command signals from the semiconductor memory controller 50 . The semiconductor memory 1 may be configured to transmit the address signals and the data signals to the semiconductor memory controller 50 . Data storage element 10 may be configured to transmit one or more data signals to data processing signals 20 . Data storage component 10 may be configured to receive one or more data signals from data processing component 20 .

The data storage component 10 may include a plurality of memory banks BANK1~BANK4. Each memory bank may include a plurality of semiconductor memory cells, a plurality of sense amplifiers (or column buffers), a column decoder, a row decoder, and/or a plurality of input/output (I/O) buffers.

During a read operation, data processing element 20 may be configured to receive one or more address signals or one or more command signals from semiconductor memory controller 50 . The data processing element 20 may be configured to process the received signals via, for example, multiplexing, and then transmit the processed signals to the data storage element 10 . The column decoder and the row decoder can receive one or more processed signals (including the address signals), and the column decoder and the row decoder can determine a plurality of memory banks corresponding to the address signals. address. The column decoder can receive one or more processed signals (including the command signals) and open multiple word lines according to the memory bank addresses, and then the data on the same column number will pass through multiple bit lines. The element wire is transmitted to the sense amplifiers to determine whether the data is "0" or "1". Then, after multiplexing of the address signals in the column decoder, the determined data signals in the sense amplifiers may be transmitted to data processing element 20 . Data processing element 20 may be configured to process the data signals via, for example, multiplexing, and then transmit the processed data signals to semiconductor memory controller 50 . The data processing device 20 can increase the bandwidth between the semiconductor memory controller 50 and the semiconductor memory 1 .

During writing, data processing element 20 may be configured to receive one or more address signals, one or more data signals, and one or more command signals from semiconductor memory controller 50 . The data processing element 20 may be configured to process the received signals via, for example, multiplexing, and then transmit the processed signals to the data storage element 10 . The column decoder and the row decoder can receive one or more address signals, and the column decoder and the row decoder can determine a plurality of memory bank addresses corresponding to the corresponding address signals. The column decoder can receive one or more commands and open a plurality of word lines according to the memory bank addresses, and then a plurality of data signals will be transmitted from the data processing element 20 to the sense amplifiers to determine the Whether the data signal is "0" or "1". Then, the determined data signals are transmitted to corresponding data units via multiple bit lines and stored in the corresponding data units. The data processing unit 20 can increase the bandwidth between the semiconductor memory controller 50 and the semiconductor memory 1 .

The semiconductor memory 1 may include a dynamic random access semiconductor memory (DRAM). Semiconductor memory controller 50 may include a logic circuit. Semiconductor memory controller 50 may include a DRAM controller.

FIG. 2 is a schematic cross-sectional view illustrating a semiconductor memory 1 integrated in a semiconductor package 100 according to some embodiments of the present disclosure. The semiconductor package 100 may include a semiconductor memory 1, a semiconductor memory controller 50, an interposer 60, a packaging substrate 70 and an electronic component 80. Interposer 60 may be disposed on package substrate 70 . The interposer 60 may be mounted on the packaging substrate 70 via a plurality of connection elements 60b. Semiconductor memory controller 50 may be provided on interposer 60 . The semiconductor memory controller 50 may be mounted on the interposer 60 via a plurality of connection elements 50b. Electronic components 80 may be disposed on interposer 60 . The electronic component 80 can be mounted on the interposer 60 via a plurality of connecting components 60b. The interposer 60 may include a plurality of wiring layers 60w1 electrically connected to the connection elements 60b. The plurality of wiring layers 60w2 of the interposer 60 can electrically connect the semiconductor memory controller 50 (eg, a physical layer (PHY) thereof) to the packaging substrate 70 (eg, a physical layer (PHY) thereof). The interposer 60 may include a plurality of wiring layers 60w3 to electrically connect the semiconductor memory controller 50 to the electronic component 80 . The interposer 60 may include a plurality of wiring layers 60w3 to be electrically connected to the connection elements 60b. The wiring layers 60w3 of the interposer 60 can electrically connect the electronic component 80 to the packaging substrate 70. The packaging substrate 70 may include a plurality of connection elements 70b for mounting to an external support substrate or support plate.

Package substrate 70 may include a printed circuit board. The electronic component 80 may include a processing unit, such as a central processing unit (CPU), graphics processing unit (GPU), system on chip (SoC), or any processing unit suitable for artificial intelligence (AI) computing.

The semiconductor memory controller 50 may include a plurality of through silicon through holes (TSVs) 50t therein and electrically connected to the physical layer PHY of the semiconductor memory controller 50 .

The semiconductor memory 1 may be provided on the semiconductor memory controller 50 . The semiconductor memory 1 can be installed on the semiconductor memory controller 50 via a plurality of connection components 10b1. The semiconductor memory 1 may include a data storage element 10, a data processing element 20, a connection layer 20c, a capping layer 30 and a contact element 40. Data storage device 10 may include a stack of multiple data storage dies 10m. An upper data storage die 10m may be mounted on a lower data storage die 10m via a plurality of connecting elements 10b2. The number of data storage dies 10m may depend on the amount of data required by the electronic component 80. For example, the number of data storage dies 10m may be 4 or higher. Each data storage die 10m of the data storage device 10 can be electrically connected to the semiconductor memory controller 50 through a plurality of silicon through holes 10t, the connection components 10b2 and the connection components 10b1.

The cover layer 30 may be disposed between the data storage component 10 and the data processing component 20 . The data processing component 20 may be disposed on the cover layer 30 . The data processing component 20 may be disposed on the data storage component 10 .

Contact element 40 may extend through cover layer 30 . Contact element 40 may be surrounded by cover layer 30 . Contact element 40 may extend through data processing element 20 (eg, a dielectric layer 21 thereof). The contact element 40 may be surrounded by the dielectric layer 21 of the data processing element 20 . The connection layer 20c is provided on the data processing element 20. The connection layer 20c can electrically connect the contact element 40 and the data processing element 20 . The contact element 40 can electrically connect the data storage element 10 and the data processing element 20 .

FIG. 3 is an enlarged top view illustrating an area surrounded by box A in FIG. 2 according to some embodiments of the present disclosure. As shown in FIG. 3 , the data processing component 20 may overlap the data storage component 10 . The size of the data storage component 10 may be larger than the size of the data processing component 20 . Alternatively, the size of data storage element 10 may be smaller than the size of data processing element 20 . The data storage device 10 may have a surrounding area 10p surrounding the memory bank of the data storage device 10. The contact element 40 overlaps the surrounding area 10p of the data storage element 10. The surrounding area 10p may include a circuit layer electrically connected to one or more memory banks of the data storage device 10. The connection layer 20c may include various patterns for connecting the data storage element 10 (or the contact element 40) to the data processing element 20.

FIG. 4 is an enlarged cross-sectional schematic diagram illustrating a region along the cross-section line BB' in FIG. 3 according to some embodiments of the present disclosure. The detailed structure of the data storage element 10, the data processing element 20, the cover layer 30 and the contact element 40 is described in Figure 4.

Referring to FIG. 4, the data processing element 10 may include a unit area, a word line 110, a bit line 120, a capacitor 130, a wiring structure 140 and a contact pad 150, and the unit area has a substrate 10s.

In some embodiments, for example, the substrate 10s may include silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbide (SiGeC), gallium (Ga), arsenide Gallium (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP) or other Group IV-IV, Group III-V or Group II-VI semiconductor materials. In some other embodiments, the substrate 10s may include a layer of semiconductor, such as silicon/silicon germanium, silicon on insulator, or silicon germanium on insulator.

In some embodiments, one or more insulating structures 102 may be formed in substrate 10s. The isolation structure 102 may include a shallow trench isolation (STI) structure. In some embodiments, the insulating structure 102 may include an isolation material, such as silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (N ₂ OSi ₂ ), silicon oxynitride (N ₂ OSi ₂ ) or fluorosilicate. In some embodiments, insulating structure 102 may define one or more active regions 104 of substrate 10s.

In some embodiments, one or more doped regions 106 may be formed in an upper portion of the active region 104 of the substrate 10 s between the two insulating structures 102 . In some embodiments, the doped region 106 may be doped with an N-type dopant for forming an NMOSFET (N-channel metal oxide semiconductor field effect transistor), and the N-type dopant may be, for example, phosphorus (P). , arsenic (As) or antimony (Sb). In some other embodiments, the doped region 106 may be doped with a P-type dopant for forming a PMOSFET, and the P-type dopant may be boron (B) or indium (In).

In some embodiments, a transistor (eg, a switching transistor) Tr1 may be formed in the active region 104 of the substrate 10 s between the two insulating structures 102 . The doped region 106 may include a source junction or a drain junction of the transistor Tr1.

Word lines 110 may be surrounded by active areas 104 . A gate dielectric layer 112 may be disposed between the active region 104 and the word line 110 . Word line 110 may be surrounded by gate dielectric layer 112 . A buried isolation layer 116 may be disposed on the word line 110 . Buried isolation layer 116 may be surrounded by gate dielectric layer 112 . The word line 110 can be used as a gate terminal of the transistor Tr1. The source junction or drain junction in the doped region 106 may extend from the word line 110 to an upper surface 10s1 of the substrate 10s.

The gate dielectric layer 112 may be selected from at least one of the following: a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an oxide/nitride/oxide (ONO), or a high dielectric constant A dielectric film, the high dielectric constant dielectric film has a dielectric constant greater than that of the silicon oxide layer. The word lines 110 may include at least one material selected from the following: titanium, tantalum, tungsten, or combinations thereof. The buried isolation layer 116 may include at least a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof.

Bit lines 120 may be disposed on substrate 10s. The bit lines 120 may extend along a direction parallel to the surface 10s1 of the substrate 10s. The bit line 120 may be connected to the doped region 106 or the active region 104 of the substrate 10 s via a plurality of conductive contacts 124 . The conductive contacts 124 may be disposed between the bit lines 120 and the substrate 10s. The bit lines 120 may be separated from the substrate 10s by an isolation layer 122. The conductive contacts 124 may be surrounded by an isolation layer 122 . Bit line 120 may be covered by isolation layer 122 . The conductive contacts 124 can be electrically insulated from each other.

In some embodiments, one or more bit lines and one or more word lines (not shown) may be formed between two adjacent transistors (eg, transistor Tr1). Furthermore, each of the bit lines and the word lines may be electrically connected to a plug (such as a conductive plug 136 as shown in FIG. 4, discussed later).

Conductive contacts 124 may include polysilicon, metal, conductive metal nitride, or combinations thereof. The bit line 120 may include at least one selected from the group consisting of doped impurity semiconductors, metals, conductive metal nitrides, or metal silicides. For example, bit line 120 may include at least doped polysilicon, TiN, TiSiN, W, tungsten silicide, or combinations thereof. The isolation layer 122 may be an oxide layer, a nitride layer, or a combination thereof.

A plurality of buried contacts 126 may be formed on the isolation layer 122 . In a cross-section different from that of Figure 4, a plurality of buried contacts 126 may be connected to the active region 104 of the substrate 10s. The plurality of buried contacts 126 may include at least a doped semiconductor, a metal, a conductive metal nitride, or a combination thereof.

A plurality of capacitors 130 may be connected to a plurality of buried contacts 126 . The capacitors 130 may be covered by a dielectric layer 132 . The capacitors 130 may be connected to the active region 104 of the substrate 10s. In some embodiments, the capacitors 130 may have a cylindrical shape, and the bottoms of the capacitors 130 may be square or circular.

Each capacitor 130 may include a lower electrode 130b, an isolation layer 130i, and an upper electrode 130t. For example, a portion of the upper electrode 130t may be surrounded by the isolation layer 130i, and a portion of the upper electrode 130t may be surrounded by the lower electrode 130b. For example, a portion of the isolation layer 130i may be surrounded by the lower electrode 130b. A support element 130s can be disposed between a plurality of capacitors to prevent the capacitors from tilting toward each other. The plurality of capacitors 130 may be supported by the supporting elements 130s.

The lower electrode 130b may be electrically connected to a source junction or a drain junction of a corresponding transistor via the buried contact 126 . Therefore, each such lower electrode 130b can serve as a storage node of a storage capacitor of a semiconductor memory cell. Furthermore, in some embodiments, the upper electrode 130t may be a common electrode that may be electrically connected to a ground node within the semiconductor memory cell. In some embodiments, the upper electrode 130t may be electrically connected through other parts of the electrode material of the upper electrode 130t or through another conductive element.

In some embodiments, the lower electrode 130b and the upper electrode 130t may include doped polycrystalline silicon (poly-Si) or metal. In some embodiments, the isolation layer 130i and the support element 130s may each include tantalum pentoxide (Ta ₂ O ₅ ), aluminum oxide (Al ₂ O ₃ ), tantalum bismuth tantalum oxide, SrBi ₂ Ta ₂ O ₉ , SBT), barium strontium titanate oxide (BaSrTiO ₃ , BST), a dielectric material with a higher dielectric constant than silicon dioxide (SiO ₂ ), or a dielectric material with a dielectric constant of approximately A dielectric material with a dielectric constant of 4.0 or greater. In some embodiments, the isolation layer 130i may include a single layer or may include a stack of multiple layers.

The capacitors 130 (or the upper electrodes 130t) can be electrically connected to the wiring structure 140 through a plurality of contact plugs 134. The contact plugs 134 may be surrounded by the dielectric layer 132 . The contact plugs 134 may include at least one of: metal, conductive metal nitride, a metal semiconductor compound, and doped polysilicon.

Referring to FIG. 4 , a conductive plug 136 may extend through the dielectric layer 132 . Conductive plugs 136 may be disposed in dielectric layer 132 . Conductive plug 136 may be surrounded by dielectric layer 132 . The conductive plug 136 can electrically connect the bit line 120 and the wiring structure 140 . The conductive plug 136 may include at least one of: metal, conductive metal nitride, a metal semiconductor compound, and doped polysilicon.

The wiring structure 140 may be disposed in a dielectric layer 142 . The wiring structure 140 can electrically connect the upper electrodes 130t of the capacitors 130 to a ground node in the semiconductor memory 1 . The wiring structure 140 can electrically connect the bit lines 120 to the contact pads 150 .

The wiring structure 140 may include a multi-layer structure. For example, wiring structure 140 may include one or more conductive lines and one or more conductive vias for connecting the conductive lines.

The wiring structure 140 may include at least one material selected from the following: metal, conductive metal nitride, a metal semiconductor compound, and a doped semiconductor. The dielectric layer 142 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a glass, a polyimide (PI), or a combination thereof.

The contact pad 150 may be disposed on a surface 101 of the data storage device 10 . Contact pad 150 may have a portion disposed on surface 101 of data storage device 10 and another portion surrounded by dielectric layer 142 . The conductive pad 150 may be electrically connected to an uppermost conductor of the wiring structure 140 . The contact pad 150 may be covered by the capping layer 30 . Although a single contact pad 150 is depicted in FIG. 4 , more than one conductive pad may be provided on the data storage device 10 . In some embodiments, the contact pads may include at least aluminum or compounds thereof.

The cover layer 30 can cover the data storage device 10 so that the data storage device 10 can avoid contamination during the process of forming the data processing device 20 . The capping layer 30 may have a thickness sufficient to protect the data storage element 10 from contamination or particles generated in the formation of the data processing element 20 . The thickness of capping layer 30 may range from approximately 0.5 μm to approximately 3 μm.

Capping layer 30 may include silicon dioxide, glass, sapphire, metal oxide, polyimide, or the like. The capping layer 30 can be regarded as an oxide substrate of the data processing element 20 . For example, the cover layer 30 may include a multi-layer structure, but is not limited thereto. Each layer of the multilayer structure may include different materials, such as silicon dioxide, sapphire, metal oxides or polyimide. For example, an uppermost layer of the capping layer 30 may include aluminum oxide, a middle layer of the capping layer 30 may include polyimide, and a lowermost layer of the capping layer 30 may include glass.

Please refer to FIG. 4 again. The data processing element 20 may include a dielectric layer 21 and a transistor Tr2. The transistor Tr2 is surrounded by the dielectric layer 21. The transistor Tr2 may include an upper gate terminal 22, an upper gate dielectric layer 23, a channel region 24, a drain terminal 25, a source terminal 26, a lower gate terminal 27 and a lower gate dielectric layer. 28.

The dielectric layer 21 may be disposed on a surface 301 of the capping layer 30 . The lower gate terminal 27 may be disposed on the surface 301 of the capping layer 30 . The lower gate terminal 27 may be covered by the dielectric layer 21 . Lower gate dielectric layer 28 may be disposed between channel region 24 and lower gate terminal 27 . The lower gate terminal 27 may be disposed between the capping layer 30 and the upper gate terminal 22 .

Channel area 24 may be provided on lower gate terminal 27 . Channel area 24 may be covered by dielectric layer 21 . Channel area 24 may be disposed between upper gate terminal 22 and lower gate terminal 27 . Channel region 24 may include the following materials: indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), germanium, and the like.

Upper gate terminal 22 may be provided on channel area 24 . The upper gate dielectric layer 23 may be disposed between the upper gate terminal 22 and the channel region 24 . Drain terminal 25 may be provided on channel region 24 . Source terminal 26 may be provided on channel region 24 . The upper gate terminal 22 may be disposed between the drain terminal 25 and the source terminal 26 .

The transistor Tr2 may include one of the following: a silicon-on-insulator (SOI) transistor, an indium gallium zinc oxide (IGZO)-based transistor, a germanium-based (Ge-based) transistor, or an N-type CMOS pseudo transistor ( pseudotransistor). Furthermore, the material of capping layer 30 may vary depending on the type of transistor to be formed.

The transistor Tr2 can be turned on or off depending on the voltage applied to the upper gate terminal 22 . For example, when the voltage applied to the upper gate terminal 22 exceeds a critical voltage of the transistor Tr2, an accumulation layer will be formed in the channel region 24, and then between the drain terminal 25 and the source terminal 26. Multiple carriers may be transported through the accumulation layer in channel region 24 . In another example, when the voltage applied to the upper gate terminal 22 is lower than the critical value of the transistor Tr2, no accumulation layer is formed in the channel region 24, so that no carriers are allowed to be transferred through the channel region 24 . In some embodiments, the transistor Tr2 may be continuously turned on. For example, when upper gate terminal 22 is unbiased, an accumulation layer exists in channel region 24 . In other words, upper gate terminal 22 may apply a voltage that exceeds a turn-off threshold voltage to reverse the accumulation layer in channel region 24 .

The lower gate terminal 27 can be used to adjust the threshold voltage of the transistor Tr2. When a voltage is applied to the lower gate terminal 27, it may provide resistance or assist in the formation of the accumulation layer in the channel region 24. In other words, the lower gate terminal 27 can partially control the transistor Tr2.

The double gate structure (eg, upper gate terminal 22 and lower gate terminal 27) in transistor Tr2 provides suitable threshold voltage control and suitable thermal conductivity. Therefore, the transistor Tr2 can be used as an electrostatic discharge (ESD) protection component or a part of an ESD protection circuit.

Upper gate terminal 22 may have a thickness from about 30 nm to about 300 nm. The upper gate dielectric layer may have a thickness from about 5 nm to about 100 nm. Channel region 24 may have a thickness from approximately 100 nm +/- 50 nm. Lower gate terminal 27 may have a thickness from about 30 nm to about 300 nm. Lower gate dielectric layer 28 may have a thickness from about 5 nm to about 100 nm.

The upper gate terminal 22 and the lower gate terminal 27 may each include at least doped poly-Si or metal. Each of the dielectric layer 21 and the upper gate dielectric layer 22 may include at least silicon dioxide (such as HfLaO or TiO ₂ ), or other dielectric materials.

A plurality of connection layers 20c1, 20c2, 20c3, and 20c4 may be disposed on a surface 201 of the data processing element 20. The connection layer 20c1 is electrically connected to the upper gate terminal 22. A voltage can be applied to the upper gate terminal 22 via the connection layer 20c1. The connection layer 20c2 is electrically connected to the drain terminal 25. A voltage can be applied to the drain terminal 25 via the connection layer 20c2. The connection layer 20c3 is electrically connected to the source terminal 26. A voltage can be applied to the source terminal 26 via the connection layer 20c3. The connection layer 20c4 can be electrically connected to the lower gate terminal 27 through a conductive via 271. A voltage can be applied to the lower gate terminal 27 via the connection layer 20c4. In some embodiments, lower gate terminal 27 may include conductive via 271 .

Contact element 40 may include a contact plug 401 extending through cover layer 30 . Contact plug 401 may be surrounded by cover layer 30 . The contact plug 401 of the contact element 40 may be disposed between the data processing element 20 and the data storage element 10 . Contact element 40 may also include a contact plug 402 extending through dielectric layer 21 . The contact plug 401 and the contact plug 402 can be connected to each other. Contact element 40 may include at least one of the following: metal, conductive metal nitride, a metal-semiconductor compound, and doped polysilicon.

As shown in FIG. 4 , the contact element 40 has a first projected area A1 on the surface 101 of the data storage element 10 , and the data processing element 20 has a second projected area A2 on the surface 101 of the data storage element 10 .

The contact element 40 is electrically connected to the connection layer 20c1. The transistor Tr2 of the data processing element 20 can be electrically connected to the contact element 40 . Contact element 40 may be electrically connected to contact pad 150 . In some embodiments, one of the capacitors 130 of the data storage device 10 may be electrically connected to the contact element 40 . The contact element 40 can be electrically connected to the bit line 120 of the data storage element 10 . The bit line 120 of the data storage device 10 can be electrically connected to the transistor Tr2 of the data processing device 20 . In some embodiments, the upper gate terminal 22 of the upper gate terminal 22 of the data processing device 20 may be electrically connected to the bit line 120 of the data storage device 10 .

The data processing element 20 may include a programmable computing unit, which is composed of a plurality of transistors (including transistor Tr2). Each transistor has a structure similar to transistor Tr2. The programmable computing unit of the data processing device 20 can have a plurality of functions, for example, multiplexing, adding, multiplying, multiply-accumulating, multiplying-and- adding), storing (storing), moving (moving), copying (copying) but it is not limited to this.

The data processing component 20 may be configured to process multiple data signals, multiple address signals, and multiple command signals before receiving the signals via the data storage component 10 . Data processing device 20 may be configured to process data signals from data storage device 10 before the signals are transmitted to an external device (such as semiconductor memory controller 50 in FIG. 2 ). Data processing element 20 may be configured to process the data signals in accordance with instructions from one of the internal controllers or the external element (eg, semiconductor memory controller 50). Since the data processing device 20 can handle various functions as described above, it can increase the bandwidth between the semiconductor memory 1 and external devices (such as the semiconductor memory controller 50 ). Therefore, off-chip bandwidth can be reduced.

Furthermore, the process of forming the data processing device 20 can be compatible with the back-end-of-line (BEOL) process of the data storage device 10 . In other words, the materials of the BEOL layers of the data storage device 20 are not limited/acceptable by the apparatus in which the data processing device 20 is formed. As mentioned, the data processing element 20 may include a plurality of transistors with higher mobility, such as IGZO N-type transistors and Ge P-type transistors. Therefore, it provides the opportunity to optimize the performance and circuit area of the programmable computing unit of the data processing device 20 .

The process temperature for forming the data processing element 20 can be lower than approximately 400° C., which is harmless to the electronic properties of the data storage element 10 .

In the present disclosure, the semiconductor memory 1 includes a data storage element 10 and a data processing element 20, and the data processing element 20 is disposed on the data storage element 10 and is electrically connected to the data storage element 10 through the contact element 40. The conductive path between the data processing element 20 and the data storage element 10 is relatively short compared to the circuit in an external component. Latency in transmission between the semiconductor memory 1 and an external device can be improved. Furthermore, the size of the semiconductor memory 1 can be adapted to the packaging substrate 70 . Therefore, the wrapper can remain the same.

Figures 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, and 17 are schematic cross-sectional views illustrating some embodiments of the present disclosure. Multiple stages of semiconductor memory preparation method. In order to better understand various aspects of the present disclosure, at least some of the figures have been simplified. In some embodiments, the semiconductor memory 1 in FIG. 4 can be configured by corresponding to FIG. 5, FIG. 6, FIG. 7, FIG. 8, FIG. 9, FIG. 10, FIG. 11, FIG. 12, FIG. 13, Manufacturing is carried out through multiple steps in Figures 14, 15, 16, and 17.

Referring to FIG. 5 , a storage element 10 can be formed. A substrate 10s, a word line 110, a bit line 120, a plurality of capacitors 130, a wiring layer 140 and/or a contact pad 150 may be formed. Surface 101 of data storage element 10 may be exposed. Contact pad 150 may be exposed.

Referring to Figure 6, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), coating, etc. can be used. Capping layer 30 may be patterned and etched to form a contact hole 89 . Contact hole 89 may pass through a portion of capping layer 30 and expose a portion of contact pad 150 .

Referring to FIG. 7 , a conductive material can be formed in the contact hole 89 and the surface 301 of the capping layer 30 , and then chemical mechanical polishing (CMP) is performed to remove the conductive material on the surface 301 of the capping layer 30 . Therefore, a contact plug 401 is formed, and an upper surface 401s is exposed through the surface 301 of the cover layer 30 .

Referring to FIG. 8 , a conductive material 90 may be formed on the upper surface 401 s of the contact plug 401 and the surface 301 of the capping layer 30 by, for example, CVD, low pressure chemical vapor deposition (LPCVD) or electroplating. A photoresist layer 91 can be formed on the conductive material 90 and patterned by a photolithography process.

Referring to FIG. 9 , the conductive material 90 can be etched in a pattern of the photoresist layer 91 , and then the remaining portion of the photoresist layer 91 can be removed. Therefore, the lower gate terminal 27 and a conductive portion 410 are formed on the capping layer 30 .

Referring to FIG. 10 , a dielectric portion 211 can be formed by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), coating, etc. , and then formed on the surface 301 of the capping layer 30 through a CMP process to cover the conductive portion 410 and the lower gate terminal 27 .

Referring to Figure 11, a channel material 241 can be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), remote plasma CVD (RPCVD), or plasma enhanced CVD (PECVD). , coating, etc. to form on the dielectric portion 211 . The channel material 241 may include indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), germanium, and the like.

Furthermore, a photoresist layer 92 can be formed on the channel material 214 and patterned.

Referring to FIG. 12 , the channel material 241 can be etched through the pattern defined by the photoresist layer 92 , and then a channel region 24 can be formed in the dielectric portion 211 and a lower gate dielectric layer 28 can be defined between the channel region 24 and the lower gate dielectric layer 24 . between gate terminals 27. Channel area 24 may be on lower gate terminal 27.

Referring to FIG. 13 , a dielectric portion 212 may be formed on the dielectric portion 211 to cover the channel region 24 through a process similar to that of the dielectric portion 211 .

Referring to FIG. 14 , for example, a conductive via 411 can be formed through etching, deposition and CMP processes. The conductive via 411 may be formed on the conductive portion 410 or the lower gate terminal 27 .

Referring to FIG. 15 , the manufacturing technology of a conductive portion 412 and an upper gate terminal 22 may include a process similar to that of the conductive portion 410 . When the material of the upper gate terminal 22 is different from the conductive portion 412, the upper gate terminal 22 may be formed separately. An upper gate dielectric layer 23 is defined between channel region 24 and upper gate terminal 22 .

Referring to FIG. 16 , a dielectric portion 213 can be formed on the dielectric portion 212 through a process similar to that of the dielectric portion 211 to cover the conductive portion 412 and the upper gate terminal 22 , thereby forming a dielectric layer 21 .

Referring to FIG. 17 , a conductive via hole may be formed in the dielectric layer 21 to connect the conductive portion 412 . Accordingly, a contact plug 402 is formed in the dielectric layer 21 and connected to the contact plug 401 to form a contact element 40 extending through the dielectric layer 21 and the capping layer 30 . The contact element 40 can be electrically connected to the bit line 120 of the data storage element 10 . In some embodiments, contact element 40 may be electrically connected to capacitor 130 of data storage element 10 . In some embodiments, the contact elements 40 may be electrically connected to the word lines 110 of the data storage device 10 .

Furthermore, a plurality of conductive vias may be formed on the upper gate terminal 22 , the lower gate terminal 27 and the channel region 24 to form a transistor Tr2 of the data processing element 20 . The transistor Tr2 of the data processing element 20 can be electrically connected to the bit line 120 of the data storage element 10 via the contact element 40 . Therefore, a vertical electrical transmission path is formed between the data processing element 20 and the data storage element 10 .

After that, a plurality of connection layers (such as the connection layers 21c1, 21c2, 21c3 or 21c4 in FIG. 4) can be formed on the surface 201 of the data processing element 20, and the contact element 40 is connected to the transistor Tr2 of the data processing element 20 to The semiconductor memory 1 of FIG. 4 is formed.

Furthermore, the process temperatures of the steps in Figures 5 to 17 are lower than 400°C. The characteristics of the data storage device 10 are not affected by the thermal budget forming the data processing device 20 .

FIG. 18 is a schematic flowchart illustrating a method 200 for manufacturing a semiconductor memory according to some embodiments of the present disclosure.

The manufacturing method 200 begins with step S201, which includes forming a data storage element.

The manufacturing method 200 continues with step S203, which includes forming a capping layer on the data storage element.

The preparation method 200 continues with step S205, which includes forming a contact element. The contact element is electrically connected to the data storage element.

The manufacturing method 200 continues with step S207, which includes forming a data processing element on the data storage element. The data processing element is electrically connected to the contact element.

The preparation method 200 continues with step S209, which includes forming a continuous layer on a dielectric layer of the data processing element.

The preparation method 200 is only an example and is not intended to limit the present disclosure beyond the scope explicitly stated in the patent application. Additional steps may be provided before, during, or after each step of the preparation method 200, and some of the steps described may be replaced, eliminated, or moved for additional embodiments of the preparation method. In some embodiments, the preparation method 200 may also include multiple steps not depicted in FIG. 18 . In some embodiments, preparation method 200 may include one or more of the steps described in Figure 18.

An embodiment of the present disclosure provides a semiconductor memory. The semiconductor memory includes a data storage element, a data processing element and a contact element. The data processing component is disposed on the data storage component. The contact element is disposed between the data storage element and the data processing element. The contact element electrically connects the data storage element and the data processing element.

An embodiment of the present disclosure provides a method for manufacturing a semiconductor memory, including forming a data storage element; forming a contact element to electrically connect to the data storage element; and forming a data processing element on the data storage element and electrically electrically connected to the contact element.

The semiconductor memory of the present disclosure includes the data storage element and the data processing element. The data processing element is disposed on the data storage element and is electrically connected to the data storage element through the contact element. The data processing element may receive or transmit multiple command signals, multiple bits from an external circuit (such as a semiconductor memory controller or a host device) before multiple signals are received through the data storage element. address signal or multiple data signals. The data storage component can transmit the data signals to the data processing component in response to the commands. The data processing device may be configured to process the data signals from the data storage device via, for example, multiplexing or other functions, and between the semiconductor memory (or the data storage device) and the external device Provides higher processing bandwidth. Therefore, bandwidth is increased without sacrificing low power performance.

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the claimed claims. For example, many of the processes described above may be implemented in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, etc. that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patentable scope of this application.

1: Semiconductor memory 10: Data storage component 10b1: Connecting components 10b2: Connecting components 10m: data storage die 10p:surrounding area 10s: base 10s1: Upper surface 10t: Silicon perforation 20:Data processing components 20c: Connection layer 20c1~20c4: connection layer 21: Dielectric layer 22: Upper gate terminal 23: Upper gate dielectric layer 24: Passage area 25:Drain terminal 26: Source terminal 27:Lower gate terminal 28: Lower gate dielectric layer 30:Cover layer 40:Contact components 50:Semiconductor memory controller 50b: Connecting elements 50t: Silicon perforation 60: Inserter 60b: Connecting elements 60w1: Wiring layer 60w2: Wiring layer 60w3: Wiring layer 70:Packaging substrate 70b: Connecting elements 80: Electronic components 89:Contact hole 90: Conductive materials 91: Photoresist layer 92: Photoresist layer 100:Semiconductor packaging 101:Surface 102:Insulation structure 104:Active zone 106: Doped area 110:Character line 112: Gate dielectric layer 116: Buried isolation layer 120:Bit line 122:Isolation layer 124:Conductive contact point 126: Buried Contact Points 130:Capacitor 130b: Lower electrode 130i: Isolation layer 130s: Support elements 130t: Upper electrode 132:Dielectric layer 134: Contact plug 136:Conductive plug 140: Wiring structure 142:Dielectric layer 150:Contact pad 200:Preparation method 201: Surface 211:Dielectric Department 212:Dielectric Department 213:Dielectric Department 241: Channel material 271:Conductive via 301: Surface 401: Contact plug 401s: upper surface 402: Contact plug 410: Conductive Department 411:Conductive via 412: Conductive Department A1: First projection area A2: Second projection area BANK1~BANK4: memory bank PHY: physical layer S201: Steps S203: Step S205: Step S207: Step S209: Step Tr1: transistor Tr2: Transistor

A more complete understanding of the present disclosure can be obtained by referring to the detailed description and claimed claims. The present disclosure should also be understood to be associated with the drawing element numbering, which represents similar elements throughout the description. FIG. 1 is a block diagram illustrating a semiconductor memory and a semiconductor memory controller according to some embodiments of the present disclosure. FIG. 2 is a schematic cross-sectional view illustrating a semiconductor memory integrated in a semiconductor package according to some embodiments of the present disclosure. FIG. 3 is an enlarged top view illustrating an area surrounded by box A in FIG. 2 according to some embodiments of the present disclosure. FIG. 4 is an enlarged cross-sectional schematic diagram illustrating a region along the cross-section line BB' in FIG. 3 according to some embodiments of the present disclosure. FIG. 5 is a schematic cross-sectional view illustrating one or more stages of a method of manufacturing a semiconductor memory according to some embodiments of the present disclosure. FIG. 6 is a schematic cross-sectional view illustrating one or more stages of a method of manufacturing a semiconductor memory according to some embodiments of the present disclosure. FIG. 7 is a schematic cross-sectional view illustrating one or more stages of a method of manufacturing a semiconductor memory according to some embodiments of the present disclosure. FIG. 8 is a schematic cross-sectional view illustrating one or more stages of a method of manufacturing a semiconductor memory according to some embodiments of the present disclosure. FIG. 9 is a schematic cross-sectional view illustrating one or more stages of a method of manufacturing a semiconductor memory according to some embodiments of the present disclosure. FIG. 10 is a schematic cross-sectional view illustrating one or more stages of a method of manufacturing a semiconductor memory according to some embodiments of the present disclosure. FIG. 11 is a schematic cross-sectional view illustrating one or more stages of a method of manufacturing a semiconductor memory according to some embodiments of the present disclosure. FIG. 12 is a schematic cross-sectional view illustrating one or more stages of a method of manufacturing a semiconductor memory according to some embodiments of the present disclosure. 13 is a schematic cross-sectional view illustrating one or more stages of a method of manufacturing a semiconductor memory according to some embodiments of the present disclosure. 14 is a schematic cross-sectional view illustrating one or more stages of a method of manufacturing a semiconductor memory according to some embodiments of the present disclosure. FIG. 15 is a schematic cross-sectional view illustrating one or more stages of a method of manufacturing a semiconductor memory according to some embodiments of the present disclosure. FIG. 16 is a schematic cross-sectional view illustrating one or more stages of a method of manufacturing a semiconductor memory according to some embodiments of the present disclosure. 17 is a schematic cross-sectional view illustrating one or more stages of a method of manufacturing a semiconductor memory according to some embodiments of the present disclosure. FIG. 18 is a schematic flowchart illustrating a method of manufacturing a semiconductor memory according to some embodiments of the present disclosure.

1: Semiconductor memory

10: Data storage component

10b1: Connecting components

10b2: Connecting elements

10m: data storage die

10t: Silicon perforation

20:Data processing components

20c: Connection layer

21: Dielectric layer

30:Cover layer

40:Contact components

50:Semiconductor memory controller

50b: Connecting elements

50t: Silicon perforation

60: Inserter

60b: Connecting components

60w1: Wiring layer

60w2: Wiring layer

60w3: Wiring layer

70:Packaging substrate

70b: Connecting elements

80: Electronic components

100:Semiconductor packaging

PHY: physical layer

Claims (20)

A method for preparing a semiconductor memory, including: forming a data storage element; forming a contact element to electrically connect to the data storage element; and A data processing element is formed on the data storage element and electrically connected to the contact element. The preparation method of claim 1, further comprising forming a cover layer on the data storage element, wherein the contact element extends through the cover layer. The preparation method of claim 2, further comprising forming a dielectric layer on the capping layer, wherein the contact element includes a second contact plug extending through the dielectric layer. The preparation method of claim 3 further includes forming a plurality of connection layers on the dielectric layer, wherein a first connection layer of the connection layers is electrically connected to the contact element. The preparation method of claim 2, wherein the cover layer includes silicon dioxide or sapphire. The preparation method of claim 1, wherein forming the data processing element is performed at a process temperature of less than 400°C. The preparation method of claim 6, wherein multiple characteristics of the data storage element are not affected by a thermal budget forming the data processing element. The preparation method of claim 5, wherein forming the data processing element includes forming a transistor to be electrically connected to a cell line of the data storage element. The preparation method of claim 8, wherein the transistor includes a first gate terminal and a second gate terminal, and the second gate terminal is disposed between the cover layer and the first gate of the transistor. Between the terminals, forming the data processing element includes forming a dielectric layer to cover the transistor. The preparation method of claim 9 further includes forming a connection layer on the dielectric layer of the data processing element to electrically connect the data processing element to the contact element. The preparation method of claim 1, wherein forming the data processing element includes forming an IGZO channel and a first gate terminal, and the first gate terminal is on the IGZP channel. The preparation method of claim 1, wherein the data processing element includes one of the following: a silicon-on-insulator (SOI) transistor, an indium gallium zinc oxide (IGZO)-based transistor, a germanium-based (Ge-based) ) transistor or an N-type CMOS pseudo transistor (pseudo transistor). The method of claim 1, wherein forming the data storage element includes forming a capacitor to be electrically connected to the contact element. The method of claim 13, wherein forming the data processing element includes forming a transistor to be electrically connected to the contact element. The preparation method of claim 8, wherein the transistor includes an indium gallium zinc oxide (IGZO) channel, and the indium gallium zinc oxide channel is disposed between the first gate terminal and the second gate terminal. The preparation method of claim 1, wherein the contact element includes a first projected area on a surface of the data storage element, and the data processing element has a second projected area on the surface of the data storage element. On the surface, the first projected area and the second projected area do not overlap. The preparation method of claim 1, wherein the data processing element overlaps the data storage element in a vertical direction, and the contact element overlaps the data storage element in a vertical direction. The preparation method of claim 1, wherein the data processing element includes one of the following: a silicon-on-insulator transistor, an indium gallium zinc oxide-based transistor, a germanium-based transistor, or an N-type CMOS pseudo-electric transistor. crystal. The preparation method of claim 1, wherein the data storage element includes a stack of a plurality of storage dies. The preparation method of claim 1, wherein a size of the data storage element is larger than a size of the data processing element, the data processing element includes an electrostatic discharge (ESD) protection circuit, and the data processing element includes a programmable calculation unit.