CN118019333A - Semiconductor memory and forming method thereof - Google Patents
Semiconductor memory and forming method thereof Download PDFInfo
- Publication number
- CN118019333A CN118019333A CN202410169256.9A CN202410169256A CN118019333A CN 118019333 A CN118019333 A CN 118019333A CN 202410169256 A CN202410169256 A CN 202410169256A CN 118019333 A CN118019333 A CN 118019333A
- Authority
- CN
- China
- Prior art keywords
- bit line
- forming
- semiconductor memory
- layer
- sacrificial mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 101
- 238000000034 method Methods 0.000 title claims abstract description 55
- 239000010410 layer Substances 0.000 claims abstract description 130
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 239000011229 interlayer Substances 0.000 claims abstract description 26
- 238000002955 isolation Methods 0.000 claims description 55
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 238000000231 atomic layer deposition Methods 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 125000006850 spacer group Chemical group 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 7
- 230000002093 peripheral effect Effects 0.000 claims description 7
- 229910021332 silicide Inorganic materials 0.000 claims description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910008484 TiSi Inorganic materials 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 238000011049 filling Methods 0.000 claims description 3
- 238000004151 rapid thermal annealing Methods 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 18
- 239000000463 material Substances 0.000 description 21
- 239000011810 insulating material Substances 0.000 description 9
- 238000003860 storage Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 229930195733 hydrocarbon Natural products 0.000 description 2
- 150000002430 hydrocarbons Chemical class 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000004215 Carbon black (E152) Chemical class 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- -1 oxide Chemical class 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present disclosure provides a semiconductor memory and a method of forming the same, which can reduce parasitic capacitance between bit lines and improve performance of the semiconductor memory. The method for forming the semiconductor memory comprises the following steps: providing a semiconductor substrate, and forming a plurality of bit line contact parts which are arranged at intervals in the semiconductor substrate; forming a plurality of bit lines on the semiconductor substrate, the plurality of bit lines being in contact with the plurality of bit line contacts, respectively; forming bit line interlayer at least covering the side wall of the bit line and forming air gap in the bit line interlayer; and a step of forming a cap layer to close the air gap.
Description
Technical Field
The present disclosure relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor memory and a method for forming the same.
Background
Semiconductor memories generally include a storage capacitor and a storage transistor connected to the storage capacitor. The storage capacitor is used to store charge representing stored information, and an active region, a drain region, and a gate electrode are formed in the storage transistor. Wherein the gate electrode is used for controlling current flow between the source region and the drain region and is connected to the word line, the source region is used for forming a bit line contact region so as to be connected to the bit line, and the drain region is used for forming a storage node contact region so as to be connected to the storage capacitor.
As the integration level increases in semiconductor fabrication processes, the pitch between bit lines becomes smaller and smaller. Therefore, parasitic capacitance is easily formed between bit lines, and as the parasitic capacitance increases, the effect on the performance of the semiconductor device increases, for example, the operation speed of the semiconductor device becomes slower, and the data refresh characteristic becomes worse.
For example, the RC delay time can be used to evaluate the delay of the transmission rate of an electrical signal of a semiconductor memory due to parasitic effects. The RC delay time satisfies the following formula:
TRC＝(ρ0·L1/tD)(kD/ε0)
Wherein ρ 0 is the line resistance of the metal;
l 1 length of metal;
k D dielectric constant of the insulating material;
epsilon 0 conductivity of the metal;
t D thickness of insulating material.
As the integration increases, the length of the wiring increases, and the thickness of the insulating material becomes thin, so that the RC delay time starts to become large according to the above equation.
Fig. 1 is a diagram illustrating a relationship between a feature size and a delay time of a semiconductor memory. As shown in fig. 1, in a design size in units of several mm, the signal transmission speed of the gate is more dominant than the RC delay effect caused by the wiring, and thus the RC delay caused by the wiring is not a great problem, but the RC delay effect caused by the wiring rapidly increases exponentially when entering an area of 1mm or less.
Thus, the RC delay effect dominates over a slight increase in the signal transmission rate of the gate, resulting in a severe delay in the signal processing speed.
Qualitatively examining the equation of the RC delay described above, an increase in wiring length and a decrease in insulating material thickness due to miniaturization are unavoidable, and thus, in order to reduce such delay, consideration of wiring materials such as replacement of wiring materials is unavoidable. In addition, it is also necessary to consider an insulating material to reduce parasitic capacitance.
According to the above formula, L 1/tD must be increased due to miniaturization, which is a negative effect of miniaturization. As a result of miniaturization, L 1 increases, T D decreases, and T RC increases. To compensate for this, adjustments are needed from the ε 0、kD aspect. However, epsilon 0、kD and the like are intrinsic values of materials, and thus replacement of materials is desired.
Disclosure of Invention
The present disclosure is directed to solving the above-mentioned problems, and an object of the present disclosure is to provide a semiconductor memory and a method for forming the same, which can reduce parasitic capacitance between bit lines and improve performance of the semiconductor memory.
The present disclosure provides a method of forming a semiconductor memory, comprising the steps of: providing a semiconductor substrate, and forming a plurality of bit line contact parts which are arranged at intervals in the semiconductor substrate; forming a plurality of bit lines on the semiconductor substrate, the plurality of bit lines being in contact with the plurality of bit line contacts, respectively; forming bit line interlayer at least covering the side wall of the bit line and forming air gap in the bit line interlayer; and a step of forming a cap layer to close the air gap.
Optionally, in the method for forming a semiconductor memory, forming a bit line interlayer at least covering sidewalls of the bit line and forming an air gap in the bit line interlayer includes: sequentially forming a first isolation layer and a sacrificial mask layer on the bit line and the semiconductor substrate; etching the sacrificial mask layer, and only reserving a part of the sacrificial mask layer on the side wall of the bit line; a step of forming a second isolation layer covering the top of the first isolation layer and the sacrificial mask layer by atomic layer deposition ALD; etching the top and bottom of the second isolation layer to expose the sacrificial mask layer; filling gaps between the bit lines by using spin-on glass SOG and performing planarization treatment; and etching the sacrificial mask layer to form an air gap.
Optionally, in the method for forming a semiconductor memory, the sacrificial mask layer is a spin-on hard mask SOH.
Optionally, in the method for forming a semiconductor memory, the step of forming the second isolation layer by atomic layer deposition ALD is performed at room temperature.
Optionally, in the method for forming a semiconductor memory, the sacrificial mask layer is silicon oxycarbide SiOC.
Optionally, in the method for forming a semiconductor memory, the method further includes a step of forming a salicide between the bit line and the bit line contact.
Optionally, in the method for forming a semiconductor memory, the step of forming a salicide between the bit line and the bit line contact includes: a step of ion implantation doping the polysilicon of the bit line contact portion when the bit line contact portion is formed; a step of depositing a metal layer of the peripheral gate; and performing rapid thermal annealing after ion implantation doping to enable the metal layer to react with the polysilicon so as to generate the self-aligned silicide.
Optionally, in the method for forming a semiconductor memory, the metal layer is TiN, and the salicide is TiSi.
The present disclosure also provides a semiconductor memory, including: a semiconductor substrate in which a plurality of bit line contacts are formed in a spaced arrangement; a plurality of bit lines formed over the semiconductor substrate and in contact with a plurality of the bit line contacts, respectively; bit line interlayer, the said bit line interlayer covers the sidewall of the said bit line at least, and there are air gaps in the said bit line interlayer; and a cap layer closing the air gap.
Optionally, in the semiconductor memory, a salicide is formed between the bit line and the bit line contact.
According to the semiconductor memory and the forming method thereof, the air gap is formed in the interlayer between the bit lines, and the air with low dielectric constant is used as the insulating material of the bit lines, so that parasitic capacitance between the bit lines can be reduced, and the performance of the semiconductor memory can be improved.
In addition, according to the semiconductor memory and the forming method thereof, the salicide is formed between the bit line and the bit line contact part, so that the contact resistance between the bit line and the bit line contact part can be reduced, the interference of the contact resistance and parasitic capacitance is restrained, and the performance of the semiconductor memory is improved.
Drawings
Fig. 1 is a diagram illustrating a relationship between a feature size and a delay time of a semiconductor memory.
Fig. 2 is a schematic diagram showing the structure of bit line-to-bit line spacers between bit lines of a semiconductor memory of the related art.
Fig. 3 is a flowchart of a method of forming a semiconductor memory according to an embodiment of the present disclosure.
Fig. 4 is a flowchart of a step of forming a bit line interlayer and forming an air gap within the bit line interlayer in a method of forming a semiconductor memory according to an embodiment of the present disclosure.
Fig. 5A to 5G are cross-sectional views illustrating when steps are performed in forming a semiconductor memory according to an embodiment of the present disclosure.
Fig. 6 is a flowchart of a step of forming a salicide between a bit line and a bit line contact in a method of forming a semiconductor memory according to an embodiment of the present disclosure.
Fig. 7 is a schematic view showing a structure in which salicide is formed between bit lines and bit line contacts in a semiconductor memory according to an embodiment of the present disclosure.
Detailed Description
The present disclosure now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the disclosure are shown. However, the present disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. The dimensions and relative dimensions of layers and regions may be exaggerated in the figures for clarity.
Unless defined otherwise, technical or scientific terms used in the claims and specification should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like in the description and in the claims, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, is intended to mean that elements or items that are immediately preceding the word "comprising" or "comprising", are included in the word "comprising" or "comprising", and equivalents thereof, without excluding other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, nor to direct or indirect connections.
In this disclosure, spatially relative terms, such as "under," "below," "lower," "above," "upper," and the like, are used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "under" or "beneath" other elements or features would then be oriented "over" the other elements or features.
Embodiments of the present disclosure are described herein with reference to cross-sectional and top-view illustrations that are schematic illustrations of idealized embodiments of the present disclosure. Thus, embodiments of the present disclosure should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing processes. An etched area, for example shown as a rectangle, will typically have rounded or curved characteristics. Accordingly, the regions illustrated in the figures are schematic in nature and are not intended to limit the scope of the present disclosure.
Unless otherwise defined, terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. The terms are to be understood to have meanings consistent with the context of the relevant art and are not to be construed as idealized or overly formal unless expressly so defined herein.
The semiconductor memory to which the present disclosure relates may be a DRAM device, a volatile memory device of an SRAM device, or a nonvolatile memory device such as a Flash device, a PRAM device, an MRAM device, an RRAM device, or the like.
In a structure of a semiconductor memory, bit line-to-bit line spacers are formed between a plurality of bit lines. In order to reduce parasitic capacitance between bit lines, one way is to reduce the dielectric constant of the bit line-to-bit line spacers. Currently, an insulating structure of Nitride-Oxide-Nitride (NON) is generally used.
Fig. 2 is a schematic diagram showing the structure of bit line-to-bit line spacers between bit lines of a semiconductor memory of the related art. As shown in fig. 2, nitride, oxide, nitride are sequentially formed along the side of the conductive layer perpendicular to the bit line and away from the conductive layer, thereby forming a NON insulating structure.
However, the dielectric constant of the NON insulating structure is still relatively high, so that the capability of reducing parasitic capacitance is limited.
Table 1 below shows the low-K materials and their corresponding dielectric constants (K). As can be seen from table 1, the dielectric constant k of air is 1, which is an excellent choice for reducing parasitic capacitance. Therefore, the parasitic capacitance can be greatly reduced by applying an air gap having a relatively low dielectric constant k to the insulating structure of the bit line interlayer.
TABLE 1
In order to reduce parasitic capacitance of the semiconductor memory, in the method for forming the semiconductor memory according to one embodiment of the present disclosure, air with a low dielectric constant is used as a bit line insulating material by forming an air gap in a bit line interlayer, so that parasitic capacitance between bit lines can be reduced, and performance of the semiconductor memory can be improved.
A method for forming a semiconductor memory according to an embodiment of the present disclosure will be described below with reference to fig. 3 and 4. Fig. 3 is a flowchart of a method of forming a semiconductor memory according to an embodiment of the present disclosure. Fig. 4 is a flowchart of a step of forming a bit line interlayer and forming an air gap within the bit line interlayer in a method of forming a semiconductor memory according to an embodiment of the present disclosure. Fig. 5A to 5G are cross-sectional views illustrating when steps are performed in forming a semiconductor memory according to an embodiment of the present disclosure. As shown in fig. 3, 4, and 5A to 5G, a method for forming a semiconductor memory according to an embodiment of the present disclosure includes the following steps.
Step S11: providing a semiconductor substrate, and forming a plurality of bit line contact parts which are arranged at intervals in the semiconductor substrate.
Illustratively, as shown in fig. 5A, a semiconductor substrate 10 is provided, and a plurality of bit line contacts (hereinafter sometimes referred to as BLC: bitline Contact) 11 are formed on the semiconductor substrate 10, the plurality of bit line contacts 11 being arranged at intervals. Specifically, the material of the semiconductor substrate 10 may be monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound, silicon-on-insulator (SOI), or the like, or other materials known to those skilled in the art. An active region, an isolation structure, a word line, a bit line contact, and the like may be formed within the semiconductor substrate 10. The active regions may be arranged in an array, the isolation structure is located at the periphery of the active regions and is used for isolating adjacent active regions, the word lines are buried word lines, intersect the active regions, and have a surface not higher than that of the semiconductor substrate 10. The bit line contact 11 is used for electrical connection with a bit line to be formed later, and may be formed by depositing polysilicon (poly) in a bit line contact hole, for example.
Step S12: and forming a plurality of bit lines on the semiconductor substrate, the plurality of bit lines being in contact with the plurality of bit line contacts, respectively.
Illustratively, as shown in fig. 5A, a plurality of bit lines 12 respectively contacting the plurality of bit line contacts 11 are formed on the semiconductor substrate 10. The bit line 12 is electrically connected to the semiconductor substrate 10 through the bit line contact 11.
The bit line 12 may include a plurality of conductive layers sequentially stacked, and the conductive layers may include one or more of a tungsten layer, a titanium layer, a nickel layer, an aluminum layer, a titanium oxide layer, and a titanium nitride layer. In some embodiments, bit line 12 may include a titanium nitride layer and a tungsten layer disposed on the titanium nitride layer.
Step S13: and forming bit line interlayer at least covering the side wall of the bit line, and forming air gap in the bit line interlayer.
Illustratively, the bit line interlayer may be formed by a double patterning technique (DPT, double patterning technology) or a quad patterning technique (QPT, quadraple pattering technology).
In some embodiments, the step of forming a bit line spacer layer at least covering sidewalls of the bit line and forming an air gap within the bit line spacer layer may include the steps of:
Step S131: and forming a first isolation layer and a sacrificial mask layer on the bit line and the semiconductor substrate in sequence.
Illustratively, as shown in fig. 5A, first, a first isolation layer 13 is formed on the semiconductor substrate 10, the bit line 12, the first isolation layer 13 covering the surface of the semiconductor substrate 10 and the top and side walls of the bit line 12. Specifically, the first isolation layer 13 is formed on the upper surfaces of the semiconductor substrate 10 and the bit line 12 by a deposition process. The first isolation layer 13 covers the exposed surface of the bit line 12, i.e., the first isolation layer 13 covers the top and sidewalls of the bit line 12 and the upper surface of the semiconductor substrate 10 that is not masked by the bit line 12.
The material of the first isolation layer 13 may be nitride, including but not limited to silicon nitride (SiN) or silicon oxynitride (SiON). The first isolation layer 13 has an isolation function to prevent the subsequent etching gas from affecting the bit line 12 and the semiconductor substrate 10. The first isolation layer 13 located between adjacent bit lines encloses to form an accommodating groove.
Next, a sacrificial mask layer 14 is formed on the first isolation layer 13 by a deposition process, the sacrificial mask layer 14 covering the top surface of the first isolation layer 13, the side walls of the accommodating groove, and the bottom surface.
The material of the sacrificial mask layer 14 is different from the material of the first isolation layer 13 and the material of the second isolation layer 15, which will be described later, so that the sacrificial mask layer 14, the first isolation layer 13 and the second isolation layer 15 may have a larger selection ratio, and thus the damage to the first isolation layer 13 and the second isolation layer 15 is smaller when the sacrificial mask layer 14 is removed later.
In some embodiments, the material of the sacrificial mask layer 14 may be spin-on-hardmask (spin-on-SOH). The SOH material may include hydrocarbons or hydrocarbon derivatives having a relatively high carbon content of about 85 wt.% to about 99 wt.% relative to the total weight of the SOH material.
In other embodiments, the sacrificial mask layer 14 may be silicon oxycarbide SiOC.
Step S132: and etching the sacrificial mask layer, wherein only a part of the sacrificial mask layer on the side wall of the bit line is reserved.
Illustratively, as shown in fig. 5B, the sacrificial mask layer 14 located on the top surface of the first isolation layer 13, and the sacrificial mask layer 14 located on the bottom surface of the accommodating groove are removed by an etching process, leaving the sacrificial mask layer 14 located on the sidewalls of the accommodating groove, i.e., the sidewalls of the bit line 12. As the etching process, a plasma etching technique or the like can be employed.
Step S133: and forming a second isolation layer covering the top of the first isolation layer and the sacrificial mask layer by atomic layer deposition ALD.
Illustratively, as shown in fig. 5C, a second isolation layer 15 is formed by atomic layer deposition ALD (Atomic Layer Deposition) overlying the top of the first isolation layer 13 and the sacrificial mask layer 14.
The material of the second isolation layer 15 may be nitride, and may include, but not limited to, silicon nitride (SiN) or silicon oxynitride (SiON). The material of the second isolation layer 15 is preferably the same as that of the second isolation layer, so that the second isolation layer 15 and the first isolation layer 13 form an integrated structure, and separation among the second isolation layer 15, the sacrificial mask layer 14 and the first isolation layer 13 can be reduced or avoided.
The step of forming the second isolation layer 15 by means of atomic layer deposition ALD may be performed at room temperature. When the material of the sacrificial mask layer 14 is SOH, the SOH is not usable at a temperature of 350 degrees or higher because the thin film volatilizes at a high temperature, but in the atomic layer deposition ALD method, deposition can be performed with a step coverage of 99 degrees even at room temperature. In this case, using SOH as a sacrificial mask, finer patterning can be achieved.
Step S134: and etching the top and bottom of the second isolation layer to expose the sacrificial mask layer.
Illustratively, as shown in fig. 5D, the top and bottom of the second isolation layer 15 are etched to expose the sacrificial mask layer 14 by an etching process such as a plasma etching technique.
Step S135: filling the gaps between bit lines by using spin-on glass SOG and performing planarization treatment.
Illustratively, as shown in FIG. 5E, the gaps between the bit lines are filled with spin-on glass SOG 16 and planarized (e.g., chemical-mechanical polishing CMP, chemical-MECHANICAL POLISHING).
Spin-on glass, SOG, is the best preferred material for improving the planarization of the wafer surface. The liquid dielectric substance is formed by mixing a solvent and a dielectric substance, contains SiO 2 or a material with a structure close to SiO 2, and is generally coated on the surface of a wafer in a spin coating mode.
Step S136: and etching the sacrificial mask layer to form an air gap.
Illustratively, as shown in fig. 5F, the sacrificial mask layer 14 between the second isolation layer 15 and the first isolation layer 13 is etched by an etching process such as a plasma etching technique, thereby forming air gaps 17 between the second isolation layer 15 and the first isolation layer 13.
Thus, the second isolation layer 15, the air gap 17, and the first isolation layer 13 constitute bit line-to-bit line isolation layers covering the sidewalls of the bit lines.
Step S14: and forming a cap layer to close the air gap.
Illustratively, as shown in FIG. 5G, the cap layer 18 is formed by a deposition process, such as a physical vapor deposition process (Physical Vapor Deposition, PVD), to close the air gap. The capping layer 18 may be made of oxide, for example.
Therefore, by forming an air gap in the bit line interlayer and using air with low dielectric constant as the bit line insulating material, parasitic capacitance between bit lines can be reduced, and the performance of the semiconductor memory can be improved.
In addition, in the method of forming the semiconductor memory according to some embodiments of the present disclosure, a step of forming a salicide between the bit line and the bit line contact may be further included. The salicide may be a metal silicide, such as TiSi.
The step of forming a salicide between a bit line and a bit line contact in some embodiments of the present disclosure is described below with reference to fig. 6 and 7. Fig. 6 is a flowchart of a step of forming a salicide between a bit line and a bit line contact in a method of forming a semiconductor memory according to an embodiment of the present disclosure. Fig. 7 is a schematic view showing a structure in which salicide is formed between bit lines and bit line contacts in a semiconductor memory according to an embodiment of the present disclosure. As shown in fig. 6 and 7, the step of forming a salicide between the bit line and the bit line contact includes the following steps.
Step S21: and performing ion implantation doping on the polysilicon of the bit line contact part when the bit line contact part is formed.
Illustratively, as shown in fig. 7, when forming the bit line contact 11, the polysilicon (poly) of the bit line contact 11 is ion-implanted (Ion Implantation) doped, for example, doped Ge ions or the like may be implanted. Before this step, the steps of polysilicon etching (BLC Poly etc) and ashing (BLC Poly ASH) of the bit line contact are performed in the same manner as in the conventional bit line contact formation process, and detailed description thereof is omitted.
Step S22: and depositing a metal layer of the peripheral grid.
Illustratively, as shown in FIG. 7, deposition of the metal layer 21 of the peripheral gate (hereinafter sometimes referred to as PG: PERIPHERY GATE) is performed by a deposition process. The material of the metal layer 21 may be TiN, for example.
Before this step, similar to the conventional process for forming the bit line contact, steps such as removal of the Oxide of the bit line contact (BLC Oxide STRIP), ashing of photoresist residue of the Oxide of the bit line contact (BLC Oxide ASH), and pre-cleaning of the peripheral gate metal layer (PG TIN PRE CLN) are also performed, and will not be described in detail herein.
Step S23: and performing rapid thermal annealing after ion implantation doping to enable the metal layer to react with the polysilicon so as to generate the self-aligned silicide.
Illustratively, as shown in fig. 7, a post ion implant doped rapid thermal anneal (BLC GE IMP RTP (RAPID THERMAL Process: rapid thermal Process) and BLC GE IMP ANNEAL) is performed to react the metal layer 21 with the polysilicon of the bit line contacts 11 to produce salicide (Salicde) 31.
The salicide 31 may be a metal silicide, for example, in the case where the material of the metal layer 21 is TiN, the salicide 31 is TiSi.
After this step, peripheral gate tungsten deposition (PG W DEP) and peripheral gate backside cleaning (PG BACKSIDE SCRUBBER) are performed, which will not be described in detail herein.
Thus, by forming the salicide between the bit line and the bit line contact, the contact resistance between the bit line and the bit line contact can be reduced, interference of the contact resistance and parasitic capacitance can be suppressed, and the performance of the semiconductor memory can be improved.
In some embodiments of the present disclosure, a semiconductor memory is also provided. As shown in fig. 5G, the semiconductor memory includes: a semiconductor substrate 10, wherein a plurality of bit line contact portions 11 are formed in the semiconductor substrate 10 at intervals; a plurality of bit lines 12, the plurality of bit lines 12 being formed over the semiconductor substrate 10 and being in contact with the plurality of bit line contacts 11, respectively; bit line spacers which cover at least the sidewalls of the bit lines 12 and in which air gaps 17 are formed; and a cap layer 18, the cap layer 18 closing the air gap 17.
Specifically, as shown in fig. 5G, the second isolation layer 15, the air gap 17, and the first isolation layer 13 constitute bit line isolation layers that cover the sidewalls of the bit lines 12.
Therefore, by forming an air gap in the bit line interlayer and using air with low dielectric constant as the bit line insulating material, parasitic capacitance between bit lines can be reduced, and the performance of the semiconductor memory can be improved.
In the semiconductor memory, as shown in fig. 7, a salicide 31 may be formed between the bit line 12 and the bit line contact 11. The salicide 31 may be a metal silicide, such as TiSi.
Thus, by forming the salicide between the bit line and the bit line contact, the contact resistance between the bit line and the bit line contact can be reduced, interference of the contact resistance and parasitic capacitance can be suppressed, and the performance of the semiconductor memory can be improved.
In the above description, technical details of patterning, forming processes, and the like of each layer are not described in too much detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, in order to form the same structure, those skilled in the art can also adopt a method which is not exactly the same as the method described above.
The present disclosure has been described in detail, but the above embodiments are merely examples of all embodiments, and the present disclosure is not limited thereto. The present disclosure may freely combine the embodiments, modify any component of the embodiments, or omit any component of the embodiments within the scope of the present invention.
Claims (10)
1. A method of forming a semiconductor memory comprising the steps of:
Providing a semiconductor substrate, and forming a plurality of bit line contact parts which are arranged at intervals in the semiconductor substrate;
forming a plurality of bit lines on the semiconductor substrate, the plurality of bit lines being in contact with the plurality of bit line contacts, respectively;
Forming bit line interlayer at least covering the side wall of the bit line and forming air gap in the bit line interlayer; and
And forming a cap layer to close the air gap.
2. The method for forming a semiconductor memory according to claim 1, wherein,
The step of forming bit line spacers at least covering sidewalls of the bit lines and forming air gaps within the bit line spacers comprises:
sequentially forming a first isolation layer and a sacrificial mask layer on the bit line and the semiconductor substrate;
Etching the sacrificial mask layer, and only reserving a part of the sacrificial mask layer on the side wall of the bit line;
a step of forming a second isolation layer covering the top of the first isolation layer and the sacrificial mask layer by atomic layer deposition ALD;
etching the top and bottom of the second isolation layer to expose the sacrificial mask layer;
filling gaps between the bit lines by using spin-on glass SOG and performing planarization treatment; and
And etching the sacrificial mask layer to form an air gap.
3. The method for forming a semiconductor memory according to claim 2, wherein,
The sacrificial mask layer is a spin-on hard mask SOH.
4. The method for forming a semiconductor memory device according to claim 3, wherein,
The step of forming the second isolation layer by atomic layer deposition ALD is performed at room temperature.
5. The method for forming a semiconductor memory according to claim 2, wherein,
The sacrificial mask layer is silicon oxycarbide SiOC.
6. The method for forming a semiconductor memory according to claim 1, wherein,
Further comprising the step of forming a salicide between the bit line and the bit line contact.
7. The method for forming a semiconductor memory according to claim 6, wherein,
The step of forming a salicide between the bit line and the bit line contact comprises:
a step of ion implantation doping the polysilicon of the bit line contact portion when the bit line contact portion is formed;
A step of depositing a metal layer of the peripheral gate; and
And performing rapid thermal annealing after ion implantation doping to enable the metal layer to react with the polysilicon so as to generate the self-aligned silicide.
8. The method for forming a semiconductor memory according to claim 7, wherein,
The metal layer is TiN, and the self-aligned silicide is TiSi.
9. A semiconductor memory device, comprising:
a semiconductor substrate in which a plurality of bit line contacts are formed in a spaced arrangement;
A plurality of bit lines formed over the semiconductor substrate and in contact with a plurality of the bit line contacts, respectively;
bit line interlayer, the said bit line interlayer covers the sidewall of the said bit line at least, and there are air gaps in the said bit line interlayer; and
And the capping layer is used for closing the air gap.
10. The semiconductor memory according to claim 9, wherein,
A salicide is formed between the bit line and the bit line contact.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410169256.9A CN118019333A (en) | 2024-02-06 | 2024-02-06 | Semiconductor memory and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410169256.9A CN118019333A (en) | 2024-02-06 | 2024-02-06 | Semiconductor memory and forming method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN118019333A true CN118019333A (en) | 2024-05-10 |
Family
ID=90951763
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410169256.9A Pending CN118019333A (en) | 2024-02-06 | 2024-02-06 | Semiconductor memory and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118019333A (en) |
-
2024
- 2024-02-06 CN CN202410169256.9A patent/CN118019333A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101669470B1 (en) | Semiconductor device including metal silicide layer | |
| US10872895B2 (en) | Method of manufacturing capacitor structure | |
| KR100854555B1 (en) | Semiconductor device and method for producing the same | |
| US7276751B2 (en) | Trench metal-insulator-metal (MIM) capacitors integrated with middle-of-line metal contacts, and method of fabricating same | |
| US7566974B2 (en) | Doped polysilicon via connecting polysilicon layers | |
| US6423591B2 (en) | Semiconductor device and method for fabricating the same | |
| US7566620B2 (en) | DRAM including a vertical surround gate transistor | |
| US6475855B1 (en) | Method of forming integrated circuitry, method of forming a capacitor and method of forming DRAM integrated circuitry | |
| US20030087499A1 (en) | Process for forming metallized contacts to periphery transistors | |
| JP2004530300A (en) | Depressed GATDRAM transistors and methods | |
| US20090001437A1 (en) | Integrated Circuit Devices Including Recessed Conductive Layers and Related Methods | |
| KR20000022801A (en) | Semiconductor device and manufacturing method thereof | |
| US20210217813A1 (en) | Rram structure and method of fabricating the same | |
| US8729618B2 (en) | Semiconductor device and method for manufacturing the same | |
| US7790613B2 (en) | Semiconductor device and method of manufacturing the same | |
| CN111863813A (en) | Method for forming integrated circuit | |
| US10903328B2 (en) | Method for fabricating semiconductor device | |
| US9368399B2 (en) | Semiconductor device and method for forming the same | |
| TWI779769B (en) | Integrated chip, memory device and method of forming the same | |
| US20070181957A1 (en) | Semiconductor device having stacked transistors and method for manufacturing the same | |
| KR100609546B1 (en) | Extended trench for preventing interaction between components of stacked capacitors | |
| CN112437983B (en) | Three-dimensional memory device and method for forming three-dimensional memory device | |
| CN118019333A (en) | Semiconductor memory and forming method thereof | |
| US20070269974A1 (en) | Methods for forming a metal contact in a semiconductor device in which an ohmic layer is formed while forming a barrier metal layer | |
| US6399440B1 (en) | Method to reduce the node contact resistance |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |