TW202336719A - Electronic device and modulating device with short frame time length - Google Patents

Abstract

An electronic device and a modulating device with short frame time lengths are provided. The electronic device includes a substrate, a plurality of first signal lines, a plurality of second signal lines and two first integrated circuits. The plurality of first signal lines are disposed on the substrate. The plurality of first signal lines are divided into a first group of signal lines and a second group of signal lines. The plurality of second signal lines are disposed on the substrate. The plurality of second signal lines are arranged alternately with the multiple first signal lines. The two first integrated circuits are bonded on the substrate. Each of the two first integrated circuits are electrically connected to the first group of signal lines and the second group of signal lines. The first group of signal lines and the second group of signal lines are arranged alternately in columns.

Description

Electronic devices with short frame time length and modulation devices

The present disclosure relates to an electronic device, and in particular to an electronic device with a short frame time length and a modulation device.

The driving method of existing electronic devices (such as displays or antenna arrays) is sequential driving, that is, column-by-column and row-by-row driving. The frame time length of an electronic device (such as a display or an antenna array) is determined by the number of data lines and the number of scan lines. However, the frame time length will be limited by the charging time of the data lines and scan lines. That is, the greater the number of data lines and the number of scan lines, the longer the length of the frame time. Therefore, the time cost for data updating of the electronic device will be longer. It can be seen from this that how to provide a driving method for an electronic device with a short frame time length is one of the research focuses of those skilled in the art.

The present disclosure is directed to an electronic device and a modulation device with a short frame time length.

According to an embodiment of the present disclosure, an electronic device includes a substrate, a plurality of first signal lines, a plurality of second signal lines, and two first integrated circuits. The plurality of first signal lines are provided on the substrate. The plurality of first signal lines are divided into a first group of signal lines and a second group of signal lines. The plurality of second signal lines are provided on the substrate. The plurality of second signal lines are interleaved with the plurality of first signal lines. The two first integrated circuits are bonded to the substrate. The two first integrated circuits are each electrically connected to a first set of signal lines and a second set of signal lines. The first group of signal lines and the second group of signal lines are arranged in alternate rows.

According to an embodiment of the present disclosure, a modulation device includes a substrate, a modulation element, a plurality of first signal lines, a plurality of second signal lines, and two first integrated circuits. The plurality of first signal lines are provided on the substrate. The plurality of first signal lines are divided into a first group of signal lines and a second group of signal lines. One of the plurality of first signal lines is electrically connected to the modulation element. The plurality of second signal lines are provided on the substrate. The plurality of second signal lines are interleaved with the plurality of first signal lines. One of the plurality of second signal lines is electrically connected to the modulation element. The two first integrated circuits are bonded to the substrate. The two first integrated circuits are each electrically connected to a first set of signal lines and a second set of signal lines. The first group of signal lines and the second group of signal lines are arranged in alternate rows.

Based on the above, the two first integrated circuits are each electrically connected to the first set of signal lines and the second set of signal lines. In addition, the first group of signal lines and the second group of signal lines are arranged in alternate rows. That is to say, the signals received by two adjacent signal lines come from different first integrated circuits. Therefore, the first signal line does not need to wait for the adjacent previous signal line to be charged before charging. In this way, the frame time length of the electronic device can be shortened.

The present disclosure may be understood by reference to the following detailed description, taken in conjunction with the drawings, as described below. It should be noted that for purposes of clarity of illustration and ease of understanding by the reader, each drawing of the present disclosure depicts a portion of an electronic device, and certain elements in each drawing may not be drawn to scale. Furthermore, the number and size of each device depicted in the drawings are illustrative only and are not intended to limit the scope of the present disclosure.

Certain terms are used throughout the description and the claims below to refer to specific elements. As those skilled in the art will understand, electronic device manufacturers may refer to components by different names. This document does not intend to differentiate between components that have different names rather than different functions. In the following description and in the claims, the terms "comprises," "including," and "having" are used in an open-ended fashion, and therefore should be interpreted to mean "including, but not limited to..." Therefore, when used herein, When the terms "comprising", "including" and/or "having" are used in the description of the disclosure, it will indicate the presence of corresponding features, regions, steps, operations and/or elements, but is not limited to the existence of one or more corresponding features, regions, Steps, actions and/or components.

The electrical connection or coupling described in this disclosure can refer to direct connection or indirect connection. In the case of direct connection, the end points of the components on the two circuits are directly connected or connected to each other with a conductor line segment, and in the indirect connection In the case of , there are switches, diodes, capacitors, inductors, resistors, other suitable components or combinations of the above components between the end points of the components on the two circuits, but are not limited to this.

Although terms such as first, second, third, etc. may be used to describe different constituent elements, such constituent elements are not limited by these terms. Terms are only used to distinguish constituent elements from other constituent elements in the specification. The claims may not use the same terms, but may use the terms first, second, third, etc. with respect to the claimed order of elements. Therefore, in the following description, a first constituent element may be a second constituent element in the claims.

The electronic device of the present disclosure may include a display device, a modulation device, a sensing device or a splicing device, but is not limited thereto. The electronic device may include a bendable or flexible electronic device. The electronic device includes, for example, a liquid crystal (liquid crystal) layer or a light emitting diode (Light Emitting Diode, LED). Electronic devices may include electronic components. Electronic components may include passive components and active components, such as capacitors, resistors, inductors, variable capacitors, filters, diodes, transistors, sensors, microelectromechanical systems (MEMS), liquid crystal chips ( liquid crystal chip), etc., but not limited to this. Diodes may include light emitting diodes or photodiodes. Light emitting diodes may include, for example, organic light emitting diodes (OLEDs), submillimeter light emitting diodes (mini LEDs), micro light emitting diodes (micro LEDs), and quantum dot light emitting diodes (quantum dots). dot LED), fluorescence, phosphor or other suitable materials, or a combination of the above, but is not limited to this. Sensors may include, for example, capacitive sensors, optical sensors, electromagnetic sensors, fingerprint sensors (FPS), and touch sensors. , or stylus (pen sensor), etc., but not limited to this. It should be noted that the electronic device can be any combination of the above, but is not limited thereto. In addition, the shape of the electronic device may be a rectangular shape, a circular shape, a polygonal shape, a shape with curved edges, or other suitable shapes. The electronic device may have peripheral systems such as a driving system, a control system, a light source system, etc. to support the display device, modulation device or splicing device, but the present disclosure is not limited thereto.

In the present disclosure, embodiments use "picture element" or "picture element unit" as a unit for describing a specific area containing at least one functional circuit for at least one specific function. The area of an "element" depends on the unit used to provide a specific function; adjacent elements can share the same parts or wires but may also contain specific parts of themselves. For example, adjacent primitives may share the same scan line or the same data line, but the primitive may also have its own transistor or capacitor.

It should be noted that technical features in different embodiments described below may be replaced, recombined, or mixed with each other to constitute another embodiment without departing from the spirit of the present disclosure.

Please refer to FIG. 1 , which is a schematic diagram of an electronic device according to a first embodiment of the present disclosure. In this embodiment, the electronic device 100 includes a substrate SB, first signal lines LC1 to LC16, second signal lines LR1 to LR6, and first integrated circuits (ICs) 110-1 and 110-2. The first signal lines LC1 to LC16 are respectively provided on the substrate SB. The second signal lines LR1 to LR6 are respectively provided on the substrate SB. The second signal lines LR1 to LR6 are interleaved with the first signal lines LC1 to LC16. Taking this embodiment as an example, the first signal lines LC1 to LC16 respectively extend along the row direction and are arranged along the column direction. The second signal lines LR1 to LR6 respectively extend along the column direction and are arranged along the row direction. The substrate SB includes an active area RA and a peripheral area RB. The first signal lines LC1 to LC16 and the second signal lines LR1 to LR6 are staggered in the action area RA.

In this embodiment, the first signal lines LC1 to LC16 are divided into a first group of signal lines GL1 and a second group of signal lines GL2. The first group of signal lines GL1 and the second group of signal lines GL2 are arranged in alternate rows. Taking this embodiment as an example, the first signal lines LC1, LC3, LC5, LC7, LC9, LC11, LC13, and LC15 are grouped into a first group of signal lines GL1. The first signal lines LC2, LC4, LC6, LC8, LC10, LC12, LC14, and LC16 are grouped into a second group of signal lines GL2. The first signal line LC2 is provided between the first signal lines LC1 and LC3. The first signal line LC3 is provided between the first signal lines LC2 and LC4. And so on.

In this embodiment, the first integrated circuits 110-1 and 110-2 are bonded to the substrate SB. The first integrated circuits 110-1 and 110-2 are each electrically connected to the first set of signal lines GL1 and the second set of signal lines GL2. Taking this embodiment as an example, the first integrated circuit 110-1 is electrically connected to the first set of signal lines GL1. The first integrated circuit 110-2 is electrically connected to the second set of signal lines GL2.

It is worth mentioning here that the first integrated circuits 110-1 and 110-2 are each electrically connected to the first set of signal lines GL1 and the second set of signal lines GL2. In addition, the first group of signal lines GL1 and the second group of signal lines GL2 are arranged in alternate rows. That is to say, the signals received by two adjacent signal lines come from different first integrated circuits. Therefore, charging of the first signal line does not need to wait for the adjacent previous signal line to be charged. For example, the signal received by the first group of signal lines GL1 comes from the first integrated circuit 110-1. The signal received by the second group of signal lines GL2 comes from the first integrated circuit 110-2. The second set of signal lines GL2 does not need to wait for the adjacent first set of signal lines GL1 to be charged before charging. In this way, the frame time length of the electronic device 100 can be shortened.

In this embodiment, the electronic device 100 may be, for example, a modulation device. The electronic device 100 also includes a plurality of modulation elements EE. For example, the plurality of modulation elements EE are arranged in multiple columns and multiple rows. The plurality of modulation elements EE may be varactor, resistor, inductor or other suitable electronic components. The modulation element EE is electrically connected to one of the first signal lines LC1 to LC16 and one of the second signal lines LR1 to LR6.

In this embodiment, the first signal lines LC1 to LC16 may be one of a data line and a scan line. The second signal lines LR1 to LR6 may be the other one of a data line and a scanning line. The first integrated circuits 110-1 and 110-2 may be one of a gate driving integrated circuit and a data driving integrated circuit. For example, the first integrated circuits 110-1 and 110-2 may be data driving integrated circuits, and the first signal lines LC1 to LC16 may be data lines respectively. The second signal lines LR1 to LR6 may respectively be scanning lines.

The electronic device 100 also includes second integrated circuits 120-1, 120-2. The second integrated circuits 120-1 and 120-2 are bonded to the substrate SB. The second signal lines LR1 to LR6 are divided into a third group of signal lines GL3 and a fourth group of signal lines GL4. The second integrated circuits 120-1 and 120-2 are each electrically connected to the third group of signal lines GL3 and the fourth group of signal lines GL4. In this embodiment, the second signal lines LR1 to LR3 are grouped into a third group of signal lines GL3. The second signal lines LR4 to LR6 are grouped into a fourth group of signal lines GL4. The second integrated circuit 120-1 is electrically connected to the third group of signal lines GL3. The second integrated circuit 120-2 is electrically connected to the fourth group of signal lines GL4. The second integrated circuits 120-1 and 120-2 may respectively be gate driving integrated circuits. For example, the gate driving integrated circuit may include a level shifter circuit, a shift register circuit, and a timing shifter circuit.

This embodiment uses 16 first signal lines LC1 to LC16, 6 second signal lines LR1 to LR6 and two first integrated circuits 110-1 and 110-2 as an example. The number of the first signal lines LC1 to LC16, the number of the second signal lines LR1 to LR6, and the number of the first integrated circuits 110-1 and 110-2 of the disclosure may be multiple respectively. However, the present disclosure is not limited to this embodiment.

In this embodiment, the peripheral area RB surrounds the active area RA. The modulation element EE is arranged in the active area RA. The first integrated circuits 110-1 and 110-2 and the second integrated circuits 120-1 and 120-2 are provided in the peripheral area RB. The first integrated circuits 110-1, 110-2 are arranged along the first side S1 of the substrate SB. The second integrated circuits 120-1, 120-2 are arranged along the second side S2 of the substrate SB.

Please refer to FIG. 1 and FIG. 2 simultaneously. FIG. 2 is a signal timing diagram according to the first embodiment of the present disclosure. Figure 2 illustrates part of the signal timing. In this embodiment, the timing diagram shown in FIG. 2 is applicable to the electronic device 100. During the time interval T1, the first integrated circuit 110-1 provides the data signal group SD1 to the first group of signal lines GL1. In the time interval T1, the second integrated circuit 120-1 provides the scanning signal SG1 to the second signal line LR1. The time length b during which the second integrated circuit 120-1 provides the scan signal SG1 is shorter than the time length a during which the first integrated circuit 110-1 provides the data signal group SD1. During the time interval T2, the first integrated circuit 110-2 provides the data signal group SD2 to the second group of signal lines GL2.

In the time interval T2, the second integrated circuit 120-1 provides the scanning signal SG2 to the second signal line LR2. The time length b for which the second integrated circuit 120-2 provides the scan signal SG2 is shorter than the time length a for which the first integrated circuit 110-2 provides the data signal group SD2.

During the time interval T3, the first integrated circuit 110-1 provides the data signal group SD1 to the first group of signal lines GL1. In the time interval T3, the second integrated circuit 120-1 provides the scanning signal SG3 to the second signal line LR2. The time length b for which the second integrated circuit 120 - 2 provides the scanning signal SG3 is less than the time length a.

During the time interval T4, the first integrated circuit 110-2 provides the data signal group SD2 to the second group of signal lines GL2. In the time interval T4, the second integrated circuit 120-2 provides the scanning signal SG4 to the second signal line LR4. The time length b for which the second integrated circuit 120 - 2 provides the scanning signal SG4 is less than the time length a.

It should be noted that based on the existing driving method, the frame time length is determined by the product of the time length a and the number G of the second signal lines LR1 to LR6, that is, the frame time length is equal to “a×G”. However, in this embodiment, the signal received by the first group of signal lines GL1 in the time interval T1 comes from the first integrated circuit 110-1. The signal received by the first group of signal lines GL2 in the time interval T2 comes from the first integrated circuit 110-2. The first group of signal lines GL2 does not need to wait for the adjacent first group of signal lines GL1 to be charged before charging. This allows time intervals T1 and T2 to partially overlap. Therefore, the frame time lengths F(N) and F(N+1) of this embodiment are determined by the product of the time length b and the number of the second signal lines LR1 to LR6 respectively. That is, the frame time lengths F(N) and F(N+1) are equal to "b×G". In this way, the frame time lengths F(N) and F(N+1) of the electronic device 100 can be shortened.

Please refer to FIG. 3 , which is a schematic diagram of an electronic device according to a second embodiment of the present disclosure. In this embodiment, the electronic device 200 includes a substrate SB, a plurality of modulation elements EE, first signal lines LC1 to LC16, second signal lines LR1 to LR6, first integrated circuits 210-1, 210-2 and a third Two integrated circuits 220-1 and 220-2. One of the first signal lines LC1 to LC16 is electrically connected to the modulation element EE. One of the second signal lines LR1 to LR6 is electrically connected to the modulation element EE. The first signal lines LC1, LC3, LC5, LC7, LC9, LC11, LC13, and LC15 are grouped into a first group of signal lines GL1. The first signal lines LC2, LC4, LC6, LC8, LC10, LC12, LC14, and LC16 are grouped into a second group of signal lines GL2. The first group of signal lines GL1 and the second group of signal lines GL2 are arranged in alternate rows. The first integrated circuit 210-1 is electrically connected to the first set of signal lines GL1. The first integrated circuit 210-2 is electrically connected to the second set of signal lines GL2.

In this embodiment, the second signal lines LR1 to LR6 are divided into a third group of signal lines GL3 and a fourth group of signal lines GL4. The second signal lines LR1, LR3, and LR5 are grouped into a third group of signal lines GL3. The second signal lines LR2, LR4, and LR6 are grouped into a fourth group of signal lines GL4. In other words, the third group of signal lines GL3 and the fourth group of signal lines GL4 are arranged in alternate rows. The second integrated circuit 220-1 is electrically connected to the third group of signal lines GL3. The second integrated circuit 220-2 is electrically connected to the fourth group of signal lines GL4.

In this embodiment, the first integrated circuits 210-1 and 210-2 are arranged along the first side S1 of the substrate SB. The second integrated circuits 220-1 and 220-2 are respectively disposed along at least one side of the substrate SB that is different from the first side S1. Taking this embodiment as an example, the second integrated circuits 220-1 and 220-2 are arranged along the second side S2 of the substrate SB.

Please refer to FIG. 3 and FIG. 4 simultaneously. FIG. 4 is a signal timing diagram according to the second embodiment of the present disclosure. Figure 4 illustrates part of the signal timing. In this embodiment, the timing diagram shown in FIG. 4 is applicable to the electronic device 200. During the time interval T1, the first integrated circuit 210-1 provides the data signal group SD1 to the first group of signal lines GL1. The first integrated circuit 210-2 provides the data signal group SD2 to the second group of signal lines GL2. In the time interval T1, the second integrated circuit 220-1 provides the scanning signal SG1 to the second signal line LR1. The second integrated circuit 220-2 provides the scanning signal SG2 to the second signal line LR2. The time length b for which the second integrated circuits 220-1 and 220-2 provide the scan signals SG1 and SG2 is shorter than the time length a for which the first integrated circuits 210-1 and 210-2 provide the data signal groups SD1 and SD2.

During the time interval T2, the first integrated circuit 210-1 provides the data signal group SD1 to the first group of signal lines GL1. The first integrated circuit 210-2 provides the data signal group SD2 to the second group of signal lines GL2. In the time interval T2, the second integrated circuit 220-1 provides the scanning signal SG3 to the second signal line LR3. The second integrated circuit 220-2 provides the scan signal SG4 to the second signal line LR4. The time length b for which the second integrated circuits 220-1 and 220-2 provide the scanning signals SG3 and SG4 is less than the time length a.

It should be noted that in this embodiment, in each time interval, the signal received by the first group of signal lines GL1 comes from the first integrated circuit 210-1. The signal received by the second group of signal lines GL2 in the time interval T2 comes from the first integrated circuit 210-2. The second set of signal lines GL2 does not need to wait for the adjacent first set of signal lines GL1 to be charged before charging. In addition, the signal received by the third group of signal lines GL3 comes from the second integrated circuit 210-1. The signal received by the fourth group of signal lines GL4 comes from the second integrated circuit 210-2. In other words, the signals received by the third group of signal lines GL3 and GL4 come from different second integrated circuits. This enables the supply timings of the time interval data signal groups SD1 and SD2 to overlap or even be identical, the supply timings of the scanning signals SG1 and SG2 to overlap or even be identical, and the supply timings of the scanning signals SG3 and SG4 can also overlap or even be identical. Therefore, the frame time lengths F(N) and F(N+1) of this embodiment are respectively determined by half of the product of the time length a and the number of the second signal lines LR1 to LR6. That is, the frame time lengths F(N) and F(N+1) are equal to "(b×G)/2". The frame time lengths F(N) and F(N+1) of the electronic device 200 are substantially half of the frame time lengths of the conventional driving method.

Please refer to FIG. 5 , which is a schematic diagram of an electronic device according to a third embodiment of the present disclosure. In this embodiment, the electronic device 300 includes a substrate SB, a plurality of modulation elements EE, first signal lines LC1 to LC16, second signal lines LR1 to LR6, first integrated circuits 210-1, 210-2 and a third Two integrated circuits 220-1 and 220-2. Different from the electronic device 200 shown in FIG. 3 , the second integrated circuit 220 - 1 is disposed along the second side S2 of the substrate SB. The second integrated circuit 220-2 is disposed along the third side S3 of the substrate SB. The third side S3 is opposite the second side S2.

Please refer to FIG. 6 , which is a schematic diagram of an electronic device according to a fourth embodiment of the present disclosure. In this embodiment, the electronic device 400 includes a substrate SB, a plurality of modulation elements EE, first signal lines LC1 to LC16, second signal lines LR1 to LR6, first integrated circuits 210-1, 210-2 and a third Two integrated circuits 220-1 and 220-2. What is different from the electronic device 300 shown in FIG. 5 is that the first integrated circuits 210-1 and 210-2 and the second integrated circuits 220-1 and 220-2 are arranged along the first side S1 of the substrate SB.

Please refer to FIG. 7 , which is a schematic diagram of an electronic device according to a fifth embodiment of the present disclosure. In this embodiment, the electronic device 500 includes a substrate SB, a plurality of modulation elements EE, first signal lines LC1 to LC4, second signal lines LR1 to LR6, a first integrated circuit 210-1 and a second integrated circuit 220-1, 220-2. The first integrated circuit 210-1 is electrically connected to the plurality of modulation elements EE through the first signal lines LC1 to LC4. The second integrated circuit 220-1 is electrically connected to the plurality of modulation elements EE through the second signal lines LR1, LR3, and LR5. The second integrated circuit 220-2 is electrically connected to the plurality of modulation elements EE through the second signal lines LR2, LR4, and LR6. The second signal lines LR1 to LR6 are staggered in the action area RA. In this embodiment, the first integrated circuit 210-1 and the second integrated circuits 220-1 and 220-2 are arranged along the first side S1 of the substrate SB.

Please refer to FIG. 8 , which is a schematic diagram of an electronic device according to a sixth embodiment of the present disclosure. The electronic device 600 includes a substrate SB, a plurality of modulation elements EE, first signal lines LC1 to LC16, second signal lines LR1 to LR6, first integrated circuits 210-1, 210-2, and a second integrated circuit 220- 1, 220-2. Different from the electronic device 200 shown in FIG. 3 , the first integrated circuit 210 - 1 is disposed along the first side S1 of the substrate SB. The first integrated circuits 210-1 and 210-2 and the second integrated circuits 220-1 and 220-2 are respectively disposed along different sides of the substrate SB. In this embodiment, the first integrated circuit 210-2 is disposed along the fourth side S4 of the substrate SB. The fourth side S4 is opposite the first side S1. The second integrated circuit 220-1 is disposed along the second side S2 of the substrate SB. The second integrated circuit 220-2 is disposed along the third side S3 of the substrate SB. The third side S3 is opposite the second side S2.

Please refer to FIG. 9 , which is a signal timing diagram according to an embodiment of the present disclosure. FIG. 9 shows the timing of scan signals SG1 to SG7. In this embodiment, the timings of the corresponding signals provided by the plurality of second integrated circuits are the same as each other. For example, this embodiment is suitable for applications with high bandwidth or special wavefronts. Based on the clock signal CLK, the timing of the scanning signal SG1 is the same as the timing of the corresponding scanning signal SG4 and the timing of the corresponding scanning signal SG7. The timing of the scanning signal SG2 is the same as the timing of the corresponding scanning signal SG5. The timing of the scanning signal SG3 is the same as the timing of the corresponding scanning signal SG6. The timing sequence of this embodiment can be implemented by at least two second integrated circuits of the first to fourth embodiments. Furthermore, the clock signal CLK is generated according to the triggering of the start signal STV. Therefore, in the first period of the clock signal CLK, the scanning signals SG1, SG4, and SG7 are generated. In the second period of the clock signal CLK, the scanning signals SG2 and SG5 are generated, and so on.

Please refer to FIG. 10 , which is a signal timing diagram according to the seventh embodiment of the present disclosure. In this embodiment, the electronic device 700 includes a substrate SB, a plurality of modulation elements EE, first signal lines LC1 to LC16, second signal lines LR1 to LR6, first integrated circuits 210-1, 210-2, and Two integrated circuits 220-1 and 220-2 and multiple anti-electrostatic discharge (Electrostatic Discharge, ESD) components ESDC. The substrate SB, the plurality of modulation elements EE, the first signal lines LC1 to LC16, the second signal lines LR1 to LR6, the first integrated circuits 210-1 and 210-2 and the second integrated circuits 220-1 and 220- The implementation of 2 has been clearly explained in the embodiment of FIG. 3 and FIG. 4 . Therefore it will not be reiterated here. In this embodiment, the plurality of anti-static discharge components ESDC are disposed in the peripheral area RB and surround the active area RA. In this embodiment, there is a gap between two anti-electrostatic discharge components ESDC that are adjacent to each other. That is, the plurality of anti-electrostatic discharge elements ESDC are not continuously provided.

In this embodiment, the anti-static discharge element ESDC can be connected to at least one of the plurality of modulation elements EE, the first signal lines LC1 to LC16 and the second signal lines LR1 to LR6. Therefore, corresponding components connected to the anti-electrostatic discharge component ESDC can avoid damage caused by ESD during the manufacturing process or during use.

Please refer to FIG. 11 , which is a schematic diagram of an electronic device according to an eighth embodiment of the present disclosure. In this embodiment, the electronic device 800 includes a substrate SB, a plurality of modulation elements EE, first signal lines LC1 to LC16, second signal lines LR1 to LR6, first integrated circuits 210-1, 210-2, and Two integrated circuits 220-1 and 220-2 and an anti-electrostatic discharge component group GESDC. The substrate SB, the plurality of modulation elements EE, the first signal lines LC1 to LC16, the second signal lines LR1 to LR6, the first integrated circuits 210-1 and 210-2 and the second integrated circuits 220-1 and 220- The implementation of 2 has been clearly explained in the embodiment of FIG. 3 and FIG. 4 . Therefore it will not be reiterated here. In this embodiment, the anti-static discharge component group GESDC is disposed in the peripheral area RB and surrounds the active area RA. The anti-electrostatic discharge element group GESDC includes a plurality of continuously arranged anti-electrostatic discharge elements (the anti-electrostatic discharge element ESDC shown in Figure 10). In this embodiment, there is no spacing between two anti-static discharge elements adjacent to each other.

The first integrated circuits are each electrically connected to the first set of signal lines and the second set of signal lines. In addition, the first group of signal lines and the second group of signal lines are arranged in alternate rows. The signals received by two adjacent signal lines come from different first integrated circuits. Therefore, charging of the first signal line does not need to wait for the adjacent previous signal line to be charged. In this way, the frame time length of the electronic device can be shortened. In some embodiments, the second signal line is divided into a third group of signal lines and a fourth group of signal lines. The third group of signal lines and the fourth group of signal lines are arranged in alternate columns. The second integrated circuit is electrically connected to the third set of signal lines. The second integrated circuit is electrically connected to the third set of signal lines. In this way, the frame time length of the electronic device can be further shortened. Additionally, in some embodiments, the electronic device further includes an anti-static discharge component. Therefore, the corresponding component connected to the anti-static discharge component can avoid damage caused by ESD during the manufacturing process or during use.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present disclosure, but not to limit it. Although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features can be equivalently replaced; and these modifications or substitutions do not deviate from the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present disclosure. Scope.

100, 200, 300, 400, 500, 600, 700, 800: electronic devices 110-1, 110-2, 210-1, 210-2: First Integrated Circuit 120-1, 120-2, 220-1, 220-2: Second integrated circuit a, b: length of time EE: modulation element ESDC: anti-electrostatic discharge component F(N), F(N+1): frame time length GESDC: Anti-electrostatic discharge component group GL1: The first set of signal lines GL2: The second set of signal lines GL3: The third set of signal lines GL4: The fourth set of signal lines LC1~LC16: first signal line LR1~LR6: second signal line RA: action area RB: surrounding area S1: first side S2: Second side S3: Third side S4: The fourth side SB:Substrate SD1, SD2: data signal group SG1~SG7: Scan signal T1~T4: time interval

FIG. 1 is a schematic diagram of an electronic device according to a first embodiment of the present disclosure. FIG. 2 is a signal timing diagram according to the first embodiment of the present disclosure. FIG. 3 is a schematic diagram of an electronic device according to a second embodiment of the present disclosure. FIG. 4 is a signal timing diagram according to the second embodiment of the present disclosure. FIG. 5 is a schematic diagram of an electronic device according to a third embodiment of the disclosure. FIG. 6 is a schematic diagram of an electronic device according to a fourth embodiment of the present disclosure. FIG. 7 is a schematic diagram of an electronic device according to a fifth embodiment of the present disclosure. FIG. 8 is a schematic diagram of an electronic device according to a sixth embodiment of the present disclosure. FIG. 9 is a signal timing diagram according to an embodiment of the present disclosure. FIG. 10 is a signal timing diagram according to the seventh embodiment of the present disclosure. FIG. 11 is a schematic diagram of an electronic device according to an eighth embodiment of the present disclosure.

100: Electronic devices

110-1, 110-2: First Integrated Circuit

120-1, 120-2: Second integrated circuit

EE: modulation element

GL1: The first set of signal lines

GL2: The second set of signal lines

GL3: The third set of signal lines

GL4: The fourth set of signal lines

LC1~LC16: first signal line

LR1~LR6: second signal line

RA: action area

RB: surrounding area

S1: first side

S2: Second side

SB:Substrate

Claims (10)

An electronic device including: substrate; A plurality of first signal lines are provided on the substrate and divided into a first group of signal lines and a second group of signal lines; A plurality of second signal lines are provided on the substrate and interleaved with the plurality of first signal lines; and Two first integrated circuits, bonded to the substrate, each electrically connected to the first set of signal lines and the second set of signal lines; The first group of signal lines and the second group of signal lines are arranged in alternate rows. The electronic device as claimed in claim 1, wherein: The plurality of first signal lines is one of a data line and a scanning line, and The plurality of second signal lines is the other one of a data line and a scanning line. The electronic device according to claim 1, wherein the two first integrated circuits are one of a gate driving integrated circuit and a data driving integrated circuit. The electronic device according to claim 3, wherein the gate driving integrated circuit includes a level shifter circuit, a shift register circuit and a timing shifter circuit. The electronic device as described in claim 1 also includes: two second integrated circuits bonded to the substrate, The plurality of second signal lines are divided into a third group of signal lines and a fourth group of signal lines, wherein the two second integrated circuits are each electrically connected to the third set of signal lines and the fourth set of signal lines, and The third group of signal lines and the fourth group of signal lines are arranged in alternate rows. The electronic device as claimed in claim 5, wherein: the two first integrated circuits are disposed along the first side of the substrate, and The two second integrated circuits are disposed along at least one side of the substrate different from the first side. The electronic device according to claim 5, wherein the two first integrated circuits and the two second integrated circuits are respectively disposed along four different sides of the substrate. The electronic device of claim 5, wherein the timings of the corresponding signals provided by the two second integrated circuits are the same as each other. The electronic device as claimed in claim 5, wherein: The substrate includes an active area and a peripheral area, The two first integrated circuits and the two second integrated circuits are respectively disposed in the peripheral area, and The electronic device further includes a plurality of anti-static discharge components disposed in the peripheral area and surrounding the active area. A modulation device including: substrate; modulation components; A plurality of first signal lines, arranged on the substrate, divided into a first group of signal lines and a second group of signal lines, wherein one of the plurality of first signal lines is electrically connected to the modulation element; A plurality of second signal lines are provided on the substrate and are interleaved with the plurality of first signal lines, wherein one of the plurality of second signal lines is electrically connected to the modulation element; and two first integrated circuits, bonded to the substrate, each electrically connected to the first set of signal lines and the second set of signal lines, The first group of signal lines and the second group of signal lines are arranged in alternate rows.

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