CN116613123A

CN116613123A - Electronic device

Info

Publication number: CN116613123A
Application number: CN202211356110.2A
Authority: CN
Inventors: 蔡秀怡; 黄郁迪; 邱郁翔; 林宜宏
Original assignee: Innolux Display Corp
Current assignee: Innolux Corp
Priority date: 2022-02-17
Filing date: 2022-11-01
Publication date: 2023-08-18

Abstract

The present disclosure provides an electronic device including a substrate, a plurality of gate driving units, and a plurality of gate lines. The gate driving unit is disposed on the substrate. The gate line is disposed on the substrate. Each gate line is electrically connected to a corresponding gate driving unit. Each gate line is used for transmitting a respective frequency signal. The plurality of gate lines includes a first gate line and a second gate line. The frequency signal transferred on the first gate line and the frequency signal transferred on the second gate line have the same timing.

Description

Electronic device

Technical Field

The present disclosure relates to an electronic device having a gate driving unit.

Background

The present electronic device can integrate the antenna substrate to receive and transmit electromagnetic wave signals. The antenna substrate includes a plurality of antenna elements. The on state of the antenna element can be controlled by a thin film transistor element. The source driver chip and the gate driver chip, which are separately fabricated, are generally disposed in a peripheral region of the antenna substrate in a chip bonding (bonding) manner, so as to control the antenna unit to transmit and receive electromagnetic wave signals. The larger the number of antenna elements, the larger the receivable bandwidth, but the more chips are required. Has an effect on the cost and yield of the electronic device.

Disclosure of Invention

The disclosure provides an electronic device, which is provided with a grid driving unit and can reduce cost and improve yield.

In an embodiment of the present disclosure, the first gate line and the second gate line are not adjacent.

In an embodiment of the present disclosure, the electronic device further comprises a plurality of electronic units. The electronic unit is arranged on the substrate. Each of the electronic units is electrically connected to a corresponding gate driving unit through a corresponding gate line, respectively. Each gate driving unit is used for controlling a corresponding electronic unit.

In an embodiment of the present disclosure, each electronic unit is a modulation unit (modulator unit).

In an embodiment of the disclosure, the electronic unit is disposed in an active region of the substrate.

In an embodiment of the present disclosure, the plurality of gate driving units includes a first gate driving unit and a second gate driving unit. The first gate driving unit is electrically connected to the first gate line. The second gate driving unit is electrically connected to the second gate line. The first gate driving unit and the second gate driving unit are used for receiving a start signal.

In an embodiment of the present disclosure, the plurality of gate driving units are divided into a plurality of groups. The first gate driving unit and the second gate driving unit are the first gate driving units of different groups.

In an embodiment of the present disclosure, the frequency signal comprises a first frequency signal. The first gate driving unit and the second gate driving unit are used for receiving the first frequency signal.

In an embodiment of the present disclosure, the frequency signal includes a first frequency signal and a second frequency signal. The first gate driving unit is used for receiving a first frequency signal. The second gate driving unit is used for receiving a second frequency signal.

In an embodiment of the present disclosure, the electronic device further comprises a synchronization circuit. The synchronization circuit is electrically connected to the plurality of gate driving units and is used for outputting frequency signals.

In order to make the foregoing more readily understood, several embodiments are described in detail below with accompanying drawings.

Drawings

FIG. 1 shows a schematic diagram of an electronic device according to an embodiment of the disclosure;

fig. 2 shows a schematic diagram of the operation signals of the electronic device of the embodiment of fig. 1;

FIG. 3A shows a schematic overview of an electronic device according to another embodiment of the disclosure;

FIG. 3B shows a schematic diagram of an electronic device according to another embodiment of the disclosure;

fig. 4A shows a schematic overview of an electronic device of another embodiment of the present disclosure;

fig. 4B shows a schematic overview of an electronic device of another embodiment of the present disclosure;

FIG. 5 shows a schematic overview of an electronic device of another embodiment of the present disclosure;

FIG. 6A shows a schematic diagram of an electronic device according to another embodiment of the disclosure;

fig. 6B shows a schematic diagram of an electronic device according to another embodiment of the disclosure.

Detailed Description

The present disclosure may be understood by reference to the following detailed description taken in conjunction with the accompanying drawings, it being noted that, in order to facilitate the understanding of the reader and for the sake of brevity of the drawings, various drawings in the present disclosure depict only a portion of the electronic device and the specific elements of the drawings are not drawn to actual scale. In addition, the number and size of the elements in the drawings are illustrative only and are not intended to limit the scope of the present disclosure.

In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to …".

It should be understood that although the terms first, second, and third … may be used to describe various constituent elements, the constituent elements are not limited by this term. This term is used only to distinguish a single component element from other component elements within the specification. The same terms may not be used in the claims but instead the first, second, third … are substituted for the order in which the elements were recited in the claims. Thus, in the following description, a first component may be a second component in the claims.

In some embodiments of the present disclosure, terms such as "connected," "interconnected," and the like, with respect to joining, connecting, and the like, may refer to two structures being in direct contact, or may refer to two structures not being in direct contact, with other structures being disposed between the two structures, unless otherwise specified. And the term coupled, connected, may also include situations where both structures are movable, or where both structures are fixed. Furthermore, the term "coupled" includes any direct or indirect electrical connection.

The electronic device of the present disclosure may include a display device, an antenna device, a sensing device, a light emitting device, or a stitching device, but is not limited thereto. The electronic device may comprise a bendable or flexible electronic device. The electronic device may include an electronic component. The electronic device comprises, for example, a liquid crystal (liquid crystal) layer or a light emitting diode (Light Emitting Diode, LED). The electronic devices may include passive devices and active devices such as, but not limited to, capacitors, resistors, inductors, variable capacitors, filters, diodes, transistors (transistors), inductors, microelectromechanical system devices (MEMS), liquid crystal chips (liquid crystal chip), controllers (controllers), etc. The diode may comprise a light emitting diode or a photodiode. The light emitting diode may include, for example, an organic light emitting diode (organic light emitting diode, OLED), a sub-millimeter light emitting diode (mini LED), a micro LED, a quantum dot LED, a fluorescent (fluorescent), a phosphorescent (phosphor) or other suitable materials, or a combination thereof, but is not limited thereto. The sensor may include, for example, but not limited to, a capacitive sensor (capacitive sensors), an optical sensor (optical sensors), an electromagnetic sensor (electromagnetic sensors), a fingerprint sensor (fingerprint sensor, FPS), a touch sensor (touch sensor), an antenna (antenna), or a stylus (pen sensor), etc. The controller may include, for example, a timing controller (timing controller) or the like, but is not limited thereto. The disclosure will be described in the following with reference to an electronic device, but the disclosure is not limited thereto.

Reference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Fig. 1 shows a schematic diagram of an electronic device according to an embodiment of the disclosure. Fig. 2 shows a schematic overview of the operation signals of the electronic device of the embodiment of fig. 1. Referring to fig. 1 and 2, the electronic device 100 includes a substrate 110, a gate driving circuit 120, a source driving circuit 130, a plurality of electronic units 140, and a plurality of gate lines GL1, GL2, GL3, GL4. The gate driving circuit 120, the source driving circuit 130, the electronic unit 140, and the plurality of gate lines GL1, GL2, GL3, GL4 are disposed on the substrate 110. In fig. 1 and 2, the number of elements and signals is not intended to limit the present disclosure. In the present disclosure, the gate driving circuit 120 is distributed on one side of the electronic unit 140, but not limited thereto. In some embodiments, the gate driving circuit 120 may be distributed on two sides or more sides of the electronic unit 140, for example. In other embodiments, the gate driving circuit 120 and the source driving circuit 130 may be distributed on one side of the electronic unit 140, for example.

The gate driving circuit 120 includes a plurality of gate driving units 122_1, 122_2, 122_3, 122_4 disposed on the substrate 110. Each gate line is electrically connected to a corresponding gate driving unit. For example, the gate line GL1 is electrically connected to the gate driving unit 122_1, the gate line GL2 is electrically connected to the gate driving unit 122_2, the gate line GL3 is electrically connected to the gate driving unit 122_3, and the gate line GL4 is electrically connected to the gate driving unit 122_4. The gate driving circuit 120 is, for example, a GOP (gate on panel) circuit.

The operation signals of fig. 2 include a start signal STV, a reference frequency signal CLK, and frequency signals X1, X2, X3, X4, X5, X6, X7. Frequency signals X1, X2, X3, X4, X5, X6, X7. For example, it can be generated according to the reference frequency signal CLK. Each gate line is used for transmitting a respective frequency signal. For example, the gate line GL1 is used for transmitting the frequency signal X1, the gate line GL2 is used for transmitting the frequency signal X2, the gate line GL3 is used for transmitting the frequency signal X3, and the gate line GL4 is used for transmitting the frequency signal X4. The relationship of the remaining gate lines for delivering frequency signals can be analogized.

In the present embodiment, the frequency signal X1 transferred on the gate line GL1 (first gate line) and the frequency signal X4 transferred on the gate line GL4 (second gate line) have the same timing, and the gate line GL1 and the gate line GL4 are not adjacent. That is, the plurality of gate lines GL1, GL2, GL3, GL4 includes a first gate line GL1 and a second gate line GL4. The frequency signal X1 transferred on the first gate line GL1 and the frequency signal X4 transferred on the second gate line GL4 have the same timing. The first and second gate lines GL1 and GL4 are not adjacent.

Each of the electronic units is electrically connected to a corresponding gate driving unit through a corresponding gate line, respectively. Each gate driving unit is used for controlling a corresponding electronic unit. For example, the electronic units 140 of the first row (row) are electrically connected to the gate driving unit 122_1 through the gate line GL1, and the gate driving unit 122_1 is used for controlling the electronic units 140 of the first row. The electronic units 140 of the second row are electrically connected to the gate driving unit 122_2 through the gate line GL2, and the gate driving unit 122_2 is used to control the electronic units 140 of the second row. The electronic units 140 of the third row are electrically connected to the gate driving unit 122_3 through the gate line GL3, and the gate driving unit 122_3 is used to control the electronic units 140 of the third row. The fourth row of electronic units 140 is electrically connected to the gate driving unit 122_4 through the gate line GL4, and the gate driving unit 122_4 is used for controlling the fourth row of electronic units 140. The electronic unit 140 is disposed in the active region 112 of the substrate 110. Each electronic unit is a modulation unit (modulator unit). The modulation unit may include a capacitor and/or a diode, etc. for modulating the frequency of the electromagnetic wave input from the electronic device.

Fig. 3A shows a schematic diagram of an electronic device according to another embodiment of the disclosure. Referring to fig. 3A, the electronic device 100 further includes a synchronization circuit 150. The synchronization circuit 150 is electrically connected to the gate driving units 122_1, 122_2, 122_3. The synchronization circuit 150 is used for outputting the clock signals CK1, CK2, CK3 to the gate driving units 122_1, 122_2, 122_3, respectively. That is, the clock signal of the present embodiment includes a first clock signal CK1 and a second clock signal CK2. The first gate driving unit 122_1 is configured to receive the first clock signal CK1. The second gate driving unit 122_2 is for receiving a second clock signal CK2 different from the first clock signal CK1. In the present embodiment, the synchronization circuit 150 outputs two or more clock signals CK1, CK2, CK3 to the gate driving units 122_1, 122_2, 122_3 to drive the gate lines GL1, GL2, GL3, so that at least two non-adjacent gate lines among the gate lines GL1, GL2, GL3 are turned on (turn on) at the same time. Fig. 3A is only a schematic diagram, and the gate lines GL1, GL2, GL3 are, for example, non-adjacent gate lines.

Fig. 3B shows a schematic diagram of an electronic device according to another embodiment of the disclosure. Referring to fig. 3B, the synchronization circuit 150 outputs clock signals CK1, CK2, CK3, CK1B, CK, B, CK B. The clock signals CK1, CK2, CK3 are used to turn on the corresponding gate lines. The clock signal CK1B, CK2B, CK B is used to turn off (turn off) the corresponding gate line. In the present embodiment, the electronic device 100 includes a plurality of gate driving units, for example, 18 gate driving units, which are respectively coupled to the gate lines GL1, GL2, GL3, GL4, GL5, GL6, GL7, GL8, GL9, GL10, GL11, GL12, GL13, GL14, GL15, GL16, GL17, and GL18, and the number thereof is not limited to the disclosure.

The gate driving units are divided into a plurality of groups GOP1, GOP2, GOP3. The first gate driving unit 322_1 and the second gate driving unit 322_2 are the first gate driving units of different groups GOP1, GOP 2. The first gate driving unit 322_1 is electrically connected to the first gate line GL1. The second gate driving unit 322_2 is electrically connected to the second gate line GL7. The first gate driving unit 322_1 and the second gate driving unit 322_2 are for receiving the start signal STV. The start signal STV is used to make each group start to perform a scanning operation. The frequency signal CK1 transferred on the first gate line GL1 and the frequency signal CK2 transferred on the second gate line GL7 have the same timing.

In the present embodiment, the number of groups, the number of gate driving units in each group and the number of frequency signals are only used for illustration, and are not used for limiting the disclosure. In addition, the layout of the wires between the synchronization circuit and the gate driving unit is not used to limit the disclosure.

Fig. 4A shows a schematic overview of an electronic device according to another embodiment of the disclosure. Referring to fig. 3A and fig. 4A, the electronic device 100 of fig. 4A is similar to the electronic device 100 of fig. 3A, and the difference between the two is that the synchronization circuit 150 is not required to be additionally arranged in the present embodiment, but the different gate driving units 122_1, 122_2, 122_3 are connected through the clock signal CK1, so that a plurality of driving units are short-circuited. That is, the frequency signal of the present embodiment includes the first frequency signal CK1. The first gate driving unit 122_1 and the second gate driving unit 122_2 are configured to receive the same first clock signal CK1. In the present embodiment, the clock signal CK1 is output to the gate driving units 122_1, 122_2, 122_3 to drive the gate lines GL1, GL2, GL3, such that at least two non-adjacent gate lines among the gate lines GL1, GL2, GL3 are turned on simultaneously. Fig. 4A is only a schematic diagram, and the gate lines GL1, GL2, GL3 are, for example, non-adjacent gate lines.

Fig. 4B shows a schematic overview of an electronic device according to another embodiment of the disclosure. Referring to fig. 4B, a group of clock signals CK1, CK1B connects different gate driving unit groups GOP1, GOP2, GOP3, so that the different driving unit groups are shorted. The frequency signal CK1 is used to turn on the corresponding gate line. The frequency signal CK1B is used to turn off the corresponding gate line. In the present embodiment, the electronic device 100 includes a plurality of gate driving units, for example, 15 gate driving units, which are respectively coupled to the gate lines GL1, GL2, GL3, GL4, GL5, GL6, GL7, GL8, GL9, GL10, GL11, GL12, GL13, GL14, and GL15, and the number thereof is not limited to the disclosure. In this embodiment, the number of gate driving units in each group is different. The gate driving units are divided into a plurality of groups GOP1, GOP2, GOP3. The first gate driving unit 322_1 and the second gate driving unit 322_2 are the first gate driving units of different groups GOP1, GOP 2. The first gate driving unit 322_1 is electrically connected to the first gate line GL1. The second gate driving unit 322_2 is electrically connected to the second gate line GL7. The first gate driving unit 322_1 and the second gate driving unit 322_2 are for receiving the start signal STV. The start signal STV is used to make each group start to perform a scanning operation. The frequency signal CK1 transferred on the first gate line GL1 and the frequency signal CK1 transferred on the second gate line GL7 have the same timing.

Fig. 5 shows a schematic diagram of an electronic device according to another embodiment of the disclosure. Referring to fig. 5, the synchronization circuit 150 is not required in the present embodiment. The present embodiment further shows that there are multiple sets of clock signals (e.g., clock signals CK1, CK1B and clock signals CK2, CK 2B), and each set of clock signals can be shorted to non-adjacent gate driving cell groups. For example, the clock signal CK1 connects the gate driving unit groups GOP1 and GOP3, and the gate driving unit groups GOP1 and GOP3 are shorted together, so that the gate lines GL1 and GL13 have the same timing. Similarly, the clock signal CK2 connects the gate driving unit groups GOP2 and GOP4, and the gate driving unit groups GOP2 and GOP4 are shorted together, so that the gate line GL7 and the gate line GL19 have the same timing.

Specifically, the clock signals CK1, CK2 are used to turn on the corresponding gate lines. The frequency signal CK1B, CK B is used to turn off the corresponding gate line. In this embodiment, the electronic device 100 includes a plurality of gate driving units, for example 24, respectively coupled to the gate lines GL1, GL2, GL3, GL4, GL5, GL6, GL7, GL8, GL9, GL10, GL11, GL12, GL13, GL14, GL15, GL16, GL17, GL18, GL19, GL20, GL21, GL22, GL23, GL24, the number of which is not limited to the present disclosure. The gate driving units are divided into a plurality of groups GOP1, GOP2, GOP3, GOP4. The frequency signal CK1 transferred on the first gate line GL1 and the frequency signal CK1 transferred on the second gate line GL13 have the same timing. Further, the frequency signal CK2 transferred on the first gate line GL7 and the frequency signal CK2 transferred on the second gate line GL19 have the same timing.

Fig. 6A shows a schematic diagram of an electronic device according to another embodiment of the disclosure. Referring to fig. 6A, the electronic device 100 of fig. 6A takes 6 frequency signals, 6 gate driving units and 6 gate lines as an example, but the number is not limited to this disclosure. The present embodiment can make the frequency signals transferred on the non-adjacent gate lines have the same timing by shorting the transfer paths of the frequency signals.

For example, the frequency signal CK1 transferred on the first gate line GL1 and the frequency signal CK4 transferred on the second gate line GL19 may have the same timing by shorting the transfer paths of the frequency signals CK1, CK4, wherein the first gate line GL1 and the second gate line GL19 are not adjacent. Similarly, the frequency signals transferred on the non-adjacent gate lines GL7, GL25 may have the same timing by shorting the transfer paths of the frequency signals CK2, CK 5; and the frequency signals transferred on the non-adjacent gate lines GL13, GL31 may have the same timing by shorting the transfer paths of the frequency signals CK3, CK 6.

Fig. 6B shows a schematic diagram of an electronic device according to another embodiment of the disclosure. Referring to fig. 6B, the present embodiment makes the clock signals CK1, CK4 transferred on the non-adjacent gate lines GL1, GL19 have the same timing by shorting the transfer paths of the clock signals CK1, CK 4.

In summary, in the embodiments of the present disclosure, the gate driving unit for controlling the electronic unit can be manufactured on the substrate by a photolithography process, so as to reduce yield loss caused by bonding the chip on the substrate, and reduce cost of the product because the gate driving chip is not required to be manufactured additionally.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. An electronic device, comprising:

a substrate;

a plurality of gate driving units disposed on the substrate; and

a plurality of gate lines disposed on the substrate, each of the plurality of gate lines being electrically connected to a corresponding one of the plurality of gate driving units, and each of the plurality of gate lines being for transmitting a respective frequency signal,

wherein the plurality of gate lines includes a first gate line and a second gate line, and the frequency signal transferred on the first gate line and the frequency signal transferred on the second gate line have the same timing.

2. The electronic device of claim 1, wherein the first gate line and the second gate line are not adjacent.

3. The electronic device of claim 1, further comprising:

and a plurality of electronic units disposed on the substrate, wherein each of the plurality of electronic units is electrically connected to a corresponding one of the plurality of gate driving units through a corresponding one of the plurality of gate lines, and each of the plurality of gate driving units is configured to control a corresponding one of the plurality of electronic units.

4. The electronic device of claim 3, wherein each of the plurality of electronic units is a modulation unit.

5. The electronic device of claim 3, wherein the plurality of electronic units are disposed in an active region of the substrate.

6. The electronic device of claim 1, wherein the plurality of gate drive units comprises:

a first gate driving unit electrically connected to the first gate line; and

a second gate driving unit electrically connected to the second gate line,

the first gate driving unit and the second gate driving unit are used for receiving a start signal.

7. The electronic device of claim 6, wherein the plurality of gate driving units are divided into a plurality of groups, and the first gate driving unit and the second gate driving unit are first gate driving units of different groups.

8. The electronic device of claim 1, wherein the frequency signal comprises a first frequency signal, and the first gate drive unit and the second gate drive unit are configured to receive the first frequency signal.

9. The electronic device of claim 1, wherein the frequency signal comprises a first frequency signal and a second frequency signal, and the first gate drive unit is configured to receive the first frequency signal and the second gate drive unit is configured to receive the second frequency signal.

10. The electronic device of claim 1, further comprising:

and a synchronization circuit electrically connected to the plurality of gate driving units and configured to output the frequency signal.