TW202334834A - Semiconductor device and data outputting method - Google Patents

Abstract

A semiconductor device and a data outputting method are provided. The semiconductor device includes a data temporary storage circuit, a control circuit and a data output circuit. The control circuit outputs a first operation signal and a second operation signal according to a previous data and a current data. The data output circuit includes a first lifting circuit and a second lifting circuit. The first lift circuit includes a first pull-up transistor and a first pull-down transistor. The second lift circuit includes a second pull-up transistor and a second pull-down transistor. The second lift circuit obtains a second pull-up control signal and a second pull-down control signal according to the first operation signal and the second operation signal, so as to turn off or turn on the second pull-up transistor and the second pull-down voltage at the same time, so that a leakage current is suppressed.

Description

Semiconductor device and data output method thereof

The present disclosure relates to an electronic device and a processing method thereof, and in particular to a semiconductor device and a data output method thereof.

In semiconductor devices, whether it is a memory or a processing chip, it is usually necessary to output data through a data output circuit. The data output circuit can pull the output voltage up or down to output 1 or 0.

However, during the process of raising or lowering the output voltage, leakage current such as crowbar current often occurs. In order to obtain a high data slew rate in the output of a high-speed semiconductor device, a higher drive current is usually required, which will make the leakage current situation more serious.

These leakage currents not only increase circuit power consumption, but also affect the accuracy of data output. Researchers are working to improve the leakage currents such as crowbar current generated by semiconductor devices to ensure the quality of semiconductor devices.

This disclosure relates to a semiconductor device and its data output method. Through the design of the lifting circuit, part of the pulling-up transistors and the pulling-down transistors are not turned off or on simultaneously, and the leakage current of the crowbar current can be effectively suppressed. . In this way, leakage currents such as crowbar current in the semiconductor device can be improved and the quality of the semiconductor device can be ensured.

According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a data temporary storage circuit, a control circuit and a data output circuit. The data temporary storage circuit is used to store at least one previous data and one current data. The control circuit is connected to the data temporary storage circuit. The control circuit outputs a first operation signal and a second operation signal based on at least the previous data and the current data. The data output circuit is connected to the control circuit. The data output circuit includes a first lifting circuit and a second lifting circuit. The first lifting circuit includes a first pulling up transistor and a first pulling down transistor. The first boost circuit obtains a first pull-up control signal and a first pull-down control signal based on the current data to synchronously close or turn on the first pull-up transistor and the first pull-down transistor, so that an output voltage is pulled up Raise or pull lower. The second lifting circuit includes a second pulling up transistor and a second pulling down transistor. The second lift circuit obtains a second pull-up control signal and a second pull-down control signal according to the first operation signal and the second operation signal to asynchronously close or open the second pull-up transistor and the second pull-down transistor. crystal so that a leakage current is suppressed.

According to another aspect of the present disclosure, a data output method of a semiconductor device is provided. The data output method of the semiconductor device includes the following steps. Get at least one previous data and one current data. At least based on the previous data and the current data, a first operation signal and a second operation signal are output. According to the current data, a first pull-up control signal and a first pull-down control signal are obtained to synchronously turn on or off a first pull-up transistor and a first pull-down transistor, so that an output voltage is pulled up or Pull low. According to the first operation signal and the second operation signal, a second pull-up control signal and a second pull-down control signal are obtained to asynchronously close or open a second pull-up transistor and a second pull-down transistor, So that a leakage current is suppressed.

In order to have a better understanding of the above and other aspects of the present disclosure, embodiments are given below and described in detail with reference to the accompanying drawings:

Please refer to FIG. 1A , which illustrates a schematic diagram of a data output circuit 930 according to an embodiment. The data output circuit 930 at least includes a pull-up transistor PMO and a pull-down transistor NMO. The pull-up transistor PM0 is, for example, a PMOS transistor, and the pull-down transistor NMO is, for example, an NMOS transistor. The pull-up transistor PM0 and the pull-down transistor NM0 are connected in series. The pull-up transistor PM0 is connected to a working voltage VDD, and the pull-down transistor NM0 is connected to a ground voltage GND. The pull-up transistor PM0 is controlled by the pull-up control signal pu0 and is turned on or off; the pull-down transistor NM0 is controlled by the pull-down control signal pd0 and is turned on or off. When the pull-up transistor PM0 is turned on and the pull-down transistor NM0 is turned off, the output voltage PAD0 is pulled up to represent 1; when the pull-up transistor PM0 is turned off and the pull-down transistor NM0 is turned on, the output voltage PAD0 is pulled down, to represent 0.

Please refer to Figure 1B, which shows the relationship between the output voltage PAD0 and the pull-up control signals pu0 and pd0. When the pull-up control signal pu0 and the pull-down control signal pd0 are both 0, the output voltage PAD0 is 1; when the pull-up control signal pu0 and the pull-down control signal pd0 are both 1, the output voltage PAD0 is 0.

Please refer to FIG. 2A , which illustrates a schematic diagram of a semiconductor device 9000 according to an embodiment. The semiconductor device 9000 is, for example, a memory device or a processing device. The semiconductor device 9000 includes a data temporary storage circuit 910, a data multiplexing circuit 920 and a data output circuit 930. For example, the data temporary storage circuit 910 outputs data D0 such as bits b0 to b31 to the data multiplexing circuit 920 . The data multiplexing circuit 920 outputs the bits b0 to b31 of the data D0 to the data output circuit 930 through several cycles CL according to the clock signal C0.

Please refer to Figure 2B, which illustrates the relationship between the output voltage PAD0, the pull-up control signals pu0, pd0 and the clock signal C0. In an embodiment using a falling edge trigger, when the clock signal C0 falls, the signal transition is triggered.

At time point T21, when the output voltage PAD0 needs to change from 1 to 0, both the pull-up control signal pu0 and the pull-down control signal pd0 need to change from 0 to 1 to turn off the pull-up transistor PM0 and turn on the pull-down transistor NM0. . However, the researchers found that it takes a certain amount of time for the pull-up transistor PM0 to turn off and the pull-down transistor NM0 to turn on. There will be a short period of time when both the pull-up transistor PM0 and the pull-down transistor NM0 are in the on state. At this time, a pry will occur. The leakage current CC of crowbar current.

At time point T22, when the output voltage PAD0 needs to change from 0 to 1, both the pull-up control signal pu0 and the pull-down control signal pd0 need to change from 1 to 0 to turn on the pull-up transistor PM0 and turn off the pull-down transistor NM0. . However, the researchers found that it takes a certain amount of time to turn on the pull-up transistor PM0 and turn off the pull-down transistor NM0. There will be a short period of time when both the pull-up transistor PM0 and the pull-down transistor NM0 are in the on state. At this time, a pry will occur. The stick current is the leakage current CC.

Please refer to FIG. 3A , which illustrates a schematic diagram of a semiconductor device 1000 according to an embodiment. The semiconductor device 1000 includes a data temporary storage circuit 110, a data multiplexing circuit 120, a data output circuit 130 and a control circuit 140. The data multiplexing circuit 120 will divide the data D0 into several cycles CL according to the clock signal C0 and output it to the data output circuit 130. Therefore, the data temporary storage circuit 110 stores the previous data D_n-1 and D_n-1 that are expected to be output at different time points. A current data D_n (or a signal equivalent to the previous data D_n-1 and the current data D_n). In another embodiment, the data temporary storage circuit 110 further stores the next data D_n+1.

The control circuit 140 is connected to the data temporary storage circuit 110 . The control circuit 140 outputs a first operation signal ENZ1 and a second operation signal ENZ2 based on at least the previous data D_n-1 and the current data D_n.

The data output circuit 130 is connected to the control circuit 140 and the data multiplexing circuit 120 . The data output circuit 130 includes a first lifting circuit 131 and a second lifting circuit 132. The first lifting circuit 131 pulls up the output voltage PAD0 or pulls down the output voltage PAD0 according to the current data D_n to be output. The second lifting circuit 132 suppresses the leakage current CC according to the first operation signal ENZ1 and the second operation signal ENZ2.

Please refer to Figure 3B, which illustrates the operation of the first lifting circuit 131 and the second lifting circuit 132. The first lifting circuit 131 includes a first pulling up transistor PM1 and a first pulling down transistor NM1. The first pull-up transistor PM1 is controlled by the first pull-up control signal pu1 and is turned on or off; the first pull-down transistor NM1 is controlled by the first pull-down control signal pd1 and is turned on or off.

At time point T31, when the previous data D_n-1 is 1 and the current data D_n is 0, the output voltage PAD0 needs to change from 1 to 0. At this time, both the first pull-up control signal pu1 and the first pull-down control signal pd1 need to change from 0 to 1 to synchronously turn off the first pull-up transistor PM1 and turn on the first pull-down transistor NM1.

At time point T32, when the previous data D_n-1 is 0 and the current data D_n is 1, the output voltage PAD0 needs to change from 0 to 1. At this time, both the first pull-up control signal pu1 and the first pull-down control signal pd1 need to change from 1 to 0 to simultaneously turn on the first pull-up transistor PM1 and turn off the first pull-down transistor NM1.

The second boost circuit 132 includes a second pull-up transistor PM2 and a second pull-down transistor NM2. The second pull-up transistor PM2 is controlled by the second pull-up control signal pu2 and is turned on or off; the second pull-down transistor NM2 is controlled by the second pull-down control signal pd2 and is turned on or off.

At time point T31, when the previous data D_n-1 is 1 and the current data D_n is 0, the output voltage PAD0 needs to change from 1 to 0. At this time, the second pull-up control signal pu2 has been turned to 1 in advance, and the second pull-up transistor PM2 is turned off first. Only the second pull-down control signal pd2 needs to change from 0 to 1 to turn on the second pull-down transistor NM2. That is to say, the second pull-up transistor PM2 and the second pull-down transistor NM2 are not turned off or on synchronously.

At time point T32, when the previous data D_n-1 is 0 and the current data D_n is 1, the output voltage PAD0 needs to change from 0 to 1. At this time, the second pull-down control signal pd2 has been turned to 0 in advance, and the second pull-down transistor NM2 is turned off first. Only the second pull-up control signal pu2 needs to change from 1 to 0 to turn on the second pull-up transistor PM2. That is to say, the second pull-up transistor PM2 and the second pull-down transistor NM2 are not turned off or on synchronously.

Since the second pull-up transistor PM2 and the second pull-down transistor NM2 are not turned off or on synchronously, the leakage current CC of the crowbar current can be effectively suppressed.

Please refer to FIG. 4 , which illustrates a detailed structure of a semiconductor device 1000 according to an embodiment. The detailed structure of the data output circuit 130 is described below. The first lifting circuit 131 is a combination of a logic circuit, a pulling up circuit and a pulling down circuit. The first lifting circuit 131 includes the first pulling up transistor PM1, the first pulling down transistor NM1, a first NAND gate (NAND) NA1 and a first NOR gate (NOR) NO1. A gate electrode of the first pull-up transistor PM1 is connected to the first inverse-AND gate NA1. A gate electrode of the first pull-down transistor NM1 is connected to the first inverse-OR gate NO1.

The second lifting circuit 132 is a combination of a logic circuit, a pulling up circuit and a pulling down circuit. The second boost circuit 132 includes the second pull-up transistor PM2, the second pull-down transistor NM2, a second inverse-AND gate NA2 and a second inverse-OR gate NO2. A gate electrode of the second pull-up transistor PM2 is connected to the second inverse-AND gate NA2. A gate electrode of the second pull-down transistor NM2 is connected to the second inverse-OR gate NO2.

The first pull-up transistor PM1 and the first pull-down transistor NM1 are connected in series at a first node Nd1, and the second pull-up transistor PM2 and the second pull-down transistor NM2 are connected in series at a second node Nd2. The first node Nd1 and the second node Nd2 are connected to the output terminal Nd12.

The control circuit 140 includes a shift register 143, a first multiplexer 141 and a second multiplexer 142. The shift register 143 of this embodiment is used to output the previous data D_n-1 and the current data D_n.

The first multiplexer 141 is connected to the shift register 143 . The first multiplexer 141 outputs the first operation signal ENZ1 based on the previous data D_n-1 and the current data D_n.

The second multiplexer 142 is connected to the shift register 143 . The second multiplexer 142 outputs the second operation signal ENZ2 based on the previous data D_n-1 and the current data D_n.

Please refer to Table 1 below. In this embodiment, the control circuit 140 can determine the first operation signal ENZ1 and the second operation signal ENZ2 based on the previous data D_n-1 and the current data D_n. The second lift circuit 132 can determine the second pull-up control signal pu2 and the second pull-down control signal pd2 based on the first operation signal ENZ1 and the second operation signal ENZ2. After the second pull-up control signal pu2 and the second pull-down control signal pd2 are respectively input to the second pull-up transistor PM2 and the second pull-down transistor NM2, the second pull-up transistor PM2 and the second pull-up transistor PM2 can be made low. Transistor NM2 is turned on or off asynchronously. Input to control circuits 140, 240 Input to the second lifting circuit 132 Input to the second pull-up transistor PM2 and the second pull-down transistor NM2 D_n-1 D_n ENZ1 ENZ2 pu2 pd2 0 0 0 1 1 0 0 1 1 1 0 0 1 0 0 0 1 1 1 1 0 1 1 0 Table I

Please refer to Figures 4 to 6 and Table 1. Figure 5 illustrates a flow chart of a data output method of the semiconductor device 1000 according to an embodiment. Figure 6 illustrates each step of Figure 5. As shown in Figure 4, in step S510, the control circuit 140 obtains the previous data D_n-1 and the current data D_n. There is a period CL between the previous data D_n-1 and the current data D_n.

For example, as shown in Figure 6, at time point T61, the previous data D_n-1 and the current data D_n are 1 and 0 respectively. At time point T62, the previous data D_n-1 and the current data D_n are 0 and 0 respectively. At time point T63, the previous data D_n-1 and the current data D_n are 0 and 1 respectively. At time point T64, the previous data D_n-1 and the current data D_n are 1 and 1 respectively. At time point T65, the previous data D_n-1 and the current data D_n are 1 and 0 respectively.

Next, as shown in Figure 4 and Table 1, in step S520, the control circuit 140 outputs the first operation signal ENZ1 and the second operation signal ENZ2 according to the sequence relationship between the previous data D_n-1 and the current data D_n.

For example, as shown in Figure 6, at time point T61, the previous data D_n-1 and the current data D_n are 1 and 0 respectively. Lookup table 1 can obtain the first operation signal ENZ1 and the second operation signal ENZ2 as 0 and 0 respectively.

At time point T62, the previous data D_n-1 and the current data D_n are 0 and 0 respectively. Lookup table 1 can obtain the first operation signal ENZ1 and the second operation signal ENZ2 as 0 and 1 respectively.

At time point T63, the previous data D_n-1 and the current data D_n are 0 and 1 respectively. Lookup table 1 can obtain the first operation signal ENZ1 and the second operation signal ENZ2 as 1 and 1 respectively.

At time point T64, the previous data D_n-1 and the current data D_n are 1 and 1 respectively. Lookup table 1 can obtain the first operation signal ENZ1 and the second operation signal ENZ2 as 0 and 1 respectively.

At time point T65, the previous data D_n-1 and the current data D_n are 1 and 0 respectively. Lookup table 1 can obtain the first operation signal ENZ1 and the second operation signal ENZ2 as 0 and 0 respectively.

Then, in step S530, the first lifting circuit 131 obtains the first pull-up control signal pu1 and the first pull-down control signal pd1 according to the current data D_n, so as to synchronously turn on or off the first pull-up transistor PM1 and the first pull-down transistor PM1. Transistor NM1 causes the output voltage PAD0 to be pulled up or down.

As shown in Figure 4, the current data D_n and an operating voltage VDD are input to the first inverse-AND gate NA1 to output the first pull-up control signal pu1. The operating voltage VDD is 1. Since the operating voltage VDD is 1, the first pull-up control signal pu1 is the opposite value of the current data D_n.

As shown in Figure 4, the current data D_n and a ground voltage GND are input to the first inverse-OR gate NO1 to output the first pull-down control signal pd1. The ground voltage GND is 0. Since the ground voltage GND is 0, the first pull-down control signal pd1 is the opposite value of the current data D_n.

When the current data D_n is 1, the first pull-up control signal pu1 is 0 and the first pull-down control signal pd1 is 0 to simultaneously turn on the first pull-up transistor PM1 and turn off the first pull-down transistor NM1, so that the output voltage PAD0 is pulled high.

When the current data D_n is 0, the first pull-up control signal pu1 is 1 and the first pull-down control signal pd1 is 1 to synchronously turn off the first pull-up transistor PM1 and turn on the first pull-down transistor NM1, so that the output voltage PAD0 is pulled low.

As shown in Figure 6, at time point T61, the current data D_n is 0, and the first pull-up control signal pu1 and the first pull-down control signal pd1 both become 1 to synchronously turn off and turn on the first pull-up transistor PM1 The first pull-down transistor NM1 causes the output voltage PAD0 to be pulled low.

At time point T62, the current data D_n is 0, and the first pull-up control signal pu1 and the first pull-down control signal pd1 are still 1, so as to synchronously turn off the first pull-up transistor PM1 and turn on the first pull-down transistor NM1. This causes the output voltage PAD0 to be pulled low.

At time point T63, the current data D_n is 1, and the first pull-up control signal pu1 and the first pull-down control signal pd1 both become 0 to simultaneously turn on the first pull-up transistor PM1 and turn off the first pull-down transistor NM1 , causing the output voltage PAD0 to be pulled up.

At time point T64, the current data D_n is 1, and the first pull-up control signal pu1 and the first pull-down control signal pd1 both become 0 to simultaneously turn on the first pull-up transistor PM1 and turn off the first pull-down transistor NM1 , causing the output voltage PAD0 to be pulled up.

At time point T65, the current data D_n is 0, and the first pull-up control signal pu1 and the first pull-down control signal pd1 both become 1 to synchronously turn off the first pull-up transistor PM1 and turn on the first pull-down transistor NM1 , causing the output voltage PAD0 to be pulled low.

Next, in step S540, the second lifting circuit 132 obtains the second pull-up control signal pu2 and the second pull-down control signal pd2 according to the first operation signal ENZ1 and the second operation signal ENZ2, so as to asynchronously close or open the second pull-up control signal pu2. The pull-up transistor PM2 and the second pull-down transistor NM2 suppress the leakage current CC.

As shown in Figure 4, the current data D_n and the first operation signal ENZ1 are input to the second inverse-AND gate NA2 to output the second pull-up control signal pu2.

The current data D_n and the second operation signal ENZ2 are input to the second inverse-OR gate NO2 to output the second pull-down control signal pd2.

As shown in Figure 6, at time point T61, the previous data D_n-1 and the current data D_n are 1 and 0 respectively. Lookup table 1 can obtain the first operation signal ENZ1 and the second operation signal ENZ2 as 0 and 0 respectively. At this time, as shown in Figure 4, the current data D_n is 0 and the first operation signal ENZ1 is 0, the second pull-up control signal pu2 output by the second inverter gate NA2 is 1; the current data D_n is 0 and the second The operation signal ENZ2 is 0, and the second pull-down control signal pd2 of the second inverter NO2 output is 1. The second pull-up transistor PM2 is turned off and the second pull-down transistor NM2 is turned on, so that the output voltage PAD0 is pulled down.

At time point T62, the previous data D_n-1 and the current data D_n are 0 and 0 respectively. Lookup table 1 can obtain the first operation signal ENZ1 and the second operation signal ENZ2 as 0 and 1 respectively. At this time, as shown in Figure 4, the current data D_n is 0 and the first operation signal ENZ1 is 0, the second pull-up control signal pu2 output by the second inverter gate NA2 is 1; the current data D_n is 0 and the second The operation signal ENZ2 is 1, and the second pull-down control signal pd2 of the second inverter NO2 output is 0. The second pull-up transistor PM2 is turned off and the second pull-down transistor NM2 is turned off, so that the leakage current CC is suppressed.

At time point T63, the previous data D_n-1 and the current data D_n are 0 and 1 respectively. Lookup table 1 can obtain the first operation signal ENZ1 and the second operation signal ENZ2 as 1 and 1 respectively. At this time, as shown in Figure 4, the current data D_n is 1 and the first operation signal ENZ1 is 1, the second pull-up control signal pu2 output by the second inverter gate NA2 is 0; the current data D_n is 1 and the second The operation signal ENZ2 is 1, and the second pull-down control signal pd2 of the second inverter NO2 output is 0. The second pull-up transistor PM2 is turned on and the second pull-down transistor NM2 is turned off, so that the output voltage PAD0 is pulled up.

At time point T64, the previous data D_n-1 and the current data D_n are 1 and 1 respectively. Lookup table 1 can obtain the first operation signal ENZ1 and the second operation signal ENZ2 as 0 and 1 respectively. At this time, as shown in Figure 4, the current data D_n is 1 and the first operation signal ENZ1 is 0, the second pull-up control signal pu2 output by the second inverter gate NA2 is 1; the current data D_n is 1 and the second The operation signal ENZ2 is 1, and the second pull-down control signal pd2 of the second inverter NO2 output is 0. The second pull-up transistor PM2 is turned off and the second pull-down transistor NM2 is turned off, so that the leakage current CC is suppressed.

At time point T65, the previous data D_n-1 and the current data D_n are 1 and 0 respectively. Lookup table 1 can obtain the first operation signal ENZ1 and the second operation signal ENZ2 as 0 and 0 respectively. At this time, as shown in Figure 4, the current data D_n is 0 and the first operation signal ENZ1 is 0, the second pull-up control signal pu2 output by the second inverter gate NA2 is 1; the current data D_n is 0 and the second The operation signal ENZ2 is 0, and the second pull-down control signal pd2 of the second inverter NO2 output is 1. The second pull-up transistor PM2 is turned off and the second pull-down transistor NM2 is turned on, so that the output voltage PAD0 is pulled down.

As shown in Figure 6, at time point T61, when the second pull-down transistor NM2 is turning on, the second pull-up transistor PM2 remains unchanged.

At time point T62, when the second pull-down transistor NM2 is turning off, the second pull-up transistor PM2 remains unchanged.

At time point T63, when the second pull-up transistor PM2 is turning on, the second pull-down transistor NM2 remains unchanged.

At time point T64, when the second pull-up transistor PM2 is turning off, the second pull-down transistor NM2 remains unchanged.

At time point T65, when the second pull-down transistor NM2 is turning on, the second pull-up transistor PM2 remains unchanged.

That is to say, when one of the second pull-up transistor PM2 and the second pull-down transistor NM2 is turned off, the other one of the second pull-up transistor PM2 and the second pull-down transistor NM2 remains unchanged. . When one of the second pull-up transistor PM2 and the second pull-down transistor NM2 is turned on, the other one of the second pull-up transistor PM2 and the second pull-down transistor NM2 remains unchanged.

In addition, as shown in FIG. 6 , during the time points T62 to T63, the second pull-down transistor NM2 is first turned off, and the second pull-up transistor PM2 is turned on again.

During the time points T64 to T65, the second pull-up transistor PM2 is first turned off, and the second pull-down transistor NM2 is turned on again.

That is to say, one of the second pull-up transistor PM2 and the second pull-down transistor NM2 is turned off first, and the other one of the second pull-up transistor PM2 and the second pull-down transistor NM2 is turned on again.

According to the above embodiment, the semiconductor device 1000 uses the design of the second lift circuit 132 so that the second pull-up transistor PM2 and the second pull-down transistor NM2 are not turned off or on simultaneously, and the leakage current CC of the crowbar current can be effectively eliminated. inhibition. In this way, the occurrence of leakage current CC such as crowbar current in the semiconductor device can be improved and the quality of the semiconductor device can be ensured.

In another embodiment, the interval between the previous data D_n-1 and the current data D_n may be half a period. Please refer to FIG. 7 , which illustrates a schematic diagram of a semiconductor device 2000 according to another embodiment. The shift register 243 of the control circuit 240 of the semiconductor device 2000 receives the clock signals C0 and C0b. The clock signal C0 is the complementary signal of the clock signal C0b. In the embodiment using a falling edge trigger, when the clock signal C0 or the clock signal C0b falls, the signal conversion will be triggered. Therefore, the interval between the previous data D_n-1 and the current data D_n input to the control circuit 240 may be half a period. In one embodiment, the clock signal C0b may be a clock signal with a frequency 2, 4, 6 or 8 times the frequency of the clock signal C0. In another embodiment, the clock signal C0 and the clock signal C0b may also be two clock signals with a phase difference of 1/2, 1/4 or 1/8 period.

Please refer to FIG. 8 , which illustrates an example of the data output method of the semiconductor device 2000 in FIG. 7 . At time point T81, the previous data D_n-1 and the current data D_n of the half-cycle CL interval are 1 and 0 respectively. Lookup table 1 can obtain the first operation signal ENZ1 and the second operation signal ENZ2 as 0 and 0 respectively. At this time, as shown in Figure 7, the current data D_n is 0 and the first operation signal ENZ1 is 0, the second pull-up control signal pu2 output by the second inverter gate NA2 is 1; the current data D_n is 0 and the second The operation signal ENZ2 is 0, and the second pull-down control signal pd2 of the second inverter NO2 output is 1. The second pull-up transistor PM2 is turned off and the second pull-down transistor NM2 is turned on, so that the output voltage PAD0 is pulled down.

At time point T82, the data D_n-1 before half cycle CL and the current data D_n are 0 and 0 respectively. Lookup table 1 can obtain the first operation signal ENZ1 and the second operation signal ENZ2 as 0 and 1 respectively. At this time, as shown in Figure 7, the current data D_n is 0 and the first operation signal ENZ1 is 0, the second pull-up control signal pu2 output by the second inverter gate NA2 is 1; the current data D_n is 0 and the second The operation signal ENZ2 is 1, and the second pull-down control signal pd2 of the second inverter NO2 output is 0. The second pull-up transistor PM2 is turned off and the second pull-down transistor NM2 is turned off, so that the leakage current CC is suppressed.

At time point T83, the previous data D_n-1 and the current data D_n of the half-cycle CL interval are 0 and 1 respectively. Lookup table 1 can obtain the first operation signal ENZ1 and the second operation signal ENZ2 as 1 and 1 respectively. At this time, as shown in Figure 7, the current data D_n is 1 and the first operation signal ENZ1 is 1, the second pull-up control signal pu2 output by the second inverter gate NA2 is 0; the current data D_n is 1 and the second The operation signal ENZ2 is 1, and the second pull-down control signal pd2 of the second inverter NO2 output is 0. The second pull-up transistor PM2 is turned on and the second pull-down transistor NM2 is turned off, so that the output voltage PAD0 is pulled up.

According to the above embodiment, the semiconductor device 2000 uses the design of the second lift circuit 132 so that the second pull-up transistor PM2 and the second pull-down transistor NM2 are not turned off or on simultaneously, and the leakage current CC of the crowbar current can be effectively eliminated. inhibition. In this way, the occurrence of leakage current CC such as crowbar current in the semiconductor device can be improved and the quality of the semiconductor device can be ensured.

Please refer to FIG. 9 , which illustrates a detailed structure of a semiconductor device 3000 according to another embodiment. The detailed structure of the data output circuit 130 is described below. The first lifting circuit 131 is a combination of a logic circuit, a pulling up circuit and a pulling down circuit. The first lifting circuit 131 includes the first pulling up transistor PM1, the first pulling down transistor NM1, a first NAND gate (NAND) NA1 and a first NOR gate (NOR) NO1. A gate electrode of the first pull-up transistor PM1 is connected to the first inverse-AND gate NA1. A gate electrode of the first pull-down transistor NM1 is connected to the first inverse-OR gate NO1.

The second lifting circuit 132 is a combination of a logic circuit, a pulling up circuit and a pulling down circuit. The second boost circuit 132 includes the second pull-up transistor PM2, the second pull-down transistor NM2, a second inverse-AND gate NA2 and a second inverse-OR gate NO2. A gate electrode of the second pull-up transistor PM2 is connected to the second inverse-AND gate NA2. A gate electrode of the second pull-down transistor NM2 is connected to the second inverse-OR gate NO2.

The first pull-up transistor PM1 and the first pull-down transistor NM1 are connected in series at a first node Nd1, and the second pull-up transistor PM2 and the second pull-down transistor NM2 are connected in series at a second node Nd2. The first node Nd1 and the second node Nd2 are connected to the output terminal Nd12.

The control circuit 340 includes a shift register 343, a first multiplexer 141 and a second multiplexer 142. The shift register 343 is used to output the previous data D_n-1, the current data D_n and the next data D_n+1.

The first multiplexer 141 is connected to the shift register 343 . The first multiplexer 141 outputs the first operation signal ENZ1 based on the previous data D_n-1, the current data D_n and the next data D_n+1.

The second multiplexer 142 is connected to the shift register 343 . The second multiplexer 142 outputs the second operation signal ENZ2 based on the previous data D_n-1, the current data D_n and the next data D_n+1.

Please refer to Table 2 below. In this embodiment, the control circuit 340 can determine the first operation signal ENZ1 and the second operation signal ENZ2 based on the previous data D_n-1, the current data D_n and the next data D_n+1. The second lift circuit 132 can determine the second pull-up control signal pu2 and the second pull-down control signal pd2 based on the first operation signal ENZ1 and the second operation signal ENZ2. After the second pull-up control signal pu2 and the second pull-down control signal pd2 are respectively input to the second pull-up transistor PM2 and the second pull-down transistor NM2, the second pull-up transistor PM2 and the second pull-up transistor PM2 can be made low. Transistor NM2 is turned on or off asynchronously. Input to control circuits 340, 440 Input to the second lifting circuit 132 Input to the second pull-up transistor PM2 and the second pull-down transistor NM2 D_n-1 D_n D_n+1 ENZ1 ENZ2 pu2 pd2 0 0 0 0 0 1 1 0 0 1 0 1 1 0 0 1 0 1 1 0 0 0 1 1 1 1 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 1 1 1 0 0 1 1 0 1 1 1 1 1 0 0 Table II

Please refer to Figures 9 to 11 and Table 2. Figure 10 illustrates a flow chart of a data output method of the semiconductor device 3000 according to an embodiment. Figure 11 illustrates each step of Figure 10. As shown in Figure 9, in step S1010, the control circuit 340 obtains the previous data D_n-1, the current data D_n and the next data D_n+1. There is a period CL between the previous data D_n-1, the current data D_n and the next data D_n+1.

For example, as shown in Figure 11, at time point T111, the previous data D_n-1, the current data D_n, and the next data D_n+1 are 1, 0, and 0 respectively. At time point T112, the previous data D_n-1, the current data D_n, and the next data D_n+1 are 0, 0, and 1 respectively. At time point T113, the previous data D_n-1, the current data D_n, and the next data D_n+1 are 0, 1, and 1 respectively. At time point T114, the previous data D_n-1, the current data D_n, and the next data D_n+1 are 1, 1, and 0 respectively. At time point T115, the previous data D_n-1, the current data D_n, and the next data D_n+1 are 1, 0, and 0 respectively.

Next, as shown in Figure 9 and Table 2, in step S1020, the control circuit 340 outputs the first operation signal ENZ1 and the first operation signal ENZ1 according to the sequence relationship of the previous data D_n-1, the current data D_n and the next data D_n+1. 2. Operation signal ENZ2.

For example, as shown in Figure 11, at time point T111, the previous data D_n-1, the current data D_n, and the next data D_n+1 are 1, 0, and 0 respectively. By looking up Table 2, we can obtain that the first operation signal ENZ1 and the second operation signal ENZ2 are 0 and 0 respectively.

At time point T112, the previous data D_n-1, the current data D_n, and the next data D_n+1 are 0, 0, and 1 respectively. By looking up Table 2, we can obtain that the first operation signal ENZ1 and the second operation signal ENZ2 are 0 and 1 respectively.

At time point T113, the previous data D_n-1, the current data D_n, and the next data D_n+1 are 0, 1, and 1 respectively. By looking up Table 2, we can obtain that the first operation signal ENZ1 and the second operation signal ENZ2 are 1 and 1 respectively.

At time point T114, the previous data D_n-1, the current data D_n, and the next data D_n+1 are 1, 1, and 0 respectively. By looking up Table 2, we can obtain that the first operation signal ENZ1 and the second operation signal ENZ2 are 0 and 1 respectively.

At time point T115, the previous data D_n-1, the current data D_n, and the next data D_n+1 are 1, 0, and 0 respectively. By looking up Table 2, we can obtain that the first operation signal ENZ1 and the second operation signal ENZ2 are 0 and 0 respectively.

Then, in step S1030, the first lifting circuit 131 obtains the first pull-up control signal pu1 and the first pull-down control signal pd1 according to the current data D_n, so as to synchronously turn on or off the first pull-up transistor PM1 and the first pull-down transistor PM1. Transistor NM1 causes the output voltage PAD0 to be pulled up or down.

As shown in Figure 9, current data D_n and an operating voltage VDD are input to the first inverse-AND gate NA1 to output the first pull-up control signal pu1. The operating voltage VDD is 1. Since the operating voltage VDD is 1, the first pull-up control signal pu1 is the opposite value of the current data D_n.

As shown in Figure 9, current data D_n and a ground voltage GND are input to the first inverse-OR gate NO1 to output the first pull-down control signal pd1. The ground voltage GND is 0. Since the ground voltage GND is 0, the first pull-down control signal pd1 is the opposite value of the current data D_n.

When the current data D_n is 1, the first pull-up control signal pu1 is 0 and the first pull-down control signal pd1 is 0 to simultaneously turn on the first pull-up transistor PM1 and turn off the first pull-down transistor NM1, so that the output voltage PAD0 is pulled high.

When the current data D_n is 0, the first pull-up control signal pu1 is 1 and the first pull-down control signal pd1 is 1 to synchronously turn off the first pull-up transistor PM1 and turn on the first pull-down transistor NM1, so that the output voltage PAD0 is pulled low.

As shown in Figure 11, at time point T111, the current data D_n is 0, and the first pull-up control signal pu1 and the first pull-down control signal pd1 both become 1 to synchronously turn off and turn on the first pull-up transistor PM1 The first pull-down transistor NM1 causes the output voltage PAD0 to be pulled low.

At time point T112, the current data D_n is 0, and the first pull-up control signal pu1 and the first pull-down control signal pd1 are still 1, so as to synchronously turn off the first pull-up transistor PM1 and turn on the first pull-down transistor NM1. This causes the output voltage PAD0 to be pulled low.

At time point T113, the current data D_n is 1, and the first pull-up control signal pu1 and the first pull-down control signal pd1 both become 0 to simultaneously turn on the first pull-up transistor PM1 and turn off the first pull-down transistor NM1 , causing the output voltage PAD0 to be pulled up.

At time point T114, the current data D_n is 1, and the first pull-up control signal pu1 and the first pull-down control signal pd1 both become 0 to simultaneously turn on the first pull-up transistor PM1 and turn off the first pull-down transistor NM1 , causing the output voltage PAD0 to be pulled up.

At time point T115, the current data D_n is 0, and the first pull-up control signal pu1 and the first pull-down control signal pd1 both become 1 to synchronously turn off the first pull-up transistor PM1 and turn on the first pull-down transistor NM1 , causing the output voltage PAD0 to be pulled low.

Next, in step S1040, the second lift circuit 132 obtains the second pull-up control signal pu2 and the second pull-down control signal pd2 according to the first operation signal ENZ1 and the second operation signal ENZ2, so as to asynchronously close or turn on the second pull-up control signal pu2. The pull-up transistor PM2 and the second pull-down transistor NM2 suppress the leakage current CC.

As shown in Figure 9, the current data D_n and the first operation signal ENZ1 are input to the second inverse-AND gate NA2 to output the second pull-up control signal pu2.

The current data D_n and the second operation signal ENZ2 are input to the second inverse-OR gate NO2 to output the second pull-down control signal pd2.

As shown in Figure 11, at time point T111, the previous data D_n-1, the current data D_n, and the next data D_n+1 are 1, 0, and 0 respectively. By looking up Table 2, we can obtain that the first operation signal ENZ1 and the second operation signal ENZ2 are 0 and 0 respectively. At this time, as shown in Figure 9, the current data D_n is 0 and the first operation signal ENZ1 is 0, the second pull-up control signal pu2 output by the second inverter gate NA2 is 1; the current data D_n is 0 and the second The operation signal ENZ2 is 0, and the second pull-down control signal pd2 of the second inverter NO2 output is 1. The second pull-up transistor PM2 is turned off and the second pull-down transistor NM2 is turned on, so that the output voltage PAD0 is pulled down.

At time point T112, the previous data D_n-1, the current data D_n, and the next data D_n+1 are 0, 0, and 1 respectively. By looking up Table 2, we can obtain that the first operation signal ENZ1 and the second operation signal ENZ2 are 0 and 1 respectively. At this time, as shown in Figure 9, the current data D_n is 0 and the first operation signal ENZ1 is 0, the second pull-up control signal pu2 output by the second inverter gate NA2 is 1; the current data D_n is 0 and the second The operation signal ENZ2 is 1, and the second pull-down control signal pd2 of the second inverter NO2 output is 0. The second pull-up transistor PM2 is turned off and the second pull-down transistor NM2 is turned off, so that the leakage current CC is suppressed.

At time point T113, the previous data D_n-1, the current data D_n, and the next data D_n+1 are 0, 1, and 1 respectively. By looking up Table 2, we can obtain that the first operation signal ENZ1 and the second operation signal ENZ2 are 1 and 1 respectively. At this time, as shown in Figure 9, the current data D_n is 1 and the first operation signal ENZ1 is 1, the second pull-up control signal pu2 output by the second inverter gate NA2 is 0; the current data D_n is 1 and the second The operation signal ENZ2 is 1, and the second pull-down control signal pd2 of the second inverter NO2 output is 0. The second pull-up transistor PM2 is turned on and the second pull-down transistor NM2 is turned off, so that the output voltage PAD0 is pulled up.

At time point T114, the previous data D_n-1, the current data D_n, and the next data D_n+1 are 1, 1, and 0 respectively. By looking up Table 2, we can obtain that the first operation signal ENZ1 and the second operation signal ENZ2 are 0 and 1 respectively. At this time, as shown in Figure 9, the current data D_n is 1 and the first operation signal ENZ1 is 0, the second pull-up control signal pu2 output by the second inverter gate NA2 is 1; the current data D_n is 1 and the second The operation signal ENZ2 is 1, and the second pull-down control signal pd2 of the second inverter NO2 output is 0. The second pull-up transistor PM2 is turned off and the second pull-down transistor NM2 is turned off, so that the leakage current CC is suppressed.

At time point T115, the previous data D_n-1, the current data D_n, and the next data D_n+1 are 1, 0, and 0 respectively. By looking up Table 2, we can obtain that the first operation signal ENZ1 and the second operation signal ENZ2 are 0 and 0 respectively. At this time, as shown in Figure 9, the current data D_n is 0 and the first operation signal ENZ1 is 0, the second pull-up control signal pu2 output by the second inverter gate NA2 is 1; the current data D_n is 0 and the second The operation signal ENZ2 is 0, and the second pull-down control signal pd2 of the second inverter NO2 output is 1. The second pull-up transistor PM2 is turned off and the second pull-down transistor NM2 is turned on, so that the output voltage PAD0 is pulled down.

As shown in Figure 11, at time point T111, when the second pull-down transistor NM2 is turning on, the second pull-up transistor PM2 remains unchanged.

At time point T112, when the second pull-down transistor NM2 is turning off, the second pull-up transistor PM2 remains unchanged.

At time point T113, when the second pull-up transistor PM2 is turning on, the second pull-down transistor NM2 remains unchanged.

At time point T114, when the second pull-up transistor PM2 is turning off, the second pull-down transistor NM2 remains unchanged.

At time point T115, when the second pull-down transistor NM2 is turning on, the second pull-up transistor PM2 remains unchanged.

That is to say, when one of the second pull-up transistor PM2 and the second pull-down transistor NM2 is turned off, the other one of the second pull-up transistor PM2 and the second pull-down transistor NM2 remains unchanged. . When one of the second pull-up transistor PM2 and the second pull-down transistor NM2 is turned on, the other one of the second pull-up transistor PM2 and the second pull-down transistor NM2 remains unchanged.

In addition, as shown in FIG. 11, during the time point T112 to T113, the second pull-down transistor NM2 is first turned off, and the second pull-up transistor PM2 is turned on again.

During the time point T114 to T115, the second pull-up transistor PM2 is first turned off, and the second pull-down transistor NM2 is turned on again.

That is to say, one of the second pull-up transistor PM2 and the second pull-down transistor NM2 is turned off first, and the other one of the second pull-up transistor PM2 and the second pull-down transistor NM2 is turned on again.

As shown in Figure 11, at time point T111, when the current data D_n and the next data D_n+1 are both 0, the second pull-down transistor NM is turned off at time point T112.

At time point T113, when the current data D_n and the next data D_n+1 are both 1, the second pull-up transistor PM2 is turned off at time point T114.

That is to say, when the current data D_n and the next data D_n+1 are both 0, the second pull-down transistor NM2 is turned off at the next time. When the current data D_n and the next data D_n+1 are both 1, the second pull-up transistor PM2 is turned off at the next time.

According to the above embodiment, the semiconductor device 3000 uses the design of the second lift circuit 132 so that the second pull-up transistor PM2 and the second pull-down transistor NM2 are not turned off or on synchronously, and the leakage current CC of the crowbar current can be effectively eliminated. inhibition. In this way, the occurrence of leakage current CC such as crowbar current in the semiconductor device can be improved and the quality of the semiconductor device can be ensured.

In the above embodiment, there is a period CL between the previous data D_n-1, the current data D_n and the next data D_n+1. When the current data D_n remains unchanged for two consecutive periods CL (equivalent to the current data D_n and When the next data D_n+1 is the same), the second pull-up transistor PM2 or the second pull-down transistor NM2 in the on state can be turned off in the next cycle CL to suppress the leakage current CC.

In another embodiment, the interval between the previous data D_n-1, the current data D_n and the next data D_n+1 may be half a period. Please refer to FIG. 12 , which illustrates a schematic diagram of a semiconductor device 4000 according to another embodiment. The shift register 443 of the control circuit 440 of the semiconductor device 4000 receives the clock signals C0 and C0b. The clock signal C0 is the complementary signal of the clock signal C0b. In the embodiment using a falling edge trigger, when the clock signal C0 or the clock signal C0b falls, the signal conversion will be triggered. Therefore, the interval between the previous data D_n-1, the current data D_n and the next data D_n+1 input to the control circuit 440 may be half a period. In one embodiment, the clock signal C0b may be a clock signal with a frequency 2, 4, 6 or 8 times the frequency of the clock signal C0. In another embodiment, the clock signal C0 and the clock signal C0b may also be two clock signals with a phase difference of 1/2, 1/4 or 1/8 period.

Please refer to FIG. 13, which illustrates an example of the data output method of the semiconductor device 4000 in FIG. 12. At time point T131, the previous data D_n-1, current data D_n, and next data D_n+1 of the half-cycle CL interval are 1, 0, and 0 respectively. By looking up Table 2, we can obtain that the first operation signal ENZ1 and the second operation signal ENZ2 are 0 and 0 respectively. At this time, as shown in Figure 12, the current data D_n is 0 and the first operation signal ENZ1 is 0, the second pull-up control signal pu2 output by the second inverter gate NA2 is 1; the current data D_n is 0 and the second The operation signal ENZ2 is 0, and the second pull-down control signal pd2 of the second inverter NO2 output is 1. The second pull-up transistor PM2 is turned off and the second pull-down transistor NM2 is turned on, so that the output voltage PAD0 is pulled down.

At time point T132, the previous data D_n-1, current data D_n, and next data D_n+1 of the half cycle CL are 0, 0, and 1 respectively. By looking up Table 2, we can obtain that the first operation signal ENZ1 and the second operation signal ENZ2 are 0 and 1 respectively. At this time, as shown in Figure 12, the current data D_n is 0 and the first operation signal ENZ1 is 0, the second pull-up control signal pu2 output by the second inverter gate NA2 is 1; the current data D_n is 0 and the second The operation signal ENZ2 is 1, and the second pull-down control signal pd2 of the second inverter NO2 output is 0. The second pull-up transistor PM2 is turned off and the second pull-down transistor NM2 is turned off, so that the leakage current CC is suppressed.

At time point T133, the previous data D_n-1, current data D_n, and next data D_n+1 of the half-cycle CL interval are 0, 1, and 1 respectively. By looking up Table 2, we can obtain that the first operation signal ENZ1 and the second operation signal ENZ2 are 1 and 1 respectively. At this time, as shown in Figure 12, the current data D_n is 1 and the first operation signal ENZ1 is 1, the second pull-up control signal pu2 output by the second inverter gate NA2 is 0; the current data D_n is 1 and the second The operation signal ENZ2 is 1, and the second pull-down control signal pd2 of the second inverter NO2 output is 0. The second pull-up transistor PM2 is turned on and the second pull-down transistor NM2 is turned off, so that the output voltage PAD0 is pulled up.

In the embodiment of Figures 12 to 13, the previous data D_n-1, the current data D_n and the next data D_n+1 are separated by half a period CL, and the current data D_n and the next data D_n within one period CL When +1 is the same, the second pull-up transistor PM2 or the second pull-down transistor NM2 in the on state can be turned off in the next half cycle CL to suppress the leakage current CC. In this way, the leakage current CC can be effectively suppressed in each cycle CL.

According to the above embodiment, the semiconductor device 4000 uses the design of the second lift circuit 132 so that the second pull-up transistor PM2 and the second pull-down transistor NM2 are not turned off or on synchronously, and the leakage current CC of the crowbar current can be effectively eliminated. inhibition. In this way, the occurrence of leakage current CC such as crowbar current in the semiconductor device can be improved and the quality of the semiconductor device can be ensured.

In summary, although the present disclosure has been disclosed in the above embodiments, they are not used to limit the present disclosure. Those with ordinary knowledge in the technical field to which this disclosure belongs can make various modifications and modifications without departing from the spirit and scope of this disclosure. Therefore, the protection scope of the present disclosure shall be subject to the scope of the appended patent application.

110,910: Data temporary storage circuit 120,920: Data multiplexing circuit 130,930: Data output circuit 131: First lifting circuit 132: Second lift circuit 140,240,340,440: Control circuit 141:First multiplexer 142: Second multiplexer 143,243,343,443: shift register 1000, 2000, 3000, 4000, 9000: Semiconductor devices b0~b31: bit C0, C0b: clock signal CC: leakage current CL: cycle D0:data D_n-1: Previous data D_n: current information D_n+1: next data ENZ1: first operation signal ENZ2: The second operation signal GND: ground voltage NA1: first anti-and gate NA2: Second anti-and gate Nd1: first node Nd2: second node Nd12: output terminal NM0: pull the transistor low NM1: The first pull-down transistor NM2: The second pull-down transistor NO1: First reverse OR gate NO2: The second reverse OR gate PAD0: output voltage PM0: pull up transistor PM1: The first pull-up transistor PM2: The second pull-up transistor pd0: Pull down the control signal pd1: first pull down the control signal pd2: The second pull-down control signal pu0: pull up control signal pu1: The first pull-up control signal pu2: The second pull-up control signal S510, S520, S530, S540, S1010, S1020, S1030, S1040: Steps T21, T22, T31, T32, T61, T62, T63, T64, T65, T81, T82, T83, T111, T112, T113, T114, T115, T131, T132, T133: time points VDD: working voltage

Figure 1A is a schematic diagram of a data output circuit according to an embodiment. Figure 1B shows the relationship between the output voltage and the pull-up control signal. Figure 2A is a schematic diagram of a semiconductor device according to an embodiment. Figure 2B shows the relationship between the output voltage, the pull-up control signal and the clock signal. Figure 3A is a schematic diagram of a semiconductor device according to an embodiment. Figure 3B illustrates the operation of the first lifting circuit and the second lifting circuit. Figure 4 shows the detailed structure of the semiconductor device. FIG. 5 illustrates a flowchart of a data output method of a semiconductor device according to an embodiment. Figure 6 illustrates the steps of Figure 5. FIG. 7 is a schematic diagram of a semiconductor device according to another embodiment. Figure 8 illustrates an example of the data output method of the semiconductor device of Figure 7. Figure 9 illustrates a detailed structure of a semiconductor device according to another embodiment. FIG. 10 illustrates a flowchart of a data output method of a semiconductor device according to another embodiment. Figure 11 illustrates the steps of Figure 10. FIG. 12 illustrates a schematic diagram of a semiconductor device according to another embodiment. FIG. 13 illustrates the data output method of the semiconductor device of FIG. 12.

110: Data temporary storage circuit

120: Data multiplexing circuit

130: Data output circuit

131: First lifting circuit

132: Second lift circuit

140:Control circuit

141:First multiplexer

142: Second multiplexer

143:Shift register

1000:Semiconductor devices

C0: Clock signal

D0:data

D_n-1: Previous data

D_n: current information

ENZ1: first operation signal

ENZ2: The second operation signal

GND: ground voltage

NA1: first anti-and gate

NA2: Second anti-and gate

Nd1: first node

Nd2: second node

Nd12: output terminal

NM1: The first pull-down transistor

NM2: The second pull-down transistor

NO1: First reverse OR gate

NO2: The second reverse OR gate

PAD0: output voltage

PM1: The first pull-up transistor

PM2: The second pull-up transistor

pd1: first pull down the control signal

pd2: The second pull-down control signal

pu1: The first pull-up control signal

pu2: The second pull-up control signal

VDD: working voltage

Claims (18)

A semiconductor device including: a data temporary storage circuit for storing at least one previous data and one current data; A control circuit connected to the data temporary storage circuit, the control circuit outputs a first operation signal and a second operation signal based on at least the previous data and the current data; and A data output circuit is connected to the control circuit. The data output circuit includes: A first lift circuit includes a first pull-up transistor and a first pull-down transistor. The first lift circuit obtains a first pull-up control signal and a first pull-down control signal based on the current data, To synchronously turn off or turn on the first pull-up transistor and the second pull-down transistor, so that an output voltage is pulled up or down; and A second lift circuit includes a second pull-up transistor and a second pull-down transistor. The second lift circuit obtains a second pull-up control signal based on the first operation signal and the second operation signal. A second pull-down control signal is used to asynchronously turn off or turn on the second pull-up transistor and the second pull-down transistor, so that a leakage current is suppressed. The semiconductor device according to claim 1, wherein When one of the second pull-up transistor and the second pull-down transistor is turned off, the other of the second pull-up transistor and the second pull-down transistor remains unchanged; When one of the second pull-up transistor and the second pull-down transistor is turned on, the other one of the second pull-up transistor and the second pull-down transistor remains unchanged. The semiconductor device of claim 1, wherein one of the second pull-up transistor and the second pull-down transistor is turned off first, and one of the second pull-up transistor and the second pull-down transistor is turned off. Another one of them is opened again. The semiconductor device according to claim 1, wherein The control circuit outputs the first operation signal and the second operation signal based on the sequence relationship of the previous data, the current data and the next data. The semiconductor device according to claim 1, wherein When the current data and the next data are both 0, the second pull-down transistor is turned off at the next time; When the current data and the next data are both 1, the second pull-up transistor is turned off at the next time. The semiconductor device of claim 1, wherein the first pull-up transistor and the first pull-down transistor are connected in series at a first node, and the second pull-up transistor and the second pull-down transistor are connected in series. A second node is connected in series, and the first node and the second node are connected to an output end. The semiconductor device according to claim 1, wherein A gate of the first pull-up transistor is connected to a first NAND gate; A gate of the first pull-down transistor is connected to a first NOR gate; A gate of the second pull-up transistor is connected to a second inverse-AND gate; A gate of the second pull-down transistor is connected to a second inverse-OR gate. The semiconductor device according to claim 7, wherein The current data and an operating voltage are input to the first NAND gate, and the operating voltage is 1; The current data and a ground voltage are input to the first inverse-OR gate, and the ground voltage is 0; The current data and the first operation signal are input to the second NAND gate; The second operation signal and the current data are input to the second NOR gate. The semiconductor device as claimed in claim 1, wherein the control circuit includes: a shift register for outputting the previous data, the current data and the next data; A first multiplexer is connected to the shift register, and the first multiplexer outputs the first operation signal based on the previous data, the current data and the next data; and A second multiplexer is connected to the shift register. The second multiplexer outputs the second operation signal based on the previous data, the current data and the next data. The semiconductor device as claimed in claim 1, wherein there is a period interval between the previous data, the current data and the next data. The semiconductor device as claimed in claim 1, wherein the previous data, the current data and the next data are separated by 1/2, 1/4, or 1/8 cycles. A data output method for a semiconductor device, including: Obtain at least one previous data and one current data; At least based on the previous data and the current data, output a first operation signal and a second operation signal; According to the current data, a first pull-up control signal and a first pull-down control signal are obtained to synchronously turn on or off a first pull-up transistor and a first pull-down transistor, so that an output voltage is pulled up or pull it down; and According to the first operation signal and the second operation signal, a second pull-up control signal and a second pull-down control signal are obtained to asynchronously close or turn on a second pull-up transistor and a second pull-down transistor. crystal so that a leakage current is suppressed. The data output method of a semiconductor device as claimed in claim 12, wherein When one of the second pull-up transistor and the second pull-down transistor is turned off, the other of the second pull-up transistor and the second pull-down transistor remains unchanged; When one of the second pull-up transistor and the second pull-down transistor is turned on, the other one of the second pull-up transistor and the second pull-down transistor remains unchanged. The data output method of the semiconductor device according to claim 12, wherein one of the second pull-up transistor and the second pull-down transistor is turned off first, and the second pull-up transistor and the second pull-up transistor are turned off first. Another one of the low-voltage transistors is turned on again. The data output method of a semiconductor device as claimed in claim 12, wherein the first operation signal and the second operation signal are output based on the sequential relationship of the previous data, the current data and the next data. The data output method of a semiconductor device as claimed in claim 12, wherein When the current data and the next data are both 0, the second pull-down transistor is turned off at the next time; When the current data and the next data are both 1, the second pull-up transistor is turned off at the next time. The data output method of a semiconductor device as claimed in claim 12, wherein there is a period interval between the previous data, the current data and the next data. The data output method of a semiconductor device as claimed in claim 12, wherein the previous data, the current data and the next data are separated by 1/2, 1/4, or 1/8 cycles.

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