TW202333390A - Semiconductor stack, semiconductor device and method for manufacturing the same - Google Patents

Abstract

The present disclosure provides a semiconductor stack, a semiconductor device and a method for manufacturing the same. The semiconductor device includes a first semiconductor layer and a light-emitting structure. The first semiconductor layer includes a first III-V semiconductor material, a first dopant and a second dopant. The light-emitting structure is on the first semiconductor layer and includes an active structure. In the first semiconductor layer, a concentration of the second dopant is higher than a concentration of the first dopant. The first dopant is carbon, and the second dopant is hydrogen.

Description

Semiconductor stack, semiconductor element and manufacturing method thereof

The present disclosure relates to a semiconductor device, and in particular to a light-emitting device including a semiconductor stack.

With the rapid advancement of science and technology, semiconductor components play a very important role in fields such as information transmission and energy conversion, and the research and development of related materials continues. For example, III-V semiconductor materials containing Group III and Group V elements can be used in various optoelectronic devices such as light emitting diodes (LEDs), laser diodes (LDs), solar Batteries (Solar cells), etc., can also be used in lighting, medical, display, communications, sensing, power supply systems and other fields. Light-emitting diode components are suitable for solid-state lighting sources and have the advantages of low power consumption and long life. Therefore, they have gradually replaced traditional light sources and are widely used in traffic signals, backlight modules, various lighting and medical equipment, etc.

SUMMARY OF THE INVENTION The present invention provides a semiconductor element, which includes a first semiconductor layer, a light-emitting structure, a second semiconductor layer and a third semiconductor layer. The first semiconductor layer includes a first III-V semiconductor material. The light emitting structure is located on the first semiconductor layer and includes an active structure. The second semiconductor layer is located under the first semiconductor layer and includes a second III-V semiconductor material. The third semiconductor layer is located between the first semiconductor layer and the light emitting structure and includes a third group III-V semiconductor material. The first semiconductor layer, the second semiconductor layer and the third semiconductor layer include first dopants and second dopants. The concentration of the first dopant in the first semiconductor layer is greater than the concentration of the first dopant in the second semiconductor layer. The concentration of the first dopant in the first semiconductor layer is greater than the concentration of the first dopant in the third semiconductor layer. The concentration of the second dopant in the first semiconductor layer is lower than the concentration of the second dopant in the second semiconductor layer. The concentration of the second dopant in the first semiconductor layer is lower than the concentration of the second dopant in the third semiconductor layer.

The present invention further provides a packaging structure of a semiconductor element, which includes a carrier, a semiconductor element and a packaging material. The semiconductor component is located on the carrier. The packaging material covers the semiconductor components.

The following embodiments will illustrate the concept of the present invention along with the drawings. In the drawings or descriptions, similar or identical components will be described with similar or identical reference numerals, and unless otherwise specified, the shape of each element in the drawings or The dimensions are only examples and are not actually limited thereto. It should be noted that components not shown or described in the drawings may be in forms known to those skilled in the art.

The general formula InGaAsP represents In _x7 Ga _1-x7 As _1-y2 P _y2 , where 0＜x1＜1, 0＜y1＜1; AlGaInAs represents (Al _y2 Ga _(1-y2) ) _1-x2 In _x2 As, where 0＜x2＜1, 0＜y2＜1; the general formula AlGaInP represents (Al _y3 Ga _(1-y3) ) _1-x3 In _x3 P, where 0＜x3＜1, 0＜y3＜1; the general formula InGaAs represents In _x4 Ga _1-x4 As, where 0 < mass spectrometer (SIMS), and the thickness of each layer can also be analyzed by any suitable method, such as transmission electron microscopy (TEM) or scanning electron microscope (SEM). In addition, each dopant mentioned in this disclosure may be intentionally added or unintentionally added. Intentional addition is, for example, by in-situ doping during epitaxial growth and/or by implanting after epitaxial growth using P-type or N-type dopants. Unintentional additions occur, for example, due to process design.

Those with ordinary skill in the art should understand that other components can be added on the basis of each embodiment described below. For example, unless otherwise specified, the description of "forming a second layer on the first layer" may include an embodiment in which the first layer is in direct contact with the second layer, or may also include an embodiment in which the first layer and the second layer are in direct contact. Embodiments with other layers in between without direct contact with each other. In addition, the upper-lower relationship of various layers may change as the structure or component is operated or used in different orientations. In addition, in this disclosure, the statement that a layer "substantially consists of material X" means that the main component of the layer is material

FIG. 1 is a schematic structural diagram of a semiconductor stack 10 according to an embodiment of the present disclosure. The semiconductor stack 10 includes a first semiconductor layer 100 and a second semiconductor layer 102 . The second semiconductor layer 102 is adjacent to the first semiconductor layer 100 . In this embodiment, a surface 100a of the first semiconductor layer 100 is in direct contact with a surface 102a of the second semiconductor layer 102. No other structure (such as a buffer layer, etc.) exists between the first semiconductor layer 100 and the second semiconductor layer 102 .

In this embodiment, the first semiconductor layer 100 includes a first group III-V semiconductor material. The first III-V semiconductor materials are materials composed of elements from Groups III and V of the periodic table of chemical elements. Group III elements can be gallium (Ga) or indium (In). The Group 5 element may be arsenic (As) or phosphorus (P), and preferably does not include nitrogen (N). In one embodiment, the first semiconductor layer 100 is substantially composed of a first III-V group semiconductor material, for example, substantially composed of a binary III-V group semiconductor material. In one embodiment, the first semiconductor layer 100 is substantially composed of InP. The first semiconductor layer 100 may include dopants. In one embodiment, the first semiconductor layer 100 includes first dopants and second dopants. In this embodiment, the concentration of the second dopant in the first semiconductor layer 100 is greater than the concentration of the first dopant. The first dopant is, for example, carbon (C), and the second dopant is, for example, hydrogen (H). Thereby, the first semiconductor layer 100 can have a surface with stable properties and fewer epitaxial defects, for example, it can be used as a surface for epitaxial layer growth. In an embodiment, the first semiconductor layer 100 may include a third dopant. The third dopant is silicon (Si), for example. In one embodiment, the dopants in the first semiconductor layer 100 may each independently have a doping concentration of about 1×10 ¹⁶ cm ⁻³ to about 1×10 ¹⁹ cm ⁻³ , for example, about 5×10 ¹⁶ cm ⁻³ to about 5×10 ¹⁷ cm ⁻³ , or 6×10 ¹⁷ cm ⁻³ to 5×10 ¹⁸ cm ⁻³ , etc. In one embodiment, the concentration of the third dopant in the first semiconductor layer 100 is less than 1×10 ¹⁹ cm ⁻³ , for example, in the range of about 6×10 ¹⁶ cm ⁻³ to about 1×10 ¹⁷ cm ⁻³ . When the dopant in the first semiconductor layer 100 has an appropriate doping concentration, the first semiconductor layer 100 may have better conductive properties. In one embodiment, the conductivity type of the first semiconductor layer 100 is N-type.

In this embodiment, the second semiconductor layer 102 includes a second group III-V semiconductor material. The second group III-V semiconductor material is a material composed of elements from Groups III and V of the periodic table of chemical elements. Group III elements can be gallium (Ga) or indium (In). The Group 5 element may be arsenic (As) or phosphorus (P), and preferably does not include nitrogen (N). The second III-V semiconductor material is different from the first III-V semiconductor material. In one embodiment, each component element of the second group III-V semiconductor material is different from each component element of the first group III-V semiconductor material. In one embodiment, the second semiconductor layer 102 is substantially composed of a second group III-V semiconductor material, for example, substantially composed of a binary group III-V semiconductor material. In one embodiment, the second semiconductor layer 102 is substantially composed of GaAs. The second semiconductor layer 102 may include a plurality of dopants. The plurality of dopants in the second semiconductor layer 102 may each independently have a doping concentration of 5×10 ¹⁵ cm ⁻³ to 1×10 ²⁰ cm ⁻³ , for example, a doping concentration of 1×10 ¹⁷ cm ⁻³ to 1×10 A doping concentration of ¹⁸ cm ⁻³ , a doping concentration of 1×10 ¹⁸ cm ⁻³ to 1×10 ¹⁹ cm ⁻³ , or a doping concentration of 1×10 ¹⁹ cm ⁻³ to 1×10 ²⁰ cm ⁻³ . When the dopant in the second semiconductor layer 102 has an appropriate doping concentration, the second semiconductor layer 102 may have better conductive properties. The dopants in the second semiconductor layer 102 may include silicon (Si), zinc (Zn), carbon (C), hydrogen (H), etc. In one embodiment, the conductivity type of the second semiconductor layer 102 is N-type. In some embodiments, the first semiconductor layer 100 and the second semiconductor layer 102 have the same conductivity type, such as P-type or N-type. In one embodiment, the resistivity of the second semiconductor layer 102 is in the range of 10 ⁷ Ω·cm or more and 10 ⁹ Ω·cm or less, for example, 10 ⁸ Ω·cm or more.

In some embodiments, both the first semiconductor layer 100 and the second semiconductor layer 102 contain first dopants, second dopants, and third dopants. In some embodiments, the concentration of the third dopant in the second semiconductor layer 102 is higher than the concentration of the third dopant in the first semiconductor layer 100 . In some embodiments, the concentration of the second dopant in the second semiconductor layer 102 is higher than the concentration of the second dopant in the first semiconductor layer 100 . In some embodiments, the concentration of the first dopant in the second semiconductor layer 102 is lower than the concentration of the first dopant in the first semiconductor layer 100 . The first dopant is, for example, carbon (C), the second dopant is, for example, hydrogen (H), and the third dopant is, for example, silicon (Si). By containing specific dopants, the first semiconductor layer 100 and the second semiconductor layer 102 can obtain appropriate conductive properties and epitaxial quality.

On the other hand, the first semiconductor layer 100 has a first lattice constant L1, and the second semiconductor layer 102 has a second lattice constant L2. In this embodiment, the first lattice constant L1 is greater than the second lattice constant L2, and the difference ΔL% between the first lattice constant L1 and the second lattice constant L2 is more than 2%, preferably 2.5%. More than 3% and less than 10%, preferably less than 5%. In detail, the difference between the first lattice constant L1 and the second lattice constant L2 can be calculated by the following formula: ΔL%=L1-L2/L2*100%. The above lattice constants refer to those obtained by measuring the X-ray diffraction pattern of semiconductor materials at a temperature of 300K. Here we only list the lattice constants of several semiconductor compounds for reference, as shown in Table 1 below.

Table 1 Lattice constant (Å) GaP 5.45 PP 5.45 GaAs 5.65 iP 5.87 GaSb 6.09

The first semiconductor layer 100 and the second semiconductor layer 102 can be formed by liquid phase epitaxy (LPE), molecular beam epitaxy (MBE), or chemical beam epitaxy (Chemical Beam Epitaxy). CBE), Metal Organic Chemical Vapor Deposition (MOCVD), or hydride vapor phase epitaxial (HVPE). In this embodiment, the first semiconductor layer 100 is directly formed on the second semiconductor layer 102 as a substrate. The thickness of the first semiconductor layer may be below 20 μm, preferably below 10 μm, more preferably below 5 μm, and may be above 1 μm. In one embodiment, the thickness of the first semiconductor layer is 2 μm. When the thickness of the first semiconductor layer 100 is within the above range, it can have better structural stability, and can further reduce the impact caused by lattice mismatch. The thickness of the second semiconductor layer 102 may be in the range of about 50 μm to about 1000 μm, such as about 100 μm to about 400 μm or about 150 μm to about 350 μm. Setting the thickness within the above range can make the semiconductor structure subsequently grown thereon have a more stable structure. When the semiconductor stack 10 including the first semiconductor layer 100 and the second semiconductor layer 102 is observed with an electron microscope, it can be observed that there are few epitaxial defects on the surface of the first semiconductor layer 100 . In some embodiments, under X-ray diffraction analysis (XRD) analysis, the XRD full width at half maximum (FWHM) of the first semiconductor layer 100 may be less than 500 arcsec, which is less than 500 arcsec. Preferably, it is 350 arcsec or less, more preferably, it is 300 arcsec or less, for example, it is in the range of 100 arcsec or more and 200 arcsec or less. Thereby, the surface of the first semiconductor layer 100 is more suitable for the growth of other epitaxial layers. Specifically, the first semiconductor layer 100 or the semiconductor stack 10 including the first semiconductor layer 100 and the second semiconductor layer 102 can be used as a growth substrate for semiconductor devices.

FIG. 2A is a partial structural diagram of a semiconductor device 20 according to an embodiment of the present disclosure. In this embodiment, the semiconductor element 20 includes a first semiconductor layer 100, a third semiconductor layer 204 and a light emitting structure 206. Regarding the composition of the first semiconductor layer 100 , please refer to the foregoing description of the first semiconductor layer 100 , and will not be described again here. In addition, the third semiconductor layer 204 and the light-emitting structure 206 can be formed by liquid phase epitaxy (LPE), molecular beam epitaxy (MBE), or chemical beam epitaxy (Chemical Beam Epitaxy). CBE), Metal Organic Chemical Vapor Deposition (MOCVD), or hydride vapor phase epitaxial (HVPE) are sequentially formed on the first semiconductor layer 100. In some embodiments, the first semiconductor layer 100, the third semiconductor layer 204 and the light-emitting structure 206 are sequentially formed on the second semiconductor layer 102 as described in previous embodiments, and then the second semiconductor layer is 102 is removed to form the structure shown in Figure 2A.

As shown in FIG. 2A , the third semiconductor layer 204 is located on the first semiconductor layer 100 and adjacent to the first semiconductor layer 100 . In this embodiment, no other structure (such as a buffer layer, etc.) exists between the first semiconductor layer 100 and the third semiconductor layer 204 . The third semiconductor layer 204 may include a third III-V semiconductor material. Group III-V semiconductor materials are materials composed of elements from Groups III and V of the periodic table of chemical elements. Group III elements can be gallium (Ga) or indium (In). The Group 5 element may be arsenic (As) or phosphorus (P), and preferably does not include nitrogen (N). In some embodiments, the third III-V semiconductor material is the same as the aforementioned first III-V semiconductor material. Specifically, in some embodiments, the third semiconductor layer 204 is substantially composed of a third group III-V semiconductor material, for example, substantially composed of a binary group III-V semiconductor material. In one embodiment, the third semiconductor layer 204 is essentially composed of InP. In addition, the third semiconductor layer 204 may also include a plurality of dopants. In some embodiments, the plurality of dopants in the third semiconductor layer 204 may each independently have a doping concentration of 5×10 ¹⁶ cm ⁻³ to 5×10 ¹⁸ cm ⁻³ , for example, having a doping concentration of 5×10 ¹⁷ cm Doping concentrations from ⁻³ to 2×10 ¹⁸ cm ⁻³ , or from 5×10 ¹⁶ cm ⁻³ to 5×10 ¹⁷ cm ⁻³ . In some embodiments, both the first semiconductor layer 100 and the third semiconductor layer 204 contain first dopants, second dopants, and third dopants. The first dopant is, for example, carbon (C), the second dopant is, for example, hydrogen (H), and the third dopant is, for example, silicon (Si). In some embodiments, forming the third semiconductor layer 204 on the first semiconductor layer 100 helps further stabilize the epitaxial surface quality. In some embodiments, the third semiconductor layer 204 can be used as a window layer to improve the luminous efficiency of the semiconductor device 20 , and the third semiconductor layer 204 is transparent to the light emitted by the light emitting structure 206 . In addition, in one embodiment, the conductivity type of the third semiconductor layer 204 is N-type.

The light emitting structure 206 includes an active structure 210, a fourth semiconductor layer 208 and a fifth semiconductor layer 212. The active structure 210 may include a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or multiple quantum wells (MQW). ) construct. When the semiconductor device 20 is operating, the active structure 210 emits radiation. The above-mentioned radiation is preferably infrared light, such as near infrared light (Near Infrared, NIR). In detail, when the radiation is near-infrared light, it can have a peak wavelength (peak wavelength) between 800 nm and 1700 nm, such as: 810 nm, 840 nm, 910 nm, 940 nm, 1050nm, 1070nm, 1100nm , 1200nm, 1300nm, 1400 nm, 1450 nm, 1550nm, 1600nm, 1650nm, 1700nm, etc. Active structure 110 may include a fourth III-V semiconductor material. The fourth group III-V semiconductor materials are materials composed of Group III and Group V elements in the periodic table of chemical elements. Group III elements can be gallium (Ga) or indium (In). The Group 5 element may be arsenic (As) or phosphorus (P), and preferably does not include nitrogen (N). The fourth III-V semiconductor material may be a quaternary III-V semiconductor material. In some embodiments, active structure 110 consists essentially of a fourth III-V semiconductor material. For example, the active structure 110 may be substantially composed of a quaternary III-V semiconductor material such as InGaAsP or AlGaInAs.

The fourth semiconductor layer 208 and the fifth semiconductor layer 212 are respectively located on both sides of the active structure 210, and the fourth semiconductor layer 208 and the fifth semiconductor layer 212 may have opposite conductive types. For example, the fourth semiconductor layer 208 and the fifth semiconductor layer 212 may be n-type semiconductors and p-type semiconductors respectively to provide electrons and holes respectively. Alternatively, the fourth semiconductor layer 208 and the fifth semiconductor layer 212 may be p-type semiconductors and n-type semiconductors respectively to provide holes and electrons respectively. The fourth semiconductor layer 208 and the third semiconductor layer 204 may have the same conductivity type, such as n-type semiconductor layers. In addition, the fourth semiconductor layer 208 and the fifth semiconductor layer 212 respectively include a fifth group III-V semiconductor material and a sixth group III-V semiconductor material. The fifth group III-V semiconductor material and the sixth group III-V semiconductor material may be binary, ternary or quaternary group III-V semiconductor materials respectively. Group III-V semiconductor materials refer to materials composed of Group III and Group V elements in the periodic table of chemical elements. Group III elements can be gallium (Ga) or indium (In). The Group 5 element may be arsenic (As) or phosphorus (P), and preferably does not include nitrogen (N). In one embodiment, the fourth semiconductor layer 208 and the fifth semiconductor layer 212 are substantially composed of quaternary semiconductor materials (such as InGaAsP, AlGaInP or AlGaInAs).

The fourth semiconductor layer 208 and the fifth semiconductor layer 212 have different conductive types by adding different dopants. Specifically, the dopant includes magnesium (Mg), zinc (Zn), silicon (Si), tellurium (Te), etc., but is not limited thereto. In some embodiments, the third step may be performed by in-situ doping during epitaxial growth and/or by implanting after epitaxial growth using P-type or N-type dopants. Doping of the fourth semiconductor layer 208 and the fifth semiconductor layer 212. In one embodiment, the dopants in the fourth semiconductor layer 208 and the fifth semiconductor layer 212 may each independently have a doping concentration of 2×10 ¹⁷ cm ⁻³ to 1×10 ²⁰ cm ⁻³ , for example, having a doping concentration of 5 Doping concentration from ×10 ¹⁷ cm ⁻³ to 5×10 ¹⁹ cm ⁻³ .

In some embodiments, an etching barrier layer may be further disposed between the first semiconductor layer 100 and the light emitting structure 206 . Referring to FIG. 2A , for example, an etch stop layer (not shown) may be located between the first semiconductor layer 100 and the third semiconductor layer 204 . Then, the first semiconductor layer 100 can be removed according to the requirements of the device structure, thereby forming the semiconductor device 20' as shown in Figure 2B. By providing the etching barrier layer, damage to the third semiconductor layer 204 and the light-emitting structure 206 can be avoided when the first semiconductor layer 100 is removed. Next, the semiconductor device 20' may include a bonding layer (not shown) and be bonded to a supporting substrate through the bonding layer, and then undergo subsequent processes. In one embodiment, the semiconductor device 20' only includes a structure as shown in FIG. 2B without a supporting substrate. In some embodiments, the etch stop layer includes a seventh III-V semiconductor material. The seventh III-V semiconductor material may be a ternary or quaternary III-V semiconductor material. Group III-V semiconductor materials are materials composed of Group III and Group V elements in the periodic table of chemical elements. Group III elements can be aluminum (Al), gallium (Ga) or indium (In). The Group 5 element may be arsenic (As) or phosphorus (P), and preferably does not include nitrogen (N). The etch stop layer preferably contains a Group 5 element different from the Group 5 element in the composition of the first semiconductor layer 100 . In one embodiment, the etch stop layer includes a ternary III-V semiconductor material of InGaAs. In one embodiment, the etch stop layer is essentially composed of a ternary semiconductor material, such as InGaAs.

Based on the above, since the first semiconductor layer 100 can have a surface with a lower defect density, it is more suitable as a base layer for the growth of a semiconductor epitaxial layer. Specifically, when the third semiconductor layer 204 and other semiconductor layers are further formed on the first semiconductor layer 100, each semiconductor layer can still have good epitaxial quality.

FIG. 3 is a schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure. In this embodiment, the semiconductor device 30 includes a first semiconductor layer 300, a third semiconductor layer 304, a light emitting structure 306, a window layer 314, a first electrode 318 and a second electrode 320. Regarding the composition of the first semiconductor layer 300 , the third semiconductor layer 304 and the light-emitting structure 306 , reference may be made to the foregoing descriptions of the first semiconductor layer 100 , the third semiconductor layer 204 and the light-emitting structure 206 , respectively, and will not be described again here. In detail, for the compositions of the fourth semiconductor layer 308, the active structure 310, and the fifth semiconductor layer 312 in the light-emitting structure 306, please refer to the aforementioned descriptions of the fourth semiconductor layer 208, the active structure 210, and the fifth semiconductor layer 212 respectively.

In this embodiment, the window layer 314 is located on the light-emitting structure 306 and adjacent to the fifth semiconductor layer 312 in the light-emitting structure 306 . In addition, the conductive type of the window layer 314 is opposite to the conductive type of the third semiconductor layer 304. For example, when the window layer 314 is a P-type semiconductor layer, the third semiconductor layer 304 is an N-type semiconductor layer. The window layer 314 can serve as a light extraction layer, thereby further improving the luminous efficiency of the semiconductor device 30 . In addition, the window layer 314 is transparent to the light emitted by the light emitting structure 306 .

The first electrode 318 and the second electrode 320 can be used to be electrically connected to an external power source, and the first electrode 318 and the second electrode 320 are electrically connected to the light emitting structure 306 . In this embodiment, the first electrode 320 is adjacent to the window layer 314, and the second electrode 318 is adjacent to the first semiconductor layer 300, but it is not limited thereto. In addition, the materials of the first electrode 318 and the second electrode 320 may be the same or different, and may include, for example, transparent conductive materials, metals, or alloys. Transparent conductive materials include metal oxides, such as indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), oxide Zinc tin (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO) or indium zinc oxide (IZO), etc. Examples of the metal include gold (Au), platinum (Pt), titanium (Ti), aluminum (Al), copper (Cu), or nickel (Ni). The alloy may include at least two selected from the group consisting of the above metal elements, such as germanium gold nickel (GeAuNi), beryllium gold (BeAu), germanium gold (GeAu), zinc gold (ZnAu), etc.

FIG. 4 is a schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure. In this embodiment, the semiconductor device 40 includes a first semiconductor layer 400 , a second semiconductor layer 402 , a third semiconductor layer 404 , a light emitting structure 406 , a window layer 414 , a contact layer 416 , a first electrode 420 and a second electrode 418 . The main difference between the semiconductor device 40 and the aforementioned semiconductor device 30 is that it further includes a second semiconductor layer 402 and a contact layer 416 . Regarding the composition of the first semiconductor layer 400, the second semiconductor layer 402, the third semiconductor layer 404, the light-emitting structure 406, the window layer 414, the first electrode 420 and the second electrode 418, please refer to the description of the previous embodiments and will not be repeated here. Again. In detail, for the compositions of the fourth semiconductor layer 408, the active structure 410, and the fifth semiconductor layer 412 in the light-emitting structure 406, please refer to the aforementioned descriptions of the fourth semiconductor layer 208, the active structure 210, and the fifth semiconductor layer 212 respectively.

The contact layer 416 is located between the first electrode 420 and the window layer 414 for conducting current. The contact layer 416 may have the same conductivity type as the window layer 314, such as a P-type semiconductor layer. In this embodiment, the contact layer 416 is adjacent to the first electrode 420 . In detail, the contact layer 416 is, for example, a doped or undoped semiconductor material layer, and may include an eighth III-V group semiconductor material. The eighth III-V semiconductor material may be a binary or ternary III-V semiconductor material, such as GaAs or InGaAs. When the first electrode 420 includes metal or alloy, an ohmic contact can be formed between the first electrode 420 and the contact layer 416, so that a good electrical contact is formed between the first electrode 420 and the light-emitting structure 406.

5A to 5B are schematic cross-sectional views of a method for manufacturing a semiconductor stack according to an embodiment of the present disclosure. FIG. 5C is a flow chart of manufacturing a semiconductor stack according to an embodiment. The above-mentioned semiconductor stack is, for example, a partial structure of a semiconductor element. As shown in FIGS. 5A and 5B , the second semiconductor layer 502 is first provided, and the first semiconductor layer 500 is formed on the second semiconductor layer 502 . For related descriptions of the first semiconductor layer 500 and the second semiconductor layer 502, please refer to the description of the first semiconductor layer 100 and the second semiconductor layer 102 in the previous embodiments, and will not be described again here.

Referring to FIGS. 5A to 5C , step S510 is performed to grow a part of the first semiconductor layer 500 at a first temperature. The first semiconductor layer 500 is grown by, for example, liquid phase epitaxy (LPE), molecular beam epitaxy (MBE), chemical beam epitaxy (CBE), It is achieved by Metal Organic Chemical Vapor Deposition (MOCVD) or hydride vapor phase epitaxial (HVPE). The first temperature is, for example, below 650°C and above 400°C, preferably no more than 520°C, more preferably in the range of 450°C to 510°C or 420°C to 500°C. By growing the first semiconductor layer 500 within the above temperature range, good epitaxial quality can be further obtained.

Next, step S520 is performed to provide a second temperature greater than the first temperature. The second temperature is, for example, above 700°C and below 850°C, preferably above 750°C, more preferably in the range of 760°C to 810°C or 780°C to 800°C. In step S520, for example, the epitaxial environment temperature is adjusted from the first temperature to the second temperature. In some embodiments, the difference between the first temperature and the second temperature is not less than 300°C, thereby achieving a better epitaxial effect. In addition, at the second temperature, the growth of the first semiconductor layer 500 may not be performed. In this step, high temperature tempering is performed by adjusting the ambient temperature to a higher second temperature. Not continuing to grow the first semiconductor layer 500 at the second temperature can allow the stress in a portion of the first semiconductor layer 500 previously grown at the first temperature to be adjusted and reduce epitaxial defects.

Then, step S530 is entered to confirm the thickness of the first semiconductor. When the first semiconductor layer 500 has reached the predetermined thickness, the preparation of the first semiconductor layer 500 and the second semiconductor layer 502 is completed. In some embodiments, the predetermined thickness may be below 20 μm, preferably below 10 μm, more preferably below 5 μm, and may be above 1 μm. When the first semiconductor layer 500 has not reached the predetermined thickness, step S540 is entered, and step S510 and step S520 are repeated, for example, step S510 and step S520 are repeated at least twice. In some embodiments, step S510 and step S520 can be repeated more than ten times to obtain a semiconductor stack of appropriate thickness and relatively stable epitaxial quality. In addition, the number of times step S510 and step S520 are repeated may be less than thirty times.

Based on the above, through the above-mentioned heating and cooling methods in the process of preparing the first semiconductor layer 500, there is no need to use other buffer structures or processes to adjust the lattice differences between the first semiconductor layer 500 and the second semiconductor layer 502. Matching the problem of stress generation, a structure with good epitaxial quality can be obtained.

In some embodiments, the stack of the first semiconductor layer 500 and the second semiconductor layer 502 can be used as the base layer, and subsequent epitaxial structure growth is performed as required, for example, on the stack of the first semiconductor layer 500 and the second semiconductor layer 502 . Light-emitting structures, etc. are further directly formed on the layer.

As shown in FIG. 5D , a third semiconductor layer 504 may be further formed on the first semiconductor layer 500 and the second semiconductor layer 502 . For related descriptions of the third semiconductor layer 504, please refer to the description of the third semiconductor layer 204 in the previous embodiments, and will not be described again here. As mentioned above, the light emitting structure may be formed on the third semiconductor layer 504. One side of the first semiconductor layer 500 is adjacent to the second semiconductor layer 502, and the other side is adjacent to the third semiconductor layer 504. The surface 500a of the first semiconductor layer 500 directly contacts the surface 502a of the second semiconductor layer 502, and the other surface 500b Directly contact the surface 504a of the third semiconductor layer 504.

FIG. 5E is a graph illustrating the relationship between concentration and thickness of elements in a portion of a semiconductor device according to an embodiment of the present disclosure. Specifically, Figure 5E is the result of secondary ion mass spectrometry (SIMS) analysis of a partial region of the light-emitting element containing the structure shown in Figure 5D. As shown in Figure 5E, according to the thickness and order of each layer in the semiconductor device, it can be roughly divided into a first area Z1, a second area Z2 and a third area Z3. Specifically, the first region Z1 corresponds to the second semiconductor layer 502, the second region Z2 corresponds to the first semiconductor layer 500, the third region Z3 corresponds to the third semiconductor layer 504, and in this embodiment, the first semiconductor layer The layer 500 and the third semiconductor layer 504 both contain a plurality of dopants and are substantially composed of InP. The second semiconductor layer 502 contains a plurality of dopants and are substantially composed of GaAs. The above-mentioned dopants include at least a first dopant, a second dopant and a third dopant. The first dopant is carbon (C) and is represented by C1, the second dopant is hydrogen (H) and is represented by C2, and the third dopant is silicon (Si) and is represented by C3. For the concentrations of C1, C2 and C3 of the first, second and third dopants, please refer to the left vertical axis of Figure 5E. In this embodiment, the first dopant and the second dopant are unintentionally doped, and the third dopant is intentionally doped.

The first semiconductor layer 500 with a single-layer structure is grown in the above manner, so that the unintentionally doped first dopant and the second dopant have a doping concentration greater than 10 ¹⁶ cm ⁻³ in the first semiconductor layer 500 , and the concentration curve of carbon (C) has a pattern similar to periodic changes. As shown in FIG. 5E , in the second region Z2, the concentration of the second dopant is higher than the concentration of the first dopant, that is, the concentration of hydrogen (H) in the first semiconductor layer 500 is greater than that of carbon (C). concentration. Furthermore, the third dopant concentration in the second zone Z2 is lower than the third dopant concentration in the first zone Z1 and is also lower than the third dopant concentration in the third zone Z3. That is, the silicon (Si) concentration in the first semiconductor layer 500 is lower than the silicon (Si) concentration in the second semiconductor layer 502 or the third semiconductor layer 504 . On the other hand, in the second region Z2, the concentration of the second dopant is higher than the concentration of the third dopant, that is, the hydrogen (H) concentration in the first semiconductor layer 500 is greater than the silicon (Si) concentration.

Figure 5F is a partially enlarged schematic diagram of the concentration curve of the first dopant (carbon (C)) in the dotted box area in the second area Z2 of Figure 5E. As shown in Figure 5F, in this embodiment, the concentration distribution of the first dopant (carbon (C)) includes at least i local maxima (concentrations C _L1 , C _L2 , ..., marked in the figure) C _Li ) and i local minima (concentrations C _M1 , _CM2 ,..., C _Mi marked in the figure), i is, for example, a positive integer greater than or equal to 5, in the local area as shown in Figure 5F i=8. Local maxima and local minima appear alternately, and any one of the local maxima is greater than any one of the local minima. As shown in Figure 5E, in the first block of the second area Z2, the concentration of the third dopant is less than part of the local maximum; in the second block of the second area Z2, the concentration of the third dopant The concentration is greater than some local minima.

As shown in Figure 5E, in this embodiment, the doping concentration of silicon (Si) in the first semiconductor layer 500 is below 1×10 ¹⁷ cm ⁻³ and is between about 5×10 ¹⁶ cm ⁻³ and about 9 ×10 ¹⁶ cm ⁻³ ; the carbon (C) concentration ranges from about 4×10 ¹⁶ cm ⁻³ to about 9×10 ¹⁶ cm ⁻³ ; the hydrogen (H) concentration ranges from about 1×10 ¹⁷ cm ⁻³ to The range is about 5×10 ¹⁷ cm ⁻³ . On the other hand, in some embodiments, the first region Z1, the second region Z2 and the third region Z3 also contain unavoidable impurities, such as oxygen (O), etc., which are not shown here for the sake of simplicity. . In one embodiment, the oxygen (O) concentration in the first zone Z1, the second zone Z2 and the third zone Z3 is distributed in the range of 3×10 ¹⁵ cm ⁻³ to 2×10 ¹⁶ cm ⁻³ , which is close to 2 Detection limits of secondary ion mass spectrometry (SIMS) analysis.

FIG. 6 is a schematic diagram of the packaging structure of a semiconductor device according to an embodiment of the present disclosure. Referring to FIG. 6 , the packaging structure 600 includes a semiconductor component 60 , a packaging substrate 61 , a carrier 63 , bonding wires 65 , contact structures 66 and packaging materials 68 . The packaging substrate 61 may include ceramic or glass materials. The package substrate 61 has a plurality of through holes 62 therein. The through hole 62 may be filled with conductive material such as metal to facilitate conduction and/or heat dissipation. The carrier 63 is located on the surface of one side of the packaging substrate 61 and also includes conductive material, such as metal. Contact structure 66 is located on the surface of the other side of package substrate 61 . In this embodiment, the contact structure 66 includes a contact pad 66 a and a contact pad 66 b, and the contact pad 66 a and the contact pad 66 b can be electrically connected to the carrier 63 through the through hole 62 . In one embodiment, the contact structure 66 may further include a thermal pad (not shown), for example, located between the contact pad 66a and the contact pad 66b. The semiconductor device 60 is located on the carrier 63 and may be a semiconductor device as described in any embodiment of this disclosure. In this embodiment, the carrier 63 includes a first part 63 a and a second part 63 b, and the semiconductor device 60 is electrically connected to the second part 63 b of the carrier 63 through the bonding wire 65 . The material of the bonding wire 65 may include metal, such as gold, silver, copper, aluminum or an alloy containing at least any of the above elements. The packaging material 68 covers the semiconductor element 60 and has the effect of protecting the semiconductor element 60 . Specifically, the encapsulating material 68 may include resin materials such as epoxy, silicone, etc. The encapsulation material 68 may further include a plurality of wavelength conversion particles (not shown) to convert the first light emitted by the semiconductor device 60 into a second light. The wavelength of the second light is greater than the wavelength of the first light.

The light-emitting components disclosed in the present disclosure can be applied to products in the fields of lighting, medical treatment, display, communication, sensing, power supply systems, etc., such as lamps, monitors, mobile phones, tablet computers, vehicle dashboards, televisions, computers, wearable devices (such as watches, bracelets, necklaces, etc.), traffic signals, outdoor displays, medical equipment, etc.

Based on the above, according to some embodiments of the present disclosure, a semiconductor structure can be provided, which has good surface epitaxial quality, can be used as a substrate for semiconductor devices, and is conducive to further reducing the production cost of semiconductor devices. According to some embodiments of the present disclosure, a semiconductor element and a manufacturing method thereof can be provided, which achieve excellent technical effects in regulating the stress caused by lattice mismatch between heteroepitalized crystals, and can avoid The epitaxial layer has defects at the interface.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Those of ordinary skill in the art will understand that slight modifications or changes may be made without departing from the spirit and scope of the present invention. Therefore, the present invention is The protection scope of the invention shall be determined by the appended patent application scope. In addition, the above-described embodiments may be combined or replaced with each other under appropriate circumstances and are not limited to the specific embodiments described. For example, the relevant parameters of a specific component or the connection relationship between a specific component and other components disclosed in one embodiment can also be applied to other embodiments, and all fall within the scope of the present invention.

10: Semiconductor stack 20, 20', 30, 40, 60: Semiconductor element 61: Package substrate 62: Through hole 63: Carrier 63a: First part 63b: Second part 65: Bonding wire 66: Contact structure 66a, 66b: Contact pad 68: packaging material 100, 300, 400, 500: first semiconductor layer 102, 402, 502: second semiconductor layer 204, 304, 404, 504: third semiconductor layer 206, 306, 406: light emitting structure 208, 308, 408: fourth semiconductor layer 210, 310, 410: active structure 212, 312, 412: fifth semiconductor layer 414: window layer 416: contact layer 600: packaging structure 318, 418: first electrode 320, 420: third Two electrodes S510, S520, S530, S540: step C ₁ : first concentration C ₂ : second concentration C ₃ : second concentration C _L1 , C _L2 , C _Li , _CM1 , _CM2 , C _Mi : concentration

FIG. 1 is a schematic structural diagram of a semiconductor stack according to an embodiment of the present disclosure.

FIG. 2A is a partial structural diagram of a semiconductor device according to an embodiment of the present disclosure.

FIG. 2B is a partial structural diagram of a semiconductor device according to an embodiment of the present disclosure.

FIG. 3 is a schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure.

FIG. 4 is a schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure.

5A to 5D are schematic diagrams of a manufacturing method of a semiconductor stack according to an embodiment of the present disclosure.

FIG. 5E is a diagram illustrating the relationship between concentration and depth of elements in a portion of a semiconductor device according to an embodiment of the present disclosure.

Figure 5F is a partially enlarged schematic diagram showing the concentration curve of carbon (C) in Figure 5E.

FIG. 6 is a schematic diagram of the packaging structure of a semiconductor device according to an embodiment of the present disclosure.

10: Semiconductor stack

100: First semiconductor layer

102: Second semiconductor layer

100a, 102a: surface

Claims (10)

A semiconductor component containing: a first semiconductor layer including a first III-V group semiconductor material; a light-emitting structure located on the first semiconductor layer and including an active structure; and a second semiconductor layer located under the first semiconductor layer and including a second III-V semiconductor material; a third semiconductor layer located between the first semiconductor layer and the light-emitting structure and including a third group III-V semiconductor material; Wherein, the first semiconductor layer, the second semiconductor layer and the third semiconductor layer include a first dopant and a second dopant, and the concentration of the first dopant in the first semiconductor layer is greater than The concentration of the first dopant in the second semiconductor layer is greater than the concentration of the first dopant in the third semiconductor layer. The concentration of the second dopant in the first semiconductor layer is lower than the concentration of the second dopant in the second semiconductor layer, and the concentration of the second dopant in the first semiconductor layer is lower than the concentration of the second dopant in the second semiconductor layer. The concentration of the second dopant in the third semiconductor layer. The semiconductor component of claim 1, wherein the light-emitting structure emits near-infrared light with a peak wavelength between 800 nm and 1700 nm. The semiconductor device of claim 1, wherein the second III-V group semiconductor material is different from the first III-V group semiconductor material. The semiconductor device according to claim 1, further comprising a fourth semiconductor layer located between the third semiconductor layer and the light-emitting structure, and comprising a binary, ternary or quaternary III-V group semiconductor material. The semiconductor device of claim 1, wherein the first semiconductor layer, the second semiconductor layer and the third semiconductor layer further include a third dopant. The semiconductor device of claim 1, wherein in the first semiconductor layer, the concentration distribution of the first dopant at least includes a plurality of local maxima and a plurality of local minima, and the local maxima are consistent with the local minima. Local minima occur alternately, and any one of the local maxima is larger than any one of the local minima. The semiconductor device of claim 1, wherein the concentration distribution of the first dopant includes at least 5 local maxima and 5 local minima. The semiconductor device of claim 1, wherein the first dopant and the second dopant include silicon (Si), zinc (Zn), carbon (C) or hydrogen (H). The semiconductor device according to claim 1, wherein in the third semiconductor layer, the concentration of the first dopant is lower than the concentration of the second dopant. A packaging structure for semiconductor components, including: a carrier; A semiconductor component located on the carrier and which is a semiconductor component as described in any one of claims 1 to 9; and Encapsulation material covers the semiconductor component.