TW202331950A - Wiring board and method for manufacturing same - Google Patents

Abstract

The present invention addresses the problem that, when forming a capacitor electrode by electrolytic plating using a seed layer, if step constriction occurs due to side etching in a step during formation of the seed layer, complete formation of the seed layer may fail, and complete formation of the electrode by electrolytic plating may fail. Thus, the purpose of the present invention is to provide a wiring board in which side etching does not occur in a seed layer. Accordingly, in the present invention, in a wiring board having an MIM capacitor structure comprising a board (1) having an insulating surface, a first seed layer (3), a first conductive layer (4), a first insulating layer (6), a second seed layer (8), and a second conductive layer (9), a step for patterning the first seed layer by etching comprises performing etching using an etching mask having a width greater than the first conductive layer in at least one direction.

Description

Wiring substrate and manufacturing method thereof

The present invention relates to a wiring substrate and a manufacturing method thereof.

Multilayer wiring boards (hereinafter referred to as "glass boards", etc.) using glass materials as core boards are often used as interposers. In these multilayer wiring boards, thin film capacitors are sometimes formed inside the board. As part of the passive circuit, the thin film capacitors have a MIM (Metal Insulator Metal, Metal Insulated Metal) that sandwiches a dielectric between the lower electrode layer and the upper electrode layer. layer metal) structure.

In Patent Document 1, it is disclosed that "a wiring substrate includes: a substrate having an insulating surface; a first conductive layer disposed on the substrate and comprising a first part and a second part, the first part having a first thickness, the aforementioned second portion has a second thickness thinner than the first thickness, and is adjacent to the first portion; the first insulating layer is disposed on the aforementioned first portion in a manner to be separated from the aforementioned second portion and the second conductive layer are arranged on the opposite side to the first part with respect to the first insulating layer. [Prior Art Literature] [Patent Document]

Patent Document 1: International Publication No. 2019/244382

[Problem to be solved by the invention]

When forming a MIM capacitor on an insulating substrate, firstly, a first seed layer is provided, and a first conductive layer is provided by plating or the like using the first seed layer, and this is used as the lower electrode of the capacitor. Next, an insulating layer is provided on the lower electrode, and a second conductive layer is further provided on the insulating layer by electroplating using the second seed layer and the second seed layer, as an upper electrode. In such a first conductive layer-insulating layer-second conductive layer capacitor, generally speaking, the coefficient of thermal expansion is different between the conductive layer and the dielectric layer, so stress and strain may occur in the capacitor. Therefore, Patent Document 1 discloses that in order to relax the stress in the first conductive layer of the MIM, a step is provided near the boundary between the first conductive layer and the first insulating layer.

However, in a capacitor in which a lower electrode or an upper electrode is formed using a seed layer, side etching tends to occur because the film thickness of the seed layer is thin. Next, the second seed layer is formed on the portion where the side etching has occurred by a method such as sputtering, so there is a high possibility that the second seed layer cannot be completely formed. Therefore, an object of the present invention is to provide a wiring board that does not cause side etching in the seed layer, and its manufacturing technique, for example. [Means to solve the problem]

In order to solve the above-mentioned problems, a representative method of manufacturing a wiring board according to the present invention is that the wiring board includes: a substrate having an insulating surface; a first seed layer arranged on the substrate; and a first seed layer arranged above the seed layer. 1 conductive layer; a first insulating layer disposed above the first conductive layer; a second seed layer disposed above the first insulating layer; and a second conductive layer disposed above the second seed layer, In the above wiring board, the step of patterning the first seed layer by etching is performed by using an etching mask having a width larger than that of the first conductive layer in at least one direction.

Furthermore, in order to solve the above-mentioned problems, a typical wiring board of the present invention is composed of Substrates with insulating surfaces and wiring substrates with layers (1) to (5) below: (1) The first seed layer arranged on the aforementioned substrate; (2) The first conductive layer arranged above the aforementioned first seed layer; (3) The first insulating layer arranged above the aforementioned first conductive layer; (4) the second seed layer arranged above the first insulating layer; and (5) the second conductive layer arranged above the aforementioned second seed layer, The layers of the aforementioned (1) to (5) constitute a MIM capacitor, In the MIM capacitor whose width is larger than that of the first conductive layer in the MIM capacitor, the width of the first seed layer in the horizontal direction is b, and the width of the first conductive layer in the horizontal direction is a In the case of , a and b satisfy the following formula (2): 50nm≦(b-a)/2≦50μm ･･･(2) [Effect of Invention]

According to the present invention, it is possible to provide a wiring board which does not cause side etching in a seed layer and a manufacturing method thereof. Problems, configurations, and effects other than those described above will be clarified by the description in the following embodiments for implementation.

[Mode for Carrying Out the Invention]

Hereinafter, the basic structure which is the object of this invention, the manufacturing method of a conventional example, the 1st embodiment, the 2nd embodiment etc. of this invention are demonstrated with reference to drawings. In addition, the present invention is not limited by these disclosures. In addition, in description of drawings, the same code|symbol is attached|subjected and shown to the same part. When there are plural components having the same or similar function, the same symbols may be described with different additional symbols. In addition, when it is not necessary to distinguish these plural constituent elements, the reference numerals may be omitted for description. Regarding the position, size, shape, range, etc. of each component shown in the drawings, the actual position, size, shape, range, etc. may not be shown in order to facilitate understanding of the invention. Therefore, the present invention is not necessarily limited to the positions, sizes, shapes, ranges, etc. disclosed in the drawings.

In addition, in the present disclosure, the so-called "surface" is not only the surface of the plate-shaped member, but may also mean the interface between layers that are approximately parallel to the surface of the plate-shaped member with respect to the layers included in the plate-shaped member. In addition, "upper side" and "lower side" mean a surface shown above or below the drawing when a plate-shaped member or a layer included in the plate-shaped member is shown in the drawing. Also, "upper side" and "lower side" are sometimes referred to as "first side" and "second side".

In addition, the term "side" refers to a surface of a plate-shaped member or a layer included in a plate-shaped member or a part of the thickness of a layer. In addition, a part of a surface and a side surface may be collectively referred to as an "end". In addition, the term "upper" means a vertically upper direction when a plate-like member or layer is placed horizontally. Furthermore, "upper" and the opposite "lower" are sometimes referred to as "Z-axis positive direction" and "Z-axis negative direction", and the horizontal direction is sometimes referred to as "X-axis direction". , "Y axis direction".

Also, the so-called "plane shape" and "plane view angle" mean: the shape of a surface or layer when viewed from above, that is, from the positive direction of the z-axis toward the negative direction. In addition, the so-called "cross-sectional shape" and "cross-sectional view angle" mean the shape seen from the horizontal direction when a plate-like member or layer is cut in a specific direction. In addition, the so-called "central part" means not the peripheral part of the surface or the layer, but the central part. Furthermore, the so-called "central direction" means the direction from the peripheral portion of the surface or layer toward the center of the planar shape of the surface or layer.

[basic structure] First, the basic structure of a wiring board having a MIM capacitor as a premise of the manufacturing method of the present invention will be described with reference to FIG. 1 . Fig. 1 is a cross-sectional view of a wiring substrate. The wiring substrate includes: a substrate 1 with an insulating surface, a first seed layer 3 disposed on the substrate 1, and a first conductive layer 4 disposed above the first seed layer 3. , the first insulating layer 6 disposed above the first conductive layer 4 , the second seed layer 8 disposed above the first insulating layer 6 , and the second conductive layer 9 disposed above the second seed layer 8 . In the wiring substrate shown in FIG. 1 , the first conductive layer 4 becomes the lower electrode of the MIM, the first insulating layer 6 becomes the dielectric layer of the MIM, and the second conductive layer 9 becomes the upper electrode of the MIM, forming a MIM capacitor on the substrate 1 .

＜Description of each element＞ Hereinafter, the material, shape, etc. of each element of the MIM capacitor which is a premise of the manufacturing method of the present invention will be described in detail. (substrate) The substrate 1 is preferably made of transparent glass with light penetration. There are no particular limitations on the components of the glass, the compounding ratio of each component contained in the glass, and the method of manufacturing the glass. For example, glass includes non-alkali glass, alkali glass, borosilicate glass, quartz glass, sapphire glass, photosensitive glass, etc. Any glass material containing silicate as a main component can also be used. Furthermore, other glass materials that are commonly used can also be used. However, in the case where the substrate 1 of the present disclosure is mounted with a semiconductor, it is preferable to use alkali-free glass. Also, the thickness of the glass substrate is preferably 1 mm or less, but it is preferably 0.1 mm or more and 0.8 mm or less in consideration of the ease of the glass through-hole forming process and the ease of manufacture.

For the manufacturing method of the glass substrate, there are float method, down-draw method, fusion method, up-draw method, roll-out method, etc. method, etc., the glass material produced by any method can be used, and it is not limited to this embodiment. The linear expansion coefficient of glass is preferably -1 ppm/K or more and 15.0 ppm/K or less. The reason is that when it is -1ppm/K or less, it is difficult to select the glass material itself, and it cannot be manufactured at low cost. On the other hand, when it is 15.0 ppm/K or more, the difference in thermal expansion coefficient with other layers becomes large, and reliability falls. Also, when the silicon chip is mounted on the substrate 1, the connection reliability with the silicon chip is lowered. In addition, the coefficient of linear expansion of glass is preferably from 0.5 ppm/K to 8.0 ppm/K, more preferably from 1.0 ppm/K to 4.0 ppm/K. Functional films such as an anti-reflection film or an IR cut filter may also be formed on the glass substrate in advance. In addition, functions such as strength, antistatic, coloring, and texture control can also be imparted. Taking the example of these functional films as an example, hard coating film can be mentioned for strength imparting, antistatic film can be mentioned for antistatic imparting, optical filter film can be mentioned for coloring, and optical filter film can be mentioned for texture control. Anti-glare film, light-scattering film, etc., but not limited thereto. For the formation method of such functional films, film formation techniques such as vapor deposition, sputtering, and wet methods can be used.

(First Seed Layer) The metal layer constituting the first seed layer 3 functions as a power supply layer for electrolytic plating during the formation of wiring by the semi-additive process. The seed metal layer disposed directly above the substrate 1 and forming the inner wall of the through-hole of the substrate 1 is formed by, for example, a sputtering method or a CVD method, and is formed using, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO, IZO, AZO, ZnO, PZT, TiN, Cu ₃ N ₄ , Cu alloy alone or in combination. An electroless plating layer (electroless copper plating, electroless nickel plating, etc.) may also be formed on the first seed layer 3 of the present disclosure.

(adhesive layer) In the embodiments of the present disclosure, before the seed layer is formed on the substrate 1 or the first insulating layer 6, it is preferable to form the seed layer on the substrate 1 or the first insulating layer 6 in view of electrical characteristics, ease of manufacture, and cost. Titanium deposited by sputtering was formed as the adhesion layer 2 . In the capacitor, the lower adhesion layer 5 has the function of improving the adhesion between the lower electrode, that is, the first conductive layer, and the dielectric layer, and the upper adhesion layer 7 has the function of improving the adhesion between the dielectric layer and the seed metal layer. . The material of the lower adhesive layer and the upper adhesive layer is, for example, Ti. In addition, for example, Cu, Ni, Al, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, Cu alloy alone or a combination of plural types can also be used. Ti is excellent in terms of adhesion, conductivity, ease of manufacture, and cost.

The thickness of the lower adhesive layer and the upper adhesive layer is preferably, for example, not less than 10 nm and not more than 1 μm. When it is less than 10 nm, the adhesion strength may be insufficient. When the thickness exceeds 1 μm, it takes too long to form a film in the process described later, which is not only detrimental to mass production, but also may take time in the step of removing unnecessary parts. The thickness of the lower adhesive layer and the upper adhesive layer is preferably not less than 10 nm and not more than 500 nm. The respective thicknesses of the lower adhesive layer and the upper adhesive layer may also be different, but they are preferably the same thickness in order to present a simple structure. In addition, if the lower electrode is sufficiently in close contact with the dielectric layer, it does not matter if there is no lower close contact layer. When the dielectric layer and the seed metal layer are sufficiently in close contact, it does not matter if there is no upper close contact layer.

(wiring) The adhesive layer 2, the first seed layer 3, and the first conductive layer 4 formed on the substrate 1 are formed on the substrate 1 other than the area where the MIM capacitor is formed, and can be used as wiring for circuit formation. For use as a circuit, the total film thickness of the titanium and copper layers is preferably 5 μm or less because it is advantageous for forming fine wiring by the semi-additive method. When it is thicker than 5 μm, it may be difficult to form fine wiring with a pitch of 30 μm or less. As for the formation method of the first conductive layer, in consideration of its use as a circuit, electrolytic copper plating is preferable because it is simple and inexpensive, and has good electrical conductivity. Of course, in addition to electrolytic copper plating, electrolytic nickel plating, electrolytic chrome plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, electrolytic iridium plating, etc. can also be used.

(1st insulating layer) From the perspective of insulation and dielectric constant, the first insulating layer 6, that is, the dielectric layer system, can be made of aluminum oxide, silicon dioxide, silicon nitride, tantalum oxide, titanium oxide, calcium titanate, barium titanate, etc. , Strontium titanate to choose. The thickness of the dielectric layer is preferably not less than 10 nm and not more than 5 μm. When the thickness of the dielectric layer is 10 nm or less, insulation cannot be maintained, and the function as a capacitor cannot be exhibited. When the thickness of the dielectric layer is more than 5 μm, it takes too much time to form a film, which is not conducive to mass production, and takes more time in the step of removing unnecessary parts. Preferably, it is 50 nm or more and 1 μm or less.

(2nd seed layer) The second seed layer 8 is used to form the power supply layer which is the second conductive layer of the capacitor, that is, the upper electrode by the semi-additive method. The second seed layer 8 can be used, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, Cu alloy alone or in combination. species. For ease of subsequent etching and removal, copper is preferred. The thickness of the seed metal layer is desirably not less than 50 nm and not more than 5 μm. When the thickness of the seed metal layer is less than 50 nm, there is a possibility that poor conduction may occur in the subsequent electrolytic plating step. When the thickness of the seed metal layer exceeds 5 μm, it takes time for etching removal. The thickness of the seed metal layer is more preferably not less than 100 nm and more preferably not more than 500 nm.

(2nd conductive layer) The second conductive layer 9, that is, the upper electrode is an electrolytic plating layer. Electrolytic copper plating is preferable because it is simple and inexpensive, and has good electrical conductivity. Of course, in addition to electrolytic copper plating, electrolytic nickel plating, electrolytic chrome plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, electrolytic iridium plating, etc. can also be used. The thickness of the upper electrode (thickness of electrolytic copper plating) is desirably not less than 3 μm and not more than 30 μm. If the thickness is less than 3 μm, the circuit may be lost due to the etching process after the upper electrode is formed. Furthermore, there is a risk of lowering the connection reliability and conductivity of the circuit. When the thickness of the electrolytic copper plating exceeds 30 μm, it is necessary to form a photoresist layer with a thickness of more than 30 μm, which cannot suppress the manufacturing cost. Furthermore, since the resolution of the photoresist image decreases, it becomes difficult to form fine wiring with a pitch of 30 μm or less. More preferably, it is not less than 5 μm and more preferably not more than 25 μm. Furthermore, it is still more preferably 10 μm or more and 20 μm or less.

[Manufacturing method of conventional example] Next, with reference to FIGS. 2 to 6, a conventional example of manufacturing a wiring board having a MIM capacitor having the structure shown in FIG. 1 will be described. First, as shown in FIG. 2 , an adhesion layer 2 and a first seed layer 3 are formed on a substrate 1 having an insulating surface, and a pattern of a resist 11 is formed thereon. Next, as shown in FIG. 3 , the first conductive layer 4 is formed by electrolytic plating using the first seed layer 3 as a power supply layer. Next, as shown in FIG. 4 , the resist 11 is removed, and as shown in FIG. 5 , using the first conductive layer 4 as an etching mask, unnecessary portions of the adhesion layer 2 and the first seed layer 3 are removed. However, once the above-mentioned manufacturing method is adopted, side etching of the adhesive layer 2 and the first seed layer 3 may occur in the region around the end of the first conductive layer 4 as shown by X in FIG. 6 . Since the thickness of the adhesive layer 2 and the first seed layer 3 is small, the etching speed in the x direction is fast, and it is difficult to prevent side etching.

In the manufacturing steps of the MIM structure, after the first conductive layer 4, which is the lower electrode, is formed, the first insulating layer 6 as a dielectric layer is formed, and the upper adhesive layer 7 and the second insulating layer 6 are formed on the first insulating layer 6. After the seed layer 8, power is supplied to the second seed layer to form the second conductive layer 9 to be the upper electrode. At this time, in the case of forming the upper adhesive layer 7 and the second seed layer 8 by sputtering, the throwing power (THROWING POWER) of the sputtered film on the side wall of the lower electrode layer, that is, the first conductive layer 4 is very low. It largely depends on the shape of the end portion of the first conductive layer 4 . Therefore, as shown in FIG. 6, once side etching occurs in the adhesion layer 2 and the first seed layer 3, the throwing power of the coating film by sputtering becomes insufficient, and the second seed layer 8 is discontinuous. . As a result, when the second conductive layer 9 is formed by electrolytic plating, power supply cannot be performed, and a problem that a plating film cannot be formed occurs.

Furthermore, when the first conductive layer 4 as shown in FIG. 6 is used as an etching mask to etch the adhesion layer 2 and the first seed layer 3, the smoothness of the upper surface of the first conductive layer 4 will be damaged, and It will adversely affect the accuracy or yield of MIM capacitors. In this regard, according to the implementation aspect of the present disclosure, the smoothness of the interface between the lower electrode and the dielectric can be maintained, and the short circuit of the capacitor caused by surface cracks or the capacitance deviation caused by the deviation of the electrode surface area can be reduced. Therefore, the yield of the capacitor can be improved, and stable manufacturing can be performed.

[First Embodiment] In order to solve the problems of the conventional production method as described above, the production method described below is adopted for the first embodiment of the present invention. Hereinafter, the first embodiment will be described with reference to FIGS. 2 to 4 and FIGS. 7 to 11 .

(step 1) Steps 1 to 6 of the first embodiment are the same as those of the conventional example, so they will be described with reference to FIGS. 2 to 4 . First, although not shown in FIGS. 2 to 11 and FIGS. 13 to 17 , the substrate 1 may have through holes penetrating from the upper surface to the lower surface of the substrate 1 . The cross-sectional shape or diameter of the through-hole may be, for example, a shape in which the central portion of the through-hole is narrower than the top and bottom diameters, or may be, for example, a shape in which the bottom diameter is smaller than the top diameter. Furthermore, the diameter of the central portion may be wider than the diameters of the top and bottom of the through-holes.

(step 2) Next, as shown in FIG. 2 , the adhesion layer 2 and the first seed layer 3 are formed on the surface of the substrate 1 . When a through hole is formed, the adhesive layer 2 and the first seed layer 3 are also formed in the through hole. The adhesive layer 2 and the first seed layer 3 function as a power supply layer for electrolytic plating in the wiring formation step of the semi-additive process. The steps of forming the adhesion layer 2 and the first seed layer 3 are preferably as follows: form titanium on the substrate 1 by sputtering as the adhesion layer 2, then form a copper layer by sputtering as the first seed layer 3, and then After that, a metal layer is additionally formed by electroless plating. Once the titanium and copper layers are formed only by sputtering, the metal coating may not be uniformly formed on the inner walls of the through-holes. Therefore, it is desirable to reinforce the metal layer by electroless plating. Examples of the electroless plating layer include electroless copper plating and electroless nickel plating, and electroless nickel plating is preferable because of good adhesion to glass, titanium, and copper layers. If the nickel plating layer is too thick, it may be difficult to form fine wiring. In addition, due to an increase in film stress, the adhesiveness may be lowered. Therefore, the thickness of the electroless plating is preferably less than 1 μm. Also, the thickness is preferably not more than 0.5 μm, more preferably not more than 0.3 μm. In addition, the electroless nickel plating film may contain phosphorus derived from the eutectoid of the reducing agent, or sulfur, lead, or bismuth contained in the electroless nickel plating solution. Through the above steps, the substrate with the seed metal layer formed on the glass substrate with the through holes can be obtained.

(step 3) Next, as shown in FIG. 2 , a pattern formed by the resist 11 is formed on the first seed layer. In the method of forming the pattern formed by the resist 11, first, the layer of the resist 11 is formed on the entire surface of the first seed layer. The resist used can include negative dry film resist, negative liquid resist, and positive liquid resist. Since the formation of the resist layer is simple and inexpensive, negative photoresist is preferred.

(step 4) Next, a pattern for forming a desired conductor circuit layer on the photoresist layer is formed by a known photolithography method. That is, the pattern of the resist 11 is patterned by performing alignment, exposure, and development so that a portion for subsequent conductor circuit layer formation is exposed. The thickness of the resist layer also depends on the thickness of the conductive circuit layer, preferably more than 5 μm, preferably less than 25 μm. If it is less than 5 μm, the film thickness of the electroplating layer that becomes the conductive circuit layer cannot be increased to more than 5 μm, and the connection reliability of the circuit may be lowered. If it exceeds 25 μm, it becomes difficult to form fine wiring with a pitch of 30 μm or less. In this way, a substrate on which a photoresist pattern is formed is obtained.

(step 5) Then, by supplying power to the first seed layer, soaking in the plating solution, and forming the first conductive layer that will later become the conductor circuit layer on the top of the first seed layer without a photoresist pattern, that is, electrolytic plating layer.

(step 6) Next, the unnecessary photoresist pattern is removed to expose the first conductive layer and the first seed layer 3 as shown in FIG. 4 . In addition, the removal method of the resist 11 is not limited to any specific method, but it can be stripped and removed by an aqueous alkali solution, for example.

(step 7) Next, as shown in FIG. 7 , the lower adhesive layer 5 , the first insulating layer 6 , the upper adhesive layer 7 , and the second seed layer 8 are sequentially deposited to cover the entire surface of the first conductive layer 4 , that is, the lower electrode. Examples of the film-forming method of the above layer include vacuum evaporation method, sputtering method, ion plating method, MBE method, laser lift-off method, CVD method, etc., but are not limited to this embodiment. The lower adhesive layer 5 located under the first insulating layer 6 has a function of improving the adhesiveness between the first insulating layer 6 and the first conductive layer 4 . However, when the adhesiveness between the first insulating layer 6 and the first conductive layer 4 is sufficient, there is no problem without the lower adhesive layer 5 . In this embodiment, after forming the first conductive layer, the first insulating layer, the second seed layer, and the like are formed without etching the first seed layer. Therefore, when forming the second seed layer, it is possible to suppress the abnormality of the throwing property of the second seed layer. As a result, the second conductive layer can also be stably formed. In addition, the second seed layer functions as a power supply layer, and is used to form the upper electrode of the capacitor by the semi-additive method.

(step 8) Next, as shown in FIG. 8 , on the second seed layer 8 , a pattern of a resist 11 is formed in a region other than where the second conductive layer 9 is formed. The formation of the pattern of the resist 11 can be performed by the same method as the aforementioned photoresist pattern. In this case, the opening area of the pattern of the resist 11 is formed so as to be further inside the first conductive layer 4 (lower electrode), and when viewed from a plane in the lamination direction, the connection line connected to the outside of the MIM capacitor is excluded. Other parts are also formed so as to be inside the first conductive layer 4 (lower electrode).

(step 9) Next, power is supplied to the second seed layer, and the second conductive layer 9 (upper electrode) is formed by electrolytic plating.

(step 10) Next, the pattern of the resist 11 is removed. The removal of the photoresist pattern can be carried out by a known method of alkali aqueous solution for removal and stripping.

(step 11) Next, as shown in FIG. 9 , a resist 11 is patterned so as to surround the second conductive layer 9 (upper electrode). The formation of the pattern of the resist 11 can be performed by the same method as the aforementioned photoresist pattern. In this case, the non-aperture region of the photoresist pattern is formed so that it is outside the upper electrode and inside the first conductor layer (lower electrode), except for the outside of the MIM capacitor when viewed from a plane in the stacking direction. The portion other than the connecting wire is also formed so as to be inside the first conductive layer 4 (lower electrode). In this way, the end faces of the second seed layer 8, the upper adhesive layer 7, the first insulating layer 6, and the lower adhesive layer 5 are etched so that they are respectively outside the second conductive layer and inside the first conductive layer. MIM capacitor construction.

(step 12) In addition, the removal of unnecessary parts of the second seed layer 8 and the upper adhesive layer 7 is not limited to this step, for example, the upper electrode can also be used as a mask before step 11, and the second seed layer 8 and the upper adhesive layer The unnecessary part of 7 is removed. In this way, the area of the first insulating layer 6 on the outer surface of the MIM capacitor element is increased, and current leakage from the side surface between the upper electrode and the lower electrode can be suppressed.

(step 13) Next, the pattern of the resist 11 is removed. The removal of the photoresist pattern can be carried out by a known method of alkali aqueous solution for removal and stripping.

(step 14) Next, as shown in FIG. 10 , a pattern of resist 11 is formed so as to surround the first conductive layer 4 again. That is, the pattern of the resist 11 is formed in such a way that it becomes an etching mask having a width larger than that of the first conductive layer in at least one width direction (direction on the xy plane perpendicular to the z axis). 11 patterns. That is, the width of the etching mask larger than that of the first conductive layer is equivalent to the width of the first seed layer 3 in the MIM capacitor. In this case, the non-aperture region of the photoresist pattern is formed so as to be outside the lower electrode, and when viewed from a plane in the stacking direction, except for the part of the connection line connected to the outside of the MIM capacitor, it also becomes The outer side of the first conductive layer 4 (lower electrode) is formed.

More specifically, the relationship between the width b of the resist 11 on the xy plane (horizontal direction) in at least one direction and the width a of the first conductive layer (lower electrode) on the xy plane in the same direction, of course satisfies The following formula (1). [Formula 1] a<b ･･･(1) Furthermore, it is preferable that a and b satisfy the following formula (2). [Formula 2] 50nm≦(b-a)/2≦50μm ･･･(2) In addition, in the formula (2), "(b-a)/2" represents the difference in the width of the first conductive layer (lower electrode) 4 and the resist 11 on one side. The upper limit of the difference in width on one side is set at 50 μm because, if it is larger than this value, there will be restrictions on the design of the pattern. In addition, it is preferable that the height (total thickness of the two layers) c of the adhesive layer 2 and the first seed layer 3 in the z-axis direction satisfies the following formula (3). [Formula 3] 50nm≦c≦5μm ･･･(3) In addition, the lower limit of c in Equation (3) is set to 50 nm because the minimum value for the adhesion layer 2 and the first seed layer 3 to function as a power supply layer must be 50 nm. Also, the upper limit of c is set to 5 μm because the wiring width that can be formed is limited when the seed layer is etched. Furthermore, a, b, and c preferably satisfy the following formula (4). [Formula 4] 0.01≦((b-a)/2)/c≦1000 ･･･(4) As long as the shape satisfies the formula (4), side etching will not occur up to the bottom of the first conductive layer (lower electrode), and in the subsequent steps, it can be formed in a sufficiently stable state without disconnection defects. 2nd seed layer. In addition, the formation method of the resist pattern can be performed by the same method as the aforementioned photoresist pattern.

(step 15) Next, the exposed portion of the first seed layer is removed. In addition, the electroless Ni layer, copper layer, and titanium layer can be sequentially removed by chemical etching. The type of etching solution is appropriately selected according to the metal species to be removed, and the removal method is not limited to the method described in this disclosure.

(step 16) Next, when the pattern of the resist 11 is removed, as shown in FIG. 11 , a wiring board on which MIM capacitors are formed can be formed. The removal of the photoresist pattern can be carried out by a known method of alkali aqueous solution for removal and stripping. A capacitor is formed through the above steps.

(step 17) After that, as shown in FIG. 12 , an insulating resin layer 12 and via holes 13 are formed on the wiring board. After that, by repeatedly forming a laminated conductor circuit layer and an insulating resin layer, a multilayer wiring board is formed. In addition, the conductive circuit or the laminated structure on the wiring board can be formed using a known semi-additive method or subtractive method. Furthermore, after forming the multilayer wiring board, external connection terminals may be formed, and solder balls may be formed on the external connection terminals. The wiring board according to the present disclosure may have a laminated conductor circuit layer, external connection terminals, and solder balls on one side, or may be formed on both sides as a modified example. Furthermore, semiconductor chips and chip components can also be mounted.

[Second Embodiment] Next, hereinafter, a second embodiment will be described with reference to FIGS. 2 to 4 and FIGS. 13 to 17 . In the second embodiment, Step 1 to Step 6 are the same as those in the first embodiment, and therefore descriptions of Step 1 to Step 6 are omitted. In the second embodiment, after step 6 in the first embodiment shown in FIG. 4, step 20 to be described below continues.

(step 20) After step 6 of the first embodiment, as shown in FIG. 13 , a resist 11 is patterned so as to surround the first conductive layer. The formation of the photoresist pattern can be performed by the same method as the aforementioned resist pattern. In this case, the non-opening region of the resist pattern is formed so as to be outside the lower electrode, and when viewed from the plane in the stacking direction, except for the part of the connecting line connected to the outside of the MIM capacitor, it also becomes The outer side of the first conductive layer 4 (lower electrode) is formed.

Furthermore, at this time, the length b of the resist 11 on the xy plane, the length a of the first conductive layer (lower electrode) in the same direction on the xy plane, and the length a of the contact layer 2 and the first seed layer 3 on the z axis The ideal relationship of the height (total thickness of two layers) c in the direction is the same as that described in step 14 in the first embodiment.

(step 21) Next, using the pattern of the resist 11 as an etching mask, the first seed layer 3 and the adhesion layer 2 are removed. In addition, the removal of the first seed layer 3 and the adhesion layer 2 can be performed by chemical etching to sequentially remove the electroless Ni layer, copper layer, and titanium layer. The type of etching solution is appropriately selected according to the metal species to be removed, and there is no limitation.

(step 22) Then, once the pattern of the resist 11 is removed, the cross section shown in FIG. 14 can be obtained. In addition, the removal of the resist 11 can be performed by a known method of alkali aqueous solution for removal and stripping.

(step 23) Next, as shown in FIG. 15 , similarly to step 7 of the first embodiment, the lower adhesive layer 5 and the first insulating layer 6 are sequentially stacked to cover the entire surface of the first conductive layer 4 , that is, the lower electrode. , The upper adhesion layer 7 and the second seed layer 8 . Examples of the film-forming method of the above-mentioned layer include vacuum evaporation method, sputtering method, ion plating method, MBE method, laser lift-off method, CVD method, etc., but are not limited to this embodiment. The lower adhesive layer 5 located under the first insulating layer 6 has a function of improving the adhesiveness between the first insulating layer 6 and the first conductive layer 4 . However, when the adhesiveness between the first insulating layer 6 and the first conductive layer 4 is sufficient, there is no problem without the lower adhesive layer 5 . In addition, the second seed layer functions as a power supply layer, and is used to form the upper electrode of the capacitor by the semi-additive method.

(step 24) Next, as shown in FIG. 16 , a resist 11 is patterned in a region other than where the second conductive layer 9 is formed. The formation of the pattern of the resist 11 can be performed by the same method as the aforementioned photoresist pattern. In this case, the opening area of the pattern of the resist 11 is formed so as to be inside of the first conductive layer 4 (lower electrode), and when viewed from a plane in the lamination direction, the connection lines connected to the outside of the MIM capacitor are excluded. In addition to the part, it is also formed so as to be inside the first conductive layer 4 (lower electrode).

(step 25) Next, power is supplied to the second seed layer, and the second conductive layer 9 (upper electrode) is formed by electrolytic plating.

(step 26) Next, the pattern of the resist 11 is removed. The removal of the photoresist pattern can be carried out by a known method of alkali aqueous solution for removal and stripping.

(step 27) Next, as shown in FIG. 17 , a resist 11 is patterned so as to surround the second conductive layer 9 (upper electrode). The formation of the pattern of the resist 11 can be performed by the same method as the aforementioned photoresist pattern. In this case, the non-aperture region of the photoresist pattern is formed so that it is outside the upper electrode and inside the first conductor layer (lower electrode), except for the outside of the MIM capacitor when viewed from a plane in the stacking direction. The portion other than the connecting wire is also formed so as to be inside the first conductive layer 4 (lower electrode). Preferably, they are formed so as to be respectively the outer side and the inner side.

(step 28) Next, similarly to step 12, using the resist 11 pattern as a mask, unnecessary portions of the second seed layer 8, the upper adhesive layer 7, the first insulating layer 6, and the lower adhesive layer 5 are removed. For the removal of the second seed layer 8 , the upper adhesive layer 7 , the first insulating layer, and the lower adhesive layer 5 , any known method such as a chemical etching method or a dry etching method can be used. Different removal methods may be used for each layer, and the removal may be performed by the same method for all layers. As mentioned above, the pattern of resist 11 is formed inside the first conductive layer 4 (lower electrode), so even if the pattern of resist 11 is used as a mask to remove unnecessary parts, the first insulating layer is still formed and only the first conductive layer remains. layer (lower electrode).

In addition, even if the unnecessary portion of the second seed layer and the upper adhesive layer 7 is not removed in step 28, it may be removed by etching immediately after step 27, for example, using the second conductive layer 9 (upper electrode) as a mask. This increases the area of the first insulating layer on the outer surface of the MIM capacitor element, and suppresses leakage of current from the side surface between the upper electrode and the lower electrode.

(step 29) Next, the pattern of the resist 11 is removed. As in the first embodiment, as shown in FIG. 11, a wiring board on which MIM capacitors are formed can be formed. Removal of the resist pattern can be performed by a known method of alkaline aqueous solution and stripping treatment. A capacitor is formed through the above steps.

The steps after step 29 in the second embodiment are the same as those in the first embodiment, and therefore description thereof will be omitted.

＜Effect＞ When MIM capacitors are manufactured by conventional manufacturing methods, the rate of side etching occurring below the first conductive layer 4 (lower electrode) and the failure to normally form the second conductive layer 9 (upper electrode) is 50%. As long as the manufacturing methods of the first embodiment and the second embodiment of the present disclosure are used, the second conductive layer 9 (upper electrode) can be normally formed at a ratio of 100%. Significant improvement can be seen.

As mentioned above, although the embodiment of this invention was described, this invention is not limited to the said embodiment, Various changes are possible in the range which does not deviate from the summary of this invention.

1: Substrate 2: Adhesive layer 3: The first seed layer 4: The first conductive layer 5: Lower bonding layer 6: The first insulating layer 7: Upper adhesive layer 8: The second seed layer 9: The second conductive layer 11: Resist 12: insulating resin layer 13: Through hole

Fig. 1 is a sectional view showing the basic structure which is the object of the present invention. Fig. 2 is a cross-sectional view illustrating a step of forming a first conductive layer. Fig. 3 is a cross-sectional view illustrating a step of forming a first conductive layer. Fig. 4 is a cross-sectional view illustrating the steps of forming the first conductive layer. Fig. 5 is a cross-sectional view illustrating a step of forming a first conductive layer. Fig. 6 is a cross-sectional view illustrating side etching in a conventional example. Fig. 7 is a cross-sectional view illustrating the steps of forming the second conductive layer in the embodiment. Fig. 8 is a cross-sectional view illustrating the steps of forming the second conductive layer in the embodiment. Fig. 9 is a cross-sectional view illustrating the steps of forming the MIM structure. Fig. 10 is a cross-sectional view illustrating an etching step of the first seed layer. FIG. 11 is a cross-sectional view illustrating a wiring board on which MIM capacitors are formed. Fig. 12 is a cross-sectional view of forming a wiring board on a multilayer wiring board. Fig. 13 is a cross-sectional view illustrating the forming steps of the second embodiment. Fig. 14 is a cross-sectional view illustrating the formation steps of the second embodiment. Fig. 15 is a cross-sectional view illustrating the formation steps of the second embodiment. Fig. 16 is a cross-sectional view illustrating the formation steps of the second embodiment. Fig. 17 is a cross-sectional view illustrating the formation steps of the second embodiment.

1: Substrate

2: Adhesive layer

3: The first seed layer

4: The first conductive layer

5: Lower bonding layer

6: The first insulating layer

7: Upper adhesive layer

8: The second seed layer

9: The second conductive layer

11: Resist

a: width

b: width

c:height

x: axis (direction) (axis direction)

z: axis (direction) (axis direction)

Claims (7)

A method of manufacturing a wiring substrate, the aforementioned wiring substrate comprising: a substrate having an insulating surface; and the following layers (1) to (5): (1) The first seed layer arranged on the aforementioned substrate; (2) The first conductive layer arranged above the aforementioned first seed layer; (3) The first insulating layer arranged above the aforementioned first conductive layer; (4) the second seed layer arranged above the first insulating layer; and (5) the second conductive layer arranged above the aforementioned second seed layer, The manufacturing method of the aforementioned wiring board includes: a step of forming the aforementioned first seed layer on the aforementioned substrate having an insulating surface; a step of forming the first conductive layer above the first seed layer; a step of forming the first insulating layer above the first conductive layer; a step of forming the second seed layer on the first insulating layer; A step of forming a pattern of the aforementioned second conductive layer on the aforementioned second seed layer; A step of forming an etching mask formed by a resist pattern on the pattern of the second conductive layer, and etching the second seed layer and the first insulating layer; and A step of etching the aforementioned first seed layer. A method of manufacturing a wiring substrate, the aforementioned wiring substrate comprising: a substrate having an insulating surface; and the following layers (1) to (5): (1) The first seed layer arranged on the aforementioned substrate; (2) The first conductive layer arranged above the aforementioned first seed layer; (3) The first insulating layer arranged above the aforementioned first conductive layer; (4) the second seed layer arranged above the first insulating layer; and (5) the second conductive layer arranged above the aforementioned second seed layer, The manufacturing method of the aforementioned wiring board includes: a step of forming the aforementioned first seed layer on the aforementioned substrate having an insulating surface; a step of forming the first conductive layer above the first seed layer; The step of etching the aforementioned first seed layer; a step of forming the first insulating layer above the first conductive layer; a step of forming the second seed layer on the first insulating layer; a step of forming a pattern of the aforementioned second conductive layer over the aforementioned second seed layer; and A step of forming an etching mask formed of a resist pattern on the pattern of the second conductive layer, and etching the second seed layer and the first insulating layer. The method of manufacturing a wiring board according to claim 1 or 2, wherein the layers (1) to (5) above constitute a MIM capacitor, The step of etching the aforementioned first seed layer is to use an etching mask whose width in at least one direction is larger than that of the aforementioned first conductive layer in the aforementioned MIM capacitor and equivalent to the width of the first seed layer in the aforementioned MIM capacitor , for etching. The method of manufacturing a wiring board according to Claim 3, wherein the width of the first seed layer in the horizontal direction in the MIM capacitor whose width is larger than that of the first conductive layer in the MIM capacitor is b, and the first seed layer is b. 1 When the width of the conductive layer in the horizontal direction is set to a, a and b satisfy the following formula (2): [Formula 2] 50nm≦(b-a)/2≦50μm ･･･(2). The method of manufacturing a wiring board according to claim 4, wherein the thickness of the first seed layer (the total thickness of the first seed layer and the lower adhesive layer when the lower adhesive layer is provided under the first seed layer) When c is assumed, a, b, and c satisfy the following formula (4): [Formula 4] 0.01≦((b-a)/2)/c≦1000 ･･･(4). A wiring board comprising: A substrate with an insulating surface; and the following layers (1) to (5): (1) The first seed layer arranged on the aforementioned substrate; (2) The first conductive layer arranged above the aforementioned first seed layer; (3) The first insulating layer arranged above the aforementioned first conductive layer; (4) the second seed layer arranged above the first insulating layer; and (5) the second conductive layer arranged above the aforementioned second seed layer, The layers of the aforementioned (1) to (5) constitute a MIM capacitor, In the MIM capacitor whose width is larger than that of the first conductive layer in the MIM capacitor, the width of the first seed layer in the horizontal direction is b, and the width of the first conductive layer in the horizontal direction is a In the case of , a and b satisfy the following formula (2): [Formula 2] 50nm≦(b-a)/2≦50μm ･･･(2). The wiring board according to claim 6, wherein the thickness of the first seed layer (the total thickness of the first seed layer and the lower adhesive layer when the lower adhesive layer is provided under the first seed layer) is set to In the case of c, a, b, and c satisfy the following formula (4): [Formula 4] 0.01≦((b-a)/2)/c≦1000 ･･･(4).