TW202329245A - Method for preparing a conductive stack with a gate contact - Google Patents

Abstract

The present disclosure provides a method for fabricating a conductive layer stack including forming an intervening layer on an under-layer; and forming a filler layer on the intervening layer, wherein the filler layer comprises tungsten. The intervening layer comprises tungsten silicide and a thickness of the intervening layer is greater than 4.1 nm. The under-layer comprises titanium nitride and comprises a columnar grain structure.

Description

Method for fabricating conductive layer stack with gate contact

This application claims priority to US Patent Application Nos. 17/573,781 and 17/573,832 (ie, the priority date is "January 12, 2022"), the contents of which are incorporated herein by reference in their entirety.

The disclosure relates to a method for preparing a conductive layer stack. In particular, it relates to a method of manufacturing a conductive layer stack with gate contacts.

Semiconductor components are used in various electronic applications, such as personal computers, mobile phones, digital cameras, or other electronic devices. The size of semiconductor devices is gradually reduced to meet the increasing demand for computing power. However, during the process of shrinking dimensions, different problems are added, and such problems continue to increase in number and complexity. Therefore, challenges remain in achieving improved quality, yield, performance and reliability, and reduced complexity.

The above "prior art" description only provides background technology, and does not acknowledge that the above "prior art" description discloses the subject of this disclosure, and does not constitute the prior art of this disclosure, and any description of the above "prior art" is It should not be part of this case.

An embodiment of the present disclosure provides a conductive layer stack, including an interposer including tungsten silicide and disposed on a lower layer; a filling layer including tungsten and disposed on the interposer. The lower layer includes titanium nitride and includes a columnar grain structure. A thickness of the interposer is greater than about 4.1 nm.

Another embodiment of the present disclosure provides a semiconductor device, including a substrate; a gate structure disposed on the substrate; a gate contact, including: a gate contact barrier layer disposed on the gate structure It also includes titanium nitride with a columnar grain structure; a gate contact intermediary layer disposed on the gate contact barrier layer and including tungsten silicide; a gate contact filling layer disposed on the gate contact barrier layer on and includes tungsten. A thickness of the gate contact interposer is greater than about 4.1 nm.

Another embodiment of the present disclosure provides a method for fabricating a conductive layer stack, including forming an interposer on a lower layer; and forming a filling layer on the interposer, wherein the filling layer includes tungsten. The interposer includes tungsten silicide and a thickness of the interposer is greater than about 4.1 nm. The lower layer includes titanium nitride and includes a columnar grain structure.

Another embodiment of the present disclosure provides a method for fabricating a semiconductor device, including providing a substrate; forming a gate structure on the substrate; and forming a gate contact point on the gate structure, including: forming a gate A contact barrier layer is on the gate structure; a gate contact intermediate layer is formed on the gate contact barrier layer; and a gate contact filling layer is formed on the gate contact barrier layer. The gate contact barrier layer includes titanium nitride with a columnar grain structure. The gate contact interposer includes tungsten silicide and a thickness of the gate contact interposer is greater than about 4.1 nm. The gate contact filling layer includes α-tungsten.

Due to the design of the semiconductor device disclosed in the present disclosure, the interposer layer is formed with a thickness greater than 4.1 nm to reduce or avoid the problem of non-uniform resistance. Therefore, the reliability, yield and performance of the semiconductor device can be improved. In addition, the fill layer deposited using a germanium-containing reducing agent reduces electrical resistance, resulting in a thin fill nucleation layer of alpha-tungsten growth, resulting in a fill bulk layer with little or no defects.

The technical features and advantages of the present disclosure have been broadly summarized above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the disclosure defined by the appended claims.

Specific examples of components and configurations are described below to simplify embodiments of the present disclosure. Certainly, these embodiments are only for illustration, and are not intended to limit the scope of the present disclosure. For example, where a first component is formed on a second component, it may include embodiments where the first and second components are in direct contact, or may include an additional component formed between the first and second components, An embodiment such that the first and second parts do not come into direct contact. In addition, embodiments of the present disclosure may repeat reference numerals and/or letters in many instances. These repetitions are for the purpose of simplicity and clarity and, unless otherwise indicated in the context, do not in themselves imply a specific relationship between the various embodiments and/or configurations discussed.

Additionally, for ease of description, spaces such as "beneath", "below", "lower", "above", "upper" may be used herein Relative relationship terms are used to describe the relationship of one element or feature to another (other) element or feature shown in the figures. The spatially relative terms are intended to encompass different orientations of elements in use or operation in addition to the orientation depicted in the figures. The device may be at other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

It should be understood that when forming a component on, connected to, and/or coupled to another component, it may include implementations where these components are formed in direct contact. Examples, and may also include embodiments in which additional components are formed between these components such that the components do not come into direct contact.

It will be understood that although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not constrained by these terms. limits. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the presently advanced concepts.

Unless the context indicates otherwise, when referring to orientation, layout, location, shapes, sizes, amounts, or other measures, Then terms such as "same", "equal", "planar", or "coplanar" as used herein are not necessarily Means an exact identical orientation, arrangement, position, shape, size, quantity, or other measurement, but it is meant to include, within acceptable variance, nearly identical orientation, arrangement, position, shape, size , quantity, or other measure, and for example, the acceptable variance may occur due to manufacturing processes (manufacturing processes). The term "substantially" may be used herein to express this meaning. For example, as substantially the same, substantially equal, or substantially planar, as being exactly the same, equal, or planar, or Yes, they may be the same, equal, or flat within acceptable variances that may occur, for example, due to manufacturing processes.

In this disclosure, a semiconductor device generally refers to a device that can operate by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a Both a semiconductor circuit and an electronic device are included in the category of semiconductor devices.

It should be understood that in the description of the present disclosure, above (or above (up)) corresponds to the direction of the Z-direction arrow, and below (or below (down)) corresponds to the relative direction of the Z-direction arrow .

It should be understood that the terms "forming", "formed" and "form" may denote and include any creating, building, patterning, planting A method of implanting or depositing an element, a dopant, or a material. Examples of formation methods may include atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, spin coating, diffusion (diffusing), deposition (depositing), growth (growing), implantation (implantation), photolithography (photolithography), dry etching and wet etching, but not limited thereto.

It should be understood that, in the description of the present disclosure, functions or steps mentioned herein may occur out of the order shown in the accompanying drawings. For example, two figures shown in succession may, in fact, be executed substantially concurrently, or may sometimes be executed in the reverse order, depending upon the functions or steps involved.

FIG. 1 is a schematic flow diagram illustrating a method 10 for fabricating a conductive layer stack 100 according to an embodiment of the present disclosure. FIG. 2 and FIG. 3 are schematic cross-sectional views illustrating a process for preparing the conductive layer stack 100 according to an embodiment of the present disclosure.

Please refer to FIG. 1 and FIG. 2 , in step S11 , a substrate 201 may be provided, and the lower layer 110 may be formed on the substrate 201 .

Please refer to FIG. 2 , the substrate 201 may include a silicon-containing material. Examples of silicon-containing materials suitable for the substrate 201 include, but are not limited to, silicon, silicon germanium, carbon-doped silicon germanium, silicon-germanium carbide, carbon-doped silicon, silicon nitride and multilayers thereof. Although silicon is the primary semiconductor material used in wafer fabrication, in some embodiments alternative semiconductor materials may be used for additional layers such as germanium, gallium arsenide, gallium nitride, silicon germanium, cadmium telluride (cadmium telluride) telluride), zinc selenide (zinc selenide), germanium tin (germanium tin), etc., but not limited thereto.

Please refer to FIG. 2 , the lower layer 110 can be a barrier layer or an adhesive layer. Non-limiting examples of the lower layer 110 include a conductive layer or a dielectric layer such as silicon oxide, silicon nitride, silicon carbide, metal oxide, metal nitride, and metal carbide, and a metal layer. In some embodiments, the lower layer 110 can be titanium nitride, titanium metal, tungsten nitride, titanium aluminide or a titanium oxide. In this embodiment, the lower layer 110 may be a barrier layer and may include titanium nitride. The titanium nitride barrier layer may include a columnar grain structure.

Referring to FIG. 1 and FIG. 2 , in step S13 , an interposer layer 120 may be formed on the lower layer 110 .

Please refer to FIG. 2 , the interposer 120 may include amorphous tungsten silicide. The thickness T1 of the interposer 120 may be greater than about 4.1 nm. In some embodiments, the thickness T1 of the interposer 120 may be greater than about 4.3 nm, greater than about 4.6 nm, or greater than about 5.2 nm. In some embodiments, the thickness T1 of the interposer 120 may be between 4.3 nm and 4.6 nm.

It should be understood that the term "about" modifies a quantity of an ingredient, a component, or a reactant of the present disclosure, and represents a numerical variation that may occur, for example In general, it goes through typical measurements and liquid handling procedures used to make concentrates or solutions. Furthermore, variations may arise from inadvertent errors in measurement procedures applied to the manufacture of compositions or in the implementation of the methods or the like, differences in manufacture, source (source), or the purity of ingredients (purity). In one aspect, the term "about" means within 10% of the reported value. On the other hand, the term "about" means within 5% of the reported value. In yet another aspect, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

Please refer to FIG. 2 , in some embodiments, the interposer layer 120 may include an intermediary nucleation layer 121 and an intermediary bulk layer 123 . First, a mediation nucleation layer 121 may be formed on the lower layer 110 . Next, a mediation bulk layer 123 may be formed on the mediation nucleation layer 121 .

In some embodiments, the intermediate nucleation layer 121 and the intermediate bulk layer 123 may include tungsten silicide. Specifically, reactive gases (such as tungsten hexafluoride), inert carrier gases (such as argon, nitrogen, and helium), and the desired silicon source gas can be combined in a premixed chamber, and then The lower layer 110 flows over the intermediate semiconductor elements. Initially, the silicon source gas may be silane. The gas mixture may be used to form the intermediary nucleation layer 121 . After the intermediate nucleation layer 121 is formed, the silicon source gas can be switched and dichlorosilane can be used as the silicon source gas for depositing the intermediate bulk layer 123 . The switching of the silicon source gas can be performed suddenly or gradually.

In some embodiments, the flow rate of the inert carrier gas may be 5 to 10 times greater than the flow rate of the silicon source gas (either silane or dichlorosilane). In some embodiments, the flow rate of the silicon source gas (either silane or dichlorosilane) may be about 50 to 100 times the flow rate of the reactant gas. In some embodiments, the silane flow rate may be approximately 400 standard cubic centimeters per minute (sccm). The flow rate of the reactant gas may be about 4 sccm. The flow rate of the inert carrier gas may be about 2800 sccm.

In some embodiments, the process temperature for forming the intermediate nucleation layer 121 may be less than 500°C. In some embodiments, the process temperature for forming the intermediate nucleation layer 121 may be about 450°C. In some embodiments, the process temperature for forming the intermediate nucleation layer 121 may be about 400°C or less than 400°C. In some embodiments, the process temperature for forming the intermediate nucleation layer 121 may be about 250°C or about 400°C. In some embodiments, the intervening bulk layer 123 may be formed at the same process temperature as the intervening nucleation layer 121 .

In some embodiments, the process duration for forming the intermediate nucleation layer 121 may be between about 1 second and about 25 seconds.

In some embodiments, the substrate temperature for forming the intermediary nucleation layer 121 may be between about 200°C and about 500°C.

Due to the presence of the intervening nucleation layer 121, the intervening bulk layer 123 can be deposited using a process that does not require any assistance from plasma-enhanced techniques. Therefore, the equipment requirements for forming the interposer 120 can be simplified, and the cost of forming the interposer 120 can be reduced.

In some embodiments, the formation of the intermediary nucleation layer 121 is optional. The intervening bulk layer 123 may be directly formed on the lower layer 110 .

Referring to FIG. 1 and FIG. 3 , in step S15 , a filling layer 130 may be formed on the interposer layer 120 .

Referring to FIG. 3 , in some embodiments, the filling layer 130 may include a filling nucleation layer 131 and a filling bulk layer 133 . First, a filling nucleation layer 131 may be formed on the interposer bulk layer 123 of the interposer 120 . Next, a filling bulk layer 133 may be formed on the filling nucleation layer 131 . In some embodiments, a grain size of the filled bulk layer 133 may be greater than 30 nm, greater than 50 nm, greater than 70 nm, greater than 80 nm, greater than 85 nm, or greater than 87 nm. In some embodiments, the filler bulk layer 133 may include α-tungsten.

In some embodiments, the filling nucleation layer 131 and the filling bulk layer 133 may include tungsten. Tungsten may be particularly useful in gate electrodes of DRAM types and word and bit lines of integrated circuit components because of its heat loss during the subsequent high temperature process. Stability, where the process temperature can reach 900°C or higher. In addition, tungsten is a high-refractive material with good oxidation resistance and low resistivity.

In some embodiments, the filled nucleation layer 131 may have a thin conformal layer that serves to facilitate subsequent formation of bulk material thereon (ie, filled bulk layer 133 ). Compliance with the underlying interposer 120 may be critical to support high quality deposition. In some embodiments, the fabrication technique for filling the nucleation layer 131 may include a pulsed nucleation layer method.

In the pulsed nucleation layer approach, pulses of reactants may be sequentially injected into or purged from the reaction chamber, typically by a pulse of a purge gas between the reactants. A first reactant can be absorbed onto the substrate (eg, interposer 120 ) and can be used to react with the next reactant. This process is repeated in a loop until the desired thickness is achieved. It should be understood that the pulsed nucleation layer method is generally distinguished from ALD by its higher operating pressure range (greater than 1 Torr) and higher growth rate per cycle (greater than 1 monolayer growth per cycle) . During the pulsed nucleation layer process, the chamber pressure may range from about 1 Torr to about 400 Torr.

In some embodiments, for example, the reactant for forming the filling nucleation layer 131 may be a boron-containing reducing agent, a silicon-containing reducing agent, a germanium-containing reducing agent, and a tungsten-containing precursor. In some embodiments, the boron-containing reducing agent can be borane or diborane. In some embodiments, the silicon-containing reducing agent can be silane. In some embodiments, the tungsten-containing precursor may include tungsten hexafluoride, tungsten hexachloride or tungsten hexacarbonyl. In some embodiments, the tungsten-containing precursor may include fluorine-free organometallic compounds, such as methylcyclopentadienyl-dicarbonylnitrosyl-tungsten (methylcyclopentadienyl-dicarbonylnitrosyl-tungsten, MDNOW) and ethylcyclopentadienyl Diene-dicarbonylnitrosyl-tungsten (ethylcyclopentadienyl-dicarbonylnitrosyl-tungsten, EDNOW).

In some embodiments, the germanium-containing reducing agent can be a germane, such as Ge _n H _n+4 , Ge _n H _n+6 , Ge _n H _n+8 , Gen _{H m} , wherein n is from 1 an integer up to 10, and n is an integer different from m. For example, other germanium-containing compounds such as alkyl germanes, alkyl germaniums, aminogermanes, carbogermanes, and halogen germanes ( Halogermanes).

An exemplary process for forming the filling nucleation layer 131 is described below. First, the intermediate semiconductor device depicted in FIG. 2 may be exposed to multiple pulses of a germanium-containing reducing agent in a hydrogen environment to form a layer of germanium on the intervening bulk layer 123 . In some embodiments, the ratio of hydrogen-containing to germanium-containing reducing agent may be about 10:1, about 50:1, about 70:1, or about 100:1. The presence of hydrogen reduces the deposited thickness per cycle and reduces the resistance of the deposited fill layer 130 .

In some embodiments, multiple pulses of one or more additional reducing agents may be used, such as multiple pulses of boron-containing or silicon-containing reducing agents. The additional reducing agents can be pulsed sequentially or simultaneously with the germanium-containing reducing agent. In some embodiments, the time period between the pulses may be between about 0.5 seconds and about 5 seconds. In some embodiments, the pulses of germanium-containing reducing agents are optional, and only boron- or silicon-containing reducing agents may be used.

In some embodiments, the duration of the pulse may be between about 0.25 seconds to about 30 seconds, between about 0.25 seconds to about 5 seconds, or between about 0.5 seconds to about 3 seconds between. This pulse may be sufficient to saturate or supersaturate the surface of the intervening bulk layer 123 . In some embodiments, a carrier gas such as argon, helium or nitrogen may be used. In some embodiments, an optional purge process may be performed to remove excess germanium-containing reductant that is still in the gas phase but not adsorbed to the surface of the intervening bulk layer 123 . The purge process can be performed by flowing an inert gas at a fixed pressure, thereby depressurizing the chamber and repressurizing the chamber before initiating another gas exposure.

Next, the intermediate semiconductor element can be exposed to pulses of the tungsten-containing precursor. The tungsten-containing precursor reacts with the deposited layer of germanium to form elemental tungsten. In some embodiments, the duration of the pulse may be between about 0.25 seconds to about 30 seconds, between about 0.25 seconds to about 5 seconds, or between about 0.5 seconds to about 3 seconds. The pulse may be sufficient to react with multiple reaction sites on the surface of the intervening bulk layer 123 where germanium is adsorbed onto the surface. In some embodiments, the time period between the pulses may be between about 0.5 seconds and about 5 seconds. In some embodiments, a carrier gas such as argon, helium or nitrogen may be used. In some embodiments, exposure to the tungsten-containing precursor may be performed in a hydrogen environment. In some embodiments, an optional purge process may be performed to remove excess tungsten-containing reducing agent that is still in the gas phase but not adsorbed to the surface of the intervening bulk layer 123 . The purge process can be performed by flowing an inert gas at a fixed pressure, thereby depressurizing the chamber and repressurizing the chamber before initiating another gas exposure.

Finally, the exposure to the germanium-containing reducing agent and the tungsten-containing precursor may be repeated until a desired thickness of the fill nucleation layer 131 is deposited on the surface of the intervening bulk layer 123 . Each repetition of the pulses of exposure to the germanium-containing reducing agent and the tungsten-containing precursor can be considered a cycle. In some embodiments, the thickness T2 of the filled nucleation layer 131 may be less than 1 nm. In some embodiments, the thickness T2 of the filled nucleation layer 131 may be between about 1 nm and about 20 nm. In some embodiments, the thickness T2 of the filled nucleation layer 131 may be between about 1 nm and about 10 nm.

In some embodiments, the order of the pulses of exposure to the germanium-containing reducing agent and the tungsten-containing precursor may be reversed such that the tungsten-containing precursor is pulsed first.

Referring to FIG. 3, for example, the bulk layer 133 can be filled by physical vapor deposition, atomic layer deposition, molecular layer deposition, chemical vapor deposition, in-situ radical assisted deposition (in-situ radical assisted deposition), metal organic chemical vapor deposition, molecular beam epitaxy, sputtering, plating, evaporation, ion beam deposition, electron beam deposition, laser assisted deposition, chemical solution deposition, or combinations thereof And formed on the filling nucleation layer 131 .

For example, deposition of the filling bulk layer 133 using chemical vapor deposition can include flowing a tungsten-containing precursor and a co-reactant, such as a reducing agent, to the intermediate semiconductor element, and the intermediate semiconductor element The nucleation layer 131 is then filled. An example process pressure may be between about 10 Torr and about 500 Torr. An example substrate temperature can be between about 250°C and about 495°C. For example, the tungsten-containing precursor can be tungsten hexafluoride, tungsten chloride or tungsten hexacarbonyl. For example, the reducing agent can be hydrogen, silane, disilane, hydrazine, diborane or germane.

Alternatively, filling the nucleation layer 131 may be optional in some embodiments. The filling nucleation layer 133 can be directly formed on the intervening bulk layer 123 by physical vapor deposition.

It should be understood that interposer 120 formed of tungsten silicide may be consumed during the formation of filling bulk layer 133 by physical vapor deposition. If the thickness of the interposer 120 is less than 4.0 nm, the interposer 120 at the edge of the wafer may be completely consumed (or more consumed), while the interposer 120 at the center of the wafer may be partially consumed (or less consumed) . Therefore, the bottom of the layer 110 having the columnar grain structure at the wafer edge may contact the filling layer 130 during the formation of the filling layer 130 to affect the final grain structure of the filling layer 130 at the wafer edge. Therefore, the resistance of the fill layer 130 at the edge of the wafer may be worse than the resistance of the fill layer 130 at the center of the wafer. In other words, the uniformity of the filling layer may be worse.

In this embodiment, the interposer 120 is formed with a thickness greater than 4.0 nm to reduce or avoid the problem of resistance uniformity.

Referring to FIG. 3 , the lower layer 110 , the interposer layer 120 and the filling layer 130 are configured together to form a conductive layer stack 100 .

FIG. 4 is a schematic flowchart illustrating a method 20 for manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. FIG. 5 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. FIG. 6 is a schematic cross-sectional view illustrating an embodiment of the present disclosure along the section line A-A' of FIG. 5 . FIG. 7 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. Fig. 8 is a schematic cross-sectional view illustrating a cross-section taken along line A-A' of Fig. 7 .

Please refer to FIG. 4 to FIG. 8 , in step S21 , a substrate 201 may be provided, an insulating layer 203 may be formed in the substrate 201 to define an active region 205 , and a well region 301 may be formed in the active region 205 .

Please refer to FIG. 5 and FIG. 6 , the substrate 201 may include a silicon-containing material. Examples of silicon-containing materials suitable for the substrate 201 include, but are not limited to, silicon, silicon germanium, carbon-doped silicon germanium, silicon-germanium carbide, carbon-doped silicon, silicon nitride and multilayers thereof. Although silicon is the primary semiconductor material used in wafer fabrication, in some embodiments alternative semiconductor materials may be used for additional layers such as germanium, gallium arsenide, gallium nitride, silicon germanium, cadmium telluride (cadmium telluride) telluride), zinc selenide (zinc selenide), germanium tin (germanium tin), etc., but not limited thereto.

A series of deposition processes can be performed to deposit a pad oxide layer (not shown) and a pad nitride layer (not shown) on the substrate 201 . A lithography process may be performed to define the location of the insulating layer 203 by forming a mask layer (not shown) on the pad nitride layer. After the lithography process, an etching process, such as an anisotropic dry etching process, may be performed to form a trench (not shown) along the pad nitride and the pad oxide through and extending to the substrate 201. ). An isolation material can be deposited into the trench. A planarization process, such as chemical mechanical polishing, may be performed sequentially to remove excess material until the upper surface of the substrate 201 is exposed, so as to form the insulating layer 203 . The upper surface of the insulating layer 203 and the upper surface of the substrate 201 may be substantially coplanar. For example, the isolation material can be silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride or fluorine-doped silicate.

It should be understood that in the description of the present disclosure, silicon oxynitride refers to a substance including silicon, nitrogen and oxygen, and a proportion of oxygen is greater than a proportion of nitrogen. Oxynitride refers to a substance that includes silicon, oxygen and nitrogen, and a proportion of nitrogen is greater than a proportion of oxygen.

Referring to FIG. 5 and FIG. 6 , the parts of the substrate 201 surrounded by the insulating layer 203 can be regarded as the active region 205 .

Referring to FIG. 7 and FIG. 8 , the well region 301 may be formed in the active region 205 . In some embodiments, a p-type impurity implantation process may be performed to form a well region 301 in the active region 205 . The p-type impurity implantation process can add impurities to an intrinsic semiconductor, and the intrinsic semiconductor generates defects of valence electrons. In a silicon-containing substrate, examples of p-type dopants, ie impurities, include, but are not limited to, boron, aluminum, gallium or indium. In some embodiments, the well region 3201 may have a first electrical type (eg, p-type).

FIG. 9 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. Fig. 10 is a schematic cross-sectional view illustrating a cross-section taken along line A-A' of Fig. 9 . FIG. 11 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. Fig. 12 is a schematic cross-sectional view illustrating a cross-section taken along line A-A' in Fig. 11 . FIG. 13 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. Fig. 14 is a schematic cross-sectional view illustrating a cross-section taken along line A-A' in Fig. 13 . FIG. 15 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. Fig. 16 is a schematic cross-sectional view illustrating a cross-section taken along line A-A' in Fig. 15 .

Please refer to FIG. 4 , FIG. 9 and FIG. 10 , in step S23 , a gate structure 410 may be formed on the well region 301 .

Referring to FIG. 9 and FIG. 10 , the gate structure 410 may be formed on the well region 301 and on the insulating layer 203 . In a top view, the gate structure 410 may extend along the direction Y and intersect the active region 205 along the direction X. Referring to FIG.

Referring to FIG. 9 and FIG. 10 , the gate structure 410 may include a gate isolation layer 411 , a gate conductive layer 413 and a gate cover layer 415 . A gate isolation layer 411 may be formed on the well region 301 . In some embodiments, the thickness of the gate isolation layer 411 may be about 50 Å or less than 50 Å.

In some embodiments, for example, the gate isolation layer 411 may include silicon oxide. In some embodiments, for example, the gate isolation layer 411 may include a high dielectric constant dielectric material, such as metal oxide, metal nitride, metal silicate, transition metal oxide, transition metal nitride , a transition metal silicate, a metal oxynitride, a metal aluminate, a zirconium silicate, a zircoaluminate, or a combination thereof.

Examples of high dielectric constant dielectric materials may include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, hafnium lanthanum oxide, lanthanum oxide, zirconium oxide, titanium oxide, hafnium oxide Tantalum, yttrium oxide, strontium titania, barium titania, barium zirconia, lanthanum silicon oxide, aluminum silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or combinations thereof, but not as a limit.

In some embodiments, the gate isolation layer 411 can be a multi-layer structure, for example, it includes a layer of silicon oxide and another layer of high-k dielectric material.

Referring to FIG. 9 and FIG. 10 , the gate conductive layer 413 may be formed on the gate isolation layer 411 . In some embodiments, for example, the gate conductive layer 413 may include (doped) polysilicon germanium, (doped) polysilicon germanium, or other suitable conductive materials.

Referring to FIG. 9 and FIG. 10 , the gate capping layer 415 may be formed on the gate conductive layer 413 . For example, the gate cap layer 415 may include silicon oxide, silicon nitride, silicon oxynitride or silicon oxynitride.

Please refer to FIG. 4 , FIG. 13 and FIG. 14 , in step S25 , a plurality of lightly doped regions 303 may be formed in the well region 301 and adjacent to the gate structure 410 .

Referring to FIG. 13 and FIG. 14 , an n-type impurity implantation process can be performed using the gate structure 410 as a plurality of masks to form a plurality of lightly doped regions 303 in the well region 301 . The N-type impurity implantation process can add dopants that donate multiple free electrons to an intrinsic semiconductor. In a silicon-containing substrate, examples of n-type dopants, ie, impurities, include, but are not limited to, antimony, arsenic, or phosphorus. In some embodiments, the plurality of lightly doped regions 303 may have a second electrical type (eg, n-type) opposite to the first electrical type.

Referring to FIG. 4 , FIG. 13 and FIG. 14 , in step S27 , a gate spacer 417 may be formed on the sidewall 410SW of the gate structure 410 .

Referring to FIGS. 13 and 14 , a layer of spacer material (not shown) may be conformally formed to cover the intermediate semiconductor device described in FIGS. 11 and 12 . In some embodiments, for example, the spacer material can be silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or other suitable isolation materials. An etching process, such as an anisotropic dry etching process, may be performed to remove some portion of the spacer material and simultaneously form the gate spacer 417 on the sidewall 410SW of the gate structure 410 . The gate spacers 417 may also cover some portions of the lightly doped regions 303 .

Referring to FIG. 4 , FIG. 15 and FIG. 16 , in step S29 , a plurality of impurity regions 305 may be formed in the well region 301 and adjacent to the gate spacers 417 .

Referring to FIG. 15 and FIG. 16 , an n-type impurity implantation process can be performed using the gate structure 410 and the gate spacer 417 as a mask to form a plurality of impurity regions 305 in the well region 301 . The N-type impurity implantation process can be similar to the process described in FIG. 11 and FIG. 12 , and the description thereof will not be repeated here. The plurality of impurity regions 305 can be adjacent to the plurality of lightly doped regions 303 . In some embodiments, the plurality of impurity regions 305 may have a second electrical type (eg, n-type) opposite to the first electrical type. The doping concentration of the plurality of impurity regions 305 may be greater than that of the plurality of lightly doped regions 303 . In some embodiments, the doping concentration of the plurality of impurity regions 305 may be approximately 1E19 atoms/cm ³ to approximately 1E21/cm ³ .

FIG. 17 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. Fig. 18 is a schematic cross-sectional view illustrating a cross-section taken along line A-A' in Fig. 17 . FIG. 19 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. 20 and 21 are schematic cross-sectional views illustrating cross-sections taken along the lines A-A' and B-B' in FIG. 19 .

Referring to FIG. 4 , FIG. 17 and FIG. 18 , in step S31 , a dielectric layer 207 may be formed on the substrate 201 , and a plurality of first openings 701 may be formed to expose the plurality of impurity regions 305 .

Referring to FIG. 17 and FIG. 18 , a dielectric layer 207 may be formed to cover the gate structure 410 , the gate spacers 417 , the plurality of impurity regions 305 and the insulating layer 203 . A planarization process, such as chemical mechanical polishing, may be performed to provide a substantially flat surface for subsequent processing steps. For example, the dielectric layer 207 may include silicon dioxide, undoped silicate glass, fluorosilicate glass, borophosphosilicate glass, a spin-on low-k dielectric material, a chemical gas Phase deposition of low-k dielectric materials or combinations thereof. The term "low-k" as used throughout this disclosure means having a dielectric constant lower than that of silicon dioxide. In some embodiments, the dielectric layer 207 may include a self-planarizing material such as spin-on-glass, or a spin-on low-k dielectric material such as SiLK™. Using a self-planarizing material avoids the need for a subsequent planarization step. In some embodiments, the fabrication technique of the dielectric layer 207 may include a deposition process, such as chemical vapor deposition, plasma enhanced chemical vapor deposition, evaporation or spin coating. In some embodiments, a planarization process, such as chemical mechanical polishing, may be performed to provide a substantially flat surface for subsequent processing steps.

Referring to FIG. 17 and FIG. 18 , a plurality of first openings 701 may be formed along the dielectric layer 207 to respectively and correspondingly expose a plurality of impurity regions 305 . The fabrication technique of the plurality of first openings 701 may include an etching process using a pattern defining the locations of the plurality of first openings 701 , such as an anisotropic dry etching process.

Referring to FIG. 4 and FIGS. 19 to 21 , in step S33 , a gate contact opening 703 may be formed along the dielectric layer 207 to expose the gate structure 410 .

Referring to FIGS. 19 to 21 , the gate contact opening 703 may be formed along the dielectric layer 207 and the gate capping layer 415 to expose the gate conductive layer 413 . Fabrication techniques for the gate contact opening 703 may include an etching process, such as an anisotropic dry etching process, using a first mask 801 defining the location of the gate contact opening 703 . The first mask 801 may also cover the plurality of first openings 701 during the etching process of the gate contact openings 703 . After the etching process of the gate contact opening 703, the first mask 801 can be removed. In a top view, the gate contact opening 703 may be away from the active region 205 . That is, the gate contact opening 703 is not directly formed on the active region 205 .

It should be understood that some elements, such as the dielectric layer 207 and the first mask 801 , are not shown in the top view for clarity.

22 to 27 are schematic cross-sectional views, illustrating the cross-sections along the lines A-A' and B-B' in FIG. 19 of a part of the process for manufacturing the semiconductor device 1A according to an embodiment of the present disclosure.

Please refer to FIG. 4 and FIG. 22 to FIG. 27. In step S35, the lower layer 110 can be conformally formed on the substrate 201, an interposer 120 can be conformally formed on the lower layer 110, and a filling layer 130 can be formed on the intermediary. on layer 120.

Referring to FIG. 22 and FIG. 23 , the lower layer 110 may be conformally formed in the plurality of first openings 701 and the gate contact openings 703 . The fabrication technique of the lower layer 110 may include a procedure similar to that described in FIG. 2 , and its description will not be repeated herein.

Referring to FIG. 24 and FIG. 25 , the interposer 120 may be conformally formed on the lower layer 110 and in the plurality of first openings 701 and the gate contact openings 703 . The interposer layer 120 may include an interposer nucleation layer 121 and an interposer bulk layer 123 . The thickness T3 of the interposer 120 may be greater than about 4.1 nm. In some embodiments, the thickness T3 of the interposer 120 may be greater than about 4.3 nm, greater than about 4.6 nm, or greater than about 5.2 nm. In some embodiments, the thickness T3 of the interposer 120 may be between about 4.3 nm and about 4.6 nm. The fabrication techniques of the intermediate nucleation layer 121 and the intermediate bulk layer 123 may include a procedure similar to that described in FIG. 2 , and the description thereof will not be repeated herein.

Please refer to FIG. 26 and FIG. 27 , the filling layer 130 may include a filling nucleation layer 131 and a filling bulk layer 133 . The fill nucleation layer 131 may be conformally formed on the interposer 120 and in the plurality of first openings 701 and the gate contact openings 703 . The filling bulk layer 133 can be formed on the filling nucleation layer 131 and completely fill up the plurality of first openings 701 and the gate contact openings 703 . The fabrication technique of filling the nucleation layer 131 and filling the bulk layer 133 may include a procedure similar to that described in FIG. 3 , and the description thereof will not be repeated herein.

FIG. 28 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. 29 and 30 are schematic cross-sectional views illustrating cross-sections taken along the lines A-A' and B-B' in FIG. 28 .

Please refer to FIG. 4 and FIG. 28 to FIG. 30, in step S37, a planarization process may be performed to form a plurality of first contact points 600 in a plurality of first openings 701 and form a gate contact point 500 in the gate contact Point in opening 703 .

Referring to FIGS. 28 to 30 , a planarization process, such as chemical mechanical polishing, may be performed until the upper surface of the dielectric layer 207 is exposed. After the planarization process, the lower layer 110 can be converted into a plurality of first contact (FC) barrier layers 610 in the plurality of first openings 701 and into a gate contact (GC) barrier layer 510 in the gate contacts in the opening 703 .

The intermediary nucleation layer 121 can be transformed into an FC intermediary nucleation layer 621 in the plurality of first openings 701 and a GC intermediary nucleation layer 521 in the gate contact opening 703 . The interposer bulk layer 123 can be transformed into a plurality of FC interposer bulk layers 623 in the plurality of first openings 701 and a GC interposer bulk layer 523 in the gate contact opening 703 . The FC interposer nucleation layer 621 and the FC interposer bulk layer 623 are configured together to form an FC interposer 620 . The GC intermediary nucleation layer 521 and the GC intermediary bulk layer 523 are configured together to form a GC intermediary layer 520 .

The thickness T4 of the FC interposer 620 and the thickness T5 of the GC interposer 520 may be greater than about 4.1 nm. In some embodiments, the thickness T4 of the FC interposer 620 and the thickness T5 of the GC interposer 520 may be greater than about 4.3 nm, greater than about 4.6 nm, or greater than about 5.2 nm. In some embodiments, the thickness T4 of the FC interposer 620 and the thickness T5 of the GC interposer 520 may be between about 4.3 nm and about 4.6 nm.

The filling nucleation layer 131 can be converted into an FC filling nucleation layer 631 in the plurality of first openings 701 and into a GC filling nucleation layer 531 in the gate contact opening 703 . The filling bulk layer 133 can be converted into an FC filling bulk layer 633 in the plurality of first openings 701 and into a GC filling bulk layer 533 in the gate contact opening 703 . The FC-filled nucleation layer 631 is configured together with the FC-filled bulk layer 633 to form an FC-filled layer 630 . The GC-filled nucleation layer 531 and the GC-filled bulk layer 533 are configured together to form a GC-filled layer 530 .

Please refer to FIG. 28 to FIG. 30 , the FC barrier layer 610 , the FC interposer 620 and the FC filling layer 630 are configured together to form a first contact point 600 . The GC barrier layer 510 , the GC interposer 520 and the GC filling layer 530 are configured together to form a gate contact 500 .

FIG. 31 is a schematic top view illustrating an intermediate semiconductor device according to another embodiment of the present disclosure. Fig. 32 is a schematic cross-sectional view illustrating a cross-section taken along line A-A' in Fig. 31 . FIG. 33 is a schematic top view illustrating a semiconductor device 1B according to another embodiment of the present disclosure. Fig. 34 is a schematic cross-sectional view illustrating a cross-section taken along line A-A' in Fig. 33 .

Referring to FIG. 31 and FIG. 32 , an intermediate semiconductor device can be manufactured in a process similar to that described in FIG. 5 to FIG. 18 , and the description thereof will not be repeated herein. A gate contact 703 may be formed along the dielectric layer 207 and the gate capping layer 415 to expose the gate conductive layer 413 . The gate contact opening 703 can be formed directly on the active region 205 .

Referring to FIG. 33 and FIG. 34 , the gate contact 500 and the first contact 600 can be formed in a process similar to that described in FIGS. 22 to 30 , and the description thereof will not be repeated herein.

An embodiment of the present disclosure provides a conductive layer stack, including an interposer including tungsten silicide and disposed on a lower layer; a filling layer including tungsten and disposed on the interposer. The lower layer includes titanium nitride and includes a columnar grain structure. A thickness of the interposer is greater than about 4.1 nm.

Another embodiment of the present disclosure provides a semiconductor device, including a substrate; a gate structure disposed on the substrate; a gate contact, including: a gate contact barrier layer disposed on the gate structure It also includes titanium nitride with a columnar grain structure; a gate contact intermediary layer disposed on the gate contact barrier layer and including tungsten silicide; a gate contact filling layer disposed on the gate contact barrier layer on and includes tungsten. A thickness of the gate contact interposer is greater than about 4.1 nm.

Another embodiment of the present disclosure provides a method for fabricating a conductive layer stack, including forming an interposer on a lower layer; and forming a filling layer on the interposer, wherein the filling layer includes tungsten. The interposer includes tungsten silicide and a thickness of the interposer is greater than about 4.1 nm. The lower layer includes titanium nitride and includes a columnar grain structure.

Another embodiment of the present disclosure provides a method for fabricating a semiconductor device, including providing a substrate; forming a gate structure on the substrate; and forming a gate contact point on the gate structure, including: forming a gate A contact barrier layer is on the gate structure; a gate contact intermediate layer is formed on the gate contact barrier layer; and a gate contact filling layer is formed on the gate contact barrier layer. The gate contact barrier layer includes titanium nitride with a columnar grain structure. The gate contact interposer includes tungsten silicide and a thickness of the gate contact interposer is greater than about 4.1 nm. The gate contact filling layer includes α-tungsten.

Due to the design of the semiconductor device disclosed in the present disclosure, the interposer 120 is formed with a thickness greater than 4.1 nm to reduce or avoid the problem of non-uniform resistance. Therefore, the reliability, yield and performance of the semiconductor device can be improved. In addition, the fill layer 130 deposited using a germanium-containing reducing agent reduces electrical resistance, resulting in a thin fill nucleation layer 131 of alpha-tungsten growth, resulting in a fill bulk layer 133 with few or no defects.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, A composition of matter, means, method, or step. Accordingly, such process, machinery, manufacture, material composition, means, method, or steps are included in the patent scope of this application.

1A: Semiconductor components 1B: Semiconductor components 10: Preparation method 100: conductive layer stack 110: lower layer 120: intermediary layer 121: Intermediary nucleation layer 123: Intermediary block layer 130: filling layer 131: fill nucleation layer 133:Fill block layer 20: Preparation method 201: Base 203: insulation layer 205: active zone 207: dielectric layer 301: well area 303: lightly doped region 305: impurity area 410:Gate structure 410SW: side wall 411: gate isolation layer 413: gate conductive layer 415: Gate cover layer 417:Gate spacer 500: gate contact point 510: Gate contact barrier layer 520:Gate Contact Interposer 521: gate contact intermediary nucleation layer 523:Gate Contact Interposer Block Layer 530: Gate contact point filling layer 531:Gate Contact Fill Nucleation Layer 533: Gate Contact Fill Block Layer 600: First point of contact 610: first contact point barrier layer 620: First touchpoint intermediary layer 621:First contact intermediary nucleation layer 623: First contact point intermediary block layer 630: First contact point filling layer 631: The first contact point fills the nucleation layer 633:First contact point filling block layer 701: first opening 703: Gate contact opening 801: First mask S11: step S13: step S15: step S21: step S23: step S25: step S27: step S29: step S31: step S33: step S35: step S37: step T1: Thickness T2: Thickness T3: Thickness T4: Thickness T5: Thickness X: direction Y: Direction Z: Direction

The disclosure content of the present application can be understood more fully when the drawings are considered together with the embodiments and the patent scope of the application. The same reference numerals in the drawings refer to the same components. FIG. 1 is a schematic flowchart illustrating a method for fabricating a conductive layer stack according to an embodiment of the present disclosure. FIG. 2 and FIG. 3 are schematic cross-sectional views illustrating a process for preparing a conductive layer stack according to an embodiment of the present disclosure. FIG. 4 is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present disclosure. FIG. 5 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. FIG. 6 is a schematic cross-sectional view illustrating an embodiment of the present disclosure along the section line A-A' of FIG. 5 . FIG. 7 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. Fig. 8 is a schematic cross-sectional view illustrating a cross-section taken along line A-A' of Fig. 7 . FIG. 9 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. Fig. 10 is a schematic cross-sectional view illustrating a cross-section taken along line A-A' of Fig. 9 . FIG. 11 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. Fig. 12 is a schematic cross-sectional view illustrating a cross-section taken along line A-A' in Fig. 11 . FIG. 13 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. Fig. 14 is a schematic cross-sectional view illustrating a cross-section taken along line A-A' in Fig. 13 . FIG. 15 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. Fig. 16 is a schematic cross-sectional view illustrating a cross-section taken along line A-A' in Fig. 15 . FIG. 17 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. Fig. 18 is a schematic cross-sectional view illustrating a cross-section taken along line A-A' in Fig. 17 . FIG. 19 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. 20 and 21 are schematic cross-sectional views illustrating cross-sections taken along the lines A-A' and B-B' in FIG. 19 . 22 to 27 are schematic cross-sectional views illustrating a partial process of manufacturing a semiconductor device according to an embodiment of the present disclosure along the lines A-A' and B-B' in FIG. 19 . FIG. 28 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. 29 and 30 are schematic cross-sectional views illustrating cross-sections taken along the lines A-A' and B-B' in FIG. 28 . FIG. 31 is a schematic top view illustrating an intermediate semiconductor device according to another embodiment of the present disclosure. Fig. 32 is a schematic cross-sectional view illustrating a cross-section taken along line A-A' in Fig. 31 . FIG. 33 is a schematic top view illustrating a semiconductor device according to another embodiment of the present disclosure. Fig. 34 is a schematic cross-sectional view illustrating a cross-section taken along line A-A' in Fig. 33 .

100: conductive layer stack

110: lower layer

120: intermediary layer

121: Intermediary nucleation layer

123: Intermediary block layer

130: filling layer

131: fill nucleation layer

133:Fill block layer

201: Base

T2: Thickness

Z: Direction

Claims (11)

A method for preparing a conductive layer stack, comprising: forming an interposer on the underlying layer, wherein the interposer includes tungsten silicide and a thickness of the interposer is greater than about 4.1 nm; forming a filling layer on the interposer, wherein the filling layer includes tungsten; Wherein the lower layer includes titanium nitride and includes a columnar grain structure. The method for fabricating a conductive layer stack as claimed in claim 1, wherein the lower layer is formed on a substrate. The preparation method of the conductive layer stack as claimed in item 2, wherein forming the interposer on the lower layer comprises: forming an intermediate nucleation layer on the lower layer; and An intermediate bulk layer is formed on the intermediate nucleation layer. The preparation method of the conductive layer stack as claimed in item 3, wherein forming the filling layer on the interposer layer comprises: forming a filled nucleation layer on the interposer; and A filled bulk layer is formed on the filled nucleation layer. The method for fabricating a conductive layer stack as claimed in claim 4, wherein the tungsten in the filling layer is α-tungsten. The preparation method of the conductive layer stack as claimed in item 5, wherein forming the intermediary nucleation layer on the lower layer comprises: flowing a reactive gas, a first silicon source gas, and an inert carrier gas over the lower layer; and The first silicon source gas is converted into a second silicon source gas to form the intermediate nucleation layer. The method for preparing a conductive layer stack as claimed in claim 6, wherein the first silicon source gas is silane, and the second silicon source gas is dichlorosilane. The method for preparing a conductive layer stack according to claim 7, wherein the reaction gas is tungsten hexafluoride. The method for preparing a conductive layer stack according to claim 8, wherein the inert carrier gas is argon, nitrogen, helium or a combination thereof. The method for fabricating a conductive layer stack as claimed in claim 9, wherein a flow rate of the inert carrier gas is 5 to 10 times greater than a flow rate of the first silicon source gas. A method for preparing a semiconductor element, comprising: provide a base; forming a gate structure on the substrate; and forming a gate contact on the gate structure comprising: forming a gate contact barrier layer on the gate structure; forming a gate contact interposer on the gate contact barrier layer; and forming a gate contact filling layer on the gate contact barrier layer; Wherein the gate contact barrier layer comprises titanium nitride having a columnar grain structure; wherein the gate contact interposer comprises tungsten silicide and a thickness of the gate contact interposer is greater than about 4.1 nm; Wherein the gate contact filling layer includes α-tungsten.