TW202327018A - Circuit protection chip packaged component and method of manufacturing the same - Google Patents

Abstract

A circuit protection chip packaged component and a method of manufacturing the same are provided. The circuit protection chip packaged component includes a circuit protection chip, an enclosing structure, and a wiring structure. The circuit protection chip includes at least one electrical contact. The enclosing structure surrounds the circuit protection chip and the electrical contact. The wiring structure is disposed on the enclosing structure and includes an inner wiring layer and an external conductive structure. The external conductive structure is electrically connected to the electrical contact through the inner wiring layer. An overlapping area between two orthographic projections of the inner wiring layer and the circuit protection chip is 0.5% to 15% of an area of the orthographic projection of the circuit protection chip.

Description

Circuit protection chip package and manufacturing method thereof

The present invention relates to a chip package component and its manufacturing method, and in particular to a circuit protection chip package and its manufacturing method.

In existing electronic products, electrostatic discharge protection components are usually used to prevent circuits in the electronic products from being damaged by electrostatic discharge (ESD). Existing electrostatic discharge protection components are chip packaged components. The electrostatic discharge protection components include chips, conductive circuit layers and lead frames. The chip passes through the conductive circuit layer arranged between the chip and the lead frame, so that multiple pads of the chip are electrically connected to different pins of the lead frame respectively.

However, parasitic capacitance will be generated between the conductive circuit layer or the lead frame and the components inside the chip, resulting in high equivalent capacitance of the ESD protection component.

The technical problem to be solved by the present invention is to provide a circuit protection chip package and a manufacturing method thereof, which can reduce the equivalent capacitance of the circuit protection chip package.

In order to solve the above technical problems, another technical solution adopted by the present invention is to provide a circuit protection chip package, which includes a circuit protection chip, a wrapping structure and a circuit structure. The circuit protection chip has at least one electrical connection point. The covering structure covers the circuit protection chip and the electrical connection point. The circuit structure is disposed on the cladding structure, and includes an inner circuit layer and an outer conductive structure. The outer conductive structure is electrically connected to at least one electrical connection point through the inner circuit layer. An overlapping area between the vertical projection of the inner circuit layer and the vertical projection of the circuit protection chip accounts for 0.5% to 15% of the vertical projection area of the circuit protection chip.

In order to solve the above-mentioned technical problems, another technical solution adopted by the present invention is to provide a method for manufacturing a circuit protection chip package, which includes the following steps: arranging a circuit protection chip on a temporary substrate, wherein the circuit protection The chip has at least one electrical connection point; a first cladding layer is formed to cover the side surface of the circuit protection chip and at least one electrical connection point, wherein at least one electrical connection point is partially exposed on the first cladding layer top surface; forming a circuit structure on the first cladding layer, wherein the circuit structure includes an inner circuit layer and an outer conductive structure, and the outer conductive structure is electrically connected to the electrical connection point through the inner circuit layer; and separating the circuit protection chip and Temporary substrate.

One of the beneficial effects of the present invention is that the circuit protection chip package and its manufacturing method provided by the present invention can occupy an overlapping area between the vertical projection of the inner circuit layer and the vertical projection of the circuit protection chip, occupying 0.5% to 15% of the vertical projected area of the protection chip" technical solution to reduce the equivalent capacitance of the circuit protection chip package.

In order to further understand the features and technical content of the present invention, please refer to the following detailed description and drawings related to the present invention. However, the provided drawings are only for reference and description, and are not intended to limit the present invention.

The following is an illustration of the implementation of the "circuit protection chip package and its manufacturing method" disclosed by the present invention through specific specific examples. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various modifications and changes can be made to the details in this specification based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only for simple illustration, and are not drawn according to the actual size, which is stated in advance. The following embodiments will further describe the relevant technical content of the present invention in detail, but the disclosed content is not intended to limit the protection scope of the present invention.

It should be understood that although terms such as "first", "second", and "third" may be used herein to describe various elements or signals, these elements or signals should not be limited by these terms. These terms are mainly used to distinguish one element from another element, or one signal from another signal. In addition, the term "or" used herein may include any one or a combination of more of the associated listed items depending on the actual situation.

[first embodiment]

Please refer to FIGS. 1 and 2 . FIG. 1 is a schematic top view of a circuit protection chip package according to a first embodiment of the present invention, and FIG. 2 is a schematic cross-sectional view of the II-II section of FIG. 1 . The circuit protection chip package M1 of the present embodiment can be applied in the circuit design of electronic products, so as to prevent electrostatic discharge from damaging the circuits of the electronic products. In this embodiment, the circuit protection chip package M1 is a fan-out package, and includes a circuit protection chip 1 , a wrapping structure 2 and a wiring structure 3 .

The circuit protection chip 1 may be a transient voltage suppressor (TSV), electromagnetic filter, varistor, or gas discharge tube, etc., which is not limited by the present invention. Further, when the circuit protection chip 1 is a transient voltage suppression chip, the circuit protection chip 1 may include, but not limited to, a diode, a bipolar transistor (BJT), a Zener diode (Zener diode), One or more of silicon controlled rectifiers (SCR). The circuit protection chip 1 of the embodiment of the present invention can be produced in the wafer manufacturing stage through the existing semiconductor manufacturing process.

As shown in FIG. 2 , the circuit protection chip 1 includes an upper surface 1 a, a bottom surface 1 b, and a side surface 1 c connected between the upper surface 1 a and the bottom surface 1 b. The circuit protection chip 1 also has at least one electrical connection point 100A, 100B located on the upper surface 1a (two are shown in FIG. 2 as an example). The aforementioned electrical connection points 100A, 100B may be solder balls, conductive bumps, conductive layers or conductive pillars, etc., which are not limited by the present invention.

Please continue to refer to FIG. 2 , the encapsulation structure 2 encloses the circuit protection chip 1 and the aforementioned electrical connection points 100A, 100B. In this embodiment, the covering structure 2 covers the upper surface 1 a , the bottom surface 1 b and the side surface 1 c of the circuit protection chip 1 . In detail, the cladding structure 2 may include a first cladding layer 21 and a second cladding layer 22 .

As shown in FIG. 2 , the first coating layer 21 covers the upper surface 1 a and the side surface 1 c of the circuit protection chip 1 . Accordingly, the circuit protection chip 1 is embedded in the first cladding layer 21 . The first cladding layer 21 has a connection surface 21a and a lower surface 21b opposite to the connection surface 21a. It should be noted that some of the electrical connection points 100A, 100B are not covered by the first coating layer 21 , but are exposed on the connection surface 21 a of the first coating layer 21 . In one embodiment, the connection surface 21a of the first cladding layer 21 is flush with the top surface 100s of the electrical connection points 100A, 100B, but the invention is not limited thereto. In another embodiment, there may also be a height difference between the connection surface 21a of the first cladding layer 21 and the top surface 100s of the electrical connection points 100A, 100B.

The second coating layer 22 covers at least the bottom surface 1 b of the circuit protection chip 1 . In this embodiment, the second cladding layer 22 also covers the lower surface 21 b of the first cladding layer 21 . That is to say, the second cladding layer 22 extends from the bottom surface 1 b of the circuit protection chip 1 to the lower surface 21 b of the first cladding layer 21 . The material of the first cladding layer 21 and the second cladding layer 22 can be a molding material, such as: epoxy resin (expoxy), polyimide (polyimide, PI), phenolic resin (phenolics), silicone resin (silicones) ), etc., the present invention is not limited. In addition, the first cladding layer 21 and the second cladding layer 22 may be made of the same material and integrally formed. However, in another embodiment, the first cladding layer 21 and the second cladding layer 22 may also be made of different materials and manufactured in different steps.

Referring to FIG. 2 , the circuit structure 3 is disposed on the covering structure 2 . The circuit structure 3 may be a laminated structure formed by stacking conductive material layers and insulating material layers, or a circuit board. The circuit structure 3 at least includes an inner circuit layer 31 and an outer conductive structure 32 . In detail, the inner circuit layer 31 is disposed on the connection surface 21a of the first cladding layer 21, and is electrically connected to the circuit protection chip 1 through the electrical connection points 100A, 100B. The outer conductive structure 32 is electrically connected to the electrical connection points 100A, 100B through the inner circuit layer 31 .

The inner circuit layer 31 will be connected to the electrical connection points 100A, 100B, and the inner circuit layer 31 is extended from the position above the circuit protection chip 1 along the connection surface 21a of the first cladding layer 21 to the side beyond the circuit protection chip 1 Surface 1c. That is to say, the inner circuit layer 31 partially overlaps with the circuit protection chip 1 in a thickness direction of the circuit protection chip 1 . It should be noted that the inner circuit layer 31 and the circuit protection chip 1 will partially overlap to generate parasitic capacitance.

Accordingly, in the embodiment of the present invention, the parasitic capacitance is reduced by reducing the overlapping area of the inner circuit layer 31 and the circuit protection chip 1 , thereby reducing the equivalent capacitance of the circuit protection chip package M1 . Specifically, in the present invention, the overlapping area between the vertical projection of the inner circuit layer 31 and the vertical projection of the circuit protection chip 1 accounts for 0.5% to 15% of the vertical projection area of the circuit protection chip 1 .

The inner line layer 31 shown in FIG. 1 is taken as an example for description. The inner wiring layer 31 includes patterned conductive portions 31A, 31B corresponding to the electrical connection points 100A, 100B. In this embodiment, the circuit protection chip 1 has two electrical connection points 100A, 100B. Therefore, the inner wiring layer 31 has two patterned conductive portions 31A, 31B respectively corresponding to the two electrical connection points 100A, 100B. However, the present invention does not limit the number of patterned conductive parts 31A, 31B. When the circuit protection chip 1 has only one electrical connection point 100A, 100B, or has more than two electrical connection points 100A, 100B, the inner circuit layer 31 may include one or more patterned conductive parts 31A, 31B.

Each patterned conductive portion 31A, 31B includes a main body portion 310 and an extension portion 311 connected to the main body portion 310 . The extension portion 311 extends from above the electrical connection points 100A, 100B to beyond the side surface 1c of the circuit protection chip 1, and the vertical projected area of the extension portion 311 is 4 to 6 times the vertical projected area of the electrical connection points 100A, 100B. In this embodiment, the overlapping area is the sum of areas of overlapping areas of the vertical projections of the two extension portions 311 and the vertical projection of the circuit protection chip 1 .

In addition, the main body portion 310 is located on the first cladding layer 21 without overlapping with the circuit protection chip 1 . The extension portion 311 extends from above the circuit protection chip 1 to the main body portion 310 . As shown in FIG. 1 , in this embodiment, the top view area of the main body portion 310 is larger than the top view area of the extension portion 311 .

Referring to FIG. 2 , the wiring structure 3 of this embodiment includes a first insulating layer 30 , and the inner wiring layer 31 and the first insulating layer 30 are jointly formed on the connecting surface 21 a of the first cladding layer 21 . In detail, the patterned conductive portions 31A, 31B of the inner circuit layer 31 are exposed outside the first insulating layer 30 . In addition, the two patterned conductive portions 31A, 31B of the inner circuit layer 31 are separated from each other to define an opening 31H. Therefore, a part of the first insulating layer 30 will fill in the opening 31H defined by the inner wiring layer 31 . In this embodiment, the upper surface of each patterned conductive portion 31A, 31B is flush with the upper surface of the first insulating layer 30 .

The circuit protection chip package M1 further includes conductive connection portions 33A, 33B corresponding to the electrical connection points 100A, 100B, respectively. As mentioned above, the circuit protection chip 1 has two electrical connection points 100A, 100B, so the two conductive connection portions 33A, 33B are respectively electrically connected to the electrical connection points 100A, 100B. Furthermore, each conductive connection portion 33A, 33B electrically and physically contacts the corresponding patterned conductive portion 31A, 31B, so as to be electrically connected to the corresponding electrical connection point 100A, 100B. In other words, in this embodiment, the inner circuit layer 31 and the outer conductive structure 32 are separated by a distance, and the conductive connection parts 33A, 33B are connected between the inner circuit layer 31 and the outer conductive structure 32 .

It should be noted that the number of the conductive connecting parts 33A, 33B is not limited by this embodiment. In addition, the conductive connection portions 33A, 33B can be any one of solder balls, conductive pillars, conductive bumps, or conductive holes. In this embodiment, the conductive connection parts 33A, 33B are solder balls. However, in other embodiments, the conductive connecting portions 33A, 33B may also be replaced by conductive pillars or conductive holes. In this embodiment, the wiring structure 3 further includes a second insulating layer 34 , and the conductive connection parts 33A, 33B are embedded in the second insulating layer 34 . In addition, the top surfaces 33s of the conductive connection portions 33A, 33B are flush with the outer surface 34s of the second insulating layer 34 .

Referring to FIG. 2 , the outer conductive structure 32 is disposed on the second insulating layer 34 and connected to the conductive connection portions 33A, 33B. In detail, the outer conductive structure 32 includes at least one electrical contact pad 32A, 32B, which is electrically and physically connected to the corresponding conductive connection portion 33A, 33B, thereby electrically connected to the corresponding electrical connection point 100A, 100B. That is to say, the electrical contact pads 32A, 32B can be used as external contacts of the circuit protection chip package M1, so that the circuit protection chip 1 can be electrically connected to another circuit board (not shown). As shown in FIG. 2 , the two electrical contact pads 32A, 32B are respectively electrically connected to the two electrical connection points 100A, 100B of the circuit protection chip 1 . However, the present invention does not limit the number of electrical contact pads 32A, 32B.

Referring to FIG. 1 again, the vertical projections of the electrical contact pads 32A, 32B overlap with the main body portions 310 of the corresponding patterned conductive portions 31A, 31B. Further, in this embodiment, the vertical projected area of the electrical contact pads 32A, 32B is larger than the vertical projected area of the main body portion 310 , but the present invention is not limited thereto.

It should be noted that, in this embodiment, a parasitic capacitance is also generated between any one of the electrical contact pads 32A ( 32B) and the patterned conductive portion 31B ( 31A) that is not electrically connected to it. Accordingly, in this embodiment, by providing the conductive connection parts 33A, 33B between the inner circuit layer 31 and the outer conductive structure 32, the distance between the electrical contact pad 32A (32B) and the patterned conductive part 31B (31A) can be increased. The distance between them further reduces the equivalent capacitance of the circuit protection chip package M1.

[Second embodiment]

Please refer to FIG. 3 , which shows a schematic cross-sectional view of a circuit protection chip package according to a second embodiment of the present invention. The same components of the circuit protection chip package M2 of the present embodiment and the circuit protection chip package M1 of the first embodiment have the same reference numerals, and the same parts will not be repeated.

In this embodiment, the circuit structure 3 is a circuit board, and includes an insulating layer 35 , an inner circuit layer 31 and an outer conductive structure 32 . The inner circuit layer 31 and the outer conductive structure 32 are respectively located on two opposite sides of the insulating layer 35, and are electrically connected to each other through the conductive connecting portions 33A, 33B. In this embodiment, the conductive connection portions 33A, 33B may be conductive pillars or conductive holes penetrating through the insulating layer 35 .

In addition, the two patterned conductive parts 31A, 31B of the inner circuit layer 31 can be fixed on the first cladding layer 21 through the conductive material L1, and are respectively electrically connected to the two electrical connection points 100A, 100B. The aforementioned conductive material L1 is, for example, conductive glue or tin, which is not limited in the present invention. In addition, in this embodiment, the insulating layer 35 is not filled into the opening 31H defined by the inner wiring layer 31 . Accordingly, the opening 31H defined by the inner circuit layer 31 is filled with air and not filled with other insulating materials.

Similar to the first embodiment, in this embodiment, the overlapping area of the vertical projection of the inner line layer 31 and the vertical projection of the circuit protection chip 1 accounts for 0.5% to 15% of the vertical projection area of the circuit protection chip 1, and can be The parasitic capacitance between the inner circuit layer 31 and the circuit protection chip 1 is reduced. In addition, compared with the prior art, the distance between the outer conductive structure 32 and the circuit protection chip 1 of this embodiment is increased due to the setting of the conductive connection parts 33A, 33B, which can also reduce the distance between the outer conductive structure 32 and the circuit protection chip 1. the parasitic capacitance between them. Overall, the equivalent capacitance of the circuit protection chip package M2 will be reduced.

[Third embodiment]

Please refer to FIG. 4 , which shows a schematic cross-sectional view of a circuit protection chip package according to a third embodiment of the present invention. The same components of the circuit protection chip package M3 of the present embodiment and the circuit protection chip package M1 of the first embodiment have the same reference numerals, and the same parts will not be repeated.

Compared with the circuit protection chip package M1 of the first embodiment, the circuit protection chip package M3 of this embodiment omits the conductive connection parts 33A, 33B. That is to say, in this embodiment, the wiring structure 3' includes the inner wiring layer 31 and the outer conductive structure 32, and the outer conductive structure 32 is in direct contact with the inner wiring layer 31.

In detail, the inner wiring layer 31 and the first insulating layer 30 of this embodiment are located on the connection surface 21 a of the first cladding layer 21 together. In addition, each electrical contact pad 32A, 32B of the outer conductive structure 32 is directly disposed on the corresponding patterned conductive portion 31A, 31B. Similar to the circuit protection chip package M1 of the first embodiment, in this embodiment, the vertical projection of each electrical contact pad 32A, 32B partially overlaps the corresponding patterned conductive portion 31A, 31B. In addition, the vertical projected area of each electrical contact pad 32A, 32B is larger than the vertical projected area of the main body portion 310 . Accordingly, each electrical contact pad 32A, 32B extends from the corresponding patterned conductive portion 31A, 31B to the first insulating layer 30 .

In this embodiment, an overlapping area between the vertical projection of the inner circuit layer 31 and the vertical projection of the circuit protection chip 1 also accounts for 0.5% to 15% of the area of the vertical projection of the circuit protection chip 1 . Therefore, the parasitic capacitance between the inner circuit layer 31 and the circuit protection chip 1 can also be reduced. In other words, even though the circuit protection chip package M1 of this embodiment omits the conductive connection portions 33A, 33B, the equivalent capacitance of the circuit protection chip package M3 can still be reduced.

Please refer to FIG. 5 , which shows a flowchart of a method for manufacturing a circuit protection chip package according to an embodiment of the present invention. In step S10, a circuit protection chip is placed on the temporary substrate; in step S11, a first coating layer is formed to cover the circuit protection chip; in step S12, a circuit structure is formed on the first coating layer ; In step S13, separate the circuit protection chip and the temporary substrate; and in step S14, form a second coating layer to cover the bottom of the circuit protection chip.

Taking the manufacturing of the circuit protection chip package M1 of the first embodiment as an example, the manufacturing method of the circuit protection chip package according to the embodiment of the present invention will be described below. Referring to FIG. 6 , the circuit protection chip 1 is disposed on the temporary substrate B1 . As mentioned above, the circuit protection chip 1 has been formed inside the circuit protection chip 1 to protect against electrostatic discharge. The circuit protection chip 1 has two electrical connection points 100A, 100B disposed on its upper surface 1a. It should be noted that the temporary substrate B1 may include a plate body (not shown in the figure) and a peelable layer (not shown in the figure) arranged on the plate body, wherein the material of the plate body may be ceramic, metal, plastic or composite materials, the present invention is not limited.

Please refer to FIG. 7 and FIG. 8 , which show the detailed steps of forming the first cladding layer 21 according to the embodiment of the present invention. As shown in FIG. 7, an initial coating layer 21' is formed to completely cover the circuit protection chip 1 and the electrical connection points 100A, 100B. At the same time, the initial cladding layer 21' will also cover the surface of the temporary substrate B1.

Referring to FIG. 8, a part of the initial cladding layer 21' is removed to expose the electrical connection points 100A, 100B of the circuit protection chip 1, and the first cladding layer 21 is formed. Accordingly, the electrical connection points 100A, 100B will be exposed outside the first cladding layer 21 . The first cladding layer 21 has a lower surface 21b connected to the temporary substrate B1 and a connecting surface 21a opposite to the lower surface 21b. In one embodiment, the initial cladding layer 21' may be removed through a grinding process until the electrical connection points 100A, 100B of the circuit protection chip 1 are exposed. Therefore, the top surfaces 100s of the electrical connection points 100A, 100B are flush with the connection surface 21a of the first cladding layer 21 , but the invention is not limited thereto.

Please refer to step S121 of FIG. 5 , and refer to FIG. 9 together, to form the inner wiring layer 31 on the first cladding layer 21 . The inner wiring layer 31 includes two patterned conductive portions 31A, 31B respectively corresponding to the electrical connection points 100A, 100B. It should be noted that, the top view shapes of the patterned conductive portions 31A, 31B can refer to FIG. 1 , which will not be repeated here. In this embodiment, the two patterned conductive portions 31A, 31B are separated from each other, and are respectively disposed on the top surfaces 100s of the two electrical connection points 100A, 100B. Accordingly, the inner wiring layer 31 defines an opening 31H.

Please refer to step S122 of FIG. 5 , and refer to FIG. 10 together, to form a first insulating layer 30' on the inner circuit layer 31. Referring to FIG. In FIG. 10 , the first insulating layer 30' will completely cover the inner wiring layer 31, and a part of the first insulating layer 30' will fill in the opening 31H of the inner wiring layer 31. Afterwards, a part of the first insulating layer 30' is removed to expose the two patterned conductive portions 31A, 31B of the inner circuit layer 31. In one embodiment, the first insulating layer 30' may be removed through a grinding process until the inner wiring layer 31 is exposed. Accordingly, the upper surface of each patterned conductive portion 31A, 31B is flush with the upper surface of the first insulating layer 30 . In other embodiments, the first insulating layer 30' covering the patterned conductive parts 31A, 31B may also be removed by laser drilling, which is not limited by the present invention.

Please refer to step S123 of FIG. 5 , and refer to FIG. 11 together, to form the conductive connection portions 33A, 33B on the inner circuit layer 31 . In this embodiment, the conductive connection portions 33A, 33B may be any one of solder balls, conductive pillars, conductive bumps or conductive holes. As shown in FIG. 11 , the two conductive connection portions 33A, 33B can be respectively disposed on the two patterned conductive portions 31A, 31B to electrically connect the two electrical connection points 100A, 100B respectively.

Please refer to step S124 in FIG. 5 , and refer to FIG. 12 together, forming a second insulating layer 34' to completely cover the inner circuit layer 31 and the conductive connection portions 33A, 33B. After that, referring to FIG. 12 , a part of the second insulating layer 34' is removed, so that the conductive connecting portions 33A, 33B can be partially exposed on the outer surface 34s of the second insulating layer 34. As mentioned above, the second insulating layer 34' can be removed through a grinding process until the conductive connecting portions 33A, 33B are exposed. Accordingly, as shown in FIG. 13 , the top surface 33s of each conductive connection portion 33A, 33B will be flush with the outer surface 34s of the second insulating layer 34 , but the invention is not limited thereto.

Please refer to step S125 of FIG. 5 , and refer to FIG. 14 in conjunction with forming an external conductive structure 32 on the top surface 33s of the conductive connecting portion 33A, 33B. Further, the two electrical contact pads 32A, 32B of the outer conductive structure 32 may respectively correspond to the positions of the two conductive connection parts 33A, 33B. By performing the above steps S121 to S125, the circuit structure 3 in the circuit protection chip package M1 of the first embodiment shown in FIG. 2 can be formed.

Please refer to FIG. 5 again, in the manufacturing method according to another embodiment of the present invention, step S123 to step S124 can also be omitted. That is, after step S122 is performed, step S125 is directly performed to form the circuit structure 3' in the circuit protection chip package M3 of the third embodiment shown in FIG. 4 . In this case, the outer conductive structure 32 is directly formed on the inner wiring layer 31 . Furthermore, each electrical contact pad 32A, 32B is directly formed on the corresponding patterned conductive portion 31A, 31B.

Besides, in the manufacturing method of another embodiment, step S122 can also be omitted. That is to say, after step S121 is performed, step S123 to step S125 are directly performed. In detail, after the inner wiring layer 31 is formed, the conductive connection portions 33A, 33B are directly formed on the inner wiring layer 31 . Afterwards, an insulating layer is formed to cover the conductive connection portions 33A, 33B and the inner circuit layer 31, and the conductive connection portions 33A, 33B are partially exposed on the outer surface of the insulating layer. Afterwards, the outer conductive structure 32 electrically contacting the conductive connecting portions 33A, 33B is formed.

Referring to FIG. 15 , after the circuit structure 3 is fabricated, the circuit protection chip 1 and the temporary substrate B1 are separated. Referring to FIG. 16 , a second coating layer 22 is formed to cover the bottom surface 1 b of the circuit protection chip 1 to form a circuit protection chip package M1 . In this embodiment, the second cladding layer 22 is formed on the lower surface 21 b of the first cladding layer 21 and the bottom surface 1 b of the circuit protection chip 1 , but the invention is not limited thereto. In another embodiment, the second cladding layer 22 may also be formed only on the bottom surface 1 b of the circuit protection wafer 1 .

Please refer to FIG. 17 , which shows a flowchart of a method for manufacturing a circuit protection chip package according to another embodiment of the present invention. In this embodiment, the step of forming the circuit structure 3 on the first cladding layer 21 (step S12) may include: in step S126, providing a pre-formed circuit structure; and in step S127, setting the circuit structure on on the first coating layer.

Referring to FIG. 18 , the steps shown in FIG. 10 can be continued. In this embodiment, the circuit structure 3 can be a circuit board, which can be fabricated in advance. The wiring structure 3 may include an insulating layer 35 , an inner wiring layer 31 , an outer conductive structure 32 and conductive connection parts 33A, 33B. The inner circuit layer 31 and the outer conductive structure 32 are respectively located on two opposite sides of the insulating layer 35, and are electrically connected to each other through the conductive connecting portions 33A, 33B.

Please refer to FIG. 19 , the preformed circuit structure 3 is directly disposed on the first cladding layer 21, and the extensions 311 of the two patterned conductive parts 31A, 31B of the inner circuit layer 31 will be respectively aligned on the two Electrical connection points 100A, 100B. The two patterned conductive parts 31A, 31B can be respectively electrically connected to the two electrical connection points 100A, 100B through the conductive material L1, and fixed on the first cladding layer 21 . The aforementioned conductive material L1 is, for example, but not limited to conductive glue or tin. However, the present invention does not limit the way of fixing the wiring structure 3 on the first cladding layer 21 . In another embodiment, the wiring structure 3 may also be fixed on the first cladding layer 21 by welding.

Referring to FIG. 20 , after the circuit structure 3 is fixed on the first cladding layer 21 , the temporary substrate B1 is separated from the circuit protection chip 1 . Referring to FIG. 21 , a second cladding layer 22 is formed on the bottom surface 1 b of the circuit protection chip 1 .

[Advantageous Effects of Embodiment]

One of the beneficial effects of the present invention is that the circuit protection chip package and its manufacturing method provided by the present invention can pass through "an overlapping area between the vertical projection of the inner circuit layer 31 and the vertical projection of the circuit protection chip 1, Accounting for 0.5% to 15% of the vertical projected area of the circuit protection chip 1", to reduce the parasitic capacitance between the inner circuit layer 31 and the circuit protection chip 1, thereby reducing the equivalent circuit protection chip package M1-M3 capacitance.

On the other hand, in the embodiment of the present invention, by providing the conductive connection parts 33A, 33B between the inner circuit layer 31 and the outer conductive structure 32, the circuit protection chip packages M1-M3 can further have a lower equivalent capacitance. In this way, when the circuit protection chip packages M1 - M3 are applied in the circuit of an electronic product, since the circuit protection chip packages M1 - M3 have a lower equivalent capacitance, the impact on the signal transmission speed can be reduced.

The content disclosed above is only a preferred feasible embodiment of the present invention, and does not therefore limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made by using the description and drawings of the present invention are included in the application of the present invention. within the scope of the patent.

M1-M3: Circuit Protection Chip Packages 1: circuit protection chip 1a: Upper surface 1b: bottom surface 1c: side surface 100A, 100B: electrical connection points 100s: top surface 2: cladding structure 21: First cladding layer 21': Initial cladding 21a: connecting surface 21b: lower surface 22: Second cladding layer 3, 3': line structure 30, 30': first insulating layer 31: Inner line layer 31A, 31B: patterned conductive part 31H: opening 310: main part 311: extension 32: External conductive structure 32A, 32B: Electrical contact pads 33A, 33B: conductive connection part 33s: Top surface of conductive connection part 34, 34': Second insulating layer 34s: Outer surface 35: insulation layer L1: Conductive material B1: Temporary substrate S10- S14, S121 -S127: Process steps

FIG. 1 is a schematic top view of a circuit protection chip package according to a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of the II-II section in FIG. 1 .

3 is a schematic cross-sectional view of a circuit protection chip package according to a second embodiment of the present invention.

4 is a schematic cross-sectional view of a circuit protection chip package according to a third embodiment of the present invention.

FIG. 5 is a flowchart of a method for manufacturing a circuit protection chip package according to an embodiment of the present invention.

FIG. 6 is a schematic diagram of the circuit protection chip package in step S10 according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of the circuit protection chip package in step S11 according to an embodiment of the present invention.

FIG. 8 is a schematic diagram of the circuit protection chip package after forming the first cladding layer according to the embodiment of the present invention.

FIG. 9 is a schematic diagram of the circuit protection chip package in step S121 according to an embodiment of the present invention.

FIG. 10 is a schematic diagram of the circuit protection chip package in step S122 according to an embodiment of the present invention.

FIG. 11 is a schematic diagram of the circuit protection chip package in step S123 according to an embodiment of the present invention.

FIG. 12 is a schematic diagram of the circuit protection chip package in step S124 according to an embodiment of the present invention.

FIG. 13 is a schematic diagram of the circuit protection chip package after forming a second insulating layer according to an embodiment of the present invention.

FIG. 14 is a schematic diagram of the circuit protection chip package in step S125 according to an embodiment of the present invention.

FIG. 15 is a schematic diagram of the circuit protection chip package in step S13 according to an embodiment of the present invention.

FIG. 16 is a schematic diagram of the circuit protection chip package in step S14 according to an embodiment of the present invention.

FIG. 17 is a flowchart of a method for manufacturing a circuit protection chip package according to another embodiment of the present invention.

FIG. 18 is a schematic diagram of a circuit protection chip package in step S126 according to another embodiment of the present invention.

FIG. 19 is a schematic diagram of a circuit protection chip package in step S127 according to another embodiment of the present invention.

FIG. 20 is a schematic cross-sectional view of a circuit protection chip package in step S13 according to another embodiment of the present invention.

FIG. 21 is a schematic cross-sectional view of a circuit protection chip package according to another embodiment of the present invention.

M1: circuit protection chip package

1: circuit protection chip

100A, 100B: electrical connection points

3: Line structure

31: Inner line layer

31A, 31B: patterned conductive part

310: main part

311: extension

32: External conductive structure

32A, 32B: electrical contact pads

33A, 33B: conductive connection part

34: Second insulating layer

34s: Outer surface

Claims (18)

A circuit protection chip package, comprising: A circuit protection chip, which has at least one electrical connection point; a wrapping structure, which wraps the circuit protection chip and at least one of the electrical connection points; and A circuit structure, which is arranged on the cladding structure, and includes an inner circuit layer and an outer conductive structure, wherein the outer conductive structure is electrically connected to at least one of the electrical connections through the inner circuit layer point, and an overlapping area between the vertical projection of the inner circuit layer and the vertical projection of the circuit protection chip accounts for 0.5% to 15% of the vertical projection area of the circuit protection chip. The circuit protection chip package as claimed in claim 1, wherein the circuit structure further comprises: a conductive connection part connected between the inner circuit layer and the outer conductive structure. The circuit protection chip package as claimed in claim 1, wherein the inner wiring layer includes a patterned conductive portion corresponding to at least one of the electrical connection points, and the patterned conductive portion includes a main body portion and an extension The main part is located on the covering structure, and the extension part extends from the main part to above the circuit protection chip and is electrically connected to at least one of the electrical connection points. The circuit protection chip package as claimed in claim 1, wherein the inner wiring layer includes a patterned conductive portion corresponding to at least one of the electrical connection points, the patterned conductive portion includes an extension portion, the The extension part extends from the electrical connection point beyond one side surface of the circuit protection chip, and a vertical projected area of the extension part is 4 to 6 times of a vertical projected area of the electric connection point. The circuit protection chip package as claimed in claim 1, wherein the outer conductive structure includes an electrical contact pad corresponding to at least one of the electrical connection points, and the patterned conductive part further includes a contact pad connected to the A main part of the extension part, and a vertical projection of the main part overlaps the electrical contact pad. The circuit protection chip package as claimed in claim 1, wherein the outer conductive structure is directly disposed on the inner wiring layer. The circuit protection chip package according to claim 1, wherein the cladding structure includes a first cladding layer and a second cladding layer, and the circuit protection chip is embedded in the first cladding layer and the top surface of at least one electrical connection point is flush with a connection surface of the first coating layer, and the second coating layer covers the bottom surface of the circuit protection chip. The circuit protection chip package as claimed in claim 1, wherein the wiring structure further includes an insulating layer located between the inner wiring layer and the outer conductive structure, and the inner wiring layer defines an opening , and the insulating layer is not filled into the opening. The circuit protection chip package as claimed in claim 1, wherein the inner wiring layer defines an opening, the wiring structure further includes a first insulating layer, and a part of the first insulating layer fills the opening middle. The circuit protection chip package as claimed in item 9, wherein the circuit structure further includes a second insulating layer and a conductive connection portion corresponding to at least one of the electrical connection points, the second insulating layer is located at the between the inner circuit layer and the outer conductive structure, and the conductive connection part is embedded in the second insulating layer and connected between the inner circuit layer and the outer conductive structure. A method of manufacturing a circuit protection chip package, comprising: disposing a circuit protection chip on a temporary substrate, wherein the circuit protection chip has at least one electrical connection point; forming a first cladding layer to cover the side surface of the circuit protection chip and at least one of the electrical connection points, wherein at least one of the electrical connection points is partially exposed on one of the first cladding layer top surface; A circuit structure is formed on the first cladding layer, wherein the circuit structure includes an inner circuit layer and an outer conductive structure, and the outer conductive structure is electrically connected to the electrical circuit through the inner circuit layer. connection points; and separating the circuit protection chip and the temporary substrate. The method for manufacturing a circuit protection chip package as claimed in claim 11, wherein an overlapping area between the vertical projection of the inner circuit layer and the vertical projection of the circuit protection chip occupies all of the circuit protection chip 0.5% to 15% of the above vertical projected area. The method for manufacturing a circuit protection chip package as claimed in claim 11, wherein the step of forming the circuit structure includes: forming the inner wiring layer on the first cladding layer; forming a first insulating layer on the inner wiring layer, wherein a part of the first insulating layer fills an opening defined by the inner wiring layer; and A part of the first insulating layer is removed to expose the inner wiring layer. The method for manufacturing a circuit protection chip package as claimed in claim 13, wherein the step of forming the circuit structure includes: After forming the inner wiring layer, forming a conductive connection part on the inner wiring layer; forming a second insulating layer to cover the inner circuit layer and the conductive connection part, wherein the conductive connection part is partially exposed on the surface of the second insulating layer; and The outer conductive structure is formed to be in electrical contact with the conductive connection portion. The method for manufacturing a circuit protection chip package as claimed in claim 11, wherein the step of forming the first cladding layer further comprises: forming an initial cladding layer to completely cover the circuit protection chip and the electrical connection points; and A part of the initial cladding layer is removed to form the first cladding layer, wherein the top surface of the electrical connection point is exposed on the top surface of the first cladding layer. The method for manufacturing a circuit protection chip package as claimed in claim 11, wherein the step of forming the circuit structure on the first cladding layer includes: providing said wiring structure pre-formed; and The circuit structure is disposed on the first cladding layer, wherein the inner circuit layer is aligned with at least one of the electrical connection points and is electrically connected to at least one of the electrical connection points. The method for manufacturing a circuit protection chip package according to claim 11, further comprising: after the step of separating the circuit protection chip and the temporary substrate, forming a second coating layer to cover the Circuitry protects the bottom surface of the die. The method for manufacturing a circuit protection chip package as claimed in claim 11, wherein the step of forming the circuit structure includes: After forming the inner wiring layer, forming a conductive connection part on the inner wiring layer; forming an insulating layer covering the inner circuit layer and the conductive connection part, wherein the conductive connection part is partially exposed on the outer surface of the insulating layer; and The outer conductive structure is formed to be in electrical contact with the conductive connection portion.

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