TW202324673A - 經塗佈聚合物的半導體裝置及混合接合以形成半導體組件 - Google Patents
經塗佈聚合物的半導體裝置及混合接合以形成半導體組件 Download PDFInfo
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- TW202324673A TW202324673A TW111132822A TW111132822A TW202324673A TW 202324673 A TW202324673 A TW 202324673A TW 111132822 A TW111132822 A TW 111132822A TW 111132822 A TW111132822 A TW 111132822A TW 202324673 A TW202324673 A TW 202324673A
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Abstract
本發明提供一種半導體裝置組件,其包括:一第一半導體裝置,其具有一正面及與該正面相對之一背面;金屬互連件,其形成於該背面上,及一聚合物材料,其沈積在該第一半導體裝置上方以囊封該等側壁、該背面及該等金屬互連件。該第一半導體裝置經平坦化以暴露該等金屬互連件之該上部表面。該組件進一步包括:一第二半導體裝置,其具有一頂側及與該頂側相對之一底側;一聚合物材料,其沈積在該第二半導體裝置上方以囊封該等側壁及該底側。該第二半導體裝置堆疊在該第一裝置上方並混合接合在一起,使得該第一半導體裝置背面上之每一金屬互連件與該第二半導體裝置底側上之一對應金屬互連件對準並電耦接。
Description
本發明係關於經塗佈聚合物之半導體裝置,且更特定言之,係關於經塗佈聚合物之半導體裝置及混合接合以形成半導體組件。
製造更小之電子裝置之趨勢導致密集填充有許多半導體薄膜及材料之半導體裝置顯著變薄。此等薄且密集填充之半導體裝置之側壁在經封裝至半導體裝置組件中之前的幾個製造過程期間容易受到損壞。下面概述了在個別半導體裝置中引入破壞封裝之半導體裝置組件之裂紋、碎屑或顆粒的一些製造過程。在自半導體裝置移除顆粒及殘留物之清潔過程期間,沿著半導體裝置側壁會形成輕微裂縫及空腔。此外,在形成個別半導體裝置之切割過程及自載體基板移除個別半導體裝置之拾取過程期間,顆粒可被引入至半導體裝置側壁中並且可沿著半導體裝置側壁形成輕微之裂縫或碎屑。此外,在形成半導體裝置組件或封裝之堆疊過程期間,可沿著半導體裝置側壁形成碎屑或裂縫。在此等過程完成之後,堆疊之半導體裝置經由例如混合接合過程接合在一起,其中產生之顆粒可導致解接合、個別半導體裝置故障及/或進一步損壞半導體裝置之側壁裂縫之發展及導致封裝半導體裝置組件之整個堆疊失效。
相關申請案之交叉參考
本申請案主張於2021年9月1日申請之美國臨時申請案第63/239,839號之權益;該美國臨時申請案以全文引用之方式併入本文中。
下文描述半導體裝置之若干實施例以及相關聯系統及方法之特定細節。熟習此項技術者將認識到,本文中所描述方法之合適階段可以晶圓級或晶粒級執行。因此,取決於使用之上下文,術語「基板」可指晶圓級基板或經單分晶粒級基板。此外,除非上下文另有指示,否則可使用習知半導體製造技術形成本文中所揭示之結構。可例如使用化學氣相沈積、物理氣相沈積、原子層沈積、電鍍、化學鍍、旋塗及/或其他合適之技術來沈積材料。類似地,可例如使用電漿蝕刻、濕式蝕刻、化學機械平坦化或其他合適之技術來移除材料。
在本發明中,論述許多具體細節以提供對本發明之實施例的全面且可行描述。一般熟習此項技術者將認識到,可在無具體細節中之一或多者的情況下實踐本發明。通常與半導體裝置相關聯之眾所周知的結構及/或操作可不會被展示及/或可不會被詳細描述以避免模糊本發明之其他態樣。一般而言,應理解,除本文中所揭示之彼等具體實施例外,各種其他裝置、系統及/或方法亦可在本發明之範疇內。
術語「半導體裝置組件」可係指一或多個半導體裝置、半導體裝置封裝及/或基板之組件,其可包括中介層、支撐件及/或其他合適之基板。半導體裝置組件可製造為但不限於離散封裝形式、條或矩陣形式,及/或晶圓面板形式。術語「半導體裝置」通常係指包括半導體材料之固態裝置。半導體裝置可包括例如半導體基板、晶圓、面板或來自晶圓或基板之單個晶粒。一種半導體裝置可進一步包括沈積在基板上之一或多個裝置層。半導體裝置在本文中可指半導體晶粒,但半導體裝置不限於半導體晶粒。
術語「半導體裝置封裝」可指具有併入至共用封裝中之一或多個半導體裝置之配置。半導體封裝可包括部分或完全囊封至少一個半導體裝置之殼體或外殼。半導體封裝亦可包括承載一或多個半導體裝置之基板。基板可附接至殼體或外殼或以其他方式併入於殼體或外殼內。
圖1A至圖1B為先前技術之經處理半導體裝置中之側壁碎屑及裂縫的簡化示意性橫截面圖及平面圖。如參考圖1A可看出,第一半導體裝置A及第二半導體裝置B經由黏著劑2附接至載體基板1並經受清潔過程11。載體基板1可為例如在清潔過程11期間保持半導體裝置A、B之載體盤或玻璃基板。雖然清潔過程11移除在製造過程之後會損壞半導體裝置A、B之大部分顆粒、殘留物及表面污染物,但清潔過程11為磨蝕性的且可沿著半導體裝置A之側壁4、5及半導體裝置B之側壁8、10蝕刻至矽中並損壞矽。例如,如在圖1A中所說明,清潔過程11可導致半導體裝置B之側壁8、10中之晶片損壞15 (例如,碎屑、裂縫、空腔及微裂隙)。
如參考圖1B可看出,第一半導體裝置C及第二半導體裝置D經由黏著劑2附接至載體基板1並經受晶粒拾取過程9。承載基板1可為例如載體盤或玻璃基板,其保持半導體裝置C、D以用於個別晶粒拾取過程9。在晶粒拾取過程9期間,半導體裝置C之側壁4、5及半導體裝置D之側壁8、10經受導致半導體裝置側壁損壞之額外力。例如,如在圖1A中所說明,晶粒拾取過程9向半導體裝置B之側壁4、5施加足夠的力以導致晶片劣化19 (例如,顆粒污染、撕裂及裂縫)。
側壁損壞可貫穿整個製造過程發展並進入半導體裝置之接合及封裝。微裂隙發展成裂縫,空腔發展成碎屑,等等。對每一個別半導體裝置之此損壞會危及封裝之半導體裝置組件的整個堆疊,從而導致半導體裝置組件之故障,並且由於一個損壞之半導體裝置而導致顯著的成本及時間損失。
本發明之實施例可藉由使用與隨後之混合接合操作相容之材料及過程為個別半導體裝置提供側壁保護來解決此等問題及其他問題。藉由在個別裝置單分之後但在將其自載體晶片移除之前保護其側壁,可避免及/或改善傳播微裂縫、碎屑及空腔之前述困難,如下文更詳細闡述。
圖2A至圖2E為根據本發明之實施例使用聚合物材料處理例示性半導體裝置之簡化示意性橫截面圖。如參考圖2A可看出,裝置晶圓293之背面處理已完成。裝置晶圓293包括正面201及背面202,正面201可藉由黏著劑291附接至載體基板290。裝置晶圓293可包括形成於正面201上之材料層292以及形成於材料層292中之複數個金屬互連件208、209、228及229。導電(例如,金屬)矽穿孔(TSV) 210、211、230及231形成於裝置晶圓293中,延伸穿過裝置晶圓293之正面201及背面202,連接形成於背面202上之複數個金屬互連件212、213、232及233中之每一者與形成於正面201上之複數個金屬互連件208、209、228及229中之對應一者。
可用於形成TSV 210、211、230及231、正面金屬互連件208、209、228及229以及背面金屬互連件212、213、232及233之金屬之實例包括銅、鋁、鎢、錫、銀、金或六種鉑類金屬(亦即,Ru、Rh、Pd、Os、Ir或Pt)中的任何一者。可使用任何方便之沈積方法,包括化學氣相沈積(CVD)、實體氣相沈積(PVD),例如濺射或電鍍。
可用於形成材料層292之材料的實例可選自氮化矽、碳化矽、矽化物、碳氮化矽、二氧化矽、聚醯亞胺、聚苯并㗁唑或苯并環丁烯中之一者。可使用任何方便之沈積方法,包括旋塗、化學氣相沈積(CVD)、原子層沈積(ALD)、氣相沈積聚合(VDP)或物理氣相沈積(PVD)。
如參考圖2B可看出,裝置晶圓293處理進一步包括切割複數個半導體裝置203及223以將其彼此分離、移除材料層292、形成鋸道或切割道281並從而暴露半導體裝置203之側壁205及207以及半導體裝置223之側壁225、227。可使用任何方便之切割方法,包括電漿切割、離子蝕刻、雷射切割或刀片切割中之一或多者。
如參考圖2C可看出,裝置晶圓293之處理進一步包括在裝置晶圓293上方沈積聚合物材料294,包括切割道281、金屬互連件212、213、232及233,以及複數個經單分半導體裝置(例如,半導體裝置203及223)。聚合物材料294分別直接囊封半導體裝置203及223之側壁205、207、225及227。此外,聚合物材料294直接囊封金屬互連件212、213、232及233。聚合物材料294可進一步囊封裝置晶圓293之背面202以及黏著劑291之頂面。聚合物材料294可部分或全部地包括單一聚合物材料或複合聚合物材料,例如聚醯亞胺、聚苯并㗁唑、苯并環丁烯或其組合。
儘管在圖2A至圖2E中未說明,但在一些實施例中,裝置晶圓293之正面201亦可設置有一層直接囊封裝置晶圓293之正面201的單一或複合聚合物材料,從而暴露正面金屬互連件208、209、228及229。例如,金屬互連件208、209、228及229可形成於裝置晶圓293之正面201上,隨後沈積聚合物材料作為直接囊封裝置晶圓293之正面201以及金屬互連件208、209、228及229之材料層292。聚合物材料層292及金屬互連件208、209、228及229接著可在附接至載體基板291之前經受圖案化過程及平坦化。替代地,聚合物材料層292以及金屬互連件208、209、228及229可在完成背面202上之處理步驟之後在正面201上形成及處理。可使用任何方便之拋光或平坦化方法,包括化學機械拋光(CMP)或旋轉蝕刻平坦化(SEP)。聚合物材料層292之厚度較佳地可在5至6 μm之範圍中,且較佳更佳地3至4 μm。聚合物材料層292之部分的移除可經組態以允許期望量或厚度之聚合物材料保留在裝置晶圓293之正面201上,以保護半導體裝置在切割、拾取、堆疊及混合接合過程期間免受損壞,並促進正-背半導體裝置混合接合過程中之金屬-金屬互連件連接,如在圖3中所展示。
如參考圖2D可看出,裝置晶圓293之處理進一步包括移除聚合物材料294之部分以暴露切割道283及黏著劑291之頂面,同時分別在半導體裝置203及223之側壁205、207、225及227上留下聚合物材料214及234之剩餘部分。可使用任何方便之單分方法來移除聚合物材料之部分並從而分離複數個半導體裝置,包括雷射移除或圖案化蝕刻中之一或多者。聚合物材料294之部分的移除可經組態以允許期望量或厚度之聚合物材料保留在側壁205、207、225及227上,以保護半導體裝置免受切割、拾取、堆疊及混合接合過程之影響。例如,自相鄰之半導體裝置203、223或沿著切割道283移除聚合物材料294之部分可分別沿著複數個半導體裝置203及223中之每一者的側壁205、207、225及227將聚合物材料214及234之剩餘部分的厚度減小至約20至35 μm之範圍。更特定而言,沿著複數個半導體裝置203及223中之每一者的側壁205、207、225及227的聚合物材料之剩餘部分214及234可具有在25至30 μm範圍內之厚度,並且更佳地約30 μm之厚度。
如參考圖2E可看出,裝置晶圓293之處理可進一步包括平坦化過程以減小裝置晶圓293之背面202上之聚合物材料214及234的厚度並暴露且視情況平坦化金屬互連件212、213、232及233。可使用任何方便之拋光或平坦化方法,包括化學機械拋光(CMP)或旋轉蝕刻平坦化(SEP)。聚合物材料214及234之背面厚度可較佳地在5至6 μm之範圍內,且更佳地3至4 μm。聚合物材料214及234之部分的移除可經組態以允許期望量或厚度之聚合物材料保留在裝置晶圓293之背面202上,以保護半導體裝置在切割、拾取、堆疊及混合接合過程期間免受損壞,並平坦化金屬互連件212、213、232及233,以便促進正-背半導體裝置混合接合過程中之金屬-金屬互連件連接,下文參考圖3更詳細地展示。
聚合物材料214、234及聚合物材料層292比鈍化層、氧化物、氮化物及碳化物(例如氮化矽、碳化矽、碳氮化矽、矽化物、二氧化矽等)更柔軟且更靈活。除其他益處及優點之外,聚合物材料214、234及聚合物材料層292之柔性亦提供對金屬(例如,銅)互連件之CMP碟形缺陷(dishing)及過度平坦化之更佳耐受性。聚合物材料更符合CMP過程並且不需要精確或剛性之平坦化過程來防止金屬互連件的過度移除/平坦化。就某些顆粒保留在接合表面上之程度而言,聚合物材料可具有足夠之順應性以適應顆粒周圍的變形而無分層之風險。此外,聚合物材料可旋塗在裝置晶圓293上,從而更容易沈積及更好地覆蓋裝置晶圓293並囊封側壁205、207、225及227、正面金屬互連件208、209、228及229,以及半導體裝置203及223之背面金屬互連件212、213、232及233。此外,由於其低得多之工作溫度、更低壓力、更低負載,以及更短時間,因此聚合物材料比使用鈍化層、氧化物、氮化物及碳化物(例如氮化矽、碳化矽、碳氮化矽、矽化物及二氧化矽)之更常用熱接合具有優勢。此外,聚合物材料214、234及聚合物材料層292將在混合接合過程期間圍繞接合線順應。此外,聚合物材料214、234及聚合物材料層292貫穿整個切割、拾取、堆疊及混合接合過程更耐受聚合物材料中之陷俘顆粒、污染物及殘留物。
儘管上文將裝置晶圓293之正面201及背面202描述為具有聚合物材料,但正面201上之材料層292可由任何非聚合物製成以獲得上文所描述益處。材料層292可包括例如鈍化層、氧化物、氮化物及碳化物,例如可根據需要使用氮化矽、碳化矽、碳氮化矽、矽化物及二氧化矽等來獲得上文所描述益處。亦即,可藉由在裝置晶圓293之背面202上沈積聚合物材料來獲得上文所描述益處,其中聚合物材料214及234分別囊封裝置晶圓293之背面202及半導體裝置203及223之側壁205、207以及側壁225、227。
圖3為根據本發明之實施例的例示性封裝半導體裝置組件。如參考圖3可看出,複數個半導體裝置被堆疊並混合接合在一起,形成封裝之半導體組件300。半導體組件300包括第一半導體裝置303,其具有由聚合物材料314直接囊封之側壁305及307以及背面金屬互連件312及313。第一半導體裝置303之正面金屬互連件308及309分別堆疊在封裝基板396之封裝觸點394及395上方並連接至該等封裝觸點。第一半導體裝置303進一步包括將正面金屬互連件308及309連接至背面金屬互連件312及313的金屬TSV 310及311。正面金屬互連件308及309以及正面被材料層302囊封。如上文所描述,材料層302可選自氮化矽、碳化矽、矽化物、二氧化矽、聚醯亞胺、聚苯并㗁唑或苯并環丁烯中之一者。第一半導體裝置303之正面及背面可被平坦化或拋光以暴露正面金屬互連件308及309以及背面金屬互連件312及313。
半導體組件300進一步包括堆疊在第一半導體裝置303上方之第二半導體裝置323。第二半導體裝置323之正面金屬互連件328及329分別堆疊在第一半導體裝置303之背面金屬互連件312及313上方並連接至該等背面金屬互連件。第二半導體裝置323具有由聚合物材料334直接囊封之側壁325及327以及背面金屬互連件332及333。第二半導體裝置323進一步包括將正面金屬互連件328及329連接至背面金屬互連件332及333之金屬TSV 330及331。正面金屬互連件328及329以及正面被材料層322囊封。如上文所描述,材料層322可選自氮化矽、碳化矽、矽化物、二氧化矽、聚醯亞胺、聚苯并㗁唑或苯并環丁烯中之一者。第一半導體裝置323之正面及背面可被平坦化或拋光以暴露正面金屬互連件328及329以及背面金屬互連件332及333。
半導體組件300可進一步包括堆疊在第二半導體裝置323上方之第三半導體裝置343。第三半導體裝置343之正面金屬互連件348及349分別堆疊在第二半導體裝置323之背面金屬互連件332及333上方並連接至該等背面金屬互連件。第三半導體裝置343具有由聚合物材料354直接囊封之側壁345及347以及背面金屬互連件352及353。第三半導體裝置343進一步包括將正面金屬互連件348及349連接至背面金屬互連件352及353之金屬TSV 350及351。正面金屬互連件348及349以及正面被材料層342囊封。如上文所描述,材料層342可選自氮化矽、碳化矽、矽化物、二氧化矽、聚醯亞胺、聚苯并㗁唑或苯并環丁烯中之一者。第一半導體裝置343之正面及背面可被平坦化或拋光以暴露正面金屬互連件348及349以及背面金屬互連件352及353。
半導體組件300可進一步包括堆疊在第三半導體裝置343上方之第四半導體裝置363。第四半導體裝置363之正面金屬互連件368及369分別堆疊在第三半導體裝置343之背面金屬互連件352及353上方並連接至該等背面金屬互連件。第四半導體裝置363具有由聚合物材料374直接囊封之側壁365及367。正面金屬互連件368及369以及正面被材料層362囊封。如上文所描述,材料層362可選自氮化矽、碳化矽、矽化物、二氧化矽、聚醯亞胺、聚苯并㗁唑或苯并環丁烯中之一者。第一半導體裝置363之正面及背面可被平坦化或拋光以暴露正面金屬互連件368及369並根據需要減小聚合物材料374之厚度。
半導體裝置303、323、343及363接合在一起,例如藉由混合接合然後囊封在囊封劑398中。焊球397形成為與封裝基板396之封裝觸點394及395接觸以形成封裝之半導體裝置組件300。
圖4為展示包括根據本發明之實施例組態之半導體裝置組件之例示性系統的示意圖。上文參考圖2A至圖2E及圖3所描述之例示性半導體裝置及半導體裝置組件中之任一者可併入至大量更大及/或更複雜之系統中的任一者中,其代表性實例為圖4中示意性展示之系統400。系統400可包括半導體裝置組件(例如,或離散半導體裝置) 402、電源404、驅動器406、處理器408及/或其他子系統或組件410。半導體裝置組件402可包括與上文參考圖2A至圖2E及圖3所描述之半導體裝置之特徵大體相似的特徵。所得系統400可執行廣泛各種功能中之任一者,例如記憶體儲存、資料處理及/或其他合適之功能。因此,代表性系統400可包括但不限於手持裝置(例如,移動電話、平板、數位閱讀器及數位音訊播放器)、電腦、車輛、電器及其他產品。系統400之組件可容納在單個單元中或分佈在多個互連單元上方(例如,經由通信網路)。系統400之組件亦可包括遠端裝置及廣泛各種電腦可讀媒體中之任一者。
圖5為說明製造半導體裝置組件之例示性方法的流程圖。例示性方法係以實例方式提供,因為存在多種方式來實施該方法。圖5中所展示之每一框表示在例示性方法中實施之一或多個過程、方法或次常式。圖2A至圖2E及圖3展示實施圖5之方法的例示性實施例。例示性方法可在框502處開始。進一步出於解釋之目的,實例過程500之框在本文中被描述為連續地或線性地發生。然而,實例過程500之多個框可並行發生。另外,實例過程500之框可以與所展示次序不同之次序執行及/或實例過程500之一或多個框可不執行。
圖5之例示性方法包括將包括複數個半導體裝置之裝置晶圓安置在臨時載體上(框502),其中複數個半導體裝置中之每一者具有面向臨時載體之正面及與正面相對之背面。
方法進一步包括在複數個半導體裝置中之每一者的背面上形成第一複數個金屬互連件(框504)。在一些例示性實施例中,形成金屬互連件可包括沈積銅、鋁、鎢、錫、銀或金中之一或多者。
方法進一步包括切割複數個半導體裝置以將半導體裝置彼此分離並暴露其側壁(框506)。在一些例示性實施例中,切割過程可包括電漿切割、雷射切割或刀片切割中之一或多者。
方法進一步包括在複數個經單分半導體裝置上方沈積第一聚合物材料,使得聚合物材料直接囊封複數個半導體裝置中之每一者的側壁、背面及第一複數個互連件(框508)。在一些例示性實施例中,第一聚合物材料可選自聚醯亞胺、聚苯并㗁唑、苯并環丁烯或其組合。與非有機鈍化層相比,聚合物材料具有更高之彈性性質,並且在化學機械拋光中對顆粒、表面粗糙度及銅碟形缺陷具有更高之耐受性。除了半導體裝置之側壁及背面之外,聚合物材料亦可沈積在半導體裝置之正面或頂側上,以提供在製造過程(例如,切割及拾取過程)中對半導體裝置之裂縫、碎屑及顆粒污染物的更高之耐受性以及在堆疊及混合接合過程中保護半導體裝置及組件免受裂縫或碎屑影響。
方法進一步包括藉由自複數個半導體裝置中之相鄰者之間移除第一聚合物材料的部分來將囊封之半導體裝置彼此單分(框510)。在一些例示性實施例中,可藉由雷射移除或圖案化蝕刻來移除複數個半導體裝置中之每一者之間的第一聚合物材料。此外,移除第一聚合物材料之部分的過程將沿著複數個半導體裝置中之每一者之側壁的第一聚合物材料之厚度減小至約30 μm。
方法進一步包括藉由平坦化聚合物材料之上部表面來暴露複數個半導體裝置中之每一者的第一複數個互連件(框512)。平坦化過程可使用化學機械拋光(CMP)或飛切來平坦化聚合物表面並暴露金屬互連件。在一些例示性實施例中,平坦化第一聚合物材料將複數個半導體裝置之背面上方的第一聚合物材料之厚度減小至約4 μm。
在一些例示性實施例中,方法可進一步包括在複數個半導體裝置中之每一者的正面上形成第二材料並在第二材料中形成第二複數個金屬互連件,其中第二複數個金屬互連件中之每一者與第一複數個金屬互連件中之對應一者對準。此外,第二材料可選自氮化矽、碳化矽、矽化物、二氧化矽、聚醯亞胺、聚苯并㗁唑或苯并環丁烯中之一者。
方法可進一步包括藉由混合接合堆疊複數個半導體裝置之子組來形成半導體裝置組件。在一些例示性實施例中,個別半導體裝置藉由黏著劑解接合自臨時載體基板移除,隨後為清潔及拾取用於聚合物混合接合。
本文中所論述之裝置,包括記憶體裝置,可形成於半導體基板或晶粒上,例如矽、鍺、矽鍺合金、砷化鎵、氮化鎵等。在一些狀況下,基板為半導體晶圓。在其他狀況下,基板可為絕緣體上矽(SOI)基板,例如玻璃上矽(SOG)或藍寶石上矽(SOP),或另一基板上之半導體材料之磊晶層。可經由使用各種化學物質(包括但不限於磷、硼或砷)摻雜來控制基板或基板之子區域的導電性。可在基板之初始形成或生長期間藉由離子植入或藉由任何其他摻雜手段執行摻雜。
本文中所描述之功能可以硬體、由處理器執行之軟體、韌體或其任一組合來實施。其他實例及實施在本發明及隨附申請專利範圍之範疇內。實施功能之特徵亦可實際上位於各種位置處,包括經分佈使得在不同實體部位處實施功能之部分。
如本文中(包括在申請專利範圍中)所使用,如在項目清單(例如,後面接以例如「中之至少一者」或「中之一或多者」之片語的項目清單)中所使用之「或」指示包括性清單,使得(例如) A、B或C中之至少一者之清單意指A或B或C或AB或AC或BC或ABC (
亦即,A及B及C)。此外,如本文中所使用,片語「基於」不應被認作對條件之閉集之參考。例如,被描述為「基於條件A」之例示性步驟可基於條件A及條件B兩者而不脫離本發明之範疇。換句話說,如本文中所使用,片語「基於」應在方式上應被認作與片語「至少部分地基於」相同。
如本文中所使用,術語「垂直」、「側向」、「上部」、「下部」、「上面」及「下面」可指代半導體裝置中之特徵鑒於圖中所展示之定向的相對方向或位置。例如,「上部」或「最上部」可指代特徵經定位比另一特徵更靠近頁之頂部。然而,此等術語應被廣義地解釋為包括具有其他定向之半導體裝置,例如倒置或傾斜定向,其中頂部/底部、上方/下方、上面/下面,上/下及左/右可取決於定向互換。
應注意,上文所描述方法描述可能實施,且可重新配置或以其他方式修改操作及步驟,且其他實施為可能的。此外,可組合來自方法中之兩個或多於兩者之實施例。
自前述內容,將瞭解,出於說明之目的,本文中已描述本發明之特定實施例,但在不脫離本發明之範疇之情況下可進行各種修改。確切而言,在前述描述中,論述許多具體細節,以便對本發明之實施例進行全面且有利之描述。然而,熟習此項技術者將認識到,在沒有具體細節中之一或多者的情況下,可實踐本發明。在其他情況下,通常與記憶體系統及裝置相關聯之已知結構或操作未展示,或未詳細描述,以避免模糊本發明之其他態樣。大體而言,應理解,除本文中所揭示之彼等特定實施例外,各種其他裝置、系統及方法可在本發明之範疇內。
1:載體基板
2:黏著劑
4:側壁
5:側壁
8:側壁
9:拾取過程
10:側壁
11:清潔過程
15:晶片損壞
19:晶片劣化
201:正面
202:背面
203:半導體裝置
205:側壁
207:側壁
208:金屬互連件
209:金屬互連件
210:TSV
211:TSV
212:金屬互連件
213:金屬互連件
214:聚合物材料
223:半導體裝置
225:側壁
227:側壁
228:金屬互連件
229:金屬互連件
230:TSV
231:TSV
232:金屬互連件
233:金屬互連件
234:聚合物材料
281:切割道
283:切割道
290:載體基板
291:黏著劑
292:聚合物材料層
293:裝置晶圓
294:聚合物材料
300:半導體組件
302:材料層
303:第一半導體裝置
305:側壁
307:側壁
308:正面金屬互連件
309:正面金屬互連件
310:金屬TSV
311:金屬TSV
312:背面金屬互連件
313:背面金屬互連件
314:聚合物材料
322:材料層
323:第二半導體裝置
325:側壁
327:側壁
328:正面金屬互連件
329:正面金屬互連件
330:金屬TSV
331:金屬TSV
332:背面金屬互連件
333:背面金屬互連件
334:聚合物材料
342:材料層
343:第三半導體裝置
345:側壁
347:側壁
348:正面金屬互連件
349:正面金屬互連件
350:金屬TSV
351:金屬TSV
352:背面金屬互連件
353:背面金屬互連件
354:聚合物材料
362:材料層
363:第四半導體裝置
365:側壁
367:側壁
368:正面金屬互連件
369:正面金屬互連件
374:聚合物材料
394:封裝觸點
395:封裝觸點
396:封裝基板
397:焊球
398:囊封劑
400:系統
402:半導體裝置組件
404:電源
406:驅動器
408:處理器
410:其他子系統
500:過程
502:框
504:框
506:框
508:框
510:框
512:框
A:第一半導體裝置
B:第二半導體裝置
C:第一半導體裝置
D:第二半導體裝置
圖1A至圖1B為先前技術之經處理半導體裝置中之側壁碎屑及裂縫之簡化示意性橫截面圖及平面圖。
圖2A至圖2E為根據本發明之實施例使用聚合物材料處理例示性半導體裝置之簡化示意性橫截面圖。
圖3為根據本發明之實施例的例示性封裝半導體裝置組件。
圖4為展示包括根據本發明之實施例組態之半導體裝置組件的例示性系統之示意圖。
圖5為說明根據本發明之實施例的製造半導體裝置組件之例示性方法的流程圖。
雖然易於對本發明作出各種修改及替代形式,但已在圖式中以實例方式展示具體實施例且將在本文中對其進行詳細描述。然而,應理解,本發明並不意欲限於所揭示之特定形式。實際上,意欲涵蓋屬於如由所附申請專利範圍所界定之本發明之範疇內的所有修改、等效內容及替代方案。
300:半導體組件
302:材料層
303:第一半導體裝置
305:側壁
307:側壁
308:正面金屬互連件
309:正面金屬互連件
310:金屬TSV
311:金屬TSV
312:背面金屬互連件
313:背面金屬互連件
314:聚合物材料
322:材料層
323:第二半導體裝置
325:側壁
327:側壁
328:正面金屬互連件
329:正面金屬互連件
330:金屬TSV
331:金屬TSV
332:背面金屬互連件
333:背面金屬互連件
334:聚合物材料
342:材料層
343:第三半導體裝置
345:側壁
347:側壁
348:正面金屬互連件
349:正面金屬互連件
350:金屬TSV
351:金屬TSV
352:背面金屬互連件
353:背面金屬互連件
354:聚合物材料
362:材料層
363:第四半導體裝置
365:側壁
367:側壁
368:正面金屬互連件
369:正面金屬互連件
374:聚合物材料
394:封裝觸點
395:封裝觸點
396:封裝基板
397:焊球
398:囊封劑
Claims (20)
- 一種半導體裝置組件,其包含: 一第一半導體裝置,其具有一正面及與該正面相對之一背面,該第一半導體裝置包括: 第一複數個金屬互連件,其形成於該背面上, 一第一聚合物材料,其沈積在該第一半導體裝置上方以直接囊封該等側壁、該背面及該第一複數個金屬互連件,其中該第一聚合物材料經平坦化以暴露該第一複數個金屬互連件之上部表面; 一第二半導體裝置,其具有一頂側及與該頂側相對之一底側,該第二半導體裝置包括: 一第二聚合物材料,其沈積在該第二半導體裝置上方以直接囊封該等側壁及該底側, 一第三材料,其沈積在形成有第二複數個金屬互連件之該第二半導體裝置的該頂側上; 其中該第二半導體裝置堆疊在該第一半導體裝置上方,使得該第二複數個金屬互連件中之每一者與該第一複數個金屬互連件中之對應一者對準並電耦接;且 其中該第一半導體裝置及該第二半導體裝置混合接合在一起。
- 如請求項1之半導體裝置組件,其中該第一聚合物材料及該第二聚合物材料選自由聚醯亞胺、聚苯并㗁唑及苯并環丁烯組成之群。
- 如請求項1之半導體裝置組件,其中沿著該第一半導體裝置及該第二半導體裝置之該等側壁的該第一聚合物材料及該第二聚合物材料之厚度為約30 μm。
- 如請求項1之半導體裝置組件,其中在該第一半導體裝置之該背面上方之該第一聚合物材料的厚度為約4 μm,且在該第二半導體裝置之底側上方之該第二聚合物材料的厚度為約4 μm。
- 如請求項1之半導體裝置組件,其進一步包含沈積在該第一半導體裝置之該正面上方之一第四材料及形成於該第二材料中之第三複數個金屬互連件,其中該第三複數個金屬互連件中之每一者與該第一複數個金屬互連件中之對應一者對準。
- 如請求項5之半導體裝置組件,其中該第三材料及該第四材料為氮化矽、碳化矽、矽化物、二氧化矽、聚醯亞胺、聚苯并㗁唑或苯并環丁烯中之一者。
- 一種半導體裝置,其包含: 一正面及與該正面相對之一背面; 第一複數個金屬互連件,其形成於該背面上; 一第一聚合物材料,其沈積在該半導體裝置上方以直接囊封該等側壁、該背面及該第一複數個金屬互連件; 其中該第一聚合物材料經平坦化以暴露該第一複數個金屬互連件之上部表面。
- 如請求項7之半導體裝置,其中該第一聚合物材料選自由聚醯亞胺、聚苯并㗁唑及苯并環丁烯組成之群。
- 如請求項7之半導體裝置,其中沿著該半導體裝置之該等側壁的該第一聚合物材料之厚度為約30 μm。
- 如請求項7之半導體裝置,其中在該半導體裝置之該背面上方的該第一聚合物材料之厚度為約4 μm。
- 如請求項7之半導體裝置,其進一步包含沈積在該半導體裝置之該正面上方的一第二材料及形成於該第二材料中之第二複數個金屬互連件,其中該第二複數個金屬互連件中之每一者與該第一複數個金屬互連件中之對應一者對準。
- 如請求項11之半導體裝置,其中該第二材料為氮化矽、碳化矽、矽化物、二氧化矽、聚醯亞胺、聚苯并㗁唑或苯并環丁烯中之一者。
- 一種製造半導體裝置組件之方法,其包含: 將包括複數個半導體裝置之一裝置晶圓安置在一臨時載體上,該複數個半導體裝置中之每一者具有面對該臨時載體之一正面及與該正面相對之一背面; 在該複數個半導體裝置中之每一者的該背面上形成第一複數個金屬互連件; 切割該複數個半導體裝置以將該半導體裝置彼此分離並暴露其側壁; 在該複數個經單分半導體裝置上方沈積一第一聚合物材料,使得該聚合物材料直接囊封該複數個半導體裝置中之每一者之該等側壁、該背面及該第一複數個金屬互連件; 藉由自該複數個半導體裝置中之相鄰者之間移除該第一聚合物材料之一部分來將該等囊封之半導體裝置彼此單分;及 藉由平坦化該聚合物材料之一上部表面來暴露該複數個半導體裝置中之每一者的該第一複數個金屬互連件。
- 如請求項13之方法,其中該第一聚合物材料選自由聚醯亞胺、聚苯并㗁唑及苯并環丁烯組成之群。
- 如請求項13之方法,其中該複數個半導體裝置中之每一者之間的該第一聚合物材料藉由雷射移除或圖案化蝕刻來移除。
- 如請求項13之方法,其中移除該第一聚合物材料之該部分將沿著該複數個半導體裝置中之每一者的該等側壁之該第一聚合物材料之一厚度減小至約30 μm。
- 如請求項13之方法,其中平坦化該第一聚合物材料將在該複數個半導體裝置之該背面上方之該第一聚合物材料的一厚度減小至約4 μm。
- 如請求項13之方法,其進一步包含在該複數個半導體裝置中之每一者的該正面上形成一第二材料並在該第二材料中形成第二複數個金屬互連件,其中該第二複數個金屬互連件中之每一者與該第一複數個金屬互連件中之對應一者對準。
- 如請求項18之方法,其中該第二材料為氮化矽、碳化矽、矽化物、二氧化矽、聚醯亞胺、聚苯并㗁唑或苯并環丁烯中之一者。
- 如請求項18之方法,其進一步包含藉由混合接合來堆疊該複數個半導體裝置之一子組。
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US17/820,199 US20230065248A1 (en) | 2021-09-01 | 2022-08-16 | Polymer coated semiconductor devices and hybrid bonding to form semiconductor assemblies |
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