TW202320174A - Method of forming semiconductor structure - Google Patents

Abstract

Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a diffusion blocking layer on a semiconductor substrate; forming channel material layers over the diffusion blocking layer; patterning the semiconductor substrate, the channel material layers, and the diffusion blocking layer to form a trench in the semiconductor substrate, thereby defining an active region being adjacent the trench; filling the trench with a dielectric material layer and a solid doping source material layer containing a dopant; and driving the dopant from the solid doping source material layer to the active region, thereby forming an anti-punch-through (APT) feature in the active region.

Description

Formation method of semiconductor structure

Embodiments of the present invention relate generally to integrated circuit devices, and more particularly to multi-gate devices such as all-wound gate devices.

The electronics industry continues to demand smaller and faster electronic devices that can simultaneously support a large number of complex functions. In order to meet these demands, there is a continuing trend in the integrated circuit industry to manufacture low cost, high performance, and low power consumption integrated circuits. The main way to achieve these goals is to reduce the size of the integrated circuit (eg, the smallest structure size of the integrated circuit), thereby improving the yield and reducing the related cost. However, shrinking the size also increases the complexity of the integrated circuit manufacturing process. Therefore, in order to achieve continuous progress in integrated circuit devices and their performance, similar progress is required in the manufacturing process and technology of integrated circuits.

Recently, multi-gate devices have been introduced to improve gate control. Multiple gate devices can increase gate-channel coupling, reduce off-state current, and/or reduce short channel effects. One of these multi-gate devices is a full-wrap gate device (also known as a multi-channel device), which includes multiple channels stacked and whose gate structure can extend partially or completely around the multiple channels to contact the channel area at least two sides of the Wrap-around gate devices can greatly shrink IC technology, maintain gate control, mitigate short channel effects, and seamlessly integrate into existing IC manufacturing processes. As all-wrap-around gate devices continue to shrink, several challenges arise. For example, punch-through resistant implants cannot be properly implemented to achieve the desired effect because dopant diffusion in the channel region (among other issues) degrades mobility and other device performance, especially for high-mobility channels. Therefore, there is an urgent need for an integrated circuit structure and a manufacturing method thereof to solve the above-mentioned problems.

An embodiment of the invention provides a method for forming a semiconductor structure. The method includes forming a diffusion barrier layer on a semiconductor substrate; forming a plurality of channel material layers on the diffusion barrier layer; patterning the semiconductor substrate, the channel semiconductor layer, and the diffusion barrier layer to form trenches in the semiconductor substrate, thereby defining an active region and adjacent to the trench; filling the trench with a dielectric material layer and a solid dopant source material layer containing dopant; and driving the dopant from the solid dopant source material layer into the active region, thereby forming an anti-breakdown structure in the trench. in the active zone.

Another embodiment of the invention provides a method for forming a semiconductor structure. The method includes forming a diffusion barrier layer on the semiconductor substrate; forming a channel material layer on the diffusion barrier layer; patterning the semiconductor substrate, the channel material layer, and the diffusion barrier layer to form trenches in the semiconductor substrate, and then defining fin-shaped active regions to be adjacent to the trench; filling the trench with a dielectric material layer to form an isolation structure; recessing the isolation structure to form a fin structure in the fin active region; and then depositing a borosilicate glass layer on the isolation structure superior.

Another embodiment of the present invention provides a semiconductor structure. The semiconductor structure includes an active region located in the semiconductor substrate and spanning from the first shallow trench isolation structure to the second shallow trench isolation structure; a plurality of channel layers of the first conductivity type located on the semiconductor substrate and spanning the first shallow trench isolation structure; between the sidewall and the second sidewall; a gate stack formed on the semiconductor substrate and extending to cover each channel layer; and an anti-breakdown structure of a first conductivity type containing a first dopant, wherein the anti-breakdown structure is located at the gate Under the stack, wherein the first shallow trench isolation structure and the second shallow trench isolation structure each include a solid dopant source material layer containing a first dopant, and wherein the first shallow trench isolation structure and the second shallow trench isolation The upper surface of the structure is lower than the upper surface of the breakdown resistant structure.

The following detailed description can be accompanied by accompanying drawings to facilitate understanding of various aspects of the present invention. It is worth noting that various structures are used for illustration purposes only and are not drawn to scale, as is the norm in the industry. In fact, the dimensions of the various structures may be arbitrarily increased or decreased for clarity of illustration.

Different embodiments or examples provided below may implement different configurations of the present invention. Multiple examples of the present invention may repeatedly use the same reference numerals for brevity, but elements with the same reference numerals in various embodiments and/or configurations do not necessarily have the same corresponding relationship. In addition, the following examples of specific components and arrangements are used to simplify the content of the present invention but not to limit the present invention. For example, a description of forming a first component on a second component includes an embodiment in which the two are in direct contact, or an embodiment in which the two are interposed by other additional components rather than in direct contact. Additionally, in embodiments of the present invention where a structure is formed on, connected to, and/or coupled to another structure, the structure may directly contact the other structure, or additional structures may be formed on the structure and another structure, so that the structure and another structure are not in direct contact.

In addition, spatially relative terms such as "below", "beneath", "lower", "above", "higher", or similar terms are used to describe the relationship between some elements or structures in the drawings and other Relationships between elements or structures. These spatially relative terms include different orientations of the device in use or operation, as well as the orientation depicted in the drawings. When the device is turned to a different direction (rotated 90 degrees or other angles), the spatially relative adjectives used will also be interpreted according to the turned direction. Additionally, when values or ranges of values are described with "about," "approximately," or similar language, it includes +/-10% of the stated value unless otherwise specified. For example, the phrase "about 5 nm" includes a size range between 4.5 nm and 5.5 nm.

1A, 1B, 1C, and 1D are flowcharts of a method 100 for fabricating a multi-gate device in various embodiments of the present invention. In some embodiments, the multi-gate device fabricated by the method 100 includes an n-type all-around gate transistor and a p-type all-around gate transistor. In step 102, doped wells such as n-type wells and p-type wells can be formed in the substrate. For example, processes such as deposition, lithography, and etching are performed to form a patterned mask covering the p-type field effect transistor region, and implanted with a p-type dopant such as boron to form a p-type dopant well. Then similarly form an n-type doped well in the p-type field effect transistor region. For example, processes such as deposition, lithography, and etching are performed to form a patterned mask covering the n-type field effect transistor region, and implanted with n-type dopants such as phosphorus to form n-type doped wells . In other embodiments, the n-type well can be formed first, and then the p-type well can be formed in a similar procedure. Step 104 can form a diffusion barrier layer on the substrate. The composition and thickness of the diffusion barrier layer can effectively prevent the dopant from diffusing into the channel layer. The diffusion barrier layer includes semiconductor material epitaxially grown on the substrate. Step 106 is to form a semiconductor layer stacked on the diffusion barrier layer. The semiconductor layer stack includes vertically stacked and alternately arranged first semiconductor layers and second semiconductor layers. Step 108 patterns the semiconductor layer stack, the diffusion barrier layer, and the substrate to form trenches and define fin-like active regions. Step 110 forms a shallow trench isolation structure in the trench, wherein the shallow trench isolation structure includes a dopant-containing solid dielectric material layer. The layer of solid dielectric material can also be regarded as the layer of solid dopant source material. In the described embodiment, the layer of solid dopant source material includes a layer of borosilicate glass. Step 112 drives dopants into the fin-shaped active region to form a breakdown-resistant structure therein. An anti-puncture structure is located below the diffusion barrier layer.

In various embodiments, the method of forming a shallow trench isolation structure with a solid doped source material layer may be step 110 . Step 110 includes multiple sub-steps, as shown in FIG. 1B . Step 114 forms a dielectric liner in the trench by deposition or thermal oxidation. Step 116 forms a solid dopant source material layer on the dielectric liner in the trench. Step 118 further fills the trench with one or more dielectric materials to form a shallow trench isolation structure, which can be formed by a suitable process such as deposition and chemical mechanical polishing. Step 120 recesses the STI structure by selective etching and forms corresponding fin active regions to protrude above the STI structure.

Step 110 of some other embodiments is shown in Figure 1C. Step 114 forms a dielectric liner in the trench. Step 122 further fills the trench with one or more dielectric materials to form a shallow trench isolation structure, which can be formed by a suitable process such as deposition and chemical mechanical polishing. Step 124 recesses the STI structure by selective etching, and forms a fin-like active region to protrude higher than the STI structure. The process of forming the solid dopant source material layer on the shallow trench isolation structure in step 126 may be deposition and etching. In this embodiment, a solid dopant source material layer is formed on the upper surface of the STI structure. The isolation structure and the solid dopant source material layer can form a shallow trench isolation structure together.

After forming the shallow trench isolation structure in step 110 and driving dopants from the solid doped source material layer in step 112 to form a breakdown-resistant structure in the fin-shaped active region, the method 100 proceeds to subsequent steps, as shown in FIG. 1D . Step 132 forms a capping layer on sidewalls of the fin-like active region. In some embodiments, the cladding layer may comprise a semiconductor material having a composition similar to that of the second semiconductor layer in the semiconductor layer stack. Step 134 forms a gate structure on the semiconductor layer stack. The gate structure includes dummy gate stacks and gate spacers. Step 136 removes portions of the semiconductor layer stack in the source/drain regions to form source/drain recesses. Step 138 forms inner spacers along sidewalls of the second semiconductor layer of the semiconductor layer stack. Step 140 forms epitaxial source/drain structures in the source/drain recesses. Step 142 forms an interlayer dielectric layer on the epitaxial source/drain structure. Step 144 removes the dummy gate stack to form a gate trench exposing the semiconductor layer stack in the gate region. Step 146 removes the first semiconductor layer from the stack of semiconductor layers exposed by the gate trenches to form gaps between the second semiconductor layers. Step 148 forms a metal gate in the gate trench around the second semiconductor layer. The metal gate fills the gap between the second semiconductor layers and covers the second semiconductor layers. The metal gate includes a gate dielectric layer and a gate. Step 150 of method 100 then forms contacts. Embodiments of the present invention may implement additional processes. Additional steps may be provided before, during, and after method 100, and additional embodiments of method 100 may swap, replace, or omit some of the described steps. Various embodiments of nanowire-based integrated circuit devices, which may be fabricated according to the method 100 , are described below.

Figures 2A to 17A, Figures 2B to 17B, Figures 2C to 17C, and Figures 2D to 17D are various embodiments of the present invention, part or whole of a multi-gate device 200 in various manufacturing stages (as shown in Figures 1A, 1B, 1C, and 100 of the method 100 in 1D). Specifically, FIGS. 2A to 4A and FIGS. 7A to 17A are top views of the multi-gate device 200 on the X-Y plane. 2B to 4B and FIGS. 7B to 17B are cross-sectional views (in the X-Z plane) of the multi-gate device 200 along the section line B-B' of FIGS. 2A to 4A and FIGS. 7A to 17A, respectively. FIGS. 2C to 4C and FIGS. 7C to 17C are cross-sectional views (in the Y-Z plane) of the multi-gate device 200 along the line C-C' of FIGS. 2A to 4A and FIGS. 7A to 17A, respectively. 2D to 4D and FIGS. 7D to 17D are cross-sectional views (in the Y-Z plane) of the multi-gate device 200 along the section line D-D' of FIGS. 2A to 4A and FIGS. 7A to 17A respectively. 5A, 5B, 5C, and 5D are cross-sectional views (in the X-Z plane) of the multi-gate device 200 along the line B-B' of FIG. 4A at various fabrication stages in some embodiments. 6A, 6B, 6C, and 6D are cross-sectional views (in the X-Z plane) of the multi-gate device 200 along the line B-B' of FIG. 4A at various fabrication stages in some embodiments. The multi-gate device 200 may be included in a microprocessor, memory, and/or other integrated circuit devices. In some embodiments, the multi-gate device 200 is a part of an integrated circuit chip, a monolithic system, or a portion thereof, and may include various passive and active semiconductor devices such as resistors, capacitors, inductors, diodes, p-type field Effect transistors, n-type field effect transistors, metal oxide semiconductor field effect transistors, complementary metal oxide semiconductor transistors, bipolar junction transistors, laterally diffused metal oxide semiconductor transistors, high voltage transistors, high frequency transistors , other suitable components, or a combination of the above. In some embodiments, the multi-gate device 200 is included in non-volatile memory such as non-volatile random access memory, flash memory, electrically erasable programmable read-only memory, electrically programmable Read memory, other suitable types of memory, or a combination of the above. 2A to 17A, 2B to 17B, 2C to 17C, and 2D to 17D have been simplified to facilitate understanding of the inventive concepts of the embodiments of the present invention. Additional structures may be added to the multi-gate device 200, and other embodiments of the multi-gate device 200 may substitute, modify, or omit some of the structures described below.

As shown in FIGS. 2A to 2D , the multi-gate device 200 includes a substrate (wafer) 202 . In the depicted embodiment, substrate 202 includes silicon. The substrate 202 may additionally or alternatively comprise another semiconductor element such as germanium; a semiconductor compound such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; a semiconductor alloy such as silicon germanium, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaAsP; or combinations thereof. The substrate 202 can be changed to a semiconductor-on-insulator substrate, such as a silicon-on-insulator substrate, a silicon-germanium-on-insulator substrate, or a germanium-on-insulator substrate. The fabrication method of the semiconductor-on-insulator substrate may adopt separation and implantation of oxygen, wafer bonding, and/or other suitable methods. The substrate 202 may include various doped regions, depending on the design requirements of the multi-gate device 200 . In the illustrated embodiment, the substrate 202 includes a p-type doped region such as a p-type well 203A (which may be configured for an n-type all-around gate transistor), and an n-type doped region such as an n-type well 203B ( It can be configured for a p-type all-wound gate transistor). The n-type doped region such as the n-type well 203B can be doped with n-type dopants such as phosphorus, arsenic, other n-type dopants, or combinations thereof. The p-type doped region such as the p-type well 203A can be doped with p-type dopants such as boron, indium, other p-type dopants, or combinations thereof. In some embodiments, the substrate 202 includes doped regions having a combination of p-type dopants and n-type dopants. For example, various doped regions can be formed directly on and/or in the substrate 202 to provide p-well structures, n-type well structures, dual well structures, raised structures, or combinations thereof. Ion implantation process, diffusion process, and/or other suitable doping processes can be performed to form various doped regions. In some embodiments, the p-type well 203A and the n-type well 203B can be formed by ion implantation. For example, a first patterned mask can be formed, which can be formed by deposition and lithography processes, and can have a first opening corresponding to the region of the p-type well 203A; perform a first ion implantation process, through the first opening introducing p-type dopants into the substrate 202; then removing the first patterned mask; forming a second patterned mask with a second opening corresponding to the area used by the n-type well 203B; performing a second ion implantation process, introducing n-type dopants into the substrate 202 through the second opening; and then removing the second patterned mask.

The diffusion barrier layer 204 is formed on the substrate 202 , wherein the composition and thickness of the diffusion barrier layer 204 are designed to effectively block dopant diffusion during the step of forming an anti-breakdown structure in a subsequent stage. In the depicted embodiment, the diffusion barrier layer 204 is a semiconductor layer. In the illustrated embodiment, the diffusion barrier layer 204 is a SiGe layer. SiGe with proper germanium concentration and sufficient thickness can block boron diffusion. For example, silicon germanium can be epitaxially grown on the substrate 202 to form the diffusion barrier layer 204 . In some embodiments, the epitaxial growth method of the diffusion barrier layer 204 may be molecular beam epitaxy, chemical vapor deposition, metalorganic chemical vapor deposition, other suitable epitaxial growth processes, or a combination thereof.

The semiconductor layer stack 205 is formed on the diffusion barrier layer 204 , wherein the semiconductor layer stack 205 includes semiconductor layers 210 and semiconductor layers 215 vertically stacked from the surface of the substrate 202 (eg, along the z-direction) and arranged alternately. In some embodiments, the semiconductor layer 210 and the semiconductor layer 215 are epitaxially grown in a staggered manner. For example, the epitaxial growth of the first semiconductor layer 210 on the substrate, the epitaxial growth of the first semiconductor layer 215 on the first semiconductor layer 210, the epitaxial growth of the second semiconductor layer 210 on the first semiconductor layer 215 , and so on, until the semiconductor layer stack 205 has the required number of semiconductor layers 210 and semiconductor layers 215 . In these embodiments, the semiconductor layer 210 and the semiconductor layer 215 can be regarded as epitaxial layers. In some embodiments, the epitaxial growth method of the semiconductor layer 210 and the semiconductor layer 215 can be molecular beam epitaxy process, chemical vapor deposition process, metalorganic chemical vapor deposition process, other suitable epitaxial growth process, or the above-mentioned combination.

The composition of the semiconductor layer 210 and the semiconductor layer 215 are different to achieve etching selectivity and/or different oxidation rates in subsequent processes. In some embodiments, the semiconductor layer 210 has a first etch rate to the etchant, the semiconductor layer 215 has a second etch rate to the etchant, and the second etch rate is greater than the first etch rate. In some embodiments, the semiconductor layer 210 has a first oxidation rate, the semiconductor layer 215 has a second oxidation rate, and the second oxidation rate is greater than the first oxidation rate. In the described embodiment, the semiconductor layer 210 and the semiconductor layer 215 include different materials, composition atomic %, composition weight %, thickness, and/or other characteristics, so as to be used in the etching process (such as forming the floating channel layer in the multi-gate device 200 The etch process in the channel region) achieves the desired etch selectivity. For example, when the semiconductor layer 210 includes silicon and the semiconductor layer 215 includes silicon germanium, the silicon etching rate of the semiconductor layer 210 is lower than the silicon germanium etching rate of the semiconductor layer 215 . In some embodiments, the semiconductor layer 210 and the semiconductor layer 215 may include the same material but different atomic % to achieve etch selectivity and/or different oxidation rates. For example, the semiconductor layer 210 and the semiconductor layer 215 may comprise silicon germanium, wherein the semiconductor layer 210 has a first silicon atomic % and/or a first germanium atomic %, and the semiconductor layer 215 has a different second silicon atomic % and a different The second source of germanium %. The semiconductor layer 210 and the semiconductor layer 215 of embodiments of the present invention may comprise any combination of semiconductor materials that can provide desired etch selectivity, desired oxidation rate differential, and/or desired performance characteristics (such as maximizing current flow). materials), and may include any of the semiconductor materials described herein.

As described below, the semiconductor layer 210 or portions thereof may form the channel region of the multi-gate device 200 . In the illustrated embodiment, the semiconductor layer stack 205 includes four semiconductor layers 210 and four semiconductor layers 215 disposed on the diffusion barrier layer 204 to form a semiconductor layer stack. After subsequent processing, this configuration will result in the multi-gate device 200 having four channels. However, the semiconductor layer stack 205 of the embodiment of the present invention may include more or fewer semiconductor layers, depending on the number of channels required by the multi-gate device 200 (such as a fully-wound gate transistor) and/or the number of channels required by the multi-gate device. Depends on the design requirements. For example, the semiconductor layer stack 205 may include two to ten semiconductor layers 210 and two to ten semiconductor layers 215 . In the embodiment, the semiconductor layer 210 has a thickness t1, and the semiconductor layer 215 has a thickness t2, and the thickness t1 and the thickness t2 are selected according to the fabrication of the multi-gate device 200 and/or device performance considerations. For example, the thickness t2 can be set to define the desired distance (or gap) between adjacent channels of the multi-gate device 200, the thickness t1 can be set to achieve the desired thickness of the channels of the multi-gate device 200, and the thickness Both t1 and thickness t2 can be set to achieve the desired performance of the multi-gate device 200 . In some embodiments, the thickness t1 and the thickness t2 are about 2 nm to about 12 nm. In some embodiments, thickness t1 is about 9 nm to about 11 nm, and thickness t2 is about 5 nm to about 7 nm. In some embodiments, the germanium concentration of semiconductor layer 215 is less than 25 atomic percent.

The diffusion barrier layer 204 differs from the semiconductor material of the semiconductor layers of the semiconductor layer stack 205 , in particular from the composition and thickness of the semiconductor layer 210 and the semiconductor layer 215 due to individual functions, as described above. For example, when the semiconductor layer 210 includes silicon and the semiconductor layer 215 includes silicon germanium, the diffusion barrier layer 204 includes silicon germanium but the germanium concentration, thickness, or both are different to effectively block diffusion. Specifically, the germanium concentration of the diffusion barrier layer 204 is greater than that of the semiconductor layer 215 , and the thickness of the diffusion barrier layer 204 may be further greater than the respective thicknesses of the semiconductor layers 215 . In some examples, the germanium concentration of the diffusion barrier layer 204 is between about 25 atomic % and about 50 atomic %, and the thickness t3 is between about 10 nm and about 15 nm. In some examples, the germanium concentration of the diffusion barrier layer 204 is greater than 25 atomic %, and its thickness t3 is greater than 8 nm.

As shown in FIGS. 3A-3D , the semiconductor layer stack 205 is patterned to form fins 218A and 218B (also referred to as fin structures, fin cells, or similar structures). The diffusion barrier layer 204 may be patterned together with the semiconductor layer stack 205 . Fins 218A and 218B include a substrate portion (such as a portion of substrate 202 ), a diffusion barrier layer portion (such as a portion of diffusion barrier layer 204 ), and a semiconductor layer stack portion (such as a semiconductor layer stack including semiconductor layer 210 and semiconductor layer 215 ). 205 reserved). Fins 218A and 218B are substantially parallel to each other along the y-direction, and have a length defined in the y-direction, a width defined in the x-direction, and a height defined in the z-direction. In some embodiments, a lithography and/or etching process may be performed to pattern the semiconductor layer stack 205 to form the fins 218A and 218B. The lithography process may include forming a photoresist layer on the semiconductor layer stack 205 (such as spin coating), performing a pre-exposure bake process, performing an exposure process using a mask, performing a post-exposure bake process, and performing a development process. During the exposure process, the photoresist layer can be irradiated with radiation energy such as ultraviolet light, deep ultraviolet light, or extreme ultraviolet light, wherein the photomask blocks, penetrates, and/or reflects the radiation to the photoresist layer, and the end view is the photomask pattern of the photomask And/or the type of photomask (such as binary photomask, phase shift photomask, or UV photomask), so that the image projected on the photoresist layer corresponds to the photomask pattern. Since the photoresist layer is sensitive to radiation energy, the exposed part of the photoresist layer will undergo chemical changes, and the exposed part (or unexposed part) of the photoresist layer can be dissolved during the development process, depending on the characteristics of the photoresist layer and the development process. Depends on the properties of the developing solution used. After development, the patterned photoresist layer includes a photoresist pattern corresponding to the photomask. The etch process may use the patterned photoresist layer as an etch mask and remove portions of the semiconductor layer stack 205 . In some embodiments, a patterned photoresist layer is formed on the hard mask layer on the semiconductor layer stack 205, a portion of the hard mask layer is removed by a first etching process to form a patterned hard mask layer, and the patterned hard mask layer is formed using The hard mask layer is patterned as an etch mask and a portion of the semiconductor layer stack 205 is removed in a second etch process. The etching process may include a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In some embodiments, the etching process is a reactive ion etching process. For example, the patterned photoresist layer (and in some embodiments, the hard mask layer) may be removed after the etch process, and the removal method may be a photoresist stripping process or other suitable processes. The formation method of the fins 218A and 218B can be changed to a multiple patterning process, such as a double patterning process (such as a lithography-etching-lithography-etching process, a self-aligned double patterning process, and a spacer that is a dielectric layer. Self-aligned double patterning process, other double patterning process, or a combination of the above), triple patterning process (such as lithography-etching-lithography-etching-lithography-etching process, self-aligned triple patterning process, other triple patterning processes, or combinations of the above), other multiple patterning processes (such as self-aligned quadruple patterning processes), or combinations of the above. In some embodiments, directed self-assembly techniques may be implemented when patterning the semiconductor layer stack 205 . In addition, the exposure process of some embodiments may implement maskless lithography, e-beam writing, and/or ion beam writing to pattern the photoresist layer.

An isolation structure 230 containing a solid dopant source material layer is formed on and/or in the substrate 202 to isolate various regions of the multi-gate device 200 such as various device regions. For example, isolation structure 230 surrounds the bottoms of fins 218A and 218B, so isolation structure 230 separates and isolates fins 218A and 218B from each other. In the illustrated embodiment, isolation structure 230 surrounds substrate portions of fins 218A and 218B (eg, doped regions of substrate 202 such as p-well 203A and n-type well 203B), and partially surrounds fins 218A and 218B. A portion of the semiconductor layer stack (eg, a portion of the bottommost semiconductor layer 210 ). However, embodiments of the present invention may implement different arrangements of the isolation structures 230 with respect to the fins 218A and 218B. The isolation structure 230 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (such as containing silicon, oxygen, nitrogen, carbon, or other suitable isolation compositions), or a combination thereof. The isolation structure 230 may include different structures, such as a shallow trench isolation structure or a deep trench isolation structure. For example, isolation structure 230 may include a shallow trench isolation structure that may define and electrically isolate fins 218A and 218B from other active device regions (eg, fins) and/or passive device regions. The formation method of the shallow trench isolation structure may be to etch a trench in the substrate 202 to define a fin-like active region (as described above, such as using a dry etching process and/or a wet etching process), and filling the trench with an insulating material (eg chemical vapor deposition process or spin-on-glass process). A chemical mechanical polishing process may be performed to remove excess insulating material and/or planarize the top surface of the isolation structure 230 . Then an etch-back process is performed to selectively etch the insulating material layer to form the isolation structure 230 . In some embodiments, the STI structure includes a multi-layer structure to fill the trench, such as a silicon nitride-containing layer on a thermal oxide-containing liner layer. In another example, the shallow trench isolation structure includes a dielectric layer on a doped liner layer including borosilicate glass or phosphosilicate glass. In yet another example, the shallow trench isolation structure includes a base dielectric layer located on the liner dielectric layer, wherein the materials included in the base dielectric layer and the liner dielectric layer depend on design requirements. Specifically, the isolation structure 230 includes a solid dopant source material layer to serve as a source for diffusing dopants into the fin-shaped active region to form a breakdown-resistant structure therein. The composition and structure of the isolation structure 230 surrounding the fin-shaped active regions such as the fins 218A and 218B can be different because of the different requirements of the solid dopant source material. Therefore, isolation structures surrounding the fin-shaped active regions such as fins 218A and 218B can be formed, respectively, which can be regarded as isolation structures 230A and 230B, respectively, as shown in FIGS. 4A to 4D . The method of forming the isolation structures 230A and 230B will be described in various embodiments.

In some embodiments shown in FIGS. 5A to 5D and FIG. 1B , step 110 forms the isolation structure 230 , and step 112 drives dopants into the fin-like active region to form the anti-puncture structure. The isolation structure 230A is formed in the region where the p-type well 203A will be formed and the n-type field effect transistor will be formed, as shown in FIG. 5A . The isolation structure 230A includes a liner 232 , a solid dopant source material layer 234 , and a filling dielectric material layer 236 . In the illustrated embodiment, the liner 232 includes an oxide material such as silicon oxide, which can be formed by deposition, thermal oxidation, or other suitable methods. In some examples, the thickness of liner 232 may be between 2 nm and 5 nm. The solid dopant source material layer 234 is a dielectric material containing desired dopants such as boron. In the illustrated embodiment, the solid dopant source material layer 234 includes borosilicate glass, which can be formed by deposition such as chemical vapor deposition or other suitable methods. The boron concentration of the solid dopant source material layer 234 is large enough to effectively form a breakdown-resistant structure in a subsequent stage. In some embodiments, the boron concentration of the solid dopant source material layer 234 may be between 1×10 21 atoms/cm ³ and 1×10 ²² atoms/cm ³ . The thickness of the solid dopant source material layer 234 may be between 5 nm and 50 nm. The filling dielectric material layer 236 includes a dielectric material such as silicon oxide, a low-k dielectric material, other suitable dielectric materials, or a combination thereof. The filling dielectric material layer 236 can be formed by deposition such as chemical vapor deposition, flowable chemical vapor deposition, other suitable methods, or a combination of the above. After the liner 232, the solid dopant source material layer 234, and the fill dielectric material layer 236 are formed, a chemical mechanical polishing process may be performed to remove these materials on top of the active region of the fin and planarize the upper surface, thereby further An isolation structure 230A is formed. These materials (such as liner 232, solid dopant source material layer 234, and filling dielectric material layer 236) can then be subjected to a selective etching process to recess the isolation structure 230A, and the selective etching process can be any suitable etching process. Processes such as dry etching, wet etching, or a combination of the above.

As mentioned above, the isolation structure 230A acts as a solid diffusion source to form the desired breakdown resistant structure. The anti-breakdown structures used by the n-type field effect transistor and the p-type field effect transistor can be doped with dopants of opposite conductivity types, and the solid doping source material layers used are different. In the illustrated embodiment, the n-well 203B is covered with the patterned mask 238 and the grooves associated with the active fin region such as the fin 218B, and the formation method can be lithography, etching, or both. The patterned mask 238 can be a soft mask formed by lithography process such as photoresist material, or a hard mask formed by lithography process and etching such as silicon oxide or silicon nitride.

As shown in FIG. 5B , a drive process is performed to drive dopants, such as boron, into the fin-shaped active region, such as fin 218A, to form the anti-puncture structure 240 . In the above embodiment, the driving process is a thermal annealing process, and the annealing temperature and annealing time can be designed to effectively drive the dopant into the fin-shaped active region, such as the fin 218A, to achieve the required dopant concentration. In some examples, the annealing temperature of the thermal annealing process is greater than 900° C. In some embodiments, the annealing temperature of the thermal annealing process is between 1000° C. and 1100° C., the annealing time is between 5 seconds and 30 seconds or a few milliseconds of peak annealing, and the annealing environment includes nitrogen, oxygen, hydrogen, or a combination of the above. Some examples may implement thermal annealing processes in rapid thermal annealing equipment.

The anti-breakdown structure 240 is a p-type doped structure disposed under the diffusion barrier layer 204, and the diffusion barrier layer 204 restricts the diffusion of the anti-breakdown structure 240 into the channel. The thickness of the anti-puncture structure 240 depends on the dopant concentration of the solid dopant source material layer 234 and the thermal annealing process (including annealing temperature and annealing time). In one example, the thickness of the anti-puncture structure 240 is greater than 100 nm, such as about 200 nm to 500 nm. In one example, the p-type dopant concentration used in the anti-puncture structure 240 is about 5×10 ¹⁷ /cm ³ to 5×10 ¹⁹ /cm ³ . The dopant concentration of the anti-puncture structure 240 may be greater than the dopant concentration of the channel layer formed in a subsequent stage. The patterned mask 238 can then be removed.

As shown in FIG. 5C , isolation structures 230B are formed in trenches associated with n-well 203B and fin-like active regions such as fins 218B by similar or different procedures. Areas of p-well 203A associated with active fins such as fins 218A may be covered by patterned mask 242 and may be formed by lithography, etching, or both. The patterned mask 242 can be a soft mask formed by lithography process, or a hard mask formed by lithography process and etching instead.

In some embodiments, the isolation structure 230B includes a liner 232 , a solid dopant source material layer 244 , and a fill dielectric material layer 236 . In the illustrated embodiment, the liner 232 and fill dielectric material layer 236 are similar in composition to the liner 232 and fill dielectric material layer 236 in the isolation region 230A. The solid dopant source material layer 244 is not copper to the solid dopant source material layer 234, and may contain dopants of opposite conductivity type, such as phosphorous. The solid dopant source material layer 244 is a dielectric material containing desired dopants such as phosphorous. In the illustrated embodiment, the solid dopant source material layer 244 includes phosphosilicate glass, which can be formed by a deposition process such as chemical vapor deposition or other suitable methods. The phosphorus concentration of the solid dopant source material layer 244 is large enough to effectively form a corresponding anti-puncture structure in a subsequent stage. In some embodiments, the phosphorus concentration of the solid dopant source material layer 244 is greater than 15 atomic %, such as between 15 atomic % and 30 atomic %. The thickness of the solid dopant source material layer 244 may be between 5 nm and 50 nm.

After forming the liner 232, the solid dopant source material layer 244, and the filling dielectric material layer 236, a chemical mechanical polishing process may be performed to remove these materials on the top of the fin-shaped active region and planarize the upper surface, thereby forming Isolation structure 230B. These materials (such as the liner 232, the solid dopant source material layer 244, and the filling dielectric material layer 236) can then be subjected to a selective etching process to recess the isolation structure 230B, and the selective etching process can be any suitable etching process. Processes such as dry etching, wet etching, or a combination of the above.

As shown in FIG. 5D , a driving process is performed to drive dopants (such as phosphorous in this embodiment) to the fin-shaped active region, such as the fin 218B, to form the anti-puncture structure 246 . The anti-puncture structure 246 is an n-type doped structure under the diffusion barrier layer 204 . In the embodiment, the driving process is a thermal annealing process, and the thermal annealing temperature and annealing time are designed to effectively drive dopants into the fin-shaped active region such as the fin 218B. The patterned mask 242 can then be removed.

In some embodiments, the design of the diffusion barrier layer 204 forming the anti-puncture structure 246 may be different to effectively block the diffusion of the phosphorus dopant. For example, the design of the composition, concentration, thickness, structure, or combination thereof of the diffusion barrier layer 204 associated with the n-type well 203B may be different from that of the diffusion barrier layer 204 associated with the p-type well 203A. For example, the diffusion barrier layer 204 associated with the n-well 203B may comprise silicon carbide, gallium arsenide, other suitable compositions, or combinations thereof. In this example, the diffusion barrier layer 204 is formed separately in the p-well region and the n-type well region. For example, the n-well region can be covered by a patterned mask (the same patterned mask used to form the p-type well can be used), and then a diffusion barrier layer of silicon germanium is epitaxially grown in the p-type well region. The p-well region can be covered by a patterned mask before or after (the same patterned mask used to form the n-well can be used), followed by epitaxial growth of a diffusion barrier layer of different composition (such as silicon carbide or gallium arsenide) on the n In the type well area.

In some embodiments, the isolation structure 230B without the solid diffusion source and the corresponding breakdown-resistant structure can be formed by other methods, such as oblique ion implantation or ion implantation via the sidewall of the trench. In some embodiments, the above-mentioned various processes may be performed in different orders. For example, the patterned mask (such as the patterned mask 238 or 242 ) can be removed before the driving process, and the corresponding anti-puncture structure (such as the anti-puncture structure 240 or 246 ) can be formed in step 112 . In some embodiments, the formation methods of the anti-puncture structures 240 and 246 may be implemented in different order, such as forming the anti-puncture structure 240 after forming the anti-puncture structure 246 .

In some other embodiments shown in FIGS. 6A to 6D and FIG. 1C , step 110 forms the isolation structure 230 , and step 112 drives dopants into the fin-like active region to form the anti-puncture structure. Isolation structure 230A includes solid dopant source material layer 234 but is located on top of isolation structure 230A. Isolation structure 230A includes solid dopant source material layer 234 but is located on top of isolation structure 230A. Similarly, isolation structure 230B includes solid dopant source material layer 244 , but on top of isolation structure 230B.

The isolation structure 230A is formed in the region associated with the p-type well 203A and the n-type field effect transistor, as shown in FIG. 6A . The isolation structure 230A includes a liner 232 , a filling dielectric material layer 236 , and a solid dopant source material layer 234 . The composition and formation method of the liner 232 and the filling dielectric material layer 236 may be the same as or similar to those of the corresponding material layer in FIG. 5A . For example, the liner 232 includes an oxide material such as silicon oxide, which can be formed by deposition, thermal oxidation, or other suitable methods. The filling dielectric material layer 236 is directly formed on the liner 232, and may include a dielectric material such as silicon oxide, a low dielectric constant dielectric material, other suitable dielectric materials, or a combination thereof, and the formation method may be Deposition such as chemical vapor deposition, flowable chemical vapor deposition, other suitable methods, or combinations thereof. After forming the liner 232 and filling the dielectric material layer 236 , a chemical mechanical polishing process may be performed to remove these materials on top of the fin-like active regions and planarize the upper surface, thereby forming the isolation structure 230A. A selective etching process can then be performed on these materials (such as the liner 232 and the filling dielectric material 236 ) to recess the isolation structure 230A, and a suitable etching process can be dry etching, wet etching, or a combination thereof.

A solid dopant source material layer 234 can then be formed on the recessed filling dielectric material layer 236 by a suitable method such as chemical vapor deposition. A subsequent etching process may be performed on the solid dopant source material layer 234 to remove the solid dopant source material layer 234 on the sidewall of the fin-shaped active region such as the fin 218A, so that the solid dopant source material layer 234 is lower than the diffusion layer. barrier layer 204 . Therefore, the diffusion barrier layer 204 can block and limit subsequent diffusion. The solid dopant source material layer 234 is a dielectric material containing desired dopants such as boron. In the described embodiment, the formation method of the solid dopant source material layer 234 includes deposition such as chemical vapor deposition or other suitable methods. The boron concentration of the solid dopant source material layer 234 is large enough to effectively form a breakdown-resistant structure in a subsequent stage. In some embodiments, the boron concentration of the solid dopant source material layer 234 is greater than 15 atomic %, such as between 15 atomic % and 30 atomic %. The thickness of the solid dopant source material layer 234 may be between 5 nm and 50 nm.

As mentioned above, the isolation structure 230A can act as a solid diffusion source to form the desired breakdown-resistant structure. The anti-breakdown structures used in n-type field effect transistors and p-type field effect transistors can be doped with opposite conductivity types, but the solid doping source material layers are different. In the illustrated embodiment, the trenches associated with the n-well 203B and the active fin region such as the fin 218B are covered with a patterned mask, which may be formed by lithography, etching, or both. The patterned mask 238 can be a soft mask formed by lithography process such as photoresist material, or a hard mask formed by lithography process and etching such as silicon oxide or silicon nitride.

As shown in FIG. 6B , a drive process may be performed to drive dopants, such as boron, to the fin-shaped active region, such as fin 218A, to form the anti-puncture structure 240 . The driving process is a thermal annealing process, and the thermal annealing temperature and annealing time are designed to effectively drive dopants into the fin-shaped active region such as the fin 218A. In the illustrated embodiment, the drive process is similar to the corresponding drive process of FIG. 5B.

The anti-breakdown structure 240 is a p-type doped structure disposed under the diffusion barrier layer 204, and the diffusion barrier layer 204 restricts the diffusion of the anti-breakdown structure 240 into the channel. The thickness of the anti-puncture structure 240 depends on the dopant concentration of the solid dopant source material layer 234 and the thermal annealing process (including annealing temperature and annealing time). In some examples, the thickness of the anti-puncture structure 240 is greater than 100 nm, such as about 200 nm to 500 nm. In one example, the p-type dopant concentration used in the anti-puncture structure 240 is about 1×10 ¹⁷ /cm ³ to 1×10 ¹⁸ /cm ³ . The dopant concentration of the anti-puncture structure 240 is greater than the dopant concentration of the channel layer formed in a subsequent stage. The patterned mask 238 can then be removed.

As shown in FIG. 6C , isolation structures 230B are formed in trenches associated with n-well 203B and fin-like active regions such as fins 218B by similar or different procedures. Areas associated with p-well 203A and active fins such as fins 218A may be covered by a patterned mask 242 formed by lithography, etching, or both. The patterned mask 242 can be a soft mask formed by lithography process, or a hard mask formed by lithography process and etching instead.

In some embodiments, the isolation structure 230B includes a liner 232 , a fill dielectric material layer 236 , and a solid dopant source material layer 244 . In the illustrated embodiment, the composition of liner 232 and fill dielectric material layer 236 is similar to the composition of liner 232 and fill dielectric material layer 236 in isolation structure 230A. A solid dopant source material layer 244 is located on top of the isolation structure 230B. The solid dopant source material layer 244 is different from the solid dopant source material layer 234 and includes dopants of opposite conductivity type, such as phosphorus. The solid dopant source material layer 244 is a dielectric material containing desired dopants such as phosphorous. In the illustrated embodiment, the solid dopant source material layer 244 includes phosphosilicate glass, which can be formed by deposition such as chemical vapor deposition or other suitable methods. The phosphorus concentration of the solid dopant source material layer 244 is large enough to effectively form a corresponding anti-puncture structure in a subsequent stage. In some embodiments, solid dopant source material layer 244 is similar to solid dopant source material layer 244 in FIG. 5C . For example, the phosphorus concentration of the solid dopant source material layer 244 is greater than 15 atomic %, such as between 15 atomic % and 30 atomic %. The thickness of the solid dopant source material layer 244 may be between 5 nm and 50 nm.

After forming the liner 232 and filling the dielectric material layer 236 , a chemical mechanical polishing process may be performed to remove these materials on top of the active area of the fin and planarize the upper surface, thereby forming the isolation structure 230B. These materials (such as the liner 232 and the filling dielectric material layer 236) can then be subjected to a selective etching process to recess the isolation structure 230B, and the selective etching process can be any suitable etching process such as dry etching, wet etching, or combination of the above.

Afterwards, a solid dopant source material layer 244 is deposited on the filling dielectric material layer 236, and the deposition method can be chemical vapor deposition or other suitable deposition methods. Afterwards, an etching process can be performed on the solid dopant source material layer 244 to remove the solid dopant source material layer 244 on the sidewall of the fin-shaped active region such as the fin 218A, so that the solid dopant source material layer 234 is lower than the diffusion barrier Layer 204. Diffusion barrier layer 204 thus blocks and limits subsequent diffusion.

As shown in FIG. 6D , a drive process may be performed to drive dopants, such as phosphorous in this example, into the fin-shaped active region, such as fin 218B, to form the anti-puncture structure 246 . The anti-puncture structure 246 can be an n-type doped structure under the diffusion barrier layer 204 . In the embodiment, the driving process can be a thermal annealing process, and the thermal annealing temperature and annealing time can be designed to effectively drive the dopants into the fin-shaped active region such as the fin 218B. The patterned mask 242 can then be removed.

In some embodiments, the diffusion barrier layer 204 forming the anti-puncture structure 246 may have different designs to effectively block the diffusion dopant phosphorus. For example, the design of the composition, concentration, thickness, structure, or combination thereof of the diffusion barrier layer 204 associated with the n-type well 203B may be different from that of the diffusion barrier layer 204 associated with the p-type well 203A. For example, the diffusion barrier layer 204 associated with the n-well 203B may comprise silicon carbide, gallium arsenide, other suitable compositions, or combinations thereof. In this example, the diffusion barrier layer 204 in the p-well region and the n-type well region can be formed separately. For example, the n-well region can be masked by patterning (the same patterned mask used to form the p-type well can be used), followed by epitaxial growth of a diffusion barrier layer of silicon germanium in the p-type well region. A patterned mask can be used to cover the p-well region before or after (the same patterned mask used to form the n-well can be used), followed by epitaxial growth of a diffusion barrier layer of different composition (such as silicon carbide or gallium arsenide) on the In the n-type well area.

As shown in FIGS. 7A-7D , a capping layer 250 may be formed on the sidewalls of the fin-shaped active regions (eg, fins 218A and 218B). In FIGS. 7A to 7D , the isolation structure 230A and the isolation structure 230B and the anti-puncture structures 240 and 246 are shown in different ways to illustrate other structures and components. In some embodiments, the cladding layer 250 may include silicon germanium, and its formation method may be chemical vapor deposition, other suitable deposition methods, or a combination thereof. Capping layer 250 may provide an etch path for subsequent via release.

As shown in FIGS. 8A-8D , gate structures 260 are formed on portions of fins 218A and 218B and isolation structures 230 . The length direction of gate structure 260 is different from (eg, perpendicular to) the length direction of fins 218A and 218B. For example, the gate structures 260 extend along the x-direction and are substantially parallel to each other, having a length defined in the y-direction, a width defined in the x-direction, and a height defined in the z-direction. Gate structures 260 are located on portions of fins 218A and 218B and define channel regions 264 and source/drain regions 262 of fins 218A and 218B. In the X-Z plane, gate structure 260 wraps the top and sidewall surfaces of fins 218A and 218B. In the Y-Z plane, gate structures 260 are located on upper surfaces of respective channel regions 264 of fins 218A and 218B such that gate structures 260 are sandwiched between respective source/drain regions 262 . Gate structures 260 each include a gate region 260-1 to correspond to a portion of an individual gate structure 260 to be provided for an n-type fully-wound gate transistor (thus corresponding to a region across the n-type fully-wrapped gate transistor region), and gate region 260-2 to correspond to a portion of an individual gate structure 260 to be provided for a p-type fully-wound gate transistor (thus corresponding to a portion across the p-type fully-wound gate transistor part of the area). Different gate structures 260 may be disposed in the gate region 260-1 and the gate region 260-2. For example, the metal gate stacks of the gate structure 260 respectively cross over the gate region 260-1 and the gate region 260-2, and may have different configurations in the gate region 260-1 and the gate region 260-2, To optimize the n-type all-around gate transistor (with n-type gate in gate region 260-1) and p-type all-around gate transistor (with p-type gate in gate region 260-1) 2) performance. In summary, the gate region 260-1 can be regarded as the n-type gate region 260-1, and the gate region 260-2 can be regarded as the p-type gate region 260-2.

In FIGS. 8A-8D , gate structures 260 each include a dummy gate stack 265 . In the illustrated embodiment, the width of the dummy gate stack 265 can define the gate length _Lg (in the y-direction) of the gate structure 260, where the gate length _Lg defines the n-type fully wound gate transistor And/or the distance (or length) between the source/drain regions 262 for current (such as carriers, such as electrons or holes) to flow when the p-type all-wound gate transistor is turned on. In some embodiments, the gate length is from about 5 nm to about 250 nm. The gate length can be adjusted to achieve the desired operating speed of the fully wound gate transistor, and/or the desired packing density of the fully wound gate transistor. For example, when a fully-wound gate transistor is turned on, current flows between the source/drain regions of the fully-wound gate transistor. Increasing the gate length increases the distance required for current to flow between the source/drain regions and increases the time required to fully turn on the fully wound gate transistor. Conversely, reducing the gate length reduces the distance required for current to flow between the source/drain regions and reduces the time required to fully turn on the fully wound gate transistor. The smaller gate length enables faster switching of the fully-wound gate transistor, which facilitates faster high-speed operation. Smaller gate lengths also facilitate tighter packaging densities (such as making more full-wound gate transistors in a given area of an IC chip), which can increase the functionality and applications on an IC chip . In the described embodiment, the gate length of one or more gate structures 260 can be set so that the channel length of the fully wound gate transistor is short. For example, the gate length of a short length channel all-wound gate transistor may be from about 5 nm to about 20 nm. In some embodiments, the multi-gate device 200 may include fully wound gate transistors with different gate lengths. For example, the gate length of one or more gate structures 260 can be set so that the channel length of the fully wound gate transistor is medium or long. In some embodiments, the gate length of the medium or long channel length fully-wound gate transistor may be about 20 nm to about 250 nm.

The dummy gate stack 265 includes dummy gates. In some embodiments, dummy gate stack 265 may include a dummy gate dielectric layer. The dummy gate includes a suitable dummy gate material, such as polysilicon. In embodiments where dummy gate stack 265 includes a dummy gate dielectric layer between the dummy gates and fins 218A and 218B, the dummy gate dielectric layer includes a dielectric material such as silicon oxide, high A dielectric material with a dielectric constant, other suitable dielectric materials, or a combination thereof. Examples of high dielectric constant dielectric materials include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, aluminum oxide, hafnium oxide-aluminum oxide, other suitable High dielectric constant dielectric material, or a combination of the above. In some embodiments, the dummy gate dielectric layer includes an interfacial layer (such as silicon oxide) on the fins 218A and 218B, and a high-k dielectric layer on the interfacial layer. The dummy gate stack 265 may include various other layers, such as capping layers, interfacial layers, diffusion layers, barrier layers, hard mask layers, or combinations thereof. For example, the dummy gate stack 265 may further include a hard mask layer on the dummy gate.

The dummy gate stack 265 can be formed by a deposition process, a lithography process, an etching process, other suitable processes, or a combination thereof. For example, a deposition process may be performed to form dummy gate layers over fins 218A and 218B and isolation structures 230 (eg, isolation structures 230A and 230B). In some embodiments, before forming the dummy gate layer, a deposition process is performed to form a dummy gate dielectric layer on the fins 218A and 218B and the isolation structure 230 . In these embodiments, the dummy gate layer is deposited on the dummy gate dielectric layer. In some embodiments, a hard mask layer is deposited on the dummy gate layer. Deposition processes include chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, organometallic chemical vapor deposition, remote plasma chemical vapor deposition, plasma-assisted chemical vapor deposition, Low pressure chemical vapor deposition, atomic layer chemical vapor deposition, atmospheric pressure chemical vapor deposition, electroplating, other suitable methods, or a combination of the above. A lithographic patterning and etching process is then performed to pattern the dummy gate layer (and in some embodiments also pattern the dummy gate dielectric layer and the hard mask layer) to form the dummy gate stack 265, so that The dummy gate stack 265 (including dummy gate layer, dummy gate dielectric layer, hard mask layer, and/or other suitable layers) is arranged as shown in FIGS. 8A-8D . The lithographic patterning process includes coating photoresist (e.g. spin coating), soft bake, aligning mask, exposing, post-exposure bake, developing photoresist, rinsing, drying (e.g. hard bake), other suitable Lithography, or a combination of the above. The etching process includes a dry etching process, a wet etching process, other etching methods, or a combination thereof.

Gate structures 260 may each further include gate spacers 267 adjacent to (eg, along sidewalls of) individual dummy gate stacks 265 . Gate spacers 267 may be formed by any suitable process and may include dielectric materials. The dielectric material may include silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, or oxycarbonitride Silicon. For example, a dielectric layer (including silicon and nitrogen such as a silicon nitride layer) may be deposited on the dummy gate stack 265 and then etched (eg, anisotropic) to form the gate spacers 267 . In some embodiments, the gate spacer 267 includes a multilayer structure such as a first dielectric layer containing silicon nitride and a second dielectric layer containing silicon oxide. In some embodiments, more than one set of spacers such as sealing spacers, compensation spacers, sacrificial spacers, dummy spacers, and/or main spacers may be formed adjacent to dummy gate stack 265 . In these embodiments, the sets of spacers include materials having different etch rates. For example, a first dielectric layer containing silicon and oxygen, such as silicon oxide, can be deposited and etched to form a first set of spacers adjacent to the dummy gate stack 265, and can be deposited and etched containing silicon and nitrogen, such as nitrogen A second dielectric layer of silicon carbide is formed adjacent to the first set of spacers to form a second set of spacers.

As shown in FIGS. 9A-9D , exposed portions of fins 218A and 218B (eg, source/drain regions 262 of fins 218A and 218B not covered by gate structure 260 ) are at least partially removed to form source pole/drain trenches 270 (eg, recesses). In the depicted embodiment, the etch process completely removes semiconductor layer stack 205 and diffusion barrier layer 204 in source/drain regions 262 of fins 218A and 218B to expose the fins in source/drain regions 262 Substrate portions of objects 218A and 218B (eg, p-well 203A and n-type well 203B). The sidewalls of the source/drain trenches 270 can thus be defined by the remaining portion of the semiconductor layer stack 205 (which lies in the channel region 264 below the gate structure 260), and the bottom can be defined by the substrate 202 (such as the source/drain The upper surface of the anti-puncture structure 240 in the p-type well 203A and the upper surface of the anti-puncture structure 246 in the n-type well 203B in the region 262). In some embodiments, the etching process may remove some, but not all, of the semiconductor layer stack 205 such that the bottom of the source/drain trench 270 may be defined by either the semiconductor layer 210 or the semiconductor layer 215 in the source/drain region 262 . In some embodiments, the etching process may further remove some, but not all, of the substrate portions of fins 218A and 218B such that source/drain trenches 270 may extend below the upper surface of substrate 202 . The etching process may include a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In some embodiments, the etching process is a multi-step etching process. For example, the etching process can change the etchant to separate and alternately remove the semiconductor layer 210 and the semiconductor layer 215 . In some embodiments, the etch process parameters are set to selectively etch the semiconductor layer stack with minimal or no etching (or no etching) of the gate structure 260 (eg dummy gate stack 265 and gate spacer 267 ) and/or or isolation structure 230 . In some embodiments, the lithography process described herein may be performed to form a patterned mask layer covering the gate structure 260 and/or the isolation structure 230, and the etching process may use the patterned mask layer as an etching mask. .

As shown in FIGS. 10A to 10D , the inner spacer 275 is formed in the channel region 264 along the sidewall of the semiconductor layer 210 by any suitable process. For example, a first etch process may be performed to selectively etch the semiconductor layer 215 exposed by the source/drain trenches 270, and to minimize (or not etch) the semiconductor layer 210 such that a gap is formed at the gate spacer. Between the substrate 202 and the semiconductor layer 210 and between the semiconductor layers 210 under the object 267. Parts (eg, edges) of the semiconductor layer 210 are thus suspended in the channel region 264 under the gate spacer 267 . In some embodiments, the gap extends partially below the dummy gate stack 265 . The first etching process may be configured to etch the semiconductor layer 215 laterally (eg, along the y direction), so as to reduce the length of the semiconductor layer 215 along the y direction. The first etching process can be a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. Next, a spacer layer is formed by a deposition process on the gate structure 260 and on the structure used to define the source/drain trench 270 (such as the semiconductor layer 215, the semiconductor layer 210, the diffusion barrier layer 204, and the substrate 202), And the deposition process can be chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, organometallic chemical vapor deposition, remote plasma chemical vapor deposition, plasma-assisted chemical vapor deposition deposition, low pressure chemical vapor deposition, atomic layer chemical vapor deposition, atmospheric pressure chemical vapor deposition, other suitable methods, or a combination of the above. The spacer layer partially fills (in some embodiments may completely fill) the source/drain trenches 270 . The deposition process is configured to ensure that the spacer layer fills the gap between the substrate 202 and the semiconductor layer 210 and between the semiconductor layers 210 under the gate spacers 267 . Then a second etching process is performed to selectively etch the spacer layer to form the inner spacer 275 shown in FIGS. Gate spacers 267 . In the illustrated embodiment, the second etching process is an anisotropic etching process (eg, plasma etching) to remove part of the spacer layer in the source/drain trenches 270 . In some embodiments, the spacer layer is removed from the sidewalls of the gate spacers 267 , the sidewalls of the semiconductor layer 210 , the dummy gate stack 265 , and the substrate 202 . The spacer layer (and the inner spacer 275) comprise a material different from that of the semiconductor layer 215 and the gate spacer 267 to achieve the desired etch selectivity during the second etch process and to provide a metal gate isolation and separation from source/drain structures. In this embodiment, the dielectric material of the spacer layer includes silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or carbon nitride. Silicon oxide. In some embodiments, dopants such as p-type dopants, n-type dopants, or combinations thereof may be introduced into the dielectric material such that the spacer layer includes the doped dielectric material.

As shown in FIGS. 11A to 11D , epitaxial source/drain structures are formed in source/drain trenches 270 . In these figures, isolation structures 230A and 230B may be labeled together as isolation structure 230 to simplify the figures. As mentioned above, the isolation structures of the embodiments may include isolation structures 230A and 230B of different compositions. The semiconductor material can be epitaxially grown from the portion of the substrate 202 exposed by the source/drain trench 270 and the semiconductor layer 210 to form an epitaxial source/drain structure 280A corresponding to the n-type fully-wound gate transistor region In the source/drain region 262 of the p-type fully-wound gate transistor region, an epitaxial source/drain structure 280B is formed in the source/drain region 262 corresponding to the p-type fully-wound gate transistor region. The epitaxy process can adopt chemical vapor deposition technology (such as vapor phase epitaxy and/or ultra-high vacuum chemical vapor deposition), molecular beam epitaxy, other suitable epitaxy growth processes, or a combination of the above. The epitaxy process can use gaseous and/or liquid precursors, which can interact with the composition of the substrate 202 and/or the semiconductor layer stack 205 (specifically, the semiconductor layer 210 ). Epitaxial source/drain structures 280A and 280B may be doped with n-type dopants and/or p-type dopants. In some embodiments, for an n-type all-around gate transistor, the epitaxial source/drain structure 280A includes silicon. The epitaxial source/drain structure 280A can be doped with carbon, phosphorus, arsenic, other n-type dopants, or a combination of the above, such as forming a carbon-doped silicon epitaxial source/drain structure, phosphorus-doped silicon Source/drain structure, or epitaxial silicon source/drain structure doped with phosphorus and carbon. In some embodiments, for a p-type all-wound gate transistor, the epitaxial source/drain structure 280B includes silicon germanium or germanium. The epitaxial source/drain structure 280B can be doped with boron, other p-type dopants, or a combination thereof, such as forming a boron-doped SiGe epitaxial source/drain structure. In some embodiments, epitaxial source/drain structure 280A and/or epitaxial source/drain structure 280B include a plurality of epitaxial semiconductor layers, wherein the epitaxial semiconductor layers may include the same or different materials and/or Dopant concentration. In some embodiments, epitaxial source/drain structures 280A and 280B include materials and/or dopants that can achieve desired tensile and/or compressive stresses in individual channel regions 264 . In some embodiments, doping (eg, in-situ doping) the epitaxial source/drain structures 280A and 280B may be doped (eg, in-situ doped) by adding impurities to the source material of the epitaxial process during deposition. In some embodiments, the epitaxial source/drain structures 280A and 280B may be doped by an ion implantation process after the deposition process. In some embodiments, an anneal process (eg, rapid thermal anneal and/or laser anneal) may be performed to activate epitaxial source/drain structures 280A and 280B and/or other source/drain regions (eg, heavily doped source/drain regions and/or lightly doped source/drain regions). In some embodiments, epitaxial source/drain structures 280A and 280B may be formed by separate process sequences, such as when forming epitaxial source/drain structure 280A in an n-type fully-wound gate transistor region. , covering the p-type fully-wound gate transistor region; and when forming the epitaxial source/drain structure 280B in the p-type fully-wrapped gate transistor region, covering the n-type fully-wound gate transistor Transistor area.

As shown in FIGS. 12A to 12D, an interlayer dielectric layer 282 is formed on the isolation structure 230 (such as the isolation structure 230A and 230B), the epitaxial source/drain structures 280A and 280B, and the gate spacer 267. The formation method Can be used for deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, organic metal chemical vapor deposition, remote plasma chemical vapor deposition, plasma-assisted chemical vapor deposition Deposition, low pressure chemical vapor deposition, atomic layer chemical vapor deposition, atmospheric pressure chemical vapor deposition, electroplating, other suitable methods, or a combination of the above. The interlayer dielectric layer 282 is located between adjacent gate structures 260 . In some embodiments, the formation method of the interlayer dielectric layer 282 can be a flowable chemical vapor deposition process, which includes depositing a flowable material (such as a liquid compound) on the multi-gate device 200, and using a suitable technique such as Thermal annealing and/or UV treatment to convert the flowable material into a solid material. For example, the interlayer dielectric layer 282 includes dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, oxide of tetraethoxysilane, phosphosilicate glass, borophosphosilicate glass, low dielectric constant dielectric material, other suitable dielectric materials, or a combination of the above. Exemplary low-k dielectric materials include fluorosilicate glass, carbon-doped silicon oxide, Black Diamond® (available from Applied Materials, Santa Clara, CA), xerogels, aerogels, amorphous fluorinated Carbon, parylene, benzocyclobutene, SiLK (available from Dow Chemical, Midland, Mich.), polyimide, other low-k dielectric materials, or combinations thereof. In the depicted embodiment, the ILD layer 282 is a dielectric layer of a material having a low dielectric constant. The interlayer dielectric layer 282 may include a multi-layer structure having various dielectric materials. In some embodiments, a contact etch stop layer is located between ILD layer 282 and isolation structure 230 , epitaxial source/drain structures 280A and 280B, and gate spacer 267 . The contact etch stop layer includes a material different from the ILD layer 282 , such as a different dielectric material from the ILD layer 282 . For example, when the ILD layer 282 includes a low-k dielectric material, the contact etch stop layer may include silicon and nitrogen such as silicon nitride or silicon oxynitride. After depositing the ILD layer 282 and/or the contact etch stop layer, a chemical mechanical polishing process and/or other planarization processes may be performed until the top or upper surface of the dummy gate stack 265 is exposed. In some embodiments, the planarization process may remove the hard mask layer of the dummy gate stack 265 to expose the underlying dummy gate, such as a polysilicon gate layer, of the dummy gate stack 265 .

The ILD layer 282 may be part of a multilayer interconnect structure on the substrate 202 . The multilayer interconnection structure is electrically coupled to various devices (such as p-type all-around gate transistors and/or n-type all-around gate transistors of the multi-gate device 200, transistors, resistors, capacitors, and/or or inductors) and/or components (such as p-type fully-wound gate transistors and/or n-type fully-wound gate transistor gate structures and/or epitaxial source/drain structures), enabling a variety of devices And/or components may operate according to the desired design specifications of the multi-gate device 200 . A multilayer interconnection structure includes a combination of dielectric layers and conductive layers, such as metal layers, arranged to form various interconnection structures. The conductive layer is configured to form vertical interconnect structures such as contacts and/or vias in the device layer, and/or horizontal interconnect structures such as conductive lines. Vertical interconnect structures typically connect structures in different layers of a multilayer interconnect structure or in different planes. In operation, the interconnect structure is configured to carry signals between devices and/or components of the multi-gate device 200, and/or to pass signals (such as timing signals, voltage signals, and/or ground signals) to the multi-gates Devices and/or components of device 200 .

As shown in FIGS. 13A-13D , dummy gate stack 265 is removed from gate structure 260 to expose fins 218A and 218B in n-type gate region 260-1 and p-type gate region 260-2. Semiconductor layer stack 205 . In the embodiment, the etching process can completely remove the dummy gate stack 265 to expose the semiconductor layer 215 and the semiconductor layer 210 in the channel region 264 . The etching process can be a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In some embodiments, the etching process may be a multi-step etching process. For example, the etching process may vary the etchant to separately remove various layers of the dummy gate stack 265 such as dummy gate layers, dummy gate dielectric layers, and/or hard mask layers. In some embodiments, the etch process is configured to selectively etch dummy gate stack 265 with minimal etching (or no etching) of other structures of multi-gate device 200 such as ILD 282, gate spacers 267. , the isolation structure 230 , the semiconductor layer 215 , and the semiconductor layer 210 . In some embodiments, the lithography process described herein is performed to form a patterned mask layer covering the ILD layer 282 and/or the gate spacers 267, and the etch process uses the patterned mask layer as an etch process. mask.

As shown in FIGS. 14A to 14D , the semiconductor layer 215 of the semiconductor layer stack 205 exposed by the gate trench 284 is selectively removed from the channel region 264 , thereby forming a suspended semiconductor layer such as the channel layer 210 ′ in the channel region 264 . In the illustrated embodiment, the etching process may selectively etch the semiconductor layer 215 while minimally (or not) etching the semiconductor layer 210 . In some embodiments, the etch process may minimally etch (or not etch) gate spacers 267 and/or inner spacers 275 . In the illustrated embodiment, the semiconductor layer 215 has the same composition as the cladding layer 250 (such as SiGe in the illustrated embodiment), and the cladding layer 250 can be selectively removed. In this example, the capping layer 250 provides an etch path to effectively remove the semiconductor layer 215 . In some embodiments, the semiconductor layer 215 and the diffusion barrier layer 204 may have a similar composition (such as silicon germanium in the described embodiment), and the diffusion barrier layer 204 may be selectively removed.

A variety of etching parameters can be adjusted to selectively etch the semiconductor layer 215, such as etchant composition, etching temperature, etching solution concentration, etching time, etching pressure, source power, RF bias voltage, RF bias power, etchant flow rate, other suitable etching parameter, or a combination of the above. For example, the etchant used in the etching process is selected such that the etching rate of the material of the semiconductor layer 215 (silicon germanium in the described embodiment) is higher than that of the material of the semiconductor layer 210 (silicon in the described embodiment). The etch rate, such as etchant, has a high etch selectivity to the material of the semiconductor layer 215 . The etching process can be a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In some embodiments, a dry etching process (such as reactive ion etching) uses a fluorine-containing gas (such as sulfur hexafluoride) to selectively etch the semiconductor layer 215 . In some embodiments, the ratio of fluorine-containing gas to oxygen-containing gas (such as oxygen), etching temperature, and/or RF power can be adjusted to selectively etch SiGe or Si. In some embodiments, the wet etching process uses an etching solution containing ammonium hydroxide and water to selectively etch the semiconductor layer 215 . In some embodiments, the chemical vapor etching process may use hydrogen chloride to selectively etch the semiconductor layer 215 .

Therefore, the gate trench 284 exposes at least one suspended semiconductor layer such as the channel layer 210' in the n-type gate region 260-1 and the p-type gate region 260-2. In the illustrated embodiment, each of the n-type gate region 260-1 and the p-type gate region 260-2 includes vertically stacked four suspended semiconductor layers, such as the channel layer 210', which are used to operate the fully wound gate electrode. The crystal can provide four channels for current flow between individual epitaxial source/drain structures (eg, epitaxial source/drain structure 280A or epitaxial source/drain structure 280B). Therefore, the suspended semiconductor layer can be regarded as the channel layer 210'. The channel layer 210' in the n-type gate region 260-1 is separated by a gap 286A, and the channel layer 210' in the p-type gate region 260-2 is separated by a gap 286B. The channel layer 210' in the n-type gate region 260-1 and the substrate 202 may also be separated by a gap 286A, and the channel layer 210' in the p-type gate region 260-2 may also be separated by a gap 286B from the substrate 202. The space s1 is defined between the channel layers 210' in the n-type gate region 260-1 along the z direction, and the space s2 is defined between the channel layers 210' in the p-type gate region 260-2 along the z direction. . The space s1 and the space s2 respectively correspond to the widths of the gap 286A and the gap 286B. In the above embodiment, the space s1 is approximately equal to the space s2, but the space s1 in the embodiment of the present invention may also be different from the space s2. In some embodiments, both the space s1 and the space s2 are approximately equal to the thickness t1 of the semiconductor layer 215 . However, the space s3 is defined along the z direction between the bottommost channel layer 210' in the n-type gate region 260-1 and the substrate 202 (specifically, the anti-puncture structure 240), and the space s4 is defined along the z direction between p between the bottommost channel layer 210 ′ in the type gate region 260 - 2 and the substrate 202 (specifically, the anti-puncture structure 246 ). Spaces s3 and s4 are different from spaces s1 and s2, respectively. In the illustrated embodiment, the spaces s3 and s4 are larger than the spaces s1 and s2 , respectively, because the thickness of the diffusion barrier layer 204 is greater than the thickness of the semiconductor layer 215 .

In addition, the channel layer 210' in the n-type gate region 260-1 has a length L1 along the x direction and a width w1 along the y direction, and the channel layer 210' in the p-type gate region 260-2 has a length L1 along the y direction. The length L2 along the y direction and the width w2 along the x direction. In the described embodiment, the length L1 is approximately equal to the length L2, and the width w1 is approximately equal to the width w2, but in embodiments of the present invention the length L1 may be different from the length L2 and/or the width w1 may be different from the width w2. In some embodiments, length L1 and/or length L2 may be from about 10 nm to about 50 nm. In some embodiments, width w1 and/or width w2 may be from about 4 nm to about 10 nm. In some embodiments, each of the channel layers 210' has a nanometer size and can be regarded as a nanowire, which generally refers to a suspended channel layer, and metal gates can physically contact at least two sides of the channel layer. In a fully-wound gate transistor, the metal gate can physically contact at least four sides of the channel layer (eg, surround the channel layer). In these embodiments, the vertical stack of suspended channel layers can be considered as a nanostructure, and the process shown in Figures 14A-14D can be considered as a channel nanowire release process. In some embodiments, after removing the semiconductor layer 215, an etching process may be performed to adjust the profile of the channel layer 210' to achieve a desired size and/or a desired shape (such as cylindrical (such as nanowire), rectangular (such as nanowire), etc. rods), sheets (such as nanosheets), or similar shapes). The channel layer 210' (nanowire) of the embodiment of the present invention may also have a sub-nanometer size, depending on the design requirements of the multi-gate device 200.

As shown in FIGS. 15A to 15D , a gate dielectric layer is formed on the multi-gate device 200 , wherein the gate dielectric layer partially fills the gate trench 284 and wraps (surrounds) the gate structure 260 n The channel layer 210' in the p-type gate region 260-1 and the p-type gate region 260-2. In the illustrated embodiment, the gate dielectric layer includes an interface layer 288 and a high-k dielectric layer 290, wherein the interface layer 288 is located between the high-k dielectric layer 290 and the channel layer 210'. In the illustrated embodiment, the interfacial layer 288 and the high-k dielectric layer 290 are partially filled between the channel layer 210 ′ in the n-type gate region 260 - 1 and between the channel layer 210 ′ and the substrate 202 gap 286A, and partially fill the gap 286B between the channel layer 210 ′ and between the channel layer 210 ′ and the substrate 202 in the p-type gate region 260 - 2 . In some embodiments, the interfacial layer 288 and/or the high-k dielectric layer 290 may also be located on the substrate 202 , the isolation structure 230 , and/or the gate spacer 267 . The interfacial layer 288 includes dielectric materials such as silicon oxide, hafnium silicon oxide, silicon oxynitride, other silicon-containing dielectric materials, other suitable dielectric materials, or combinations thereof. The high-k dielectric layer 290 includes a high-k dielectric material, such as hafnium oxide, hafnium silicon oxide, hafnium silicate, hafnium silicon oxynitride, hafnium lanthanum oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium oxide Zirconium, hafnium aluminum oxide, zirconia, zirconia, zirconia silicon oxide, aluminum oxide, aluminum oxide silicon, aluminum oxide, titanium oxide, titanium dioxide, lanthanum oxide, lanthanum silicon oxide, tantalum trioxide, tantalum pentoxide , yttrium oxide, strontium titanate, barium zirconium oxide, barium titanate, barium strontium titanate, silicon nitride, hafnium oxide-aluminum oxide, other suitable dielectric materials with high dielectric constant, or combinations thereof. A high-k dielectric material is generally regarded as a dielectric material having a high dielectric constant (eg, greater than that of silicon oxide, eg, about 3.9). The formation method of the interfacial layer 288 can be any process described herein, such as thermal oxidation, chemical oxidation, atomic layer deposition, chemical vapor deposition, other suitable processes, or a combination thereof. In some embodiments, interfacial layer 288 may have a thickness from about 0.5 nm to about 1 nm. The high-k dielectric layer 290 can be formed by any of the processes described herein, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, oxidation-based deposition processes, other suitable processes, or the above-mentioned combination. In some embodiments, the high-k dielectric layer 290 has a thickness of about 1 nm to about 2 nm.

As shown in FIGS. 16A to 16D , gate material is formed in gate trench 284 to form metal gate stack 360A in gate region 260 - 1 and metal gate stack 360B in gate region 260 - 2 . The gate of the gate stack 360B in the gate region 260 - 2 includes a p-type work function layer 320 and a fill metal layer 330 . The gate may further include other conductive materials such as a cap layer, a barrier layer, or both.

In the gate stack 360A for n-type field effect transistors, the n-type work function layer 310 is formed on the multi-gate device 200, specifically the high-k dielectric in the n-type gate region 260-1 of the gate structure 260. constant dielectric layer 290 . For example, the ALD process can conformally deposit the n-type work function layer 310 on the high-k dielectric layer 290 such that the n-type work function layer 310 has a substantially uniform thickness along the n-type gate The gate trench 284 is partially filled in the gate length direction in the pole region 260 - 1 . In the n-type gate region 260-1, the n-type work function layer 310 is located on the high-k dielectric layer 290 and surrounds the high-k dielectric layer 290, the interface layer 288, and the channel layer 210' . For example, the n-type work function layer 310 is along the sidewall, top, and bottom of the channel layer 210'. In this embodiment, the thickness of the n-type work function layer 310 may partially fill or completely fill in the gap between the channel layer 210' in the n-type gate region 260-1 and between the channel layer 210' and the substrate 202. the rest of the gap 286A. In some embodiments, the thickness of the n-type work function layer 310 is about 1 nm to about 5 nm. The n-type work function layer 310 includes any suitable n-type work function material, such as titanium, aluminum, silver, manganese, zirconium, titanium aluminum, titanium aluminum carbide, titanium aluminum silicon carbide, tantalum carbide, tantalum carbonitride, tantalum nitride Silicon, tantalum aluminum, tantalum aluminum carbide, tantalum aluminum silicon carbide, titanium aluminum nitride, other n-type work function materials, or a combination of the above. In the depicted embodiment, n-type work function layer 310 includes aluminum. For example, the n-type work function layer includes titanium and aluminum, such as titanium aluminum, titanium aluminum carbide, titanium aluminum silicide, or titanium aluminum silicon carbide. The formation method of the n-type work function layer 310 can be changed to another suitable deposition process, such as chemical vapor deposition, physical vapor deposition, high-density plasma chemical vapor deposition, metalorganic chemical vapor deposition, remote electrodeposition, etc. Plasma chemical vapor deposition, plasma assisted chemical vapor deposition, low pressure chemical vapor deposition, atomic layer chemical vapor deposition, atmospheric pressure chemical vapor deposition, spin coating, electroplating, other deposition processes, or a combination of the above.

In the gate stack 360B for p-type field effect transistors, the p-type work function layer 320 is formed on the multi-gate device 200, specifically the high-k dielectric in the p-type gate region 260-2 of the gate structure 260. constant dielectric layer 290 . For example, the atomic layer deposition process can conformally deposit the p-type work function layer 320 on the high-k dielectric layer 290, so that the p-type work function layer 320 has a substantially uniform thickness and partially or completely fills the into the gate trench 284 . In the p-type gate region 260-2, the p-type work function layer 320 is located on the high-k dielectric layer 290 and surrounds the high-k dielectric layer 290, the interface layer 288, and the channel layer 210' . For example, the p-type work function layer 320 is along the sidewall, top, and bottom of the channel layer 210'. The thickness of the p-type work function layer 320 is set to at least fill the gap 286B between the channel layers 210' and between the channel layer 210' and the substrate 202. In some embodiments, the thickness of the p-type work function layer 320 may be about 1 nm to about 10 nm. The p-type work function layer 320 includes any suitable p-type work function material, such as titanium nitride, tantalum nitride, tantalum silicon nitride, ruthenium, molybdenum, aluminum, tungsten nitride, tungsten carbonitride, zirconium silicide, molybdenum Silicide, tantalum silicide, nickel silicide, other p-type work function materials, or combinations thereof. In the illustrated embodiment, the p-type work function layer 320 may include titanium and nitrogen, such as titanium nitride. The formation method of the p-type work function layer 320 can adopt another suitable deposition process, such as chemical vapor deposition, physical vapor deposition, high-density plasma chemical vapor deposition, organic metal chemical vapor deposition, remote plasma chemical vapor deposition, etc. Vapor deposition, low pressure chemical vapor deposition, atomic layer chemical vapor deposition, atmospheric pressure chemical vapor deposition, spin coating, electroplating, other deposition processes, or a combination of the above.

The metal filling layer 330 (or metal matrix layer) is formed on the multi-gate device 200, especially on the n-type work function layer in the n-type gate region 260-1, and on the n-type work function layer in the p-type gate region 260-2. on top of the p-type work function layer. For example, the chemical vapor deposition or physical vapor deposition process can deposit the metal filling layer 330 in the n-type work function layer 310 and the p-type work function layer 320, so that the metal filling layer 330 fills the gate trench 284 and the gap 286A and any remaining portion of 286B, including any remaining portion of gap 286A in n-type gate region 260-1 and any remaining portion of gap 286B in p-type gate region 260-2. Metal fill layer 330 includes a suitable conductive material such as aluminum, tungsten, and/or copper. The metal filling layer 330 may additionally or jointly include other metals, metal oxides, metal nitrides, other suitable materials, or combinations thereof. In some embodiments, before forming the metal filling layer 330 , a barrier layer may be optionally formed on the n-type work function layer and the p-type work function layer, so that the metal filling layer 330 is located on the barrier layer. For example, the atomic layer deposition process can conformally deposit a barrier layer on the n-type work function layer 310 and the p-type work function layer 320, so that the barrier layer has a substantially uniform thickness and partially fills the gate trench 284 and the gate trench 284. Gaps 286A and 286B. The blocking layer includes materials that block and/or reduce diffusion between the gate layers. The formation method of the metal filling layer 330 and/or the barrier layer can be changed to another suitable deposition process such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, high density plasma chemical vapor deposition, metalorganic chemical vapor phase deposition, remote plasma chemical vapor deposition, plasma assisted chemical vapor deposition, low pressure chemical vapor deposition, atomic layer chemical vapor deposition, atmospheric chemical vapor deposition, spin coating, electroplating, other deposition processes, or a combination of the above.

Since the gate stack 360A and the gate stack 360B have different compositions (specifically, different work function materials), the gate stack 360A and the gate stack 360B can be formed by various suitable procedures. In some embodiments, gate stack 360A and gate stack 360B may be formed separately. For example, when the gate stack 360A is formed in the n-type gate region 260-1, the p-type gate region 260-2 may be covered by a patterned mask. Next, when the gate stack 360B is formed in the p-type gate region 260-2, another patterned mask may cover the n-type gate region 260-1. In some embodiments, the above order can be reversed, that is, the gate stack 360B is formed first, and then the gate stack 360A is formed. In some other embodiments, gate stack 360A and gate stack 360B may be formed together. For example, n-type work function material can be deposited in n-type gate region 260-1 and p-type gate region 260-2, and then removed from p-type gate region 260-2 by lithography and etching processes. type work function layer. A p-type work function material is then deposited. After depositing metal fill layer 330 in gate trench 284 and gaps 286A and 286B, a chemical mechanical polishing process may be performed to remove excess fill metal and planarize the top surface.

Thus the multi-gate device 200 shown in FIGS. 16A to 16D is formed. In the multi-gate device 200 , the anti-puncture structure 240 is formed in the fin-shaped active region, such as the fin 218A, and under the gate stack 360A. Specifically, the anti-puncture structure 240 spans from the upper surface to the lower surface of the isolation structure 230A. In particular, a part of the gate stack 360A is sandwiched between the anti-puncture structure 240 and the bottom channel layer 210', and the thickness of this part of the gate stack 360A is greater than that of other gate stacks 360A sandwiched between the adjacent channel layers 210'. part thickness. This is because the thickness of the diffusion barrier layer 204 is different from the thickness of the semiconductor layer 215, as described above. In addition, the isolation structure 230A includes three layers such as a liner 232 , a solid dopant source material layer 234 (containing p-type dopants), and a filling dielectric material layer 236 . Similarly, the isolation structure 230B includes a liner 232 , a solid dopant source material layer 244 (containing n-type dopants), and a filling dielectric material layer 236 . The isolation structure 230A or 230B may have a structure different from that shown in FIGS. 17A to 17D . Specifically, the solid dopant source material layer 234 or 244 may be the topmost of the isolation structure 230A or 230B.

The multi-gate device 200 can be fabricated continuously. For example, various contacts can be formed to facilitate operation of n-type all-around gate transistors and p-type all-around gate transistors. For example, one or more ILD layers (similar to ILD layer 282 ) and/or contact etch stop layers may be formed over substrate 202 , specifically between ILD layer 282 and gate structure 260 . superior. Contacts may then be formed in the ILD layer 282 and/or in the ILD layer above the ILD layer 282 . For example, the contacts are respectively electrically and/or physically coupled to the gate structure 260, and the contacts may be respectively electrically and/or physically coupled to the n-type all-wound gate transistor and the p-type all-wound gate transistor. Source/drain regions of gate transistors (specifically, epitaxial source/drain structures 280A and 280B). The contacts include conductive material such as metal. Metals include aluminum, aluminum alloys (such as aluminum, silicon, and copper alloys), copper, copper alloys, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicide, other suitable metals, or the above combination. The metal silicide may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or combinations thereof. In some embodiments, the interlayer dielectric layer on the interlayer dielectric layer 282 and the contact (such as a contact extending through the interlayer dielectric layer 282 and/or other interlayer dielectric layers) is the above-mentioned multilayer interconnection. part of the structure.

The invention provides many different embodiments. The exemplary method forms a multi-gate device having a breakdown-resistant structure, and the method includes forming an isolation structure having a solid dopant source material layer corresponding to a dopant, forming a diffusion barrier layer on the substrate to prevent the dopant from diffusing into the channel, and A thermal process is performed to drive dopants into the fin-shaped active region to form a breakdown-resistant structure. The disclosed method has advantages such as process compatibility, cost reduction, and other advantages such as enhanced device performance.

An embodiment of the invention provides a method for forming a semiconductor structure. The method includes forming a diffusion barrier layer on a semiconductor substrate; forming a plurality of channel material layers on the diffusion barrier layer; patterning the semiconductor substrate, the channel semiconductor layer, and the diffusion barrier layer to form trenches in the semiconductor substrate, thereby defining an active region and adjacent to the trench; filling the trench with a dielectric material layer and a solid dopant source material layer containing dopant; and driving the dopant from the solid dopant source material layer into the active region, thereby forming an anti-breakdown structure in the trench. in the active zone.

In some embodiments, the step of forming the diffusion barrier layer includes epitaxially growing a semiconductor material layer on the semiconductor substrate; and the step of forming the channel material layer includes epitaxially growing a plurality of first semiconductor films and a plurality of second semiconductor films arranged alternately A film is on the diffusion barrier layer, wherein the composition of the first film of semiconducting material is different from that of the second film of semiconducting material.

In some embodiments, the first semiconductor material film is a silicon film; the second semiconductor material film is a silicon germanium film; and the semiconductor material layer is a silicon germanium layer and has a composition different from that of the second semiconductor material film.

In some embodiments, the germanium concentration of the layer of semiconductor material is greater than the germanium concentration of the second film of semiconductor material.

In some embodiments, the thickness of the layer of semiconductor material is greater than the respective thicknesses of the second films of semiconductor material.

In some embodiments, the germanium concentration of the semiconductor material layer is between 25 atomic % and 50 atomic %, and the thickness is between 10 nm and 15 nm.

In some embodiments, the method further includes implanting before patterning the semiconductor substrate to introduce p-type dopants into the semiconductor substrate in the first region, thereby forming p-type doped wells in the first region.

In some embodiments, after the step of driving the dopant from the solid doped source material layer to the active region, further comprising: forming a dummy gate stack on the channel material layer; forming a source/drain structure on the dummy gate on the side of the electrode stack; form an interlayer dielectric layer on the channel material layer; remove the dummy gate stack to form a gate trench; selectively remove the second semiconductor material film to form a suspended channel in the anti-breakdown structure and forming a metal gate stack in the gate trench to extend and cover the suspended channel.

In some embodiments, the layer of solid dopant source material containing the dopant is a layer of borosilicate glass; and the step of driving the dopant from the layer of solid dopant source material to the active region includes temperature-controlled A thermal anneal process greater than 900° C. to drive boron from the borosilicate glass layer into a portion of the active region below the diffusion barrier layer.

In some embodiments, the step of filling the trench with the dielectric material layer and the dopant-containing solid dopant source material layer includes: forming a dielectric liner in the trench; depositing a borosilicate glass layer in the trench on the dielectric liner; then depositing a dielectric material layer on the borosilicate glass layer in the groove; and performing a chemical mechanical polishing process on the dielectric material layer.

In some embodiments, the step of filling the trench with the dielectric material layer and the solid dopant source material layer containing the dopant includes: forming a dielectric liner in the trench; depositing the dielectric material layer in the trench On the dielectric liner; performing a chemical mechanical polishing process on the dielectric material layer to form a shallow trench isolation structure; recessing the shallow trench isolation structure to form a fin structure in the active area; and then depositing borosilicate The glass layer is on the shallow trench isolation layer.

Another embodiment of the invention provides a method for forming a semiconductor structure. The method includes forming a diffusion barrier layer on the semiconductor substrate; forming a channel material layer on the diffusion barrier layer; patterning the semiconductor substrate, the channel material layer, and the diffusion barrier layer to form trenches in the semiconductor substrate, and then defining fin-shaped active regions to be adjacent to the trench; filling the trench with a dielectric material layer to form an isolation structure; recessing the isolation structure to form a fin structure in the fin active region; and then depositing a borosilicate glass layer on the isolation structure superior.

In some embodiments, the method further includes performing an etching process on the borosilicate glass to remove a portion of the borosilicate glass layer on the sidewall of the fin-shaped active region.

In some embodiments, the method further includes driving boron from the borosilicate glass layer to the fin structure by a thermal annealing process, thereby forming a breakdown resistant structure in the active region of the fin, wherein the breakdown resistant structure is located under the diffusion barrier layer.

Some embodiments further include forming a dummy gate stack on the channel material layer after driving boron from the borosilicate glass layer to the fin structure; forming source/drain structures on the sides of the dummy gate stack ; forming an interlayer dielectric layer on the channel material layer; removing the dummy gate stack to form a gate trench; selectively removing the second semiconductor material film to form a suspended channel on the breakdown-resistant structure; and forming a metal gate The metal gate is stacked in the gate trench, wherein the metal gate extends to cover the suspended channel.

In some embodiments, the step of forming the diffusion barrier layer includes epitaxially growing a semiconductor material layer on the semiconductor substrate; and the step of forming the channel material layer includes epitaxially growing a plurality of first semiconductor material films and a plurality of second semiconductor material films alternately arranged The semiconductor material film is on the diffusion barrier layer, wherein the first semiconductor material film is a silicon film, the second semiconductor material film is a silicon germanium film, the semiconductor material layer is a silicon germanium layer, and the concentration of germanium in the semiconductor material layer is greater than that of the second semiconductor material film germanium concentration, and the thickness of the semiconductor material layer is greater than the respective thicknesses of the second semiconductor material films.

Another embodiment of the present invention provides a semiconductor structure. The semiconductor structure includes an active region located in the semiconductor substrate and spanning from the first shallow trench isolation structure to the second shallow trench isolation structure; a plurality of channel layers of the first conductivity type located on the semiconductor substrate and spanning the first shallow trench isolation structure; between the sidewall and the second sidewall; a gate stack formed on the semiconductor substrate and extending to cover each channel layer; and an anti-breakdown structure of a first conductivity type containing a first dopant, wherein the anti-breakdown structure is located at the gate Under the stack, wherein the first shallow trench isolation structure and the second shallow trench isolation structure each include a solid dopant source material layer containing a first dopant, and wherein the first shallow trench isolation structure and the second shallow trench isolation The upper surface of the structure is lower than the upper surface of the breakdown resistant structure.

In some embodiments, the first dopant is boron; and the solid dopant source material layer is borosilicate glass.

In some embodiments, the solid dopant source material layer exists in the top of the first STI structure and the second STI structure, but does not exist in the first STI structure and the second STI structure. in the bottom of the isolation structure.

In some embodiments, the solid dopant source material layer extends laterally in the bottom of the first STI structure and the second STI structure, and further extends upwards in the first STI structure and the second STI structure. In the edge part of the groove isolation structure.

The features of the above-mentioned embodiments are helpful for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and change other processes and structures to achieve the same purpose and/or the same advantages of the above-mentioned embodiments. Those skilled in the art should also understand that these equivalent replacements do not depart from the spirit and scope of the present invention, and can be changed, replaced, or modified without departing from the spirit and scope of the present invention.

B-B', C-C', D-D': section line L _g : gate length L1, L2: length s1, s2, s3, s4: space t1, t2: thickness w1, w2: width 100: method 102, 104, 106, 108, 110, 112, 114, 116, 118.120, 122, 124, 126, 132, 134, 136, 138, 140, 142, 144, 146, 148, 150: step 200: multi-gate device 202: substrate 203A: p-type well 203B: n-type Well 204: diffusion barrier layer 205: semiconductor layer stack 210, 215: semiconductor layer 210': channel layer 218A, 218B: fin 230, 230A, 230B: isolation structure 232: liner 234, 244: solid dopant source material layer 236: filled dielectric material layer 238, 242: patterned mask 240, 246: anti-breakdown structure 250: cladding layer 260: gate structure 260-1,260- 2: Gate region 262: Source/drain region 264: Channel region 265: Dummy gate stack 267: Gate spacer 270: Source/drain trench 275: Inner spacer 280A, 280B: Epitaxy Source/drain structure 282: interlayer dielectric layer 284: gate trenches 286A, 286B: gap 288: interface layer 290: high dielectric constant dielectric layer 310: n-type work function layer 320: p-type work function Layer 330: Fill Metal Layer 360A, 360B: Gate Stack

1A, 1B, 1C, and 1D are flowcharts of methods for fabricating a multi-gate device in various embodiments of the present invention. Figures 2A to 4A, Figures 2B to 4B, Figures 2C to 4C, and Figures 2D to 4D are various embodiments of the present invention, part or whole of a multi-gate device in various manufacturing stages (such as the manufacturing related to the method in Figure 1A stage) part of the schema. 5A, 5B, 5C, and 5D are partial diagrams of parts or the whole of a multi-gate device at various stages of fabrication, such as those associated with the method of FIG. 1B, in various embodiments of the present invention. 6A, 6B, 6C, and 6D are partial diagrams of parts or the whole of a multi-gate device at various stages of fabrication, such as those associated with the method of FIG. 1C, in various embodiments of the present invention. Figures 7A to 17A, Figures 7B to 17B, Figures 7C to 17C, and Figures 7D to 17D are various embodiments of the present invention, part or the whole of the multi-gate device is in various manufacturing stages (such as the manufacturing related to the method in Figure 1D stage) part of the schema.

100: method

102, 104, 106, 108, 110, 112: steps

Claims (1)

A method of forming a semiconductor structure, comprising: forming a diffusion barrier layer on a semiconductor substrate; forming a plurality of channel material layers on the diffusion barrier layer; patterning the semiconductor substrate, the channel semiconductor layers, and the diffusion barrier layer to form a trench in the semiconductor substrate, thereby defining an active region adjacent to the trench; filling the trench with a layer of dielectric material and a layer of solid dopant source material containing a dopant; and The dopant is driven from the solid dopant source material layer into the active region, thereby forming an anti-breakdown structure in the active region.

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