TW202318152A - Power management based on limiting hardware-forced power control - Google Patents

Abstract

Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Specifically, a power manager circuit in an integrated circuit (e.g., a system on a chip) may modify power budgets for various components in the integrated circuit to reduce the amount of power control caused by external signaling that indicates a voltage regulator overload (e.g., a voltage droop).

Description

Power Management Based on Limited Hardware Forced Power Control

Embodiments described herein relate to power management in integrated circuits, and more specifically, to trigger circuits for controlling power delivery to integrated circuits.

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FIG. 1 is a block diagram of one embodiment of a system including a system-on-chip (SOC) 110 coupled to memory 120 and a power management unit (PMU) 140 . PMU 140 may be configured to supply power to SOC 110 and other components that may be included in the system, such as memory 120 . For example, PMU 140 may be configured to generate one or more supply voltages to power SOC 110 and may be further configured to generate supply voltages for other components of the system not shown in FIG. 1 . Additionally, PMU 140 (or accompanying circuitry coupled to PMU 140 ) can be configured to monitor the supply voltage and detect transient undervoltage conditions, overcurrent conditions, power limit conditions, temperature conditions, or Other conditions for erroneous operation. When such conditions occur (eg, the electrical load of SOC 110 exceeds the capacity of PMU 140 ), PMU 140 may assert a trigger output signal to SOC 110 . As an example, for a power limit condition, power may be averaged over different power constants with different power limits for different time constants (e.g., a short averaging time constant may have a higher limit than a longer time averaging time constant), And triggers may be established based on exceeding any of the power limits for different time constants. In some embodiments, a power limit may be imposed using a current squared (I ² ) RMS constraint.

In various embodiments, the trigger output signal may be communicated to the SOC 110 via a wired transmission (eg, a hardwired interface between two components) or a serial communication interface (eg, a two-way communication interface). Limited trigger signaling may be provided to global power control circuitry 130 incorporated into SOC 110, while serial trigger signaling may be provided directly to processor engines such as, via serial controller 124 and/or communication fabric 170 processor cluster 150 , GPU 160 , or peripheral device 180 ) simultaneously receive the trigger input. Serial controller 124 may be a system power management interface (SPMI) that provides bi-directional communication between the processor engine and PMU 140 . Although the serial controller 124 is shown in FIG. 1 as communicating with the processor engines through the communication fabric 170, in various embodiments, the serial controller 124 may communicate directly with one or more of the processor engines. Wired trigger signaling and serial trigger signaling are discussed in more detail below for the embodiment of the PMU 140 depicted in FIG. 2 . Although the SOC embodiment is used as an example herein, systems including multiple integrated circuits coupled to a communication fabric can be used in other embodiments.

As the name implies, the components of the SOC 110 may be integrated onto a single semiconductor substrate as an integrated circuit "chip." In the depicted embodiment, components of SOC 110 include at least one processor cluster 150, at least one graphics processing unit (GPU) 160, one or more peripheral components such as peripheral component 180 (more briefly, "peripheral device"), at least one memory controller 122, global power control circuit 130, and communication fabric 170. Components 150, 160, 180, 122, and 130 may all be coupled to communication fabric 170. Memory controller 122 is in Can be coupled to the memory 120 during use. In some embodiments, there may be more than one memory controller coupled to the corresponding memory. In such embodiments, the memory address space can span the memory in any desired manner. In the illustrated embodiment, processor cluster 150 may include a plurality of processors (P) 152. Processors 152 may form the central processing unit (CPU) of SOC 110. Processor cluster 150 may further includes one or more processors (e.g., coprocessor 154 in FIG. 1 ) that may be optimized for a subset of the processor's instruction set and that may be used by processor 152 to execute instructions in the subset. For example, Coprocessor 154 may be a matrix engine optimized to perform vector and matrix operations.

As noted above, processor cluster 150 may include one or more processors 152 , which may act as CPUs for SOC 110 . The system's CPU includes processor(s) that execute the system's main controlling software, such as an operating system. Usually, the software executed by the CPU can control other components of the system during use, so as to realize desired functions of the system. The processor can also execute other software, such as application programs. Applications can provide user functionality and can rely on the operating system for lower-level device control, scheduling, memory management, and so on. Therefore, the processor can also be called an application processor.

In general, a processor may include any circuitry and/or microcode configured to execute instructions defined in the instruction set architecture implemented by the processor. A processor may encompass a processor core implemented on an integrated circuit with other components as a system-on-chip (SOC 110 ) or other levels of integration. A processor may further encompass discrete microprocessors, processor cores, and/or microprocessors integrated into multi-chip module implementations, processors implemented as multiple integrated circuits, and the like.

Memory controller 122 may generally include circuitry for receiving memory operations from other components of SOC 110 and for accessing memory 120 to complete the memory operations. Memory controller 122 can be configured to access any type of memory 120 . For example, memory 120 may be static random access memory (SRAM), dynamic RAM (DRAM), such as synchronous DRAM (SDRAM), including double data rate (DDR, DDR2, DDR3, DDR4, etc.) DRAM. Can support low-power/mobile versions of DDR DRAM (eg, LPDDR, mDDR, etc.). Memory controller 122 may include queues for memory operations, which are used to sequence (and possibly reorder) and commit operations to memory 120 . The memory controller 122 may further include a data buffer to store write data waiting to be written to the memory and read data waiting to be returned to the source of the memory operation. In some embodiments, the memory controller 122 may include a memory cache to store recently accessed memory data. In SOC implementations, for example, memory caching can reduce power consumption in the SOC by avoiding re-accessing data from memory 120 if the data is expected to be accessed again soon. In some cases, a memory cache may also be called a system cache, as opposed to a private cache that only serves certain components, such as an L2 cache or a cache in a processor. Additionally, in some embodiments, the system cache need not be located within the memory controller 122 .

Peripherals 180 may be any set of additional hardware functions included in SOC 110 . For example, peripherals 180 may include video peripherals such as image signal processors, video encoders/decoders, scalers, rotators, fusion controller, display controller, etc. Peripherals may include audio peripherals such as microphones, speakers, interfaces to microphones and speakers, audio processors, digital signal processors, mixers, and the like. Peripheral devices may include interface controllers for various interfaces external to SOC 110, including interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect (PCI) including PCI Express (PCIe), Serial Row and parallel ports, etc. Interconnections to external devices are depicted by dashed arrows in FIG. 1 , which extend outside of the SOC 110 . Peripherals may include networked peripherals, such as media access controllers (MACs). Any set of hardware can be included.

Communication fabric 170 may be any communication interconnect and protocol used to communicate between components of SOC 110 . Communication fabric 170 may be bus-based, including shared bus configurations, cross bar configurations, and hierarchical buses with bridges. Communication fabric 170 may also be packet-based, and may be hierarchical in bridge, cross-wire, point-to-point, or other interconnections.

Note: The number of components of SOC 110 (and the number of subcomponents of those shown in Figure 1, such as processors 152 in each processor cluster 150) may vary from embodiment to embodiment. Furthermore, the number of processors 152 in one processor cluster 150 may be different than the number of processors 152 in another processor cluster 150 when multiple processor clusters are included. There may be a greater or lesser number of components/subcomponents than shown in FIG. 1 .

As described herein, PMU 140 may be configured to assert one or more trigger signals upon detection of various conditions that may result in erroneous operation in SOC 110 . FIG. 2 is a block diagram of one embodiment of the PMU 140 . In the depicted embodiment, PMU 140 includes voltage regulator 142 and power delivery trigger circuit 144 . In some embodiments, the power delivery trigger circuit 144 is configured to monitor the supply voltage in the voltage regulator 142 and provide a trigger signal(s) when a transient undervoltage condition is detected in the voltage regulator. For example, power delivery trigger circuit 144 may provide a trigger signal when the supply voltage provided by voltage regulator 142 drops below a threshold (eg, an undervoltage threshold).

FIG. 3 is a block diagram of another embodiment of the PMU 140 . In the depicted embodiment, PMU 140 includes a voltage regulator 142 , a wired power delivery trigger circuit 144 , and a serial power delivery trigger circuit 146 . As shown in FIG. 3 , PMU 140 may include multiple voltage regulators 142 (eg, voltage regulators 142A, 142B, 142C) connected to sets of power delivery trigger circuits (eg, wired power delivery trigger circuits 144A, 144B , 144C and serial power delivery trigger circuits 146A, 146B, 146C). In PMU 140, any number of voltage regulators 142, wired power delivery trigger circuits 144, and serial power delivery trigger circuits 146 are contemplated. Voltage regulators 142A, 142B, 142C may represent different voltage regulators providing different supply voltages to different portions of SOC 110 . For example, voltage regulator 142A may provide a supply voltage to processor cluster 150 , while voltage regulator 142B provides a supply voltage to GPU 160 . In various embodiments, the voltage regulators 142A, 142B, 142C may be part of a hierarchical power delivery system (eg, the hierarchical power delivery system 900 described in FIG. 9 ).

As noted above, wired power delivery trigger circuit 144 may be routed directly to SOC 110 (eg, global power control circuit 130 in SOC 110 ), while serial power delivery trigger circuit 146 may be routed via a serial communication interface (eg, SPMI). Coupled to SOC 110 (eg, communication fabric 170 in SOC 110 ). In various embodiments, the serial power transfer trigger circuit 146 includes a SPMI for communicating with the SOC 110 (eg, via the serial controller 124 ). Thus, serial power delivery trigger circuit 146 may be capable of two-way communication with SOC 110 , while wired power delivery trigger circuit 144 provides unidirectional communication from wired power delivery trigger circuit 144 to SOC 110 .

In some embodiments, wired power delivery trigger circuit 144 and serial power delivery trigger circuit 146 are configured to monitor one or more conditions (e.g., voltage, current, or temperature) in voltage regulator 142 and to Trigger signal(s) are provided when conditions exceed various thresholds as determined by the power delivery trigger circuit. Various embodiments of fast (on the order of nanoseconds) and slow (on the order of microseconds or milliseconds) responses may be implemented in either the wired power transfer trigger circuit 144 or the serial power transfer trigger circuit 146 . In some embodiments, fast response is implemented in the wired power delivery trigger circuit 144 to take advantage of the high transmission speed of wired connections. Conversely, slow response can be implemented in the serial power delivery trigger circuit 146 because the serial connection provides a signal transmission speed of about the slow response.

In various embodiments, a serial connection between the serial power transfer trigger circuit 146 and the SOC 110 allows the condition to be polled by the SOC 110 . For example, when the operation of the SOC 110 changes or another event occurs, the SOC 110 may provide requests for conditional information. The SOC 110 can provide the request query to the serial power delivery trigger circuit 146 through the serial communication interface. The serial power delivery trigger circuit 146 may then provide a conditional status (eg, the conditional value is above or below a threshold) via a trigger signal output back to the SOC 110 through the serial communication interface.

In some embodiments, the trigger signal is provided when the electrical load experienced in the voltage regulator 142 exceeds a threshold (eg, the voltage drops below an undervoltage threshold). Voltage threshold comparisons may be implemented, for example, using voltage sensing elements such as voltage-based comparator circuits. The voltage-based comparator circuit may be a fast response circuit typically used in wired power delivery trigger circuit 144 . In some embodiments, a trigger signal is provided when the current experienced in the voltage regulator 142 exceeds a current threshold (eg, when the current rises above a predefined current limit). Current threshold comparisons may be implemented by output current comparator circuits (eg, current sensing elements), which may be used in fast response circuits such as in wired power delivery trigger circuit 144 . In some contemplated embodiments, current sensing capabilities are implemented to monitor current conditions (eg, to determine if the current exceeds an over-current threshold). Current sensing capabilities may include, for example, filtered current sensing capabilities, which may be implemented in the slow response serial power transfer trigger circuit 146 . In some embodiments, a trigger signal is provided when the temperature experienced in voltage regulator 142 exceeds a predefined temperature in order to prevent overheating in PMU 140 . Temperature sensing, which is generally slow to respond to the serial power delivery trigger circuit 146, can be implemented in a temperature sensing scheme.

The description above provides example embodiments of various response schemes for the different conditions described herein. It should be understood, however, that the location and number of response schemes between voltage regulator 142 , wired power delivery trigger circuit 144 , and serial power delivery trigger circuit 146 may vary for desired operation of PMU 140 and SOC 110 . For example, in various embodiments, both wired power transfer trigger circuit 144 and series power transfer trigger circuit 146 may be implemented to monitor similar operating conditions (eg, voltage or current) in the same voltage regulator 142 . In such embodiments, the wired power delivery trigger circuit 144 provides a fast response time, while the serial power delivery trigger circuit 146 provides a slower response.

In some embodiments, wired power delivery trigger circuit 144 and serial power delivery trigger circuit 146 can provide different capabilities in power management based on different response times and where trigger signals are sent in SOC 110 . As an example, as shown in FIGS. 1 and 3 , the wired power delivery trigger circuit 144 provides a wired trigger signal to the global power control circuit 130 , and the serial power delivery trigger circuit 146 provides a serial trigger signal to the communication fabric 170 , and Next to components such as processor cluster 150 or GPU 160 . As described herein, global power control circuit 130 is capable of providing fast response and fast clock rate control in order to prevent failure of functions in SOC 110 or PMU 140 . However, the serial trigger signal provided by serial power delivery trigger circuit 146 may be implemented by components in SOC 110 (eg, processor cluster 150 or GPU 160 ) to determine more precise control for the operation of SOC 110 ( For example, by using dynamic voltage and frequency control in components of the SOC 110).

Thus, in some embodiments, the threshold for the wired power delivery trigger circuit 144 is closer to the point of functional failure of the SOC 110 or PMU 140 than the threshold for the serial power delivery trigger circuit 146 . Thresholds for wired power delivery trigger circuit 144 may be closer to the point of functional failure of SOC 110 or PMU 140 to provide a quick response when operating conditions may indicate a functional failure of SOC 110 or PMU 140 . Conversely, a slower response may be more appropriate when the SOC 110 or PMU 140 is farther from the point of failure. As an example, the voltage threshold for wired power delivery trigger circuit 144 may be closer to an undervoltage causing a malfunction in SOC 110 or PMU 140 than the voltage threshold for serial power delivery trigger circuit 146 ( For example, the finite voltage threshold is lower than the string voltage threshold). Therefore, if the voltage begins to drop slowly, the string voltage threshold will cross first, and the SOC 110 may respond to the string trigger signal from the string power delivery trigger circuit 146 before reaching the limited voltage threshold. However, if the voltage drops rapidly, even if the wired voltage threshold is reached after the string voltage threshold, the fast response provided by the wired power delivery trigger circuit 144 and the global power control circuit 130 may occur before the SOC 110 has the opportunity to respond to the string trigger. before the signal. The response to the wired signal may remain functional until a serial trigger signal read is performed later and the SOC 110 reacts to the read. Such a hierarchical response scheme may provide improved performance of the SOC 110 and PMU 140 while preventing functional failures in the device.

In some embodiments, the response scheme is based on a hierarchy of hierarchies in the power delivery system (eg, hierarchies between voltage regulators 142A, 142B, 142C). For example, voltage regulator 142A may have a higher hierarchy than voltage regulator 142B. Accordingly, the trigger signal from wired power delivery trigger circuit 144A or serial power delivery trigger circuit 146A may have a higher hierarchy (eg, higher priority order). Furthermore, in a hierarchical power delivery system, a power curtailment response (eg, power curtailment of a component or power supply) can be triggered in one component by a trigger signal for another component. For example, a trigger signal from wired power delivery trigger circuit 144B or serial power delivery trigger circuit 146B may trigger power reduction in voltage regulator 142A.

In various embodiments, one or more of the voltage regulators 142 are coupled to a battery pack (or other power supply unit) to provide power to the SOC 110 . In some embodiments, one or more of the wired power transfer trigger circuit 144 or the serial power transfer trigger circuit 146 is configured to monitor the voltage in the battery pack. Directly monitoring the voltage in the battery pack can help prevent temporary low voltages in the SOC 110 resulting from low battery state of charge.

Returning to FIG. 1 , in various embodiments, global power control circuit 130 receives trigger signal(s) from PMU 140 . When an event associated with the trigger signal occurs, the global power control circuit 130 may respond by rapidly reducing the clock frequency at which the components operate to prevent malfunctions in the SOC 110 or the PMU 140 . In accordance with the present disclosure, an integrated circuit (eg, SOC 110 ) may include a plurality of components (eg, processor cluster 150 , GPU 160 , peripherals 180 ) coupled to the plurality of components (via communication fabric 170 ) and global power control circuit 130.

FIG. 4 is a block diagram of one embodiment of the global power control circuit 130 . In the illustrated embodiment, the global power control circuit 130 includes a trigger logic circuit 132 and a rate control circuit 134 . Global power control circuit 130 receives trigger signal(s) from PMU 140 . In some embodiments, the trigger signal is an asynchronous trigger signal with respect to the clock cycle of the SOC 110 . For example, a trigger signal may be received by global power control circuit 130 at any time during a clock cycle of SOC 110 .

In various embodiments, trigger logic circuit 132 receives a trigger signal from PMU 140 and determines a power reduction signal based on the received trigger signal. The power reduction signal may be, for example, a synchronization signal provided to one or more components in the SOC 110 at the clock rate of the SOC 110 . One or more components may then implement power reduction or metering based on the received power reduction signal. In various embodiments, the trigger logic circuit 132 includes a combination of enable, hysteresis, and synchronizer to convert the asynchronous trigger signal into a synchronous power reduction signal.

Examples of techniques implemented by trigger logic 132 to provide the power reduction signal include clock dithering, clock gating, selective pulse removal, clock division, and the like. These techniques are effective in allowing the SOC 110 to continue to operate error-free as the reduced clock frequency compensates for slower evaluating transistors at reduced voltage. For example, dividing the clock frequency by 2 (relatively fast operation) degrades performance by about ½. In some cases, the performance reduction may be even greater (eg, 75% or greater) to ensure error-free operation. Global power control circuit 130 may thus be coupled to various components of SOC 110, such as processor 152 or GPU 160, or at least may be coupled to the clock resources of various components (e.g., phase-locked loop (PLL), delay-locked loop ( DLL), clock divider, clock gate, clock tree, etc.) to implement frequency reduction that can help ensure error-free (or correct) operation during undervoltage operation.

While the trigger logic circuit 132 provides a relatively fast power reduction response to the trigger signal from the PMU 140 , a faster response time for reducing the clock frequency may be desired in various embodiments of the SOC 110 . For example, in embodiments where SOC 110 is a multi-die SOC (e.g., SOC 110 has multiple die operating as a single die), faster response times may be required to reduce clock frequency to prevent functional failure due to the large number of Parallel trading may overrun the PMU 140.

In various embodiments, the rate control circuit 134 in the global power control circuit 130 implements a faster response time to trigger signals received by the global power control circuit. Rate control circuit 134 may include, for example, fabric or other logic to control the clock rate in SOC 110 based on a received trigger signal. For example, rate control circuit 134 may rapidly reduce the clock rate in communication fabric 170 in response to receiving a trigger signal. As shown in FIG. 4 , rate control circuit 134 may receive selected trigger signals from PMU 140 . In certain embodiments, the selected trigger signal is provided to the rate control circuit 134 using selected wiring in place between the power delivery trigger circuit 144 (shown in FIGS. 2 and 3 ) and the rate control circuit. For example, the wiring to the rate control circuit 134 may branch off from the wiring between the selected power delivery trigger circuit 144 and the trigger logic circuit 132 . Accordingly, rate control circuit 134 may receive selected trigger signals from selected power delivery circuits 144 asynchronously. In one contemplated embodiment, the selected trigger signal is received from one or more voltage regulators 142 in PMU 140 that supplies power to communication fabric 170 .

In some embodiments, rate control circuit 134 controls the clock rate of SOC 110 or one or more components of SOC 110 based on receiving a selected trigger signal. For example, rate control circuit 134 may decrease the clock rate based on receiving a selected trigger signal. Since the selected trigger signal is received asynchronously (from a clock cycle of SOC 110 ), rate control circuit 134 is able to asynchronously reduce the clock rate rather than waiting for another clock cycle before scaling down power in SOC 110 . Reducing the clock rate reduces power consumption in SOC 110 , thereby preventing failure of PMU 140 or functions in SOC 110 . The rate control circuit 134 provides a fast, asynchronous response time for reducing the clock rate (eg, within nanoseconds) when a trigger signal is received. The response time provided by the rate control circuit 134 is orders of magnitude faster than the response time for power control using dynamic voltage and frequency control in the components of the SOC 110 (e.g., the time window for the response of the rate control circuit 134 is faster than that for the SOC 110 The time window for the response of components of 110 is orders of magnitude smaller). Such a fast response time can improve protection against functional failures in power management for multi-die SOC systems.

In some embodiments, as shown in FIG. 4 , rate control circuit 134 receives a power reduction signal from trigger logic 132 . For example, in one contemplated embodiment, rate control circuit 134 may receive a power reduction signal intended for a CPU (processor 152 ) in SOC 110 . As mentioned above, the power reduction signal is synchronized with the clock cycle of the SOC 110 . Thus, the rate control circuit 134 may implement a slower but synchronous clock rate reduction based on the power reduction signal. However, providing both the selected trigger signal and the power reduction signal into the rate control circuit 134 may provide a redundant power reduction response in the SOC 110 in case of a failure of the PMU 140 or a function in the SOC 110 .

In some embodiments, as shown in FIG. 4 , trigger logic 132 may receive a power reduction signal from another SOC 110′ managed by PMU 140 (eg, another die or die). Trigger logic 132 may implement power reduction signals from SOC 110' to provide power reduction signals to components in SOC 110. In some embodiments, trigger logic 132 may provide power reduction to another SOC 110″ managed by PMU 140. The other SOC 110'' may then implement a power reduction scheme (eg, using trigger logic in the SOC 110'') to reduce power based on the received power reduction signal. An implementation of providing/receiving power reduction signals from other SOCs allows trigger logic 132 and SOC 110 to be part of a multi-die (eg, multi-die) power reduction scheme.

Returning to FIG. 1 , in various embodiments, rate limiting may be provided in the SOC through the memory controller 122 . For example, memory controller 122 may implement transaction rate monitoring in pipelines associated with the memory controller and slow down transactions as needed. Slowing transactions may prevent or reduce power supply degradation in PMU 140 caused by many transactions across many sources (eg, multiple SOCs in a multi-die configuration).

FIG. 5 is a block diagram of one embodiment of a memory controller pipeline 500 . Pipeline 500 is depicted as a simplified block diagram of one embodiment of a memory controller pipeline. It should be understood that the components of the pipeline 500 and the memory controller pipeline may vary beyond what is depicted in FIG. 5 without departing from the scope of this description and the claims herein. For example, additional components or elements may be included in the memory controller pipeline and/or the location of the components or elements may be varied.

Memory controller pipeline 500 may include various control logic and data structures to queue memory requests, arbitrate between requests, and route memory requests to the memory cache and ultimately to the memory cache if there is a memory cache miss. Memory 120. Communication interfaces 550A- 550B may be part of communication fabric 170 and may supply memory requests from other components of SOC 110 to memory controller 122 . Requests can be received into request buffers 540A and 540C, which can pass data or update memory as the request flows through memory controller pipeline 500 and by returning data on communication interfaces 550A to 550B (for reads). These requests are tracked as they complete through the volume cache or memory 120 (for writes). Response buffers 540B and 540D may be used for read data and other responses to be sent back to the request component for read transactions (e.g., completion responses for certain write transactions and coherent requests for coherent transactions ) of the buffer. There may be more request buffers and response buffers for other communication interfaces 550 (not shown in FIG. 5 ). Request buffers 540A and 540C (among others) may provide input into memory arbiter 525 , which may arbitrate requests into memory cache 530 . Requests received by the memory cache 530 may pass through tag and directory pipes 520, which may include tag memory for the memory cache (storing the address label). In one embodiment, the tag and directory management 520 may include a coherent directory that tracks which coherent components in the SOC 110 have copies of cache blocks from the memory cache. The coherence directory and associated logic can generate coherence requests, which can be routed out to components via response buffers 540B and 540D.

If the request hits the memory cache (e.g., the address matches one of the tags in the tag memory), the tag and directory pipe 520 request can be placed in the data pipe queue 560 to access the cached data memory Body 595. Read arbiter 565A may arbitrate between read requests in data pipe queue 560 to read cache data memory 595, and write arbiter 565B may arbitrate between write requests in data pipe queue 560 Arbitrate to write to cache data memory 595 . Read data from cache data memory 595 may be provided to memory output buffer 580 . For those write requests that use a reply, the write reply may also be placed in the memory output buffer 580 .

If the request misses the memory cache (eg, the address does not match what is in the tag's memory), the tag and directory manager 520 may place the request in the memory queue 570 for transmission to the memory 120 . The memory queue 570 may interface to a memory channel controller that accesses the memory 120 . Data (for read requests) or optional write completions (for write requests) may later be passed back by the memory channel controller to the memory output buffer 580 .

Data/write responses from memory output buffer 580 may be provided to tag and directory pipe 520 when data is to be installed in memory cache 530, and may also be provided to output arbitrators 590B, 590D, which output The arbiter can arbitrate to output data/write responses to the response buffers 540B, 540D, respectively. The data/write responses may then be provided to the requesting component via communication interfaces 550A-550B.

Memory cache 530 may include multiple sectors or planes that handle different portions of the memory address space mapped to memory controller 122 . Planes allow multiple memory requests to be made in parallel. One plane is shown as memory cache 530 in FIG. 5, but other planes may be similarly configured. There may be a memory arbiter 525 for each plane.

In various embodiments, a plurality of rate limiters 510 are placed throughout pipeline 500 . For example, rate limiters 510 may be placed at various arbitration points within pipeline 500 . An example of a location for rate limiter 510 is shown in FIG. 5 . In the illustrated embodiment, rate limiter 510A is placed at the connection between read arbiter 565A or write arbiter 565B and data pipe queue 560, and rate limiter 510B is placed at the tag and directory pipe 520 and memory arbiter 525, rate limiter 510C is placed at the connection between output arbiters 590B and 590D and response buffers 540B and 540D, and rate limiter 510D is placed at the response buffer Connections between 540B and 540D and communication interfaces 550A, 550B. The number and location (eg, arbitration points) of rate limiters 510 in pipeline 500 may vary depending on the control of the desired transaction rate in pipeline 500 .

Rate limiter 510 may be implemented to actively cap the peak power level in pipeline 500 at times of atypically high activity. In various embodiments, rate limiter 510 reduces command flow by inserting bubble (eg, stall) cycles at arbitration points. In some embodiments, rate limiter 510 is disabled by default, but can be configured by the system (eg, SOC 110 or memory controller 122 ) to provide a desired cap on power consumption of pipeline 500 . For example, each rate limiter 510 location may have a rate limiter interface toolset associated therewith.

FIG. 6 is a block diagram of one embodiment of a rate limiter interface toolkit 600 . The rate limiter interface toolset 600 may be implemented with any of the rate limiters 510 described herein. The rate limiter interface toolset 600 may provide control over the operation and generation of the pause control signal for the rate limiter 510 . In the depicted embodiment, rate limiter interface toolset 600 includes rate limiter pattern generation 610 , local activity detection 620 , and rate limiter control 630 .

Rate limiter pattern generation 610 may include pattern arbiter 612 , pattern register 614 , and pointer 616 . Rate limiter pattern generation 610 can be programmed using a Vmin pattern input, a Vnom pattern input, or a Vmax pattern input. The rate limiter pattern output may be determined based on an operating point input (eg, a memory operating point) provided to the pattern arbiter 612 . In various embodiments, rate limiter pattern generation 610 determines a rate limiter pattern by cycling through pattern register 614 based on input from pattern arbiter 612 . For example, a different profile may be generated for a higher performance (higher power) operating point with more stall cycles than a lower performance (lower power) operating point.

In some embodiments, local activity detection 620 is implemented to track local memory activity. Partial activity detection 620 includes a shift register 622, which receives a historical depth input and an activity indication input; an activity counter 624, which receives an activity indication input; and an activity threshold comparator 626, which compares the activity count with the activity threshold. limit. Activity indications may include, for example, local activity indications such as verification against arbiter, transfer valid (e.g., tag pipe transfer valid), read enable control, write enable control, completion buffer write arbiter grant, completion buffer reset Pass, and downstream interface arbiter authorization.

The shift register 622 may be a configurable register for tracking activity history. For example, the history depth can be programmed to shift a register to track the history for a set number of cycles (eg, 32, 16, or 8 cycles) before making a comparison with an active threshold. The activity counter 624 may count activity during programming a set of cycle numbers into the shift register 622 . At that time, the activity count is compared with the activity threshold in the activity threshold comparator 626 to generate a raw pause signal output when the activity is higher than the predefined activity threshold.

The raw pause signal is provided to a rate limiter control 630, which can selectively block or pass the raw pause signal according to, for example, a programmed rate limiter pattern. The enable arbiter 632 may be programmed in the rate limiter mode and makes a decision on the mode enforced by the rate limiter control 630 . One mode may be "statically on" where the raw pause signal is passed and the pause signal is output from the rate limiter interface tool set 600 in the rate limiter pattern determined by the rate limiter pattern generation 610 . Another mode may be "static off," where the original stall signal is blocked and no rate limiting occurs. For example, shutdown mode may be used if the power at a given memory operating point is known to be low enough that causing PMU voltage degradation is not a concern.

Additional embodiments are contemplated having power management circuitry (PMGR) included in any of the systems described herein. FIG. 7 is a block diagram of one embodiment of a system including a system-on-chip (SOC) 110 coupled to memory 120 and a power management unit (PMU) 140 . PMU 140 may be configured to supply power to SOC 110 and other components that may be included in the system, such as memory 120 . For example, PMU 140 may be configured to generate one or more supply voltages to power SOC 110 , and may be further configured to generate supply voltages for other components of the system not shown in FIG. 7 . Additionally, PMU 140 (or accompanying circuitry coupled to PMU 140 ) may be configured to monitor the supply voltage and detect transient undervoltage conditions or other overload conditions that may result in erroneous operation in SOC 110 . PMU 140 may assert a trigger input to SOC 110 when such conditions occur (typically resulting from the electrical load of SOC 110 exceeding the capacity of PMU 140 ). In the depicted embodiment, global power control circuitry 130 incorporated into SOC 110 may receive a trigger input. Although the SOC embodiment is used as an example herein, systems including multiple integrated circuits coupled to a communication fabric can be used in other embodiments.

As the name implies, the components of the SOC 110 may be integrated onto a single semiconductor substrate as an integrated circuit "chip." In the depicted embodiment, components of SOC 110 include at least one processor cluster 150, at least one graphics processing unit (GPU) 160, one or more peripheral components, such as peripheral components (more simply, "peripherals") , memory controller 122 , power management circuit (PMGR) 700 , global power control circuit 130 , and communication fabric 170 . Components 150 , 160 , 180 , 122 , and 700 may all be coupled to communication fabric 170 . Memory controller 122 may be coupled to memory 120 during use. In some embodiments, there may be more than one memory controller coupled to a corresponding memory. In such embodiments, the memory address space may be mapped across memory controllers in any desired manner. In the illustrated embodiment, processor cluster 150 may include a plurality of processors (P) 152 . Processor 152 may form a central processing unit (CPU) of SOC 110 . Processor cluster 150 may further include one or more processors (e.g., coprocessor 154 in FIG. Centralized instructions. For example, coprocessor 154 may be a matrix engine optimized to perform vector and matrix operations.

PMGR 700 may be configured to manage power consumption in SOC 110 . As shown in FIG. 7, PMGR 700 may include telemetry tables 702, a power management processor (PMP) 704, and power budget control code 710, which may be stored in memory within PMGR 700 (e.g., local memory, Such as local Static Random Access Memory (SRAM) or ROM) and/or memory 120 . Power budget control code 710 may be stored in ROM or other form of non-volatile memory, and may be loaded into PMGR 700/memory 120 during system initialization, for example. Telemetry table 702 may be any type of memory (eg, static random access memory (SRAM), scratchpad, etc.). Various components of the SOC 110 can report activity, performance information, power consumption data, etc. to the PMGR 700 in a "push" mode with some degree of regularity, and thus can be used for analysis in the PMGR 700 without PMGR 700 polling Various components to collect information. More specifically, in this embodiment, in addition to the power budget control code 710, the PMP 704 can be configured to execute code to analyze data in the telemetry table.

As previously mentioned, PMU 140 may be configured to assert a trigger signal upon detection of an undervoltage event. When such an event occurs, the SOC 110 (and more specifically, the global power control circuit 130 ) can respond by rapidly reducing the clock frequency at which the components operate, using techniques such as clock dithering, clock gating, etc. , selective pulse removal, clock division, control within various components to reduce processing performance and thereby reduce power. While these techniques can effectively continue to operate without errors (because the reduced clock frequency compensates for slower evaluating transistors at reduced voltage), performance degradation can be dramatic. For example, dividing the clock frequency by 2 (relatively fast operation) degrades performance by about ½. In some cases, the performance reduction may be even greater (eg, 75% or greater) to ensure error-free operation. Global power control circuit 130 may thus be coupled to various components of SOC 110 (not explicitly depicted in FIG. , clock divider, clock gate, clock tree, etc.) to implement frequency reduction that can help ensure error-free (or correct) operation during undervoltage operation. In one embodiment, the global power control circuit 130 can be configured to record the frequency (e.g., how often) the trigger input is established to the global power control circuit 130 in the telemetry table 702 (or the participating frequency of the global power control circuit 130 , which is dependent on the frequency established by the trigger input), is shown by the dotted arrow in FIG. 7 .

In many cases, a less severe performance degradation will be sufficient to reduce the load sufficiently that brownout events will occur less often. For example, if an undervoltage event occurs because the PMU 140 is slightly overloaded, the amount of load reduction that will prevent the event from occurring is relatively small and can be reduced slightly by temporarily reducing the power consumption of one or more controllable components in the system. performance while remaining within the capacity of the PMU 140 . PMP 704 and power budget control code 710 may be used to attempt to reduce the frequency of undervoltage events, or more specifically, to reduce the frequency with which global power control circuitry is invoked to provide undervoltage control. For example, in one embodiment, power budget control code 710 may analyze telemeter data and may determine the frequency of undervoltage events during a given time window, or the amount of time during which global power control circuit 130 is engaged in reducing power consumption. The power budget control code 710 may modify the power budget to one or more components in the next time window in an attempt to reduce the occurrence of undervoltage events. For example, the power budget can be reduced, and thus the components can consume less power in the next time window, reducing the overall load current on the PMU 140 . While the performance achievable by the components may be reduced in the next time window, undervoltage events are reduced and severe performance loss due to undervoltage events may be reduced, while overall performance may be higher. For example, power budget control code 710 may attempt to reduce undervoltage triggering by a specified percentage (eg, 1% of a given time window). Additional details are provided further below.

At least some of the components can be configured to control power consumption based on a power budget. For example, one or more of processor cluster 150, GPU 160, and peripherals 180 may include power control circuits (PwrCtl) 720A-720C, which include respective power budgets 722A-722C. Power control circuits 720A-720C can monitor the operation of individual components and measure/estimate power consumption. The power control circuits 720A-720C can compare the measured/estimated power consumption to the power budget. If the budget is exhausted or falls below a threshold, the power control circuits 720A-720C may invoke various power consumption mitigation mechanisms. For example, power control circuitry 720A may employ mitigation mechanisms such as disabling one or more processors 152 and/or disabling one or more pipelines in processors 152 . The instruction issue rate can be reduced, and bubbles inserted in the pipeline so that the corresponding circuitry does not actively evaluate each cycle. Any set of one or more mitigation mechanisms may be used. Similarly, GPU 160 may reduce the number of active pipelines, limit the instruction issue rate, and/or implement any other mitigation mechanism. Mitigation mechanisms may be specific to a given component being controlled, and different components may employ different mechanisms, or some similar mechanisms and some specific mechanisms as desired. The PMP 704/power budget control code 710 may be independent of a specific mechanism, the details of setting the budget 722A-722C and following the budget 722A-722C are implemented by the power control circuit 720A-720C.

If the power budget control code 710 reduces the power budget 722A-722C in one or more of the power control circuits 720A-720C, while the frequency of undervoltage events is still higher than desired in the next time window, the power budget 710 may be used in the next time window. further power budget in the time window of . Any algorithm for reduction can be used. For example, each budget may be reduced by a specific amount to effect the reduction, so that the performance reduction is relatively evenly spread over the components that can be controlled. In another algorithm, different budgets 722A-722C may be lowered in different time windows, rotated among different subsets of one or more components, and then restored to the reduced power budget in subsequent time windows to the original value.

Note that while some example embodiments are described as implementing power budget control as code 710 executable by PMP 704, other embodiments may implement all or a portion of power budget control in hardware (e.g., state machines and/or combinational logic) .

PMGR 700 can be configured to control the magnitude of supply voltage requested from external PMU 140 . There may be multiple supply voltages generated by PMU 140 for SOC 110 . For example, there may be a supply voltage for processor cluster 150 and at least one supply voltage for the rest of SOC 110 outside processor cluster 150 . In one embodiment, the same supply voltage can be supplied to components of the SOC 110 outside the processor cluster 150, and power gating can be used to control one or more independent power domains supplied by the power supply voltage. In some embodiments, there may be multiple supply voltages for the remainder of the SOC 110 . In some embodiments, there may also be memory supply voltages for the various memory arrays in processor cluster 150 and/or SOC 110 . The memory supply voltage may be used in conjunction with the voltage supplied to the logic circuitry, which may be of a lower voltage magnitude than required to ensure robust memory operation. PMGR 700 may be directly under software control (eg, software may directly request power on and/or power off of components), and/or may be configured to monitor SOC 110 and determine when various components are about to power on or power off. Various power states within components (eg, the power state of the processor 152 ) can be controlled through the PMGR 700 and the sequencing of changes to power states, different requested voltages and frequencies, and the like.

As mentioned above, processor cluster 150 may include one or more processors 152 , which(s) may act as the CPU of SOC 110 . The system's CPU includes processor(s) that execute the system's main controlling software, such as an operating system. Usually, the software executed by the CPU can control other components of the system during use, so as to realize desired functions of the system. The processor can also execute other software, such as application programs. Applications can provide user functionality and can rely on the operating system for lower-level device control, scheduling, memory management, and so on. Therefore, the processor can also be called an application processor.

In general, a processor may include any circuitry and/or microcode configured to execute instructions defined in the instruction set architecture implemented by the processor. A processor may encompass a processor core implemented on an integrated circuit with other components as a system-on-chip (SOC 110 ) or other levels of integration. A processor may further encompass discrete microprocessors, processor cores, and/or microprocessors integrated into multi-chip module implementations, processors implemented as multiple integrated circuits, and the like.

Memory controller 122 may generally include circuitry for receiving memory operations from other components of SOC 110 and for accessing memory 120 to complete the memory operations. Memory controller 122 can be configured to access any type of memory 120 . For example, memory 120 may be static random access memory (SRAM), dynamic RAM (DRAM), such as synchronous DRAM (SDRAM), including double data rate (DDR, DDR2, DDR3, DDR4, etc.) DRAM. Can support low-power/mobile versions of DDR DRAM (eg, LPDDR, mDDR, etc.). Memory controller 122 may include queues for memory operations, which are used to sequence (and possibly reorder) and commit operations to memory 120 . The memory controller 122 may further include a data buffer to store write data waiting to be written to the memory and read data waiting to be returned to the source of the memory operation. In some embodiments, the memory controller 122 may include a memory cache to store recently accessed memory data. In SOC implementations, for example, memory caching can reduce power consumption in the SOC by avoiding re-accessing data from memory 120 if the data is expected to be accessed again soon. In some cases, a memory cache may also be called a system cache, as opposed to a private cache that only serves certain components, such as an L2 cache or a cache in a processor. Additionally, in some embodiments, the system cache need not be located within the memory controller 122 .

Peripherals 180 may be any set of additional hardware functions included in SOC 110 . For example, peripherals 180 may include video peripherals such as image signal processors, video encoders/decoders, scalers, rotators, fusion controller, display controller, etc. Peripherals may include audio peripherals such as microphones, speakers, interfaces to microphones and speakers, audio processors, digital signal processors, mixers, and the like. Peripheral devices may include interface controllers for various interfaces external to SOC 110, including interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect (PCI) including PCI Express (PCIe), Serial And parallel ports, etc. Interconnections to external devices are depicted by dashed arrows in FIG. 7 , which extend outside of the SOC 110 . Peripherals may include networked peripherals, such as media access controllers (MACs). Any set of hardware can be included.

Communication fabric 170 may be any communication interconnect and protocol used to communicate between components of SOC 110 . Communication fabric 170 may be bus-based, including shared bus configurations, cross-wire configurations, and hierarchical buses with bridges. Communication fabric 170 may also be packet-based, and may be hierarchical in bridge, cross-wire, point-to-point, or other interconnections.

Note: The number of components of SOC 110 (and the number of subcomponents of those shown in Figure 7, such as processors 152 in each processor cluster 150) may vary from embodiment to embodiment. Furthermore, the number of processors 152 in one processor cluster 150 may be different than the number of processors 152 in another processor cluster 150 when multiple processor clusters are included. There may be a greater or lesser number of components/subassemblies than shown in FIG. 7 .

According to the present disclosure, an integrated circuit (eg, SOC 110 ) may include: a plurality of components; global power control circuitry coupled to the plurality of components; and power management circuitry. A given component of the plurality of components is configured to manage power consumption based on a budget amount assigned to the given component. The global power control circuit is configured to apply power control across the plurality of components in response to trigger inputs to the integrated circuit. The power management circuit is configured to: detect whether the power control applied by the global power control circuit exceeds a threshold; and based on the detection that the power control applied by the global power control circuit exceeds the threshold, reduce the number of components assigned to the plurality of components. A budget amount for at least one. For example, the threshold may include the percentage of time that power control is applied by the global power control circuit.

The power management circuit can be configured to measure the percentage of time within a fixed time window. For example, the power management circuit can be configured to detect a percentage of the duration of the first instance of a fixed time window, and can be configured to reduce the amount of budget for an instance under the fixed time window, where the next instance is the next The first instance item. For example, the power management circuit can be configured to reduce the budget amount to a first component of the plurality of components in a given fixed time window, and reduce the budget amount to a second component of the plurality of components in another given fixed time window. The budget amount for the component.

FIG. 8 is a block diagram illustrating various power management mechanisms in one embodiment of the SOC 110 . In FIG. 8 the mechanisms are ordered from left to right based on how quickly they can respond to power management needs. On the left is the global power management mechanism (element number 800), which operates based on a trigger input to rapidly reduce the clock frequency. Global power management mechanisms are primarily focused on ensuring correctness in the event of an undervoltage event. As mentioned above, since the extent of the undervoltage event is unknown, the mechanism can be rather crude, and thus the control can be designed to ensure correctness for worst case events.

The second fastest mechanism may be a PMP/power budget control mechanism (element number 802). The PMP mechanism can be slower than the global mechanism, but can have more granular and precise control. The PMP mechanism can attempt to improve efficiency and performance by taking actions to limit the participation of global power management mechanisms. For example, as mentioned above, the PMP mechanism may include modifying the power budgets of various components used to implement power management on a budget basis. In another embodiment, the PMP mechanism may include temporarily modifying the clock frequency and/or power supply voltage to one or more components.

Additionally, a third power management mechanism - CPU based power control (element number 804 ) may be employed. The CPU-based power control mechanism can employ software executed by the processor 152, and thus can share execution time with the operating system and various applications. The CPU-based power control mechanism can examine many metrics, including telemetry data in telemetry table 702, as well as various performance measurements in the system. CPU-based power control mechanisms may employ dynamic voltage and frequency control, reducing voltage and frequency settings (e.g., "power state") in PMGR 700 as a means of mitigating power control mitigation involving global power control circuit 130 and PMP power control mechanisms Mechanisms to control the amount of power and restore power states to their original settings as desired to increase performance. For example, CPU-based power control mechanisms can reduce power states if reducing global and PMP-based mitigation to the point that lower power states will result in higher overall performance/efficiency, even if the system runs slower. Typically, CPU-based mechanisms can employ system-wide analysis and power management.

Global mechanisms can have timescales on the order of tens to hundreds of nanoseconds; PMP mechanisms can have time windows on the order of hundreds of microseconds; and CPU-based mechanisms can have timescales of hundreds of milliseconds. That is, PMP mechanisms may operate with time windows that are one or more decades longer than global mechanisms, and CPU-based mechanisms may have time windows that are one or more decades longer than PMP mechanisms. In one embodiment, the time window for the CPU-based mechanism may be an integer multiple of the time window for the PMP mechanism.

FIG. 9 illustrates an embodiment of a power control window (elements 900A-900N) and a CPU power control window 902 implemented using PMP-based power budget control. In Figure 9, time increases from right to left in arbitrary units. As noted previously, PMP-based mechanisms can measure under-voltage events and/or global power control activity in a given PMP window (e.g., window 900A) and in the next subsequent or immediately adjacent window (e.g., window 900B) Modify the power budget for one or more components.

FIG. 10 is a flowchart illustrating the operation of one embodiment of PMP-based power budget control 710 . Although the blocks are shown in a particular order for ease of understanding, other orders may be used. In a hardware-based embodiment, the blocks may be executed in parallel in combinational logic. For software-based embodiments, instructions executed by PMP 704 may cause PMP 704 to perform specified operations. The operations in FIG. 10 may be performed, for example, at or near the end of a given PMP time window 900A-900N in FIG. 9 .

The power budget control may read the global telemetry from the telemetry table 702 (block 1000). Based on the telemetry data, power budget control 710 may determine whether the occurrence of under voltage events/triggers in previous time windows 900A-900N is greater than a desired threshold. For example, thresholds may be measured in terms of number of events, percentage of time that global power control circuit 130 participates in mitigation mechanisms, and the like. Thresholds can be fixed or programmable as desired.

If the occurrence of the event is greater than the desired threshold (decision block 1002, "yes" branch), power budget control 710 may reduce the power budget for one or more components during the current window (block 1004). If not (decision block 1002, "No" branch), power budget control 710 may increase the power budget for the current window (block 1006). The increase and/or decrease may be subject to a certain amount of hysteresis. For example, if the most recent change was an increase in the power budget, a reduction in the power budget may be delayed until the reduction is indicated within two or more successive PMP time windows. Similarly, if the most recent change was a decrease in the power budget, an increase may be delayed until indicated within two or more successive PMP time windows.

Note that power budget reductions and power budget increases can be performed with different weights or magnitudes. For example, the reduction applied window by window may be greater than the increase applied window by window. Therefore, if frequent undervoltage events are observed, the power budget will be reduced more rapidly, allowing the coarser correctness-based control to quickly reach a lower rate. Once the lower rate is achieved, increasing the power budget slowly allows the system to settle to some degree of steady state.

Thus, in one embodiment, at least one of the components of the integrated circuit may include one or more central processing unit (CPU) processors. The CPU can be configured to execute a plurality of instructions to implement power control in the integrated circuit using dynamic voltage and frequency control. The plurality of instructions can implement power control within a second fixed time window larger than the fixed time window used by the power management circuit. For example, the second fixed time window is one or more orders of magnitude longer than the fixed time window. In one embodiment, the second fixed time window may be an integer multiple of the fixed time window. The power management circuit can be configured to: detect that the power control applied by the global power control circuit is less than a threshold; and based on the detection that the power control applied by the global power control circuit exceeds the threshold, increase assignments to one of the plurality of components A budget amount for at least one. The increase in the budgeted amount may be limited to a maximum amount for at least one of the plurality of components. The power management circuit can be configured to apply hysteresis when changing between increasing and decreasing budget amounts. As previously mentioned, in one embodiment, a power management circuit may include a power management processor and a memory coupled to the power management processor storing a plurality of instructions that when executed by the power management processor , causing the power management processor to perform operations including the operations described above for the power management circuit. instance method

11 is a flowchart illustrating a method for power reduction in integrated circuits, according to some embodiments. Method 1100 may be implemented using any of the embodiments of the SOC as disclosed herein along with any circuitry in an integrated circuit or other mechanism.

At 1102, in the depicted embodiment, the integrated circuit receives a plurality of supply voltages from a plurality of voltage regulators, wherein the integrated circuit includes a plurality of components that generate memory transactions to access the memory, control the memory A plurality of memory controller circuits, and a communication fabric including a plurality of circuits interconnecting the plurality of components with the plurality of memory controller circuits.

At 1104, in the depicted embodiment, a plurality of power delivery trigger circuits coupled to the integrated circuit and the plurality of voltage regulators generates a plurality of trigger signals based on an electrical load experienced by the plurality of voltage regulators.

At 1106, in the depicted embodiment, trigger logic coupled to the plurality of power delivery trigger circuits generates a power curtailment signal based on the plurality of trigger signals received from the plurality of power delivery trigger circuits.

At 1108, in the depicted embodiment, a clock rate for a plurality of circuits in a communication fabric is controlled via a rate control circuit coupled to at least one of a plurality of power delivery trigger circuits, wherein the clock The rate is decreased based on at least one of a plurality of trigger signals from at least one of the power delivery trigger circuits.

At 1110, in the depicted embodiment, a given memory controller circuit of the plurality of memory controller circuits is rate limited according to a plurality of rates at a plurality of locations in a pipeline within the given memory controller circuit The register circuit controls the rate at which memory transactions flow through the plurality of locations.

12 is a flowchart illustrating another method for power reduction in integrated circuits, according to some embodiments. Method 1200 may be implemented using any of the embodiments of the SOC as disclosed herein along with any circuitry in an integrated circuit or other mechanism.

At 1202, in the depicted embodiment, the integrated circuit receives a plurality of supply voltages from a plurality of voltage regulators, wherein a plurality of power delivery trigger circuits is coupled to the integrated circuit and the plurality of voltage regulators.

At 1204, in the depicted embodiment, a first set of power delivery trigger circuits coupled to the integrated circuit by wires generates a trigger signal when the electrical load experienced by the plurality of voltage regulators satisfies a first threshold.

At 1206, in the illustrated embodiment, when the electrical load experienced by the plurality of voltage regulators satisfies a second threshold (where the first threshold is closer to the point of functional failure of the integrated circuit than the second threshold) A trigger signal is generated by a second group of power transmission trigger circuits coupled to the integrated circuit through a plurality of serial communication interfaces. Example power delivery system:

Referring now to FIG. 13, a block diagram of a system with a power delivery system and computing elements is shown. In the depicted embodiment, system 1300 includes hierarchical power delivery system 1310 and computing element 1320 . Hierarchical power delivery system 1310 includes a first power converter stage 1312 coupled to receive an input voltage V_in from an external source (eg, a battery pack). The first power converter stage 1312 includes one or more power converters configured (etc.) to generate one or more first stage regulated supply voltages. These first level regulated supply voltages are received by one or more power converters of the second power converter level 1314 . Power converters using one or more first level regulated supply voltage power converter stages 1314 generate one or more second level regulated supply voltages. These voltages are provided to the various loads of the computing element 1320 .

In the illustrated embodiment, the computing element 1320 includes one or more integrated circuits (IC or SOC) 1322, generally shown here as ICs 1322-1 through 1322-N. Computing element 1320 is configurable and scalable, with different implementations having different IC counts. For example, in a first embodiment, computing element 1320 may include a single IC die, while in a second embodiment, computing element 1320 may include two or more IC dies. Implementations in which only a portion of the IC die are enabled are also possible and contemplated.

While the computing element 1320 can be scaled accordingly, the number of ICs for a particular implementation is apparent from the software architecture executing thereon. Thus, regardless of the number of particular ICs in a given implementation, software executing thereon may view computing element 1320 as a single entity. Thus, computing element 1320 in the illustrated embodiment can implement a computing architecture that can be scaled up or down as desired, and can execute software on various implementations regardless of this scaling.

In the illustrated embodiment, each IC 1322-1 through 1322-N may include several different types of circuitry. For example, ICs 1322-1 through 1322-N may include various types of processor cores, graphics processing units (GPUs), neural network processors, memory controllers, input/output (I/O) circuits, A network switch, etc., on which various networks are implemented. When implementing two or more instances of ICs 1322-1 through 1322-N to form a computing element, the various functional circuits thereon may form a complex that is larger than implementations using a single IC or a portion thereof. For example, ICs 1322-1 and 1322-N may each include a processor core complex, and thus, in implementations of computing element 1320 with two or more ICs, enable larger processors that span the number of ICs core complex. The processor core of one IC may communicate with the processor core of another IC through one or more die-to-die interfaces between the individual ICs.

To account for the different power requirements from different types of circuitry implemented on instances of IC 1322-1 through 1322-N, multiple power converters may thus exist that generate corresponding voltages to meet the efficiency needs of these loads. For example, a processor core may have different power requirements than I/O circuits. Accordingly, the power converter stage 1314 may include one or more power converters adapted to provide a first second-level supply voltage to a processor core and one or more power converters to provide a different second-level supply voltage to an I/O circuit power converter.

The hierarchical power delivery system 1310 in the illustrated embodiment is also scalable, mirroring the scalability of the computing elements 1320 . In various embodiments, the power converter hierarchy of the hierarchical power delivery system 1310 may include several power converters (eg, switching voltage regulators and the like) to meet the electrical needs of various loads, as discussed above. The number of power converters enabled for a particular implementation may thus correspond to the number of ICs 1322 - 1 through 1322 -N in a particular implementation of computing element 1320 . More generally, power converter stages 1312 and 1314 may be configured to enable more power supply capacity as more computing capacity is implemented in computing element 1320 . In this way, the design of the hierarchical power delivery system 1310 is reusable for several different implementations of the computing element 1320 . The design of the hierarchical power delivery system 1310, which is reusable across the scalability range of the computing elements 1320, can then obviate the need to provide custom power delivery solutions for various implementations. This in turn can significantly simplify the design of various systems based on different implementations of computing element 1320, as well as reduce the amount of time to implement a working system for any particular implementation of such a design. Computer-readable media and manufacturing systems:

FIG. 14 is a block diagram of one embodiment of a manufacturing system 1400 . The system includes a non-transitory computer readable medium 1420 on which are stored instructions/description 1450 for the power delivery system of any embodiment falling within the scope of the present disclosure. Computer-readable medium 1420 can be one of several different types of non-transitory media, including magnetic disk storage, solid-state drives (e.g., using flash memory), optical storage (e.g., using CD-ROM), various types of random access memory (RAM), etc., which can provide persistent storage of information.

Computer system 1440 is configured to read circuit instructions/description 1450 from computer readable medium 1420 . Additionally, computer system 1440 may execute various instructions and use the circuit description to cause fabrication system 1445 to fabricate one or more instances of the circuit represented by circuit instructions/description 1450 . Manufacturing system 1445 may be any type of automated system that can manufacture electronic circuits. Example system:

Referring next to FIG. 15 , a block diagram of one embodiment of a system 1500 that can incorporate and/or otherwise utilize the methods and mechanisms described herein is shown. In the depicted embodiment, system 1500 includes at least one instance of system-on-chip (SoC) 1506, which may include various types of processing units, such as central processing units (CPUs), graphics processing units (GPUs), or otherwise Communication fabric, and interface to memory and input/output devices. In some embodiments, one or more processors in SoC 1506 include multiple execution lanes and instruction issue queues. In various embodiments, SoC 1506 is coupled to external memory 1502 , peripherals 1504 , and power supply 1508 .

A power supply 1508 is also provided that supplies a supply voltage to SoC 1506 and one or more supply voltages to memory 1502 and/or peripherals 1504 . In various embodiments, power supply 1508 represents a battery pack (eg, a rechargeable battery in a smartphone, laptop, or tablet, or other device). In some embodiments, more than one instance of SoC 1506 is included (and also more than one external memory 1502 is included).

Memory 1502 is any type of memory such as Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM such as mDDR3, etc.) and/or low-power versions of SDRAM such as LPDDR2), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices are coupled to the circuit board to form a memory module, such as a single inline memory module (SIMM), dual inline memory module (DIMM), and the like. Alternatively, the device is mounted where the SOC or integrated circuit is in a chip-on-a-wafer configuration, a package-on-package configuration, or a multi-chip module configuration.

Peripherals 1504 include any desired circuitry depending on the type of system 1500 . For example, in one embodiment, peripherals 1504 include means for various types of wireless communications such as WiFi, Bluetooth, cellular, GPS, etc. In some embodiments, peripheral device 1504 also includes additional storage, including RAM storage, solid state storage, or disk storage. Peripheral devices 1504 include user interface devices, such as display screens (including touch display screens or multi-touch display screens), keyboards, or other input devices, microphones, speakers, and the like.

As depicted, system 1500 is shown to have application in a wide variety of fields. For example, system 1500 may be used as a chip, circuit, or chip for desktop computer 1510, laptop computer 1520, tablet computer 1530, cellular or mobile phone 1540, or television 1550 (or via a set-top box coupled to a television). Part of a system, component, etc. A smart watch and fitness monitoring device 1560 is also shown. In some embodiments, smart watch 1560 may include various general computing related functions. For example, a smart watch may provide access to email, cell phone service, a user's calendar, and more. In various embodiments, the health monitoring device may be a dedicated medical device or otherwise include dedicated health-related functionality. For example, health monitoring devices can monitor the user's vital signs, track the user's proximity to other users for epidemic and social distancing purposes, contact tracing, and provide communication to emergency services in the event of a health crisis. Epidemiological functions (such as contact tracing), providing communication to emergency medical services, etc. In various embodiments, the smartwatches mentioned above may or may not include some or any of the health monitoring related functions. Other wearable devices are also contemplated, such as devices worn around the neck, devices implantable in the human body, glasses designed to provide augmented and/or virtual reality experiences, and the like.

System 1500 may further be used as part of cloud-based service(s) 1570 . For example, the previously mentioned devices and/or other devices may access computing resources in the cloud (ie, remotely locate hardware and/or software resources). Still further, system 1500 may be used in a home device other than one or more previously mentioned. For example, appliances in the home can monitor and detect conditions of concern. For example, various devices in a home (eg, refrigerators, air-conditioning systems, etc.) can monitor the status of the devices and provide alerts to the homeowner (or, eg, repair facilities) that certain events should be detected. Alternatively, a thermostat can monitor the temperature in the home and can automatically adjust the heating/cooling system based on the homeowner's history of responses to various conditions. Figure 15 also illustrates the application of the system 1500 to various modes of transportation. For example, the system 1500 may be used in control and/or entertainment systems of aircraft, trains, buses, taxis, private passenger cars, surface vessels ranging from private watercraft to large yachts, locomotives (for rental or personal use), and the like. In various cases, system 1500 may be used to provide automated guidance (eg, self-driving cars), general system control, and others. These and many other embodiments are possible and contemplated. It should be noted that the devices and applications depicted in Figure 15 are illustrative only and not intended to be limiting. Other arrangements are possible and contemplated.

The present disclosure further contemplates the use of a common scalable computing architecture among some or all of the various devices depicted in FIG. 15 . Thus, computing elements can be scaled according to the needs of the particular system in which they are implemented. For example, smart watch/fitness monitor device 1560 may use a first implementation of computing elements of a scalable architecture, while tablet 1530 uses a second implementation, and desktop 1510 uses a third implementation. In this particular example, the implementation of computing elements in tablet computer 1530 may be scaled up relative to smart watch/health monitor device 1560 . Similarly, the implementation of computing elements in desktop computer 1510 may be scaled up relative to tablet computer 1530 . Accordingly, each of these devices may utilize a common computing architecture implemented at a scale according to the needs of their respective systems. A power delivery system according to the present disclosure, along with a scalable architecture, can be provided in each of these applications, and can be scaled accordingly along with the computing elements. Thus, while each of the examples discussed here may utilize a power delivery system with a common design, an implementation for a desktop computer 1510 may have more power delivery capacity than a tablet computer 1530, which in turn has a greater than The power delivery capacity of the watch/health monitor device 1560. However, the common design of the power delivery systems used in these different devices can significantly simplify their implementation, because the power delivery system can be configured for a specific application by enabling/disabling the appropriate ones of the power converters therein application. ***

References to "an embodiment" or "groups of "embodiments" (eg, "some embodiments" or "various embodiments") are included in this disclosure. references. The embodiments are various implementations or instances of the disclosed concepts. References to "an embodiment," "one embodiment," "a particular embodiment," and the like are not necessarily all referring to the same embodiment. Numerous possible embodiments are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the spirit or scope of the disclosure.

This disclosure may discuss potential advantages that may result from the disclosed embodiments. Not all implementations of these examples will necessarily exhibit any or all of the potential advantages. Whether an advantage is realized for a particular implementation depends on many factors, some of which are outside the scope of this disclosure. In fact, there are a number of reasons why implementations falling within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular implementation may include other circuitry outside the scope of this disclosure (in conjunction with one of the disclosed embodiments) that would negate or reduce one or more of the disclosed advantages. Furthermore, sub-optimal design execution of a particular implementation (eg, implementation technique or tool) may also nullify or reduce disclosed advantages. Even assuming a skilled implementation, the realization of advantages may still depend on other factors, such as the circumstances of the environment in which the implementation is deployed. For example, inputs applied to a particular implementation may prevent one or more of the problems addressed in this disclosure from occurring in a particular situation, with the result that the benefits of its solution may not be realized. Given the existence of possible factors external to the present disclosure, it is expressly intended that any potential advantages described herein should not be construed as having to meet the claims limitations in order to prove infringement. Rather, the identification of such potential advantages is intended to illustrate the types of improvement(s) available to designers having the benefit of this disclosure. Permissively describing such advantages (eg, stating that a particular advantage "may result from") is not intended to convey doubt as to whether such advantages are in fact achievable, but rather a recognition that the technical reality of achieving such advantages often depends on additional factors.

The examples are non-limiting unless otherwise stated. That is, the disclosed embodiments are not intended to limit the scope of draft claims based on the present disclosure, even if only a single instance of a particular feature is described. The disclosed embodiments are intended to be illustrative rather than limiting and no statement to the contrary is made in this disclosure. Accordingly, this application is intended to allow patent claims to cover the disclosed embodiments as well as such alternatives, modifications, and equivalents, which would be apparent to those of ordinary skill in the art having the benefit of this disclosure. of.

For example, the features of this application may be combined in any suitable manner. Accordingly, new claims may be made to any such combination of features during the prosecution of this application (or an application claiming priority thereto). In particular, with reference to the appended claims, features from independent claims may be combined with features of other independent claims, including claims dependent on other dependent claims, if appropriate. Similarly, features from separate dependent claims may be combined where appropriate.

Accordingly, while accompanying dependent claims may be drafted such that each is dependent on a single other claim, additional dependencies are also contemplated. Any combination of features in dependent claims consistent with this disclosure is contemplated and may be claimed in this or another application. In short, combinations are not limited to those specifically listed in the appended claims.

It is also contemplated that a claim drafted in one format or legal type (eg, device) is intended to support a corresponding claim in another format or legal type (eg, method), as appropriate. ***

Because this disclosure is a legal document, various terms and phrases are subject to administrative and judicial interpretation. The Notice hereby provides the definitions in the following paragraphs and throughout the disclosure that will be used to determine how to interpret claims drafted based on this disclosure.

References to an item in the singular (i.e., a noun or noun phrase preceded by "a/an", or "the") are intended to mean "one or more" unless the context clearly dictates otherwise. or more)"). Thus, reference to "an item" in a claim does not exclude additional instances of that item in the absence of accompanying context. "Plurality" of an item refers to a collection of one of two or more items.

As used herein, the word "may" is used herein in a permissive sense (ie, has the potential to, can), and not in a mandatory sense (ie, must).

The terms "comprising" and "including" and their forms are open-ended and mean "including, but not limited to".

When the term "or" is used in this disclosure in relation to a list of options, it will generally be read to be used in an inclusive sense, unless the context dictates otherwise. Thus, the statement "x or y (x or y)" is equivalent to "x or y, or both (x or y, or both)", so: 1) covers x, but not y; 2) covers y, but does not cover x; and 3) covers both x and y. On the other hand, phrases such as "either x or y, but not both" clearly indicate that "or" is used in an exclusive sense.

The statement "w, x, y, or z, or any combination thereof (w, x, y, or z, or any combination thereof)" or ": at least one of w, x, y, and z of ... w, x, y, and z)" is intended to cover all possibilities involving a single element up to a total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element of the set (e.g., w but not x, y, or z (w but not x, y, or z)), Any two elements (e.g., w and x, but not y or z (w and x, but not y or z)), any three elements (e.g., w, x, and y, but not z (w, x, and y, but not z)), and all four elements. Thus, the phrase "at least one of ... w, x, y, and z" refers to at least one element of the set [w, x, y, z] , thereby covering all possible combinations in this bill of materials. This phrase is not to be read as requiring at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

In this disclosure, various "markers" may be placed before nouns or noun phrases. Different designations used for a feature (e.g., "first circuit", "second circuit", "specific circuit", "given circuit" unless the context dictates otherwise) (given circuit)", etc.) refer to different instances of this feature. Additionally, the designations "first", "second", and "third" when applied to a feature do not imply any type of order (e.g., spatial , time, logic, etc.).

The phrase "based on" is used to describe one or more factors that affect a decision. This term does not exclude the possibility that additional factors may affect the determination. That is, a determination may be based on the specified factors alone, or on those specified factors and other unspecified factors. Consider the term "determine A based on B". This term indicates that B is a factor used to determine A, or that B affects A's determination. This term does not exclude that A may also be determined based on some other factor such as C. This term is also intended to encompass an embodiment in which A is determined based on B alone. As used herein, the term "based on" is synonymous with the term "based at least in part on".

The phrase "in response to/response to" describes one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger an effect, either in conjunction with or independently of the particular factors. That is, an effect may be responsive to those factors alone, or may be responsive to those noted factors in addition to other unspecified factors. Consider the phrase "perform A in response to B". This phrase specifies that B is the factor that triggers the execution of A or triggers a specific result of A. This phrase does not exclude that A may also be performed in response to some other factor (such as C). The phrase also does not preclude performing A in joint response to B and C. This phrase is also intended to cover embodiments where A is performed in response to B only. As used herein, the phrase "responsive to" is synonymous with the phrase "responsive at least in part to." Similarly, the phrase "in response to" is synonymous with the phrase "at least in part in response to". ***

In this disclosure, various entities (which may be referred to variously as "units," "circuits," other components, etc.) may be described or claimed to be "configured" to Perform one or more tasks or actions. The notation ("entity" configured to "perform one or more tasks") is used herein to refer to structures (ie, things that are entities). Specifically, this notation is used to indicate that the structure is configured to perform the one or more tasks during operation. Even though the structure is not currently being manipulated, the structure can still be said to be "configured to" perform certain tasks. Thus, an entity described or described as being "configured to" perform certain tasks refers to a physical thing, such as a device, a circuit, a system having a processor unit, and a program stored executable to perform a task instruction memory, etc. This phrase is not used in this article to refer to an intangible thing.

In some cases, various units/circuits/components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured to" perform such tasks/operations, even if not specifically mentioned.

The term "configured to" is not intended to mean "configurable to". For example, an FPGA that has not been programmed will not be considered "configured to" perform a specific function. However, the unprogrammed FPGA may be "configurable to" perform this function. After being properly programmed, the FPGA can then be claimed to be "configured to" perform a specific function.

For the purposes of a U.S. patent application based on this disclosure, stating in a claim that a structure is "configured to" perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112(f) for that claim element to interpret. If the applicant intended to invoke Section 112(f) during prosecution of a US patent application based on the present disclosure, the claim elements would be stated using the phrase "means for "performing a function"."

Various "circuits" may be described in this disclosure. These circuits or "circuitry" constitute hardware that includes various types of circuit elements, such as combinational logic, clocked storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, Memory (eg, Random Access Memory, Embedded Dynamic Random Access Memory), Programmable Logic Array, etc. Circuitry can be custom designed or taken from standard libraries. In various implementations, the circuitry may include digital components, analog components, or a combination of both, as desired. Certain types of circuits are often referred to as "units" (eg, decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such units are also referred to as circuits or circuitry.

Accordingly, the disclosed circuits/units/components and other elements shown in the drawings and disclosed herein include hardware elements such as those described in the preceding paragraphs. In many instances, the internal configuration of hardware elements within a particular circuit can be specified by describing the function of that circuit. For example, a specific "decode unit" may be described as executing "processing an opcode of an instruction and routing that instruction" to one or more of a plurality of functional units. to one or more of a plurality of functional units), which means that the decoding unit is "configured to (configured to)" to perform this function. The description of this function is sufficient for those with ordinary knowledge in the field of computer technology to imply a set of possible configurations for the circuit.

In various embodiments, as discussed in the preceding paragraphs, circuits, units, and other elements may be defined by the functions or operations they are configured to perform. The configuration and the manner in which such circuits/units/components and the like interact with each other form the microarchitecture definition of the hardware that is ultimately fabricated in an integrated circuit or programmed into an FPGA to form the microarchitecture definition The physical implementation plan. Thus, the micro-hierarchical definition is a structure recognized by those of ordinary skill in the art as a structure from which many physical implementations can be derived, all of which fall within the broad structure described by the micro-hierarchical definition. That is, a person of ordinary knowledge who proposes the definition of micro-hierarchy provided by the present disclosure can, without undue experimentation and with the application of common knowledge, by using a hardware description language (hardware description language, HDL) (such as Verilog or VHDL) to encode a description of the circuit/unit/component to implement the structure. HDL descriptions are often expressed in a way that can be functional. But to those of ordinary skill in the art, the HDL description is the means by which the structure of a circuit, unit, or component is transformed into the next level of implementation detail. Such an HDL description can take the form of behavioral code (which is generally not synthesizable), register transfer language (RTL) code (which is generally synthesizable, as opposed to behavioral code), or structural program code (for example, a wiring comparison table specifying logic gates and their connectivity). HDL descriptions can then be synthesized from a library of components designed for a given IC fabrication technology, and can be modified for timing, power, and other reasons to produce a final design database that is sent to manufacturing The factory makes masks and finally produces integrated circuits. Some hardware circuits or parts thereof can also be customized in a schematic editor and transferred to the integrated circuit design along with the synthesized circuit system. An integrated circuit may include transistors and other circuit elements (eg, passive elements such as capacitors, resistors, inductors, etc.) and interconnects between the transistors and the circuit elements. Some embodiments may implement multiple integrated circuits coupled together to implement a hardware circuit, and/or may use discrete components in some embodiments. Alternatively, the HDL design can be synthesized to a programmable logic array, such as a field programmable gate array (FPGA), and implemented in the FPGA. The decoupling between the design of this group of circuits and the subsequent underlying implementation of these circuits often results in situations where the circuit or logic designer never targets the underlying implementation when the process is executed at a different stage of the circuit implementation process. A scheme specifies a particular set of structures that go beyond a description that a circuit is configured to perform an action.

In fact, many different underlying combinations of circuit elements can be used to implement the same specification circuit, resulting in a large number of equivalent structures for the circuit. As mentioned, these underlying circuit implementations may vary according to variations in manufacturing technology, the foundry selected to manufacture the integrated circuit, the library of components provided for a particular project, and the like. In many cases, the choice of different design tools or methodologies to produce these different implementations may be arbitrary.

Furthermore, it is common for a single implementation of a particular functional specification of a circuit to include a large number of devices (eg, millions of transistors) for a given embodiment. Accordingly, the sheer volume of this information makes it impractical to provide a complete statement of the underlying structure for implementing a single embodiment, let alone a vast array of equivalently feasible implementations. For this reason, this disclosure describes circuit structures using functional shorthand commonly employed in the industry.

Numerous changes and modifications will become apparent to those of ordinary skill in the art once the above disclosure has been fully appreciated. It is intended that the following claims be construed to cover all such changes and modifications.

110: System Single Chip (SOC) 110': System on Chip (SOC) 110": System-on-Chip (SOC) 120: memory 122: Memory controller 124: serial controller 130: global power control circuit 132: trigger logic circuit; trigger logic 134: Rate control circuit 140: Power Management Unit (PMU) 142:Voltage regulator 142A: Voltage Regulator 142B: voltage regulator 142C: voltage regulator 144: Power delivery trigger circuit 144A: Power delivery trigger circuit 144B: Power delivery trigger circuit 144C: Power delivery trigger circuit 146: Serial power transmission trigger circuit 146A: Serial power delivery trigger circuit 146B: Serial power delivery trigger circuit 146C: Serial Power Delivery Trigger Circuit 150: processor cluster 152: Processor (P) 154: Coprocessor 160: Graphics Processing Unit (GPU) 170: Communication structure 180: Peripheral equipment 500: memory controller pipeline; pipeline 510: rate limiter 510A: Rate Limiter 510B: Rate Limiter 510C: Rate Limiter 510D: Rate Limiter 520: Label and catalog tube 525: Memory arbiter 530:Memory cache 540A: Request Buffer 540B: Response buffer 540C: request buffer 540D: Response buffer 550: communication interface 550A: communication interface 550B: communication interface 560:Data pipe queue 565A: Read arbiter 565B: Write to the arbiter 570:Memory Queue 580: Memory output buffer 590B: output arbiter 590D: output arbiter 595:Cache data memory 600:Rate limiter interface toolset 610: Rate limiter pattern generation 612: Pattern Arbiter 614: Model temporary register 616:Indicator 620: Local activity detection 622: shift register 624: Activity counter 626: Active Threshold Comparator 630: Rate limiter control 632:Enable arbiter 700: Power management circuit (PMGR) 702: Telemetry table 704: Power Management Processor (PMP) 710: power budget control code; power budget; code 720A: Power control circuit (PwrCtl) 720B: Power control circuit (PwrCtl) 720C: Power control circuit (PwrCtl) 722A: Electricity budget; budget 722B: Electricity budget; budget 722C: Electricity budget; budget 800:Global Power Management Mechanism 802: PMP/power budget control mechanism 804: CPU-based power control 900: Hierarchical power transmission system 900A: electric control window; window 900B: electric control window; window 900N: electric control window; window 902: CPU power control window 1000: block 1002: Decision block 1004: block 1006: block 1100: method 1102: block 1104: block 1106: block 1108: block 1110: block 1200: method 1202: block 1204: block 1206: block 1300: system 1310: Hierarchical power transmission system 1312:First power converter class; power converter class 1314:Second Power Converter Class; Power Converter Class 1320: computing element 1322: Integrated circuit (IC or SOC) 1322-1:IC 1322-2:IC 1322-N:IC 1400: Manufacturing Systems 1420: Computer-readable media 1440: Computer system 1445: Manufacturing Systems 1450: Instruction/Description 1500: system 1502: external memory; memory 1504: peripheral equipment 1506: System on a Chip (SoC) 1508: Electricity supply 1510: Desktop computer 1520: Laptop 1530: Tablet PC 1540: cellular or mobile phone 1550: TV 1560: Smart Watch/Health Monitoring Device 1570: Cloud-based services

The features and advantages of the methods and apparatus of embodiments of the present disclosure will be further enhanced by reference to the following detailed description of a presently preferred but illustrative embodiment of embodiments of the present disclosure together with the accompanying drawings. fully understood, where:

[FIG. 1] is a block diagram of one embodiment of a system including a system-on-chip (SOC) coupled to memory and a power management unit (PMU). [Fig. 2] is a block diagram of an embodiment of the PMU. [Fig. 3] is a block diagram of another embodiment of the PMU. [Fig. 4] is a block diagram of an embodiment of the global power control circuit. [FIG. 5] is a block diagram of one embodiment of a memory controller pipeline. [FIG. 6] is a block diagram of one embodiment of a rate limiter interface toolset. [FIG. 7] is a block diagram of another embodiment of a system-on-chip (SOC). [Fig. 8] is a block diagram of an embodiment of the power management mechanism. [Fig. 9] is a timing diagram showing the power control window. [FIG. 10] is a flowchart illustrating an embodiment of operating a power management processor. [ FIG. 11 ] is a flowchart illustrating a method for power reduction in integrated circuits according to some embodiments. [ FIG. 12 ] is a flowchart illustrating another method for power reduction in integrated circuits, according to some embodiments. [ Fig. 13 ] is a block diagram of an embodiment of a power transmission system. [FIG. 14] is a block diagram illustrating an embodiment of a computer system, a computer readable medium, and a manufacturing system. [FIG. 15] is a block diagram of one embodiment of the example system.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one of ordinary skill in the art would recognize that aspects of the disclosed embodiments may be practiced without these specific details. In some instances, well-known circuits, structures, signals, computer program instructions, and techniques have not been shown in detail to avoid obscuring the disclosed embodiments.

110: System Single Chip (SOC)

120: memory

122: Memory controller

130: global power control circuit

140: Power Management Unit (PMU)

150: processor cluster

152: Processor (P)

154: Coprocessor

160: Graphics Processing Unit (GPU)

170: Communication structure

180: Peripheral equipment

700: Power management circuit (PMGR)

702: Telemetry table

704: Power Management Processor (PMP)

710: Power budget control code

720A: Power control circuit (PwrCtl)

720B: Power control circuit (PwrCtl)

722A: Electricity Budget

722B: Electricity Budget

722C: Power Budget

Claims (20)

An integrated circuit comprising: a plurality of components, wherein a given one of the plurality of components is configured to manage power consumption based on a budget assigned to the given component; a global power control circuit coupled to the plurality of components and configured to apply power control across the plurality of components in response to a trigger input to the integrated circuit; and a power management circuit configured to: detecting whether the power control applied by the global power control circuit exceeds a threshold; and A budget amount assigned to at least one of the plurality of components is decreased based on a detection that the power control applied by the global power control circuit exceeds the threshold. The integrated circuit of claim 1, wherein the threshold comprises a percentage of time that the power control is applied by the global power control circuit. The integrated circuit of claim 2, wherein the power management circuit is configured to measure a percentage of time within a fixed time window. The integrated circuit of claim 3, wherein the power management circuit is configured to detect a percentage during a first instance of the fixed time window and is configured to decrease for a next instance of the fixed time window The budget amount of , where the next instance is a continuation of the first instance. The integrated circuit of claim 4, wherein the power management circuit is configured to reduce the amount of budget to a first component of the plurality of components in a given fixed time window and reduce another given fixed time window A budget amount to a second component of the plurality of components in the time window. The integrated circuit of claim 3, wherein at least one of the components includes one or more central processing unit (CPU) processors, and wherein the CPUs are configured to execute a second plurality of instructions for use Dynamic voltage and frequency control implements power control in the IC. The integrated circuit of claim 6, wherein the second plurality of instructions implement power control within a second fixed time window greater than the fixed time window. The integrated circuit of claim 7, wherein the second fixed time window is one or more orders of magnitude longer than the fixed time window. The integrated circuit according to claim 7, wherein the second fixed time window is an integer multiple of the fixed time window. The integrated circuit of claim 1, wherein the power management circuit is configured to: detecting that the power control applied by the global power control circuit is less than the threshold; and A budget amount assigned to at least one of the plurality of components is increased based on a detection that the power control applied by the global power control circuit exceeds the threshold. The integrated circuit of claim 10, wherein the budget increase is limited to a maximum amount for the at least one of the plurality of components. The integrated circuit of claim 10, wherein the power management circuit is configured to apply hysteresis when changing between increasing the budget amount and decreasing the budget amount. The integrated circuit of claim 1, wherein the power management circuit includes a power management processor and a memory coupled to the power management processor storing a plurality of instructions, the plurality of instructions being executed by the power management processor When executed, causes the power management processor to perform operations including the operations described above for the power management circuit. A system comprising: An integrated circuit comprising: a plurality of components, wherein a given one of the plurality of components is configured to manage power consumption based on a budget assigned to the given component; a global power control circuit coupled to the plurality of components and configured to apply power control across the plurality of components in response to a trigger input to the integrated circuit; and a power management circuit configured to: detecting whether the power control applied by the global power control circuit exceeds a threshold; and reducing the budget amount assigned to at least one of the plurality of components based on a detection that the power control applied by the global power control circuit exceeds the threshold; and A power management unit coupled to the integrated circuit, wherein the power management unit is configured to supply power to the integrated circuit and generate the trigger input. The system of claim 14, wherein the power management circuit is configured to: detecting that the power control applied by the global power control circuit is less than the threshold; and A budget amount assigned to at least one of the plurality of components is increased based on a detection that the power control applied by the global power control circuit exceeds the threshold. The system of claim 15, wherein the increase in the budget amount is limited to a maximum amount for the at least one of the plurality of components. The system of claim 14, wherein the threshold comprises a percentage of time that the power control is applied by the global power control circuit. The system of claim 17, wherein the power management circuit is configured to measure a percentage of time within a fixed time window. The system of claim 18, wherein the power management circuit is configured to detect a percentage during a first instance of the fixed time window and is configured to reduce a budget for a next instance of the fixed time window amount, where the next instance is the continuation of the first instance. A non-transitory computer readable medium storing instructions for a power management processor in a power management circuit of an integrated circuit, the integrated circuit also comprising a plurality of components, wherein one of the plurality of components A given component is configured to manage power consumption based on a budget assigned to the given component, and the integrated circuit further includes a global power control circuit configured to respond to the A trigger input of a bulk circuit applies power control across the plurality of components, and wherein the plurality of instructions, when executed by the power management processor, cause the power management processor to perform operations comprising: detecting whether the power control applied by the global power control circuit exceeds a threshold; and A budget amount assigned to at least one of the plurality of components is decreased based on a detection that the power control applied by the global power control circuit exceeds the threshold.

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