TW202314688A - Semiconductor memory apparatus - Google Patents

Abstract

A semiconductor memory apparatus including a memory cell array, a switch circuit and a sensing circuit is provided. The memory cell array includes a plurality of memory cells. The switch circuit includes at least one switch. Each switch receives a control signal and is turned on or off under control of the control signal. When performing erase verification, the sensing circuit sequentially receives erase verification currents generated by each memory cell through the switch circuit to verify an erase state of each memory cell.

Description

semiconductor memory device

The present invention relates to a memory device, and in particular to a semiconductor memory device for storing option bits or status bits required for chip power-up.

In memory products, there are some mini-arrays for storing option bits or status bits outside the main memory (main memory). The option bit or status bit is information necessary for the operation of the memory, such as related parameters that can determine the operation. These necessary information will be read during power-on of the memory product. Typically, the read voltage applied to the bit lines in the mini-array needs to be controlled to correctly read the option bit or status bit from the memory cell.

In order to provide a stable voltage source, a bandgap reference (BGR) circuit is widely used in memory products. A BGR circuit is a voltage reference circuit that generates a substantially constant voltage regardless of power supply changes, temperature changes, and circuit load changes from on-chip devices or off-chip devices. When the memory product is powered on, the BGR circuit can be used to generate a reference voltage. At this time, the charge pump circuit can generate a read voltage applied to the bit line according to the reference voltage, so as to read the option bit or the status bit from the memory cell.

However, during power-up, since the supply voltage (VCC) may be unstable, the BGR circuit cannot yet accurately provide a reference voltage. Therefore, there is no guarantee that the charge pump circuit can generate a predetermined read voltage according to the reference voltage. The read voltage may not reach the target value, resulting in an error in reading the option bit or status bit.

The invention provides a semiconductor memory device, which can correctly read the information of the option bit or the status bit during power-on.

The semiconductor memory device of the present invention includes a memory cell array, a switch circuit and a sensing circuit. The memory cell array includes a plurality of memory cells. The switch circuit is coupled to the memory cell array and includes at least one switch. Each switch receives a control signal and is turned on or off under the control of the control signal. The sensing circuit is coupled to the switch circuit. When erasing verification is performed, the sensing circuit sequentially receives the erasing verification current generated by each memory unit cell through the switch circuit, so as to verify the erasing state of each memory unit cell.

Based on the above, when the option bit or the status bit is read during power-on, the sensing circuit can simultaneously receive at least two read currents generated from the memory cell. Therefore, the problem that the read current is reduced due to the read voltage not reaching the target value can be solved, and the margin of the read operation is increased, so that the option bit or the status bit can be read correctly.

FIG. 1 is a schematic block diagram of a semiconductor memory device according to an embodiment of the invention. FIG. 2 is a schematic circuit diagram of a semiconductor memory device according to an embodiment of the invention. Please refer to FIG. 1 and FIG. 2 at the same time. The semiconductor memory device 100 includes a memory cell array 110 , a switch circuit 120 and a sensing circuit 130 . The memory cell array 110 includes memory cells C0 and C1. In this embodiment, the memory cell array 110 is, for example, a mini-array (mini-array) in a NOR flash memory, and the memory cells C0 and C1 are, for example, used to store option bits or status bits.

As shown in FIG. 2 , the memory cells C0 and C1 are commonly coupled to the word line WL0 , and are respectively coupled to the switch circuit 120 and the sensing circuit 130 through different bit lines BL0 and BL1 . In order to facilitate understanding, in this embodiment, two memory cells are used for illustration, but the present invention is not limited thereto, as long as the memory cells are jointly coupled to a word line, and are respectively connected via different For the circuit structure in which the bit line is coupled to the sensing circuit, those skilled in the art can analogize the number of memory cells used to more according to the teaching of the present invention according to their actual needs.

The switch circuit 120 is coupled to the memory cell array 110 . The switch circuit 120 includes switches SW0 and SW1. The switch SW0 is disposed on the bit line BL0 and coupled between the memory cell C0 and the sensing circuit 130 . The switch SW1 is disposed on the bit line BL1 and coupled between the memory cell C1 and the sensing circuit 130 .

The switches SW0 and SW1 receive control signals Y0 and Y1 respectively. The switch SW0 can be turned on or off under the control of the control signal Y0 . The switch SW1 can be turned on or off under the control of the control signal Y1. The switches SW0 and SW1 can be electronic components such as transistors. For example, when the control signal is at a high logic level (conduction level ONL), the switch controlled by it will be turned on. When the control signal is at a low logic level (off level OFFL), the switch controlled by it will be turned off. The on-level ONL is, for example, about 3 volts, and the off-level OFFL is, for example, about 0 volts. It should be noted that, in other embodiments, the control signal can also control the state of the switch according to the logic level in the opposite manner to the above, and the present invention is not limited thereto.

The sensing circuit 130 is coupled to the switch circuit 120 . The sensing circuit 130 includes, for example, a circuit composed of a sense amplifier (sense amplifier). The internal structure, circuit operation and implementation thereof can obtain sufficient teachings, suggestions and implementation descriptions based on common knowledge in the technical field.

In this embodiment, when performing erase verification, the sensing circuit 130 can sequentially receive the erase verification current IEV0 generated by the memory cell C0 and the erase current IEV0 generated by the memory cell C1 through the switch circuit 120 . In addition to verifying the current IEV1, the erasing state of each memory cell C0 and C1 is verified.

In order to describe in detail the operation modes of the erasing operation, erasing verification and reading operation in this embodiment, please refer to FIGS. 3A to 3E for description below.

FIG. 3A is an operation schematic diagram of an erase operation of a semiconductor memory device according to an embodiment of the invention. Please refer to FIG. 3A , when an erase operation is performed, the switches SW0 and SW1 are turned off based on the control signals Y0 and Y1 of the off-level OFFL, and the memory cells C0 and C1 are turned off based on the erase operation applied to the word line WL0. erase voltage VES at the same time. The erase voltage VES is, for example, about -9 volts. In this way, the data stored in the memory cells C0 and C1 will become, for example, a bit “1” after erasing, so as to complete the erasing operation.

FIG. 3B is a schematic diagram of an erase verification operation of a semiconductor memory device according to an embodiment of the invention. FIG. 3C is a signal timing diagram of erase verification of the semiconductor memory device according to an embodiment of the invention. Please refer to FIG. 3B and FIG. 3C at the same time. As shown in FIG. 3B , when erasing verification is performed, the erasing verification voltage VEV is applied to the word line WL0 and the control signals Y0 and Y1 of the conduction level ONL are sequentially applied. To the switches SW0 and SW1 , the sensing circuit 130 sequentially receives the erase verification currents IEV0 and IEV1 generated by the memory cells C0 and C1 (as shown from left to right in FIG. 3B ). The erase verification voltage VEV is about 6 volts, for example. In other words, the memory cells C0 and C1 respectively generate verification currents IEV0 and IEV1 based on the erase verification voltage VEV applied to the word line WL0 . And as shown in FIG. 3C , the control signal Y0 will change from the OFF level OFFL to the ON level ONL at the time point t1, so that the switch SW0 is turned on and the sensing circuit 130 receives the erasing generated by the memory cell C0. Verify current IEV0. Next, the control signal Y1 changes from the off level OFFL to the on level ONL at the time point t2, so that the switch SW1 is turned on so that the sensing circuit 130 receives the erase verification current IEV1 generated by the memory cell C1.

In this way, the sensing circuit 130 can sequentially receive the erase verification current IEV0 generated by the memory cell C0 and the erase verification current IEV1 generated by the memory cell C1, and respectively compare the erase verification currents IEV0 and IEV1 with the reference The currents are compared to complete the erase verification for the memory cells C0 and C1 respectively. The reference current is, for example, 5 microamperes. For example, taking the erase verification current IEVO as an example, when the erase verification current IEVO is greater than the reference current, it means that the memory cell C0 has passed the erase verification. When the erase verification current IEV0 is not greater than the reference current, it means that the memory cell C0 fails the erase verification.

FIG. 3D is an operation schematic diagram of a read operation of the semiconductor memory device according to an embodiment of the present invention. FIG. 3E is a signal timing diagram of a read operation of the semiconductor memory device according to an embodiment of the invention. The read operation in this embodiment is, for example, a read operation performed during power-on of the semiconductor memory device 100 . Please refer to FIG. 3D and FIG. 3E at the same time. As shown in FIG. 3D , when the read operation is performed, the read voltage VR is applied to the word line WL0 and the control signals Y0 and Y1 of the conduction level ONL are applied to the switch at the same time. SW0 and SW1, the sensing circuit 130 can simultaneously receive the read currents IR0 and IR1 generated by the memory cells C0 and C1 through the switches SW0 and SW1. In other words, the memory cells C0 and C1 respectively generate read currents IR0 and IR1 based on the read voltage VR applied to the word line WL0 . And as shown in FIG. 3E , the control signals Y0 and Y1 change from the off level OFFL to the on level ONL at the time point t3 , so that the switch SW0 and the switch SW1 are turned on at the same time. The target value of the read voltage VR is, for example, about 6 volts, but is usually less than the target value during power-up.

In this way, the sensing circuit 130 can simultaneously receive the read currents IR0 and IR1 generated by the memory cells C0 and C1, and combine the summed current (IR0+IR1) and A reference current (for example, 5 microamperes) is compared to complete the read operation. For example, when the total current obtained by summing the read currents IR0 and IR1 is greater than the reference current, it means that the erased data stored in the memory cells C0 and C1 (for example, bit "1"). When the total current obtained by summing the reading currents IR0 and IR1 is not greater than the reference current, it means that the data stored in the memory cells C0 and C1 that have not been erased (for example, bit "0") has been read. ").

FIG. 4 is a schematic circuit diagram of a semiconductor memory device according to another embodiment of the present invention. Please refer to FIG. 4 , the semiconductor memory device 200 includes a memory cell array 210 , a switch circuit 220 and a sensing circuit 230 . The memory cell array 210 includes memory cells C2 and C3. In this embodiment, the memory cell array 210 is, for example, a mini-array (mini-array) in a NOR flash memory, and the memory cells C2 and C3 are, for example, used to store option bits or status bits, but the present invention is not limited thereto.

As shown in FIG. 4 , the memory cells C2 and C3 are respectively coupled to different word lines WL2 and WL3 , and are coupled to the switch circuit 220 and the sensing circuit 230 through a common bit line BL2 . In order to facilitate understanding, two memory cells are used for illustration in this embodiment, but the present invention is not limited thereto, as long as the memory cells are respectively coupled to different word lines and connected via a common For the circuit structure in which the bit line is coupled to the sensing circuit, those skilled in the art can analogize the number of memory cells used to more according to the teaching of the present invention according to their actual needs.

The switch circuit 220 is coupled to the memory cell array 210 . The switch circuit 220 includes a switch SW2. The switch SW2 is disposed on the bit line BL2 and coupled between the memory cells C2 and C3 and the sensing circuit 230 .

The switch SW2 receives the control signal Y2. The switch SW2 can be turned on or off under the control of the control signal Y2. The switch SW2 can be an electronic component such as a transistor. For example, when the control signal is at a high logic level (conduction level ONL), the switch controlled by it will be turned on. When the control signal is at a low logic level (OFFL), the switch controlled by it will be turned off. It should be noted that, in other embodiments, the control signal can also control the state of the switch according to the logic level in the opposite manner to the foregoing, and the present invention is not limited thereto.

The sensing circuit 230 is coupled to the switch circuit 220 . The sensing circuit 230 is, for example, a circuit composed of a sense amplifier (sense amplifier), and its internal structure, circuit operation and implementation may be the same as the sensing circuit 130 of the foregoing embodiment, for example.

In this embodiment, when performing erase verification, the sensing circuit 230 can sequentially receive the erase verification current IEV2 generated by the memory cell C2 and the erase current IEV2 generated by the memory cell C3 through the switch circuit 220 . In addition to verifying the current IEV3, the erasing state of each memory cell C2 and C3 is verified.

In order to describe in detail the operation modes of the erasing operation, erasing verification and reading operation in this embodiment, please refer to FIGS. 5A to 5C for description below.

FIG. 5A is an operation schematic diagram of an erase operation of a semiconductor memory device according to an embodiment of the present invention. Please refer to FIG. 5A , when performing an erase operation, the switch SW2 will be turned off based on the control signal Y2 of the off level OFFL, and the memory cells C2 and C3 will be based on the erase voltage applied to the word lines WL2 and WL3 VES while erasing. In this way, the data stored in the memory cells C2 and C3 will become, for example, a bit “1” after erasing, so as to complete the erasing operation.

FIG. 5B is a schematic diagram of an erase verification operation of a semiconductor memory device according to an embodiment of the present invention. Referring to FIG. 5B , when erasing verification is performed, the sensing circuit 230 is sequentially applied to the word lines WL2 and WL3 by applying the erasing verification voltage VEV to the word lines WL2 and WL3 and applying the control signal Y2 of the conduction level ONL to the switch SW2. The erase verification currents IEV2 and IEV3 generated by the memory cells C2 and C3 are sequentially received (as shown from left to right in FIG. 5B ). In other words, during the period when the control signal Y2 changes from the off level OFFL to the on level ONL to turn on the switch SW2, the erase verification voltage VEV will first be applied to the word line WL2 (the voltage V0 is applied to the word line WL2 at this time). line WL3 ), so that the sensing circuit 230 receives the erase verification current IEV2 generated by the memory cell C2 . Next, the erase verification voltage VEV is applied to the word line WL3 (the voltage V0 is applied to the word line WL2 at this time), so that the sensing circuit 230 receives the erase verification current IEV3 generated by the memory cell C3. The voltage V0 is, for example, about 0 volts.

In this way, the sensing circuit 230 can sequentially receive the erase verification current IEV2 generated by the memory cell C2 and the erase verification current IEV3 generated by the memory cell C3, and respectively compare the erase verification currents IEV2 and IEV3 with the reference The currents are compared to complete the erase verification for the memory cells C2 and C3 respectively. For example, taking the erase verification current IEV2 as an example, when the erase verification current IEV2 is greater than the reference current, it means that the memory cell C2 has passed the erase verification. When the erase verification current IEV2 is not greater than the reference current, it means that the memory cell C2 fails the erase verification.

FIG. 5C is an operation schematic diagram of a read operation of the semiconductor memory device according to an embodiment of the invention. The read operation in this embodiment is, for example, a read operation performed during power-on of the semiconductor memory device 100 . Referring to FIG. 5C , when performing a read operation, by simultaneously applying the read voltage VR to the word lines WL2 and WL3 and applying the control signal Y2 of the conduction level ONL to the switch SW2, the sensing circuit 230 can pass the switch SW2 At the same time, the read currents IR2 and IR3 generated by the memory cells C2 and C3 are received. In other words, the memory cells C2 and C3 generate read currents IR2 and IR3 respectively based on the read voltage VR applied to the word lines WL2 and WL3 . Moreover, the control signal Y2 changes from the off level OFFL to the on level ONL, so that the switch SW2 is turned on.

In this way, the sensing circuit 130 can simultaneously receive the read currents IR2 and IR3 generated by the memory cells C2 and C3, and combine the total current (IR2+IR3) and The reference current is compared to complete the read operation. For example, when the total current obtained by summing the read currents IR2 and IR3 is greater than the reference current, it means that the erased data stored in the memory cells C2 and C3 (for example, bit "1"). When the total current obtained by summing the read currents IR2 and IR3 is not greater than the reference current, it means that the data stored in the memory cells C2 and C3 that have not been erased (for example, bit "0") has been read. ").

Through the above operations, when the option bit or the status bit is read during power-on, the sensing circuit can receive at least two read currents. Even if the read voltage applied to the word line does not reach the target value and the read current decreases, the reduced part can be compensated by summing at least two read currents to increase the margin of the read operation, thereby Read option bits or status bits correctly.

To sum up, the semiconductor memory device of the present invention can solve the problem that the read current is reduced due to the read voltage not reaching the target value, so as to correctly read the option bit or the status bit during power-on.

100, 200: semiconductor memory device 110, 210: memory cell array 120, 220: switch circuit 130, 230: sensing circuit BL0, BL1, BL2: bit lines C0, C1, C2, C3: memory cell IEV0, IEV1, IEV2, IEV3: erase verification current IR0, IR1, IR2, IR3: read current OFFL: off level ONL: conduction level SW0, SW1, SW2: switch V0: Voltage VES: erase voltage VEV: erase verification voltage VR: read voltage WL0, WL2, WL3: word line Y0, Y1, Y2: control signal

FIG. 1 is a schematic block diagram of a semiconductor memory device according to an embodiment of the invention. FIG. 2 is a schematic circuit diagram of a semiconductor memory device according to an embodiment of the invention. FIG. 3A is an operation schematic diagram of an erase operation of a semiconductor memory device according to an embodiment of the invention. FIG. 3B is a schematic diagram of an erase verification operation of a semiconductor memory device according to an embodiment of the invention. FIG. 3C is a signal timing diagram of erase verification of the semiconductor memory device according to an embodiment of the invention. FIG. 3D is an operation schematic diagram of a read operation of the semiconductor memory device according to an embodiment of the present invention. FIG. 3E is a signal timing diagram of a read operation of the semiconductor memory device according to an embodiment of the invention. FIG. 4 is a schematic circuit diagram of a semiconductor memory device according to another embodiment of the present invention. FIG. 5A is an operation schematic diagram of an erase operation of a semiconductor memory device according to an embodiment of the present invention. FIG. 5B is a schematic diagram of an erase verification operation of a semiconductor memory device according to an embodiment of the present invention. FIG. 5C is an operation schematic diagram of a read operation of the semiconductor memory device according to an embodiment of the invention.

100:Semiconductor memory device

110: memory cell array

120: switch circuit

130: sensing circuit

Claims (10)

A semiconductor memory device, comprising: A memory cell array, including a plurality of memory cells; A switch circuit, coupled to the memory cell array, including at least one switch, each of the at least one switch receives a control signal, and is controlled by the control signal to be turned on or off; and A sensing circuit, coupled to the switch circuit, when performing an erasing verification, the sensing circuit sequentially receives an erasing verification current generated by each of the memory cells through the switching circuit, so as to perform an erasing verification current on each of the memory cells The erased state of the unit cell is verified. The semiconductor memory device as claimed in claim 1, wherein the memory cells are coupled to at least one word line, and when an erase operation is performed, the memory cells are based on the voltage applied to the at least one word line The erasing is performed at the same time as erasing the voltage. The semiconductor memory device according to claim 1, wherein when performing a read operation, the sensing circuit simultaneously receives a read current generated by each of the memory cells through the switch circuit. The semiconductor memory device as claimed in claim 1, wherein the memory cells are commonly coupled to a word line, and are respectively coupled to the switch circuit and the sensing circuit via different bit lines, Each of the at least one switch is disposed on the corresponding bit line and coupled between the corresponding memory unit cell and the sensing circuit. The semiconductor memory device according to claim 4, wherein when performing the erase verification, by applying an erase verification voltage to the word line and sequentially applying the control signal of a turn-on level to the at least one switch , making the sensing circuit sequentially receive the erase verification current generated by each of the memory cells. The semiconductor memory device according to claim 5, wherein the at least one switch includes a first switch and a second switch, and the bit lines include a first bit line and a second bit line, the first bit line A switch is disposed on the first bit line, and the second switch is disposed on the second bit line. When performing the erase verification, the semiconductor memory device sequentially applies the control signal of the conduction level to the first switch and the second switch, so that the sensing circuit sequentially receives the erase verification current generated by each of the memory cells. The semiconductor memory device as claimed in claim 1, wherein the memory cells are respectively coupled to different multiple word lines, and are coupled to the switch circuit and the sensing circuit via a common bit line, The at least one switch is disposed on the bit line and coupled between the memory cells and the sensing circuit. The semiconductor memory device according to claim 7, wherein when performing the erase verification, by sequentially applying an erase verification voltage to the word lines and applying the control signal of the conduction level to the at least one The switch enables the sensing circuit to sequentially receive the erasing verification current generated by each of the memory cells. The semiconductor memory device according to claim 8, wherein the word lines include a first word line and a second word line, and when performing the erase verification, the erase verification voltage is first applied to The first word line, so that the sensing circuit receives the erasing verification current generated by the memory cell coupled to the first word line, and then the erasing verification voltage is applied to the first word line the second word line, so that the sensing circuit receives the erase verification current generated by the memory cell coupled to the second word line. The semiconductor memory device as claimed in claim 1, wherein the memory cell array is a mini-array in an NOR flash memory, and the memory cells are used to store option bits or status bits .

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