TW202312493A - Transistor structure and related manufacture method - Google Patents

Abstract

A transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region, and a first isolation region. The semiconductor substrate has a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. The first isolation region is next to the first conductive region. A length of the first conductive region is controlled by a single photolithography process which is originally configured to define the length of the gate structure.

Description

Transistor structure and related manufacturing method

The present invention relates to a transistor structure and its related manufacturing method, especially to a transistor structure and its related manufacturing method which can accurately control the length of the source/drain and the contact opening to effectively reduce the size.

Because in 1974, in the paper published by R. Dennard et al., the design criteria for reducing all the dimensions of the metal-oxide-semiconductor field-effect transistor (MOSFET) were disclosed, so how Reducing the size of transistors has become a major technical requirement that has changed the linear dimensions of silicon wafers from a few micrometers down to a few nanometers in minimum feature size. This minimum feature size or length is usually referred to as Lamda (λ), which is determined by the miniaturization capability using photolithographic masking technology and component shrinking technology (for simplicity of illustration and comparison, by minimizing the printed line width analysis What is measured by degrees is also called λ). But another uncontrollable factor that limits the shrinkage of components is the misalignment tolerance caused by the inadequacy and inaccuracy of lithographic equipment, that is, Delta-Lamda (Δλ). In addition, because of the misalignment tolerance, it is difficult to make the distance between the gate edge to the source (or drain) edge of the transistor smaller than the sum of λ and Δλ. Afterwards, if it is necessary again to make a square contact hole on the drain (or source) by using the photolithography mask technology as a connection between the future metal interconnection to the drain (or the source) , then the minimum size of each side of the contact hole is difficult to be smaller than λ. In addition, to ensure that the contact hole within the drain contains misalignment tolerances, the length of each side of the drain (with a rectangular periphery) is also difficult to achieve less than the sum of λ and Δλ. However, reducing the size of transistors is necessary to integrate more transistors in one planar area of a silicon wafer, and reducing the areas occupied by the transistor's drain and source respectively is one of the ways to achieve the above goals. Necessary and effective way, it also helps to reduce leakage current and power consumption.

An embodiment of the present invention discloses a method for manufacturing a transistor, wherein the transistor includes a gate structure and a first conductive region. The manufacturing method includes forming an active region on a substrate; forming the gate structure and a dummy shield gate structure (dummy shield gate structure) over the active region; forming a first isolation region to replace the dummy shield gate structure structure; forming a self-alignment pillar over the active region; and removing the self-alignment pillar, and forming the first conductive region between the gate structure and the first isolation region.

In another embodiment of the present invention, before the step of removing the self-aligned pillar, the manufacturing method further includes forming a second isolation region above the first isolation region, wherein the self-aligned pillar is located at the gate pole structure and the second isolation region.

In another embodiment of the present invention, after the step of removing the self-aligned pillar, the manufacturing method further includes forming a spacer between the gate structure and the first isolation region to define a contact hole, Wherein the contact hole is located above the first conductive region.

In another embodiment of the present invention, the length of the contact hole is less than a minimum feature length.

In another embodiment of the present invention, the substrate is a silicon substrate, and the self-aligned pillar is an intrinsic silicon pillar formed by selective epitaxy growth.

Another embodiment of the present invention discloses a method for manufacturing a transistor, wherein the transistor includes a gate structure and a first conductive region. The manufacturing method includes forming an active region on a substrate; forming the gate structure on the active region; and forming a self-aligned pillar, wherein the self-aligned pillar is used to distribute an contact holes.

In another embodiment of the present invention, the manufacturing method further includes forming an isolation region on the active region before forming the self-aligned pillar.

In another embodiment of the present invention, the manufacturing method further includes removing the self-aligned pillar, wherein the self-aligned pillar is formed between the gate structure and the isolation region; and between the gate structure and the isolation region. A spacer layer is formed between the isolation regions to define a contact hole, wherein the contact hole is located above the first conductive region.

In another embodiment of the present invention, the length of the contact hole is less than a minimum characteristic length.

Another embodiment of the present invention discloses a method for manufacturing a transistor, wherein the transistor includes a gate structure and a first conductive region. The manufacturing method includes forming an active region on a substrate; forming the gate structure above the active region; forming the first conductive region next to the gate structure; and defining a contact hole above the first conductive region, Wherein the definition of the contact hole is not related to a photolithography (photolithography) process.

In another embodiment of the present invention, the first conductive region is formed between the gate structure and an isolation region, wherein the isolation region extends upwardly above the active region.

In another embodiment of the present invention, the contact hole is defined by forming a spacer layer, wherein the spacer layer covers a sidewall of the gate structure and a sidewall of the isolation region.

In another embodiment of the present invention, the length of the contact hole is less than a minimum characteristic length.

Another embodiment of the present invention discloses a method for manufacturing a transistor, wherein the transistor includes a gate structure and a first conductive region. The manufacturing method includes performing a first photolithography process, wherein the first photolithography process is used to define the width of the gate structure and the length of an active region; performing a second photolithography process, wherein the second photolithography The process is used to define the length of the gate structure in the active region, wherein the second photolithography process is also used to define the length of the first conductive region.

In another embodiment of the present invention, the length of the first conductive region defined by the second photolithography process is equal to or substantially equal to a minimum feature length.

In another embodiment of the present invention, the length of the gate structure defined by the second photolithography process is equal to or substantially equal to a minimum feature length.

In another embodiment of the present invention, the length of the active region defined by the first photolithography process is approximately equal to 4 times a minimum feature length.

Another embodiment of the present invention discloses a method for manufacturing a transistor, wherein the transistor includes a gate structure and a first conductive region. The manufacturing method includes forming an active region on a substrate; forming the gate structure on the active region; forming the first conductive region next to the gate structure; and forming a contact hole above the first conductive region, The shape of the contact hole does not need to be defined by a photolithography process.

In another embodiment of the present invention, the first conductive region is formed between the gate structure and an isolation region.

In another embodiment of the present invention, the contact hole is defined by forming a spacer layer, wherein the spacer layer covers a sidewall of the gate structure and a sidewall of the isolation region.

In another embodiment of the present invention, the length of the contact hole is less than a minimum characteristic length.

Another embodiment of the present invention discloses a transistor structure. The transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region and a contact hole. The semiconductor base has a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. The contact hole is located above the first conductive region. Wherein the periphery of the contact hole is surrounded by the periphery of the first conductive region.

In another embodiment of the present invention, the periphery of the first conductive region is a rectangle.

In another embodiment of the present invention, the length of the contact hole is less than a minimum characteristic length.

Another embodiment of the present invention discloses a transistor structure. The transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region and a contact hole. The semiconductor base has a semiconductor surface. The channel region is located under the gate structure. The contact hole is located above the first conductive region. Wherein the length of the contact hole is less than a minimum characteristic length.

In another embodiment of the present invention, a horizontal distance between a sidewall of the gate structure and a sidewall of the contact hole is less than the minimum characteristic length, wherein the sidewall of the contact hole is away from the gate structure side wall.

In another embodiment of the present invention, a horizontal distance between a sidewall of the gate structure and a sidewall of the first conductive region is approximately equal to the minimum characteristic length, wherein the sidewall of the first conductive region is away from the sidewalls of the gate structure.

Another embodiment of the present invention discloses a transistor structure. The transistor structure includes a semiconductor base, a gate structure, a channel region, a first isolation region, a first spacer layer, a second spacer layer, a first conductive region and a first contact hole. The semiconductor base has a semiconductor surface. The gate structure has a length. The channel region is located under the semiconductor surface. The first isolation region extends upward and downward from the semiconductor surface. The first spacer layer covers a first sidewall of the gate structure, and the second spacer layer covers a sidewall of the first isolation region. The first conductive region is electrically coupled to the channel region and is located between the gate structure and the first isolation region. The first contact hole is formed between the first spacer layer and the second spacer layer.

In another embodiment of the present invention, the transistor structure further includes a capping layer and a first metal region. The covering layer covers the gate structure. The first metal region is filled in the first contact hole and contacts the first conductive region, the first metal region extends upward from the first conductive region to a predetermined position, wherein the predetermined position is higher than the top of the covering layer .

In another embodiment of the present invention, the width of the first metal region is substantially equal to the length of the first contact hole plus a minimum feature length.

In another embodiment of the present invention, the transistor structure further includes a second isolation region and a second conduction region. The second isolation region extends upward and downward from the semiconductor surface. The second conductive region is electrically coupled to the channel region and is located between the gate structure and the second isolation region.

In another embodiment of the present invention, a horizontal distance between a second sidewall of the gate structure and a sidewall of the second isolation region is substantially equal to a minimum feature length, wherein the first isolation region The sidewall is a sidewall away from the gate structure.

In another embodiment of the present invention, the transistor structure further includes a second contact hole. The second contact hole is located above the second conductive region, wherein the length of the second contact hole is less than a minimum feature length.

In another embodiment of the present invention, the transistor structure further includes a third spacer layer and a fourth spacer layer. The third spacer layer covers a second sidewall of the gate structure. The fourth spacer layer covers a sidewall of the second isolation region, wherein the second contact hole is formed between the third spacer layer and the fourth spacer layer.

Another embodiment of the present invention discloses a transistor structure. The transistor structure includes a semiconductor base, a gate structure, a channel region, a first conductive region and a first isolation region. The semiconductor base has a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. The first isolation region is located beside the first conductive region. The length of the first conductive region is controlled by a single photolithography process, and the single photolithography process is originally used to define the length of the gate structure.

In another embodiment of the present invention, the length of the first conductive region is equal to or substantially equal to a minimum characteristic length.

Another embodiment of the present invention discloses a transistor structure. The transistor structure includes a semiconductor base, a gate structure, a channel region, a first conductive region and a first contact hole. The semiconductor base has a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. Wherein the periphery of the first contact hole has nothing to do with a photolithography process.

In another embodiment of the present invention, the length of the first contact hole is less than a minimum characteristic length.

In another embodiment of the present invention, the length of the first conductive region is equal to or substantially equal to the minimum characteristic length.

In another embodiment of the present invention, the first contact hole is located above the first conductive region.

The present invention discloses a new method for accurately controlling the linear dimension of the source (or drain) of a transistor, wherein the dimension can be as small as the minimum feature dimension Lamda (λ), that is to say, the transistor does not need to add a misalignment tolerance Delta-Lamda (Δλ) is printed or fabricated on a wafer (such as a silicon wafer). Furthermore, a contact hole with a linear dimension smaller than λ can be realized in the drain (or source) of the transistor. Thus, the present invention results in a new source and drain structure with a minimum feature size from the edge of the gate structure of the transistor to the source (or drain) next to the edge of the transistor isolation region. pole) edge, and have contact holes with a linear dimension smaller than λ on the source and the drain. Therefore, the present invention can avoid the misalignment tolerance caused by the photolithography mask technology when forming the source electrode and the drain electrode respectively.

Please refer to Figure 1. FIG. 1 is a top view of a miniaturized metal oxide semiconductor field effect transistor 100 disclosed by an embodiment of the present invention. As shown in Figure 1, the metal oxide half field effect transistor 100 includes: (1) a gate structure 101, wherein the gate structure 101 has a length G (L) and a width G (W), (2) a gate structure On the left of 101 is a source 103, wherein the source 103 has a length S(L) and a width S(W), and the length S(L) is a linear dimension from the edge of the gate structure 101 to the edge of an isolation region 105 , (3) on the right side of the gate structure 101 is a drain 107, wherein the drain 107 has a length D (L) and a width D (W), and the middle length D (L) is from the edge of the gate structure 101 to A linear dimension of the edge of the isolation region 105, (4) in the center of the source electrode 103 is a contact hole 109 formed by self-alignment technology, wherein the length and width of the contact hole 109 are respectively C-S (L) and C-S(W) C-D(W).

To form the metal oxide semiconductor field effect transistor 100, a first photolithography process can be used to define the width G (W) and a pseudo length (pseudo length) of the active region, and a second photolithography process can be used to define the width G (W) in the active region. The length G(L) in the active region, wherein the second photolithography process can be used to control the length S(L) between the gate structure 101 and the isolation region 105, in an embodiment of the present invention, through the The pseudo-length of the active region defined by the first photolithography process is about 4 times of the minimum characteristic length λ. In an embodiment of the present invention, the length G(L) may be equal to or substantially equal to the minimum characteristic length λ. Of course, in other embodiments, the length G(L) may be greater than the minimum characteristic length λ.

The first feature of the present invention is that both the length S(L) and the length D(L) can be accurately designed and defined according to the target size which can be fabricated on the surface of the wafer without being impossible Avoid the influence of photolithographic misalignment tolerances (photolithographic Misalignment Tolerances, PMT).

A second feature of the present invention is that both the length S(L) and the length D(L) can be as small as the minimum characteristic length λ, which is a specific process constraint defined at a process node (e.g., the minimum characteristic length The length λ is 7 nm at the 7 nm node, or 28 nm at the 28 nm node, or 180 nm at the 180 nm node).

The third feature of the present invention is that if the length G (L) is designed as λ, then the minimum dimension along the length direction of the metal oxide semiconductor field effect transistor 100 (that is, the distance from the left edge of the source electrode 103 to the drain electrode 107 The distance between the right edges) can be as small as 3λ (ie 1λ is the length S(L), 1λ is the length D(L), and 1λ is the length G(L)). Then the linear dimension of the metal oxide half field effect transistor 100 along the length direction can be miniaturized, otherwise when the linear dimension of the metal oxide half field effect transistor 100 along the length direction does not include the isolation region 105, the metal oxide half field effect transistor 100 The linear dimension of transistor 100 is reduced to only 3λ along the length.

A fourth feature of the present invention is that the length S(L) and the length D(L) can create the narrower length C-S(L) of the contact hole 109 and the narrower length C-D(L) of the contact hole 111 without being affected by This limitation of lithographic misalignment tolerance (since most of the critical photomask steps of making contact holes 109 and contact holes 111 are eliminated), other lengths S(L) and D(L) can be obtained by self-alignment techniques (self- alignment technology) clearly defined. Furthermore, the deposited interconnect layer of the first metal layer (metal-1) can be effectively defined by the photolithographic masking technique to achieve the narrower width of the first metal layer (ie, the contact hole opening and twice the lithographic misalignment tolerance), wherein the deposited interconnect layer can sufficiently fill the contact hole 109 and the contact hole 111 to make a natural connection between the first metal layer to the source 103 and the drain 107, respectively. metal contact points.

As in the aforementioned invention, the minimum element length dimension of the MOSFET structure (including the isolation region and the interconnection of the first metal layer) can be miniaturized without being enlarged by the unavoidable lithography misalignment tolerance.

Please refer to Figures 2A, 2B, 2C, 2D, 2E, 2F, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19. FIG. 2A is a flow chart of a manufacturing method of a miniaturized metal oxide semiconductor field effect transistor disclosed by another embodiment of the present invention. The manufacturing method of the metal oxide half field effect transistor in Fig. 2A can accurately control the lengths of the source and the drain of the metal oxide half field effect transistor. The detailed steps of the manufacturing method are as follows:

Step 10: start;

Step 20: forming an active region and a trench structure on the substrate 102;

Step 30: forming a dummy shield gate (dummy shield gate) and a true gate (true gate) of the MOSFET on the horizontal silicon surface (horizontal silicon surface, HSS) of the substrate 102;

Step 40: replacing the dummy shield gate with an isolation region to define a source/drain boundary of the MOSFET;

Step 50: forming the source and the drain of the MOSFET;

Step 60: forming a smaller contact hole within the boundary of the source and the drain, and forming a first metal layer interconnect to contact the source or the drain through the contact hole;

Step 70: end.

Please refer to Figure 2B and Figures 3 and 4. Step 20 may include:

Step 202: forming a pad oxide layer 302 and depositing a pad nitride layer 304 on the substrate 102;

Step 204: defining the active region of the MOSFET, and removing part of the silicon material outside the active region to manufacture the trench structure;

Step 206: Deposit a first oxide layer in the trench structure, and etch back the first oxide layer to form a shallow trench isolation-first oxide layer 306 (shallow trench isolation-oxide- 1, STI-oxide-1);

Step 207 : remove the pad oxide layer 302 and the pad nitride layer 304 , and form a dielectric insulating layer 402 on the horizontal silicon surface HSS.

Please refer to Figure 2C and Figure 6. Step 30 may include:

Step 208: depositing a gate layer 602 and a nitride layer 604 on the horizontal silicon surface HSS;

Step 210: Etching the gate layer 602 and the nitride layer 604 to form a true gate and a pseudo-shielded gate of the metal oxide semiconductor field effect transistor, wherein there is a required gap between the pseudo-shielded gate and the true gate. linear distance.

Please refer to Figure 2D and Figures 7, 8, 9, and 10. Step 40 may include:

Step 212: Deposit a spin-on dielectric layer (spin-on dielectrics, SOD) 702, and then etch back the spin-on dielectric layer 702;

Step 214: Forming a well-designed gate mask layer 802 through the photolithography mask technology;

Step 216: using anisotropic etching technique to remove the nitride layer 604 on the dummy shielded gate DSG, and remove the dummy shielded gate DSG, the dielectric insulating layer 402 corresponding to the dummy shielded gate DSG and Substrate 102 corresponding to the dummy shielded gate DSG;

Step 218 : remove the gate mask layer 802 , etch the spin-on dielectric layer 702 , deposit a second oxide layer, and then etch back the second oxide layer to form the STI-second oxide layer 1002 .

Please refer to Figure 2E and Figures 15, 16, and 17. Step 50 may include:

Step 220: Deposit and etch back a third oxide layer to form a third oxide spacer layer 1502, form a lightly doped drain (LDD) 1504 in the substrate 102, deposit and etch back a nitride layer to forming a nitride spacer layer 1506, and removing the dielectric insulating layer 402;

Step 222: using a selective epitaxy growth (SEG) technique to generate an intrinsic silicon (intrinsic silicon) 1602;

Step 224: Deposit and etch back a chemical vapor deposition-shallow trench isolation-third oxide layer 1702, remove the intrinsic silicon 1602, and form the source (n+source) 1704 and drain of the metal oxide semiconductor field effect transistor pole (n+drain) 1706.

Please refer to Figure 2F and Figures 18 and 19. Step 60 may include:

Step 226: Deposit and etch an oxide spacer 1802 to form contact-hole openings on the source (n+source) 1704 and drain (n+drain) 1706;

Step 228: Deposit and etch a first metal layer 1902 to form the first metal layer interconnect.

Part 1: Using the pseudo-shielded gate added on the gate mask (dummy-shield-gate, DSG) And by avoiding the lithographic misalignment tolerance to achieve the design distance from the edge of the gate to the boundary edge between the source and the isolation region GEBESI . Likewise, there is also a design distance from the edge of the gate to the boundary edge between the drain and the isolation region GEBEDI .

Taking an n-type metal oxide semiconductor field effect transistor as an example, the substrate 102 may be a p-type substrate, and the detailed description of the aforementioned manufacturing method is as follows. Beginning with step 20, refer to Figure 2B and Figures 3 and 4. In step 202 , a pad oxide layer 302 is formed over the horizontal silicon surface HSS of the substrate 102 , and then a pad nitride layer 304 is deposited over the pad oxide layer 302 .

In step 204, the active region of the MOSFET can be defined by the photolithography mask technique, resulting in the exposed horizontal silicon surface HSS outside the active region. Since the horizontal silicon surface HSS outside the active region is exposed, part of the silicon material outside the active region can be removed by the anisotropic etching technique to manufacture the trench structure.

In step 206, the first oxide layer is deposited to fill the trench structure, and then the first oxide layer is etched back to form shallow trench isolation-first oxide layer 306 below the horizontal silicon surface HSS, as in step 4. As shown in the figure. Fig. 4 is a cross-sectional view along the X-axis direction shown in Fig. 3 . In addition, because FIG. 3 is a top view, only the pad nitride layer 304 and the STI-first oxide layer 306 are shown in FIG. 3 . Then, in step 207, the pad oxide layer 302 and the pad nitride layer 304 on the active region are removed, and a dielectric insulating layer 402 (with a high dielectric constant) is formed over the horizontal silicon surface HSS.

FIG. 5 is a schematic diagram illustrating a prior art technique for realizing the geometrical relationship between the gate and the transistor isolation region with a smaller size. After forming the dielectric insulating layer 402 over the horizontal silicon surface HSS, a gate layer 404 (metal gate) is deposited over the dielectric insulating layer 402 . A nitride layer 406 (nitride cap layer) with a well-designed thickness is then deposited on the gate layer 404 . Next, as shown in FIG. 5, the photolithographic mask technology is used to define the gate structure 1, wherein the gate structure 1 includes a gate layer 404 and a nitride layer 406 so that the gate structure 1 has a suitable metal gate material , and the metal gate material can provide the required work function of the metal insulator to the substrate 102 to achieve a proper threshold voltage of the metal oxide semiconductor field effect transistor. In addition, because the shallow trench isolation-first oxide layer 306 is formed under the horizontal silicon surface HSS, a tri-gate transistor (Tri-gate FET) structure or a fin field-effect transistor (fin field-effect transistor, FinFET) structure (as shown in Figure 5).

After using the first photolithography process to define a dummy length of the active region and using the second photolithography process to define the length G(L) of the active region, from the edge of the gate structure 1 to the metal oxide half field The distance between the source of the effective transistor and the boundary edge of the shallow trench isolation (called GEBESI) can be defined (as shown in Figure 5). Similarly, the distance from the edge of the gate structure to the boundary edge between the drain of the MOSFET and the shallow trench isolation (referred to as GEBEDI) can also be defined.

However, as shown in FIG. 5, after using the photolithographic mask technology to align the edge of the gate structure 1 and the source of the metal oxide half field effect transistor (or the drain electrode of the metal oxide half field effect transistor) and When STI-first oxide layer 306 is separated from the boundary edge, there will be an unavoidable non-ideal factor, which is called the lithography dislocation tolerance. If the linear dimension of the lithographic misalignment tolerance measured along the X-axis direction is Δλ, then Δλ should be related to the minimum feature size dictated by the lithographic resolution of the equipment available at a particular process node. For example, the 7nm process node should have a minimum feature size λ equal to 7nm and a lithographic misalignment tolerance Δλ of 3.5nm. Therefore, if the desired actual size of the source electrode of the MOS field effect transistor (or the drain electrode of the MOS field effect transistor) is determined as λ (for example, 7 nanometers), then in the prior art process method Among them, the desired length of the source of the MOSFET (or the drain of the MOSFET) must be greater than the sum of λ and Δλ (for example, greater than 10.5 nm).

Therefore, the present invention utilizes a new structure to eliminate the negative effect caused by the photolithography misalignment tolerance. That is to say, the distance GEBESI from the edge of the gate structure to the boundary edge between the source of the MOS FET and the shallow trench isolation (or from the edge of the gate structure to the MOS FET Any size of the distance (GEBEDI) of the boundary edge between the drain electrode of the transistor and the boundary edge between the shallow trench isolation can be realized, and does not need to be along the length direction of the metal-oxide-semiconductor field-effect transistor (that is, as in the 4th, 5 shown in the X-axis direction) to reserve additional dimensions for the photolithography misalignment tolerance.

In step 208 , as shown in FIG. 6 , after forming the dielectric insulating layer 402 over the horizontal silicon surface HSS, a gate layer 602 and a nitride layer 604 are deposited. Then in step 210, the gate layer 602 and the nitride layer 604 are etched to form the gate structure (wherein the gate layer 602 may be the gate structure of the MOSFET). The main difference between the new structure shown in Fig. 6 and the structure shown in Fig. 5 is that when the true gate TG of the MOSFET is defined by the photolithography mask technology, parallel to the true gate The dummy shielded gate DSG of the TG can also be defined as required so that a target linear distance (eg λ, 7nm in the 7nm process node) can exist between the dummy shielded gate DSG and the true gate TG , without reserving any additional dimension (ie, Δλ) for the lithographic misalignment tolerance. The dummy shield gate DSG and the true gate TG designed on the same mask can be simultaneously formed on top of the dielectric insulating layer 402 covering the active region. In addition, as shown in FIG. 6, the true gates TG2 and TG3 correspond to other metal-oxide-semiconductor field-effect transistors.

The next step is to illustrate how to replace the dummy shielded gate DSG with an isolation region raised above the horizontal silicon surface HSS. In step 212, as shown in FIG. 7, a spin-on dielectric layer 702 is deposited, and then the spin-on dielectric layer 702 is etched back using a chemical mechanical polishing (CMP) technique to make the spin-on dielectric layer 702 The top of is as high as the top of nitride layer 604.

In step 214, as shown in FIG. 8, the gate mask layer 802 is deposited, and then the gate mask layer 802 is etched by the photolithography mask technology to cover the real gate TG, TG2, TG3 but expose the pseudo-shielding gate. The target of the pole DSG, where the exposed dummy shield gate DSG has a safe lithographic misalignment tolerance Δλ in the middle of the lengths of distance GEBESI and distance GEBEDI, respectively.

For clarity, in Figure 8, the distance between the true gate TG under the gate reticle layer 802 and the dummy shielded gate DSG on the left can be denoted as GEBESI, and the true gate TG under the gate reticle layer 802 The distance between pole TG and the dummy shield gate DSG on the right can be denoted as GEBEDI. Because after replacing the dummy shielded gate DSG with the isolation region shown in the next figure 9-10, the distance between the real gate TG and the dummy shielded gate DSG in figure 8 will become from the real gate TG The distance from the edge to the boundary edge between the source of the MOS field effect transistor (or the drain of the MOS field effect transistor) and the isolation region, that is, the GEBESI (or GEBEDI).

In step 216, as shown in FIG. 9(a), the anisotropic etching technique can be used to etch the dummy shielded gate DSG and the nitride layer 604 corresponding to the dummy shielded gate DSG, and can also be used to etch the corresponding dummy shielded gate DSG. The dielectric insulating layer 402 of the gate DSG reaches the horizontal silicon surface HSS. Then use the anisotropic etching technique to remove the silicon material of the substrate 102 under the horizontal silicon surface HSS to form a trench 902 under the horizontal silicon surface HSS, wherein the depth of the trench 902 can be equal to the shallow trench isolation-th The depth of the bottom of the oxide layer 306 . Therefore, as shown in Fig. 9(a), this lithographic misalignment tolerance is avoided in creating the precisely controlled distance GEBESI and distance GEBEDI, respectively. Since the lengths of the distance GEBESI and the distance GEBEDI are well defined by the true gate TG and the dummy shielded gate DSG on the same reticle, the length S(L) of the source and the length D( L) can be well defined. That is to say, the single photolithography mask technology is not only used to define the true gate TG and the dummy shielded gate DSG, but also can be used to control the lengths of the distance GEBESI and the distance GEBEDI. Therefore, the dimensions of the length S(L) and the length D(L) can be accurately controlled, even reaching an optimal miniaturized size as small as the minimum feature size λ. Since the length S(L) and the length D(L) can be equal to λ, the length S(L) and the length D(L) are substantially equal to the length of the true gate TG (ie, the gate structure). In addition, Fig. 9(b) is a plan view corresponding to Fig. 9(a).

In step 218, as shown in FIG. 10(a), the gate mask layer 802 and the spin-on dielectric layer 702 are removed, and then a second oxide layer is deposited to fill the trenches 902 and other voids in the horizontal silicon surface HSS , and then the second oxide layer can be etched back to the same surface height as the horizontal silicon surface HSS to form STI-second oxide layer 1002 . Fig. 10(b) is a plan view corresponding to Fig. 10(a).

Therefore, the temporarily formed dummy shielding gate DSG can be replaced by shallow trench isolation-second oxide layer 1002 to define the source/drain boundary. The MOSFET can then be completed using any prior art technique capable of forming a lightly doped drain (LDD), a spacer surrounding the true gate TG, the source, and the drain, wherein The source and the drain are formed according to the accurately controlled distance GEBESI and the distance GEBEDI, respectively.

Part II: Utilizing Pseudo-Shielded Gates DSG Design principles, through adaptive pseudo-shielded gate design to achieve the distance GEBESI and distance GEBEDI The target length for variable-shape active regions ( in an active zone (AA) On the mask ) .

Since the shape of an isolation region of a transistor and the location of the isolation region between the transistor and an adjacent transistor may vary considerably (even in the embodiments described above), another structure will be described below, which is An adaptive pseudo-shielded gate is designed by extending the principles of the above embodiments.

FIG. 11 illustrates an arrangement geometric condition of an active region adjacent to a transistor, wherein the arrangement geometric condition of the active region adjacent to a transistor is different from FIG. 6 . For example, as shown in FIG. 6, adjacent active regions of adjacent transistors are connected before the deposition of the true gate TG, true gate TG2, true gate TG3, and dummy shield gate DSG. The connected active regions can then be segmented into individual precise target distances by the length of the dummy shield gate DSG. But as shown in Figure 11, assume that the active region on the source (or drain) of the transistor has been completely isolated from any other active region by isolation region 1102 before and after the true gate of the transistor is defined of. Therefore, what is proposed here is how to design the active region on the source and the adaptive dummy shielded gate DSG (and the drain as well), as described below. For example, if the final length of the distance GEBESI is determined to be λ (or any other target length L(S)), the length of the active area mask (AA mask) corresponding to the distance GEBESI should be designed to be equal to the sum of λ and Δλ ( or the sum of length L(S) and Δλ). Then on the gate photomask, the dummy shielded gate DSG can have the shape shown in Figure 11, that is to say the length of the rectangular shape of the dummy shielded gate DSG is equal to λ, and the width is equal to the sum of the width of the active region and 2Δλ (each side shares 0.5Δλ separately). In addition, the designed distance between the true gate TG and the dummy shielded gate DSG on the source side is still exactly the length (eg λ) of the distance GEBESI.

The results derived from the active area and gate of Figure 11 from the mask stage to the wafer stage are depicted in Figure 12. As shown in Figure 12, when the true gate TG is defined by the lithography mask technology, the dummy shielded gate DSG is designed to be parallel to the real gate TG, and there is a gap between the dummy shielded gate DSG and the true gate TG. Target distance (e.g. λ, where λ is 7nm at the 7nm process node). As a result of the nominal process (that is, no significant dislocations are introduced in the lithographic process), the dummy shielded gate DSG covers the active region (corresponding to the source) at a distance Δλ, and the true gate TG and The dummy shield gates DSG are all disposed above the dielectric insulating layer 402 covering the active region. In addition, there is a nitride cap layer (that is, a nitride layer 604 ) above the real gate TG and the dummy shield gate DSG.

As shown in Figure 13, if the lithographic misalignment tolerance causes a displacement (eg Δλ) to the right of the active region for both the true gate TG and the dummy shielded gate DSG, the next process is to remove the dummy shielded gate DSG to realize the isolation region STI-oxide-2 (that is, shallow trench isolation-second oxide layer 1002), where the position of the isolation region STI-oxide-2 is exactly the original process step described in the first part The location of the dummy shield gate DSG that exists. In addition, the following process can make the length of the isolation region STI-oxide-2 λ, and the isolation region STI-oxide-2 can become the physical geometry of the source, wherein the gap between the true gate TG and the source The length of the distance GEBESI is equal to λ (because the distance between the true gate TG and the dummy shield gate DSG is designed as λ). On the other hand, as shown in FIG. 14, if the lithographic misalignment tolerance causes a displacement (eg, Δλ) to the left of the active region for both the real gate TG and the dummy shielded gate DSG, then the subsequent removal of the dummy The process steps of shielding the gate DSG and forming the isolation region STI-oxide-2 will make the length of the isolation region STI-oxide-2 be λ, and make the distance between the true gate TG and the source GEBESI be is equal to lambda.

When the lithographic misalignment tolerance causes undesirable displacement along the width direction (that is, the up-down direction) of the active region, then the design of the adaptive pseudo-shielded gate (the width of the pseudo-shielded gate is the width of the active region and 2Δλ) does not affect the geometry of the active region. This innovative design using an adaptive pseudo-shielded gate always produces an isolation region STI-oxide-2 with a length λ and a distance GEBESI whose length meets the design target (eg λ). The present invention can certainly be applied to all different shapes of isolation regions, sources and drains having respective target lengths, respectively.

Part III: Precisely Defined Sources ( or drain ) Contact holes can be opened by self-aligned spacers (contact-hole opening) Precisely controlled to reduce touch mask and aperture process steps.

After disclosing how to optimally design and manufacture distance GEBESI and distance GEBEDI to a precisely controlled small size (as small as λ), another new invention is how to fabricate ), wherein the length C-S(L) and the length C-D(L) are less than the distance GEBESI and the distance GEBEDI, respectively. Two designs and processes are described below.

a. Design and Process (I)

Please continue to refer to Fig. 10(a) and use the true gate TG for the following description. In step 220, as shown in FIG. 15(a), the third oxide layer is deposited and etched back to form a third oxide spacer layer 1502, wherein the third oxide spacer layer 1502 covers the true gate TG. Next, a lightly doped region is formed in the substrate 102 , and rapid thermal annealing (RTA) is performed on the lightly doped region to form a lightly doped drain 1504 next to the true gate TG. The nitrided layer is then deposited and etched back to form a nitrided spacer layer 1506 , wherein the nitrided spacer layer 1506 covers the third oxide spacer layer 1502 . The dielectric insulating layer 402 not covered by the nitride spacer layer 1506 and the third oxide spacer layer 1502 is then removed. In addition, Fig. 15(b) is a plan view corresponding to Fig. 15(a).

In step 222, as shown in FIG. 16(a), by using the exposed horizontal silicon surface HSS as a silicon seed, the selective epitaxial growth technique is used to grow intrinsic silicon 1602 only above the exposed horizontal silicon surface HSS, and The height of the intrinsic silicon 1602 is as high as the top of the nitride layer 604 (on top of the true gate TG). In addition, Fig. 16(b) is a plan view corresponding to Fig. 16(a).

In step 224, as shown in FIG. 17(a), a chemical vapor deposition-shallow trench isolation-third oxide layer 1702 is deposited to fill all vacancies, and chemical-mechanical polishing (Chemical-Mechanical Polishing, CMP) Technology planarization chemical vapor deposition - shallow trench isolation - third oxide layer 1702 so that the height of chemical vapor deposition - shallow trench isolation - third oxide layer 1702 is flush with the top of the nitride layer 604, where the nitride Layer 604 is on top of the true gate TG. Next, the intrinsic silicon 1602 is removed to expose the horizontal silicon surface HSS corresponding to the source and the drain, wherein the horizontal silicon surface HSS corresponding to the source and the drain is chemical vapor deposited - shallow trench isolation - Surrounded by a third oxide layer 1702 and a nitride spacer layer 1506 .

Essentially, the silicon 1602 is like a self-alignment pillar (SPR) used to enclose or seal the area where a contact hole will be disposed later, but the self-alignment pillar is not limited to silicon material. According to the material of the seed crystal used for the selective epitaxial growth technology, the self-aligned column can be a metal material or other semiconductor material (for example: silicon carbide (SiC), silicon germanium (SiGe), (gallium nitride GaN), etc. ). In addition, the substrate 102 may be a silicon substrate, a silicon carbide substrate, a silicon germanium substrate, or a gallium nitride substrate or the like.

Any existing technology that can form the source (n+source) 1704 and drain (n+drain) 1706 of the MOSFET can use the horizontal silicon surface HSS to realize the flat surfaces of the source 1704 and the drain 1706, The source (n+source) 1704 can be a first conductive region, and the drain (n+drain) 1706 can be a second conductive region. In addition, as shown in Figure 17(a), a channel region exists between the lightly doped drains 1504 and below the horizontal silicon surface HSS, and the channel region can be electrically coupled to the source (n+ source pole) 1704 and drain (n+drain) 1706. In addition, as shown in Figure 17(a), the source (n+source) 1704 is placed on the gate structure (that is, the true gate TG (gate layer 602)) and on the left side of the gate structure Between the shallow trench isolation-second oxide layer 1002 and chemical vapor deposition-shallow trench isolation-third oxide layer 1702, wherein the shallow trench isolation-second oxide layer 1002 and chemical vapor deposition on the left side of the gate structure Vapor deposition-shallow trench isolation-third oxide layer 1702 may be referred to as a first isolation region, and the first isolation region is adjacent to the first conductive region (ie, source (n+source) 1704 ). In addition, as shown in Figure 17(a), the drain (n+drain) 1706 is placed on the gate structure and the shallow trench isolation-second oxide layer 1002 and chemical gas on the right side of the gate structure between phase deposition-shallow trench isolation-third oxide layer 1702, wherein on the right side of the gate structure is shallow trench isolation-second oxide layer 1002 and chemical vapor deposition-shallow trench isolation-third oxide layer 1702 It may be referred to as a second isolation region, and the second isolation region is adjacent to the second conductive region (ie, the drain (n+drain) 1706 ). In addition, as shown in FIG. 17(a), it is very obvious that the first isolation region and the second isolation region extend upward and downward from the horizontal silicon surface HSS. In addition, Fig. 17(b) is a plan view corresponding to Fig. 17(a).

In step 226, as shown in FIG. 18(a), because the chemical vapor deposition-shallow trench isolation-third oxidation on the isolation region (that is, the first isolation region and the second isolation region) Layer 1702 and the nitride spacer 1506 surrounding the true gate TG are higher than the horizontal silicon surface HSS, like four sidewalls, so a well-designed oxide spacer 1802 (called oxide spacer for contact holes for contact hole, oxide-SCH)) can be manufactured outside the four side walls to form a first contact hole 1804, wherein the position of the first contact hole 1804 is in the first conductive region (that is, the source (n+source ) 1704) and within the boundary of source (n+source) 1704. Likewise, a second contact hole 1806 is located above the second conductive region (ie, the drain (n+drain) 1706 ) and within the boundary of the drain (n+drain) 1706 . Therefore, as shown in FIG. 18(a), the first contact hole 1804 and the second contact hole 1806 are naturally formed in a self-aligned manner without using any etching technique to manufacture the contact hole opening, and And by a suitable design of the oxide spacer layer for the contact hole (having a thickness tOSCH) the length of the contact hole opening can be smaller than the distance GEBESI and the distance GEBEDI respectively. The innovative part of the present invention is that the position of the contact hole opening is almost in the center of the boundary of the source electrode 1704 (or the drain electrode 1706), and the length of the contact hole opening can be designed to be less than λ (because the contact hole opening Length = length from GEBESI - 2 times thickness tOSCH. So for example, if thickness tOSCH = 0.2λ, length from GEBESI = λ, then the length of the contact hole opening = 0.6λ). Thus, the perimeter of the first contact hole 1804 (and the second contact hole 1806) is independent of the photolithographic mask technology because the length of the contact hole opening is primarily dominated by the thickness tOSCH of the oxide spacer layer 1802, and And as shown in Figure 18(b), it can be clearly seen that the periphery of the first contact hole 1804 is in the periphery of the first conductive region, and the periphery of the second contact hole 1806 is in the periphery of the second conductive region Inside.

In addition, as shown in Figure 18(b), since the length of the contact hole opening is less than λ, the length of the first contact hole 1804 (the length of the second contact hole 1806) is smaller than the length of the gate structure (because as shown in the first contact hole 1806) 6, the length of the gate structure is equal to λ). In addition, as shown in FIG. 18(a), since the oxide spacer 1802 has a thickness tOSCH, and the distance from GEBESI is equal to the length of the gate structure, it is obvious that a first sidewall of the gate structure (located on the The horizontal distance between the left side of the gate structure) and the sidewall of the first contact hole 1804 away from the gate structure is smaller than the length (ie, λ) of the gate structure. In addition, as shown in FIG. 18(a), the horizontal distance between the first sidewall of the gate structure and the sidewall of the first conductive region (that is, the source 1704) away from the gate structure is approximately equal to that of the gate structure. length of the polar structure. Similarly, as shown in Figure 18(a), the horizontal distance between a second sidewall of the gate structure (located on the right side of the gate structure) and the sidewall of the second isolation region away from the gate structure substantially equal to the length of the gate structure.

In addition, as shown in FIG. 18(a), an oxide spacer 1802 (that is, a first spacer) located on the left side of the gate structure and close to the gate structure covers the first sidewall of the gate structure, and The oxide spacer layer 1802 on the left side of the gate structure and away from the gate structure (that is, a second spacer layer) covers the sidewall of the first isolation region, wherein the first contact hole 1804 is between the first spacer layer and the first spacer layer. formed between the second spacer layers.

In addition, as shown in FIG. 18(a), an oxide spacer 1802 located on the right side of the gate structure and close to the gate structure (such as a third spacer) covers a second sidewall of the gate structure (located on the the right side of the gate structure), the oxide spacer layer 1802 located on the right side of the gate structure and far away from the gate structure (for example, a fourth spacer layer) covers the side wall of the second isolation region, wherein the second contact hole 1806 is formed between the third spacer layer and the fourth spacer layer.

In addition, as shown in Figure 18(b), obviously the periphery of the first contact hole 1804 is surrounded by the periphery of the first conductive region (or source 1704), and the shape of the periphery of the first contact hole 1804 is similar to the first The shape of the periphery of the conductive region and the periphery of the first conductive region are similar to a rectangle. In addition, a similar situation is also applicable to the second contact hole 1806 and the second conductive region (or the drain 1706).

According to the present invention, the self-aligned contact holes (the first contact hole 1804 and the second contact hole 1806) exhibit the smallest contact hole length (its size can be smaller than λ), which is better than any prior art design and through this lithography. The length of the contact hole opening produced by the mask technology and the complex etching process is even smaller. In addition, the present invention omits most of the uncontrollable factors and most of the resources used to define and make the first metal layer contacts (such as first contact hole 1804 and second contact hole 1806 for source 1704 and drain 1706, respectively). The expensive photomask and subsequent drilling task of digging this contact hole opening. In addition, Fig. 18(b) is a plan view corresponding to Fig. 18(a).

In step 228, as shown in FIG. 19, after depositing the first metal layer 1902 to fill the contact holes (first contact hole 1804 and second contact hole 1806), the photolithographic mask technique can be used to define The first metal layer 1902 . As shown in FIG. 19, the first metal layer 1902 must have a width of precisely controlled dimensions, wherein the width of the first metal layer 1902 must be able to completely cover the contact hole opening, and must be reserved for any unavoidable photolithographic misalignment. tolerance. That is to say, the width of the first metal layer 1902 corresponding to the source 1704 is equal to the length C-S (L) of the contact hole opening (on the source 1704 ) plus 2Δλ, and the width of the first metal layer 1902 corresponding to the drain 1706 Equal to the length C-D(L) of the contact hole opening (on the drain 1706) plus 2Δλ. If the length of the contact hole opening can be controlled at 0.6λ (it should be controllable, because the size of the oxide spacer 1802 in the contact hole can be well controlled from the calculation described above), then the first metal layer The width of 1902 can be as small as the sum of the length of the contact hole opening and 2Δλ (if in an embodiment of the present invention, Δλ=0.5λ (that is, half the length of the gate structure), the length of the contact hole opening = 0.6λ, the width of the first metal layer 1902 can be narrowed to 1.6λ in order to completely cover the opening of the contact hole under the unavoidable photolithographic misalignment tolerance. To completely cover the opening of the contact hole, the width of the first metal layer 1902 may be equal to the length of the first contact hole 1804 plus the length of the gate structure). According to the present invention, the width of the first metal layer 1902 as narrow as 1.6λ may be one of the smallest widths of the first metal layer interconnects. Additionally, a minimum space 1904 between two closest first metal level interconnects cannot be smaller than λ. In addition, as shown in FIG. 19, the first metal layer 1902 (that is, a first metal region) is filled in the first contact hole 1804 and contacts the first conductive region (that is, the source electrode 1704), wherein the first The metal region extends upward from the first conductive region to a predetermined position, and the predetermined position is higher than the top of the nitride layer 604 (ie, the nitride cap layer).

In addition, as shown in FIG. 20, if there is no adjacent first metal layer interconnection for the source (and/or drain), for example, using a merged semiconductor junction and metal conductor structure (merged semiconductor junction and metal conductor (MSMC) structure) (published in US Patent Application No. 16/991,044, filing date 2020/08/12, cited in its entirety), the chemical vapor deposition-shallow trench defined by the pseudo-shielded gate Isolation - The width of the third oxide layer 1702 can be made as small as the minimum feature size λ without being constrained by the space between any adjacent first metal layer interconnects where the source (and/or drain pole) is grounded and directly connected to the substrate 102 of the MOSFET. In addition, as shown in FIG. 20, the source includes a first semiconductor region (n+ heavily doped semiconductor region) 1906 and a first metal-containing region 1908, and the drain includes a second semiconductor region (n+ heavily doped heterosemiconductor region) 1910 and a second metal-containing region 1912, wherein a first oxide guard layer (OGL) 1914 only covers the sidewall of the first metal-containing region 1908, but does not cover the first At the bottom of the metal region 1908 , a second protective oxide layer 1916 (in the recess shown in FIG. 20 ) covers the sidewalls and bottom of the second metal-containing region 1912 . Therefore, the first metal-included region 1908 is coupled to the substrate 102 through the bottom of the first metal-included region 1908 .

An important advantage of the present invention is that almost every critical dimension, such as the length of the distance GEBESI and the distance GEBEDI, the length of the contact hole opening, and the width of the first metal layer interconnection can be precisely controlled without undue influence. Determined lithographic misalignment tolerances. In this way, based on the consistency of critical dimensions, the repeatability, quality and reliability of each critical dimension can be ensured.

b. Design and Process (II)

The above principles will continue to be used in the following embodiments, but the difference lies in how to form the spacer layer and the opening of the contact hole. Continuing from FIG. 9(a), as shown in FIG. 21(a), the gate mask layer 802 is removed, and then the second oxide layer is deposited to fill the trench 902 and other vacancies above the horizontal silicon surface HSS to form A shallow trench isolation-second oxide layer 2102 . The shallow trench isolation-second oxide layer 2102 is then planarized by the chemical mechanical polishing technique so that the top of the shallow trench isolation-second oxide layer 2102 and the top of the spin-on dielectric layer 702 and the top of the nitride layer 604 are planarized. Qi, wherein the nitride layer 604 is above the true gate TG. In addition, Fig. 21(b) is a plan view corresponding to Fig. 21(a).

Then, as shown in FIG. 22(a), the spin-on dielectric layer 702 is removed. Then deposit the third oxide layer, and use the anisotropic etching technique to etch back the third oxide layer to form a third oxide spacer layer 2202, wherein the third oxide spacer layer 2202 covers the true gate TG. A lightly doped region is then formed in the substrate 102, and a rapid thermal anneal is performed on the lightly doped region to form the lightly doped drain 2204 next to the true gate TG. The nitride layer is then deposited and etched back to form a nitride spacer layer 2206 , wherein the nitride spacer layer 2206 covers the third oxide spacer layer 2202 . The dielectric insulating layer 402 under the pre-existing spin-on dielectric layer 702 is then removed. In addition, Fig. 22(b) is a plan view corresponding to Fig. 22(a).

Next, as shown in FIG. 23(a), by using the exposed horizontal silicon surface HSS region as a silicon seed, the selective epitaxial growth technique is used to generate an intrinsic silicon 2302 only above the exposed horizontal silicon surface HSS, wherein the intrinsic silicon The height of 2302 is level with the top of the nitride layer 604, and the nitride layer 604 is above the top of the true gate TG. Different from paragraph A of the third part above, the shape of the intrinsic silicon 2302 grown by the selective epitaxy can be better controlled, because the two sides of the intrinsic silicon 2302 are sandwiched between the shallow trench isolation-second oxide layer 2102 and Between the true gate TG and the other two sides of the intrinsic silicon 2302 facing the air above the cliff edge of the active region, where the active region is still covered by the dielectric insulating layer 402 and isolated in the adjacent shallow trench- above the first oxide layer 306 (STI-oxide-1). A CVD-STI-third oxide layer 2304 is then deposited (as shown in FIG. 23(b)) to fill all gaps, and planarized by the CMP technique to make the CVD- Shallow Trench Isolation - The top of the third oxide layer 2304 is flush with the top of the nitride layer 604 (over the top of the true gate TG). In addition, Fig. 23(b) is a plan view corresponding to Fig. 23(a).

In addition, as shown in FIG. 24(a), the intrinsic silicon 2302 is removed to expose the horizontal silicon surface HSS corresponding to a source (n+source) 2402 and a region corresponding to a drain (n+drain) 2404, wherein the source The electrode 2402 and the drain electrode 2404 are chemical vapor deposition-shallow trench isolation-the two walls of the third oxide layer 2304, one wall of the nitrided spacer layer 2206 on the shallow trench isolation-second oxide layer 2102, and surrounding Surrounded by a wall of the nitrided spacer 2206 of the true gate TG. Any prior art that can form the source 2402 and the drain 2404 of the MOSFET can use the horizontal silicon surface HSS to realize the planar surfaces of the source 2402 and the drain 2404 .

As shown in Figure 24(a), because of the chemical vapor deposition-shallow trench isolation-the two walls of the third oxide layer 2304, the nitride spacer 2206 on the shallow trench isolation-second oxide layer 2102, and The nitride spacer 2206 around the true gate TG is higher than the horizontal silicon surface HSS like four sidewalls, so another well-designed four oxide spacers 2406 (called oxide spacers for contact holes (oxide spacers) spacer for contact hole, oxide-SCH))) can be newly created to cover the four side walls. Therefore, the contact hole opening is naturally formed in a self-aligned manner without using any etching technique used to manufacture the contact hole opening, and through the oxide spacer (oxide-SCH) for the contact hole With proper design (with thickness tOSCH), the length dimension of the contact hole opening can be smaller than the distance GEBESI and the distance GEBEDI, respectively. The innovative part of the present invention is that the position of the contact hole opening is respectively in the center of the boundary of the source and the drain electrode, and the length of the contact hole opening can be designed to be less than λ (because the length of the contact hole=distance from GEBESI Length - 2 times thickness tOSCH. So eg if thickness tOSCH = 0.2λ and length from GEBESI = λ, length of contact hole = 0.6λ). According to the present invention, the self-aligned contact hole exhibits the smallest contact hole length (its size can be smaller than λ), which is better than any prior art design and contact hole manufactured by the photolithographic mask technology and complex etching process. The length of the opening is even smaller. In addition, the present invention eliminates most of the unmanageable factors and most of the tasks of expensive photomasks and subsequent drilling of the contact hole openings used to define and fabricate the first metal layer contacts. In addition, Fig. 24(b) is a plan view corresponding to Fig. 24(a).

FIG. 25 is a schematic diagram illustrating defining the first metal layer 2502 using the photolithography mask technique after depositing a first metal layer 2502 to fill the contact hole opening. As shown in FIG. 25, the first metal layer 2502 must have a width of precisely controlled dimensions, wherein the width of the first metal layer 2502 must be able to completely cover the contact hole opening, and must be reserved for any unavoidable photolithographic misalignment. tolerance. That is to say, the width of the first metal layer 2502 corresponding to the source is equal to the length C-S (L) of the contact hole opening (on the source) plus 2Δλ, and the width of the first metal layer 2502 corresponding to the drain is equal to The length C-D(L) of the contact hole opening (on the drain) plus 2Δλ. If the length of the contact hole opening can be controlled at 0.6λ (it should be controllable, because the size of the oxide spacer 2406 in the contact hole can be well controlled from the calculation described above), then the first metal layer The width of 2502 can be as small as the sum of the length of the contact hole opening and 2Δλ (if in an embodiment of the present invention, Δλ=0.5λ, the length of the contact hole opening=0.6λ, then in order to prevent the unavoidable photolithography dislocation The contact hole opening can be completely covered under the tolerance, and the width of the first metal layer 2502 can be as narrow as 1.6λ. According to the present invention, the width of the first metal layer 2502 as narrow as 1.6λ can be the width of the first metal layer interconnection One of the minimum widths. In addition, a minimum space 2504 between two closest first metal layer interconnects cannot be less than λ. In addition, the important advantage of the present invention is that almost every key dimension, such as distance GEBESI and distance The length of the GEBEDI, the length of the contact hole opening, and the width of the first metal layer interconnection can be precisely controlled without being affected by uncertain photolithographic misalignment tolerances, so that, based on critical dimension consistency, it is possible to Ensure reproducibility, quality and reliability of every critical dimension.

In summary, the metal-oxide-semiconductor field-effect transistor structure disclosed in the embodiments of the present invention can avoid photolithography dislocation tolerances, especially with regard to gate and source, gate and drain, first metal layer and source The geometric relationship between the opening of the contact hole between the drain and the drain, the width of the first metal layer interconnection and the self-alignment method for filling the contact hole, etc., the design and process improvement, for the design of future integrated circuits Brings several major advances:

(1) The length S(L) and the length D(L) respectively from the two edges of the gate are precisely defined by eliminating the uncertain factors caused by the photolithography misalignment tolerance.

(2) Both the length S(L) and the length D(L) can be designed to be the minimum characteristic length λ allowed by the photolithography mask and process resolution, so as to significantly reduce the size of the source and the drain. In this way, the area of the MOS field effect transistor can be reduced and the standby and operating current and power consumption can be reduced, thereby increasing the operating speed of the MOS field effect transistor.

(3) Since both the length S(L) and the length D(L) can be precisely controlled, the self-alignment technique of the present invention can accurately Self-alignment contact holes (SACH) of controllable shape and size are fabricated close to the center of the source and the drain, respectively.

(4) The length of the self-aligned contact hole can be designed to be smaller than the minimum feature size λ, for example as small as 0.6λ or even narrower.

(5) Other width dimensions of the self-aligned contact hole can be well designed by the self-aligned spacer layer and well-defined active area width; because the formation of the self-aligned contact hole is by the spacer layer technology, not Contact holes are defined by prior art photolithographic mask techniques with difficult-to-control misalignment tolerances and contact hole shapes, where the spacer layer technology is dependent on using chemical film deposition with controllable thickness and exploiting the anisotropy Etching technology has developed a mature technology. The contact hole opening of the present invention can be well designed and defined (although the contact hole may not have a consistent square contact shape, the contact hole has a well defined rectangular shape and the filling result actually depends on the narrower length dimension of the contact hole ).

(6) Eliminate the most difficult and expensive contact steps and masks.

(7) Completely separate a square hole or a plurality of square holes from a plurality of contact holes into a rectangular single contact hole or a single contact trench to change the design of the contact hole; therefore, the width of the source (or the drain) (or length) can be exactly the same as the width (or length) of the gate without being limited by using a dog-bone layout to adjust the width of the gate and possibly having multiple square contact holes The dimensional difference between the width of the source (or the drain).

(8) Since the successful filling of the first metal layer interconnection with a well-designed thickness depends on the minimum size of the contact hole (usually the length of the self-aligned contact (SACH) hole), the first The metal layer interconnection can indeed fill all the existing contact holes, so that the two steps used to form the contact pillars in the prior art (such as filling tungsten plus planarization process, that is, the tungsten pillar process disclosed in the prior art and the second step) A metal layer embedding process) can be simplified into a first metal layer deposition process.

(9) Forming the self-aligned contact hole and the first metal layer through the above integrated process and the gate is covered under the nitride cap layer and protected by the spacer layer (wherein the nitride cap layer and the Spacer layers can create a flat surface on the area outside the self-aligned contact hole), the first metal level interconnection can be designed to have a variety of layouts to create an optimally distributed first metal level interconnection network.

(10) Based on the above advantages, the metal oxide half field effect transistor structure disclosed in the present invention can be manufactured to have a very small size, wherein the metal oxide half field effect transistor structure has a minimum length dimension of 4λ (that is to say contains equal to λ of length S(L), equal to λ of length D(L), equal to λ of the gate length, 1/2λ for isolation on the left, and 1/2λ for isolation on the right) and a minimum width dimension of 2λ , that is to say, the world's smallest single transistor with a contact hole and a first metal layer interconnection connected to the source and the drain can be realized within an area of 8λ2.

Of course, according to design requirements, the length G(L), length S(L) or length D(L) may be greater than the minimum characteristic length λ.

Because the present invention eliminates the uncertainty of lithographic misalignment tolerances and adopts new self-alignment design and process technology, all the advantages of the present invention are not limited to the application of a single metal oxide semiconductor field effect transistor, but can also be applied to In complementary metal oxide semiconductor (CMOS) circuits, for example, many functional units have been optimized in terms of area (such as static random access memory (Static Random Access Memory, SRAM), NAND gate (NAND gate) ), NOR gate, and any logic gate) can reduce chip area, current, power consumption and speed through the design and manufacturing principles of the present invention, and have accuracy, repeatability, consistency and Better margin. The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: Gold Oxygen Half Field Effect Transistor 101:Gate structure 103, 1704, 2402: source 105, 1102: quarantine area 107, 1706, 2404: drain 109, 111: contact hole 102: Base 302: pad oxide layer 304: Liner nitride layer 306: Shallow trench isolation - first oxide layer 402: Dielectric insulator 404, 602: gate layer 406, 604: nitride layer 702: spin coating dielectric layer 802:Gate mask layer 902: Groove 1002, 2102, STI-oxide-2: shallow trench isolation - second oxide layer 1502, 2202: the third oxide spacer layer 1504, 2204: lightly doped drain 1506, 2206: nitrided spacer layer 1602, 2302: essential silicon 1702, 2304: Chemical Vapor Deposition - Shallow Trench Isolation - Third Oxide Layer 1802, 2406: oxide spacer 1804: First contact hole 1806: Second contact hole 1902, 2502: first metal layer 1904, 2504: Minimum space 1906: First semiconductor area 1908: First metal-bearing area 1910:Second Semiconductor Region 1912: Second metal-bearing zone 1914: First oxidation protection layer 1916:Second oxidation protective layer D(L), G(L), S(L), C-S(L), C-D(L): Length D(W), G(W), S(W), C-S(W), C-D(W): Width GEBESI, GEBEDI: distance HSS: Horizontal Silicon Surface DSG: Dummy Shielded Gate TG, TG2, TG3: true gate λ: minimum characteristic length Δλ: photolithography misalignment tolerance 10-70, 202-228: Steps

FIG. 1 is a top view of a miniaturized metal-oxide-semiconductor field-effect transistor disclosed by an embodiment of the present invention. FIG. 2A is a flow chart of a manufacturing method of a miniaturized metal oxide semiconductor field effect transistor disclosed by another embodiment of the present invention. Figures 2B, 2C, 2D, 2E, and 2F are flowcharts illustrating Figure 2A. FIG. 3 is a top view illustrating a pad nitride layer and an STI-first oxide layer. Fig. 4 is a cross-sectional view along the X-axis direction in Fig. 3 . Figure 5 illustrates the photolithographic misalignment tolerance (PMT) of the alignment of the gate structure edge to the source and shallow trench isolation-first oxide boundary edge of a metal oxide semiconductor field effect transistor. schematic diagram. FIG. 6 is a schematic diagram illustrating a new structure that eliminates the negative effects of lithographic misalignment tolerances. Figure 7 is a schematic diagram illustrating the deposition of a spin-on dielectric layer. FIG. 8 is a schematic diagram illustrating the deposition and etching of a well-designed gate mask layer. FIG. 9 is a schematic diagram illustrating the removal of dummy shielded gates, nitride layers, dielectric insulators, and substrates corresponding to dummy shielded gates by anisotropic etching techniques. FIG. 10 is a schematic diagram illustrating removing the gate mask layer, etching the spin-on dielectric layer, depositing the second oxide layer, and etching back the second oxide layer to form STI-second oxide layer. Figures 11, 12, 13 and 14 are diagrams illustrating the relationship between the position of the true gate and the position of the pseudo-shield gate. Figure 15 illustrates depositing and etching a third oxide layer to form a third oxide spacer, forming a lightly doped drain in the substrate, depositing and etching back a nitride layer to form a nitride spacer, and removing the dielectric insulator schematic diagram. FIG. 16 is a schematic diagram illustrating the growth of intrinsic silicon by selective epitaxy. FIG. 17 is a schematic diagram illustrating the deposition and etch-back of chemical vapor deposition-STI-third oxide layer, removal of intrinsic silicon, and formation of source and drain of a MOSFET. FIG. 18 is a schematic diagram illustrating deposition and etching of an oxide spacer layer to form a contact hole opening. FIG. 19 is a schematic diagram illustrating the deposition and etch back of the first metal layer to form the first metal layer interconnects. FIG. 20 is a schematic diagram of forming a source and a drain and forming a first metal layer interconnect using a merged semiconductor junction and metal conductor structure according to another embodiment of the present invention. Figure 21 illustrates the removal of the gate mask layer and the deposition of a second oxide layer to fill the trenches and other vacancies on the horizontal silicon surface to form the STI-second oxide layer, followed by chemical mechanical polishing Schematic diagram of planarizing the shallow trench isolation-second oxide layer. FIG. 22 illustrates depositing and etching a third oxide layer to form a third oxide spacer, forming a lightly doped region in the substrate, depositing and etching back a nitride layer to form a nitride spacer, and removing a dielectric insulator. schematic diagram. FIG. 23 is a schematic diagram illustrating the formation of intrinsic silicon using the selective epitaxial growth technique. FIG. 24 is a schematic diagram illustrating deposition and etching of an oxide spacer layer to form a contact hole opening. FIG. 25 is a schematic diagram illustrating deposition and etching of a first metal layer to form first metal layer interconnects.

100: Gold Oxygen Half Field Effect Transistor

101:Gate structure

103: source

105: Quarantine

107: drain

109, 111: contact hole

D(L), G(L), S(L), C-S(L), C-D(L): Length

D(W), G(W), S(W), C-S(W), C-D(W): Width

Claims (15)

A transistor structure comprising: A semiconductor substrate having a semiconductor surface; a gate structure with a length; a passage area; - the first isolation zone; a first semiconductor region electrically coupled to a first end of the channel region; a second semiconductor region electrically coupled to a second end of the channel region; and A metal region at least contacts a top surface of the first semiconductor region and a sidewall of the first semiconductor region; wherein the first semiconductor region is located between the first isolation region and the gate structure. The transistor structure as claimed in claim 1, wherein the metal region comprises a first metal-containing region and a first metal layer, wherein the first metal layer contacts the top surface of the first semiconductor region, the first A metal-containing region contacts the sidewall of the first semiconductor region. The transistor structure as claimed in claim 2, further comprising a contact hole located between the first isolation region and the gate structure; a part of the first metal layer fills the contact hole, and another part of the first metal layer A portion is located outside the contact hole. In the transistor structure according to claim 3, the lateral length of the contact hole is not greater than a minimum feature length. The transistor structure of claim 2, wherein the first metal layer is located above the semiconductor surface, and the first metal-containing region is located below the semiconductor surface. The transistor structure as claimed in claim 5, further comprising a contact hole located between the first isolation region and the gate structure; a part of the first metal layer fills the contact hole, and a part of the first metal layer The other part is located outside the contact hole. The transistor structure as claimed in claim 1, wherein the metal region further contacts a bottom surface of the first semiconductor region. The transistor structure as claimed in claim 1, further comprising a first protection layer located under the metal region and the first semiconductor region; the first protection layer isolates a bottom surface of the metal region from contacting the semiconductor substrate, and isolates A bottom surface of the first semiconductor region is in contact with the semiconductor substrate. The transistor structure as claimed in claim 8, wherein the first protection layer is an L-type oxide protection layer. A transistor structure comprising: A semiconductor substrate having a semiconductor surface; a gate structure with a length; a passage area; - the first isolation zone; a first semiconductor region electrically coupled to a first end of the channel region; a second semiconductor region electrically coupled to a second end of the channel region; a first metal region contacts the first semiconductor region; and A first protection layer is located under the first metal region and the first semiconductor region, the first protection layer isolates a bottom surface of the first semiconductor region from contacting the semiconductor substrate, wherein the first protection layer is an L-type oxide The protective layer. The transistor structure as claimed in claim 10, wherein the first protective layer further isolates a bottom surface of the first metal region from contacting the semiconductor substrate. The transistor structure as claimed in claim 11 further comprises a second metal region contacting the second semiconductor region, wherein a bottom surface of the second metal region contacts the semiconductor substrate. The transistor structure as claimed in claim 11 further comprises a second protection layer under the second semiconductor region to isolate a bottom surface of the second semiconductor region from contacting the semiconductor substrate. The transistor structure as claimed in claim 10, further comprising a contact hole between the first isolation region and the gate structure; a part of the first metal layer fills the contact hole and contacts the first semiconductor region, Another part of the first metal layer is located outside the contact hole. In the transistor structure according to claim 14, the lateral length of the contact hole is not greater than a minimum feature length.

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