TW202306317A - Clock generator device and clock generation method - Google Patents

Abstract

A clock generator device includes a first clock generator circuit, a second clock generator circuit, a detector circuit, and a selection circuit. The first clock generator circuit has a first starting voltage and generates a first clock signal in response to a supply voltage. The second clock generator circuit has a second starting voltage, and generates a second clock signal in response to the supply voltage. The detector circuit detects the second clock signal to generate a valid signal. The selection circuit selectively outputs one of the first clock signal and the second clock signal according to the valid signal. The first starting voltage is lower than the second starting voltage.

Description

Clock generating device and clock generating method

This case is about a clock generating device, especially about a clock generating device and a clock generating method that can shorten system start-up time.

In some applications that require a real time clock (RTC), when the system is powered on, the digital circuits in the system need a stable clock signal to start operating. However, generally oscillator circuits operate at relatively high voltages. When the supply voltage does not reach the minimum operating voltage of the oscillator circuit, the oscillator circuit cannot provide a proper clock signal. Therefore, the digital circuit can obtain a proper clock signal only after the level of the supply voltage rises to the minimum operating voltage. As a result, the digital circuit needs to wait for a period of time before starting to operate after the system is turned on, which cannot meet the application scenarios where the system needs to be quickly started.

In some embodiments, the clock generating device includes a first clock generating circuit, a second clock generating circuit, a first detecting circuit and a selecting circuit. The first clock generating circuit has a first startup voltage and generates a first clock signal in response to a supply voltage. The second clock generating circuit has a second startup voltage and generates a second clock signal in response to the supply voltage. The first detection circuit detects the second clock signal to generate a validation signal. The selection circuit selects to output one of the first clock signal and the second clock signal according to the validation signal. The first startup voltage is lower than the second startup voltage.

In some implementation aspects, the clock generation method includes the following operations: using a first clock generation circuit to generate a first clock signal in response to a supply voltage, wherein the first clock generation circuit has a first start-up voltage; Using a second clock generating circuit to generate a second clock signal in response to the supply voltage, wherein the second clock generating circuit has a second startup voltage, and the first startup voltage is lower than the second startup voltage; detecting measuring the second clock signal to generate a validation signal; and selecting to output one of the first clock signal and the second clock signal according to the validation signal.

In some embodiments, the clock generating device includes a first clock generating circuit, a second clock generating circuit, a first detecting circuit and a selecting circuit. The first clock generating circuit generates a first clock signal when a supply voltage is greater than or equal to a first level. The second clock generating circuit generates a second clock signal when the supply voltage is greater than or equal to a second level, wherein the first level is lower than the second level. The detection circuit detects the second clock signal to generate a validation signal. The selection circuit selects to output one of the first clock signal and the second clock signal according to the validation signal.

About the feature, implementation and effect of this case, hereby cooperate with drawing as preferred embodiment and describe in detail as follows.

All terms used herein have their ordinary meanings. The definitions of the above-mentioned terms in commonly used dictionaries, and the use examples of any terms discussed here in the content of this case are only examples, and should not limit the scope and meaning of this case. Likewise, this case is not limited to the various embodiments shown in this specification.

As used herein, "coupling" or "connection" can refer to two or more elements in direct physical or electrical contact with each other, or indirect physical or electrical contact with each other, and can also refer to two or more components. Components operate or act on each other. As used herein, the term "circuit" can be a device that is connected in a certain way to process signals by at least one transistor and/or at least one active and passive element.

FIG. 1A is a schematic diagram of a clock generating device 100 according to some embodiments of the present invention. In some embodiments, the clock generating device 100 can be applied to an image processing chip. For example, the clock generating device 100 can provide the final clock signal CKF to a security chip, so that the security chip has a shorter start-up time to start monitoring the environment.

The clock generating device 100 includes a clock generating circuit 110 , a clock generating circuit 120 , a detection circuit 130 and a selection circuit 140 . In some embodiments, the clock generating circuit 110 has a first starting voltage, the clock generating circuit 120 has a second starting voltage, and the first starting voltage is lower than the second starting voltage. In some embodiments, the precision of the clock signal CK2 generated by the clock generating circuit 120 is higher than the precision of the clock signal CK1 generated by the clock generating circuit 110 . In some embodiments, the frequency of the clock signal CK1 is close to (or identical to) the frequency of the clock signal CK2 .

For example, the clock generating circuit 110 can be (but not limited to) a free running oscillator, which can generate the clock signal CK1 in response to the supply voltage VDD. The clock generating circuit 120 can be (but not limited to) a crystal oscillator, which can generate the clock signal CK2 in response to the supply voltage VDD. In some embodiments, the operating voltage range of the clock generating circuit 110 is about 0.5-3.3 volts, and the operating voltage range of the clock generating circuit 120 is about 0.9-3.3 volts. It can be seen that the first voltage of the clock generating circuit 110 The starting voltage is 0.5 volts, and the second starting voltage of the clock generating circuit 120 is 0.9 volts. When the supply voltage VDD is greater than or equal to the first startup voltage, the clock generating circuit 110 starts to operate to generate the clock signal CK1 . When the supply voltage VDD is greater than or equal to the second startup voltage, the clock generating circuit 120 starts to operate to generate the clock signal CK2. With the above arrangement, when the clock generating device 100 is powered on, the supply voltage VDD will start to rise from a low voltage level. Since the first startup voltage is lower than the second startup voltage, the clock generator circuit 110 generates a clock signal The time of CK1 is earlier than the time when the clock generating circuit 120 generates the clock signal CK2.

The detection circuit 130 is used to detect whether the clock signal CK2 is stable and whether the characteristics (such as frequency) of the clock signal CK2 are suitable, so as to generate the validation signal SV. In some embodiments, as shown in FIG. 2A , the detection circuit 130 can be implemented by an analog circuit. In some embodiments, as shown in FIG. 2B , the detection circuit 130 may be implemented by a digital circuit. In other embodiments, the detection circuit 130 may be implemented by a mixed signal circuit.

The selection circuit 140 can select and output one of the clock signal CK1 and the clock signal CK2 as the final clock signal CKF according to the validation signal SV. For example, when the clock generating device 100 is powered on, the supply voltage VDD starts to increase. When the supply voltage VDD is greater than or equal to the first start-up voltage, the clock generating circuit 110 can start to operate to generate the clock signal CK1, and the clock generating circuit 120 has not been started yet. Under this condition, the detection circuit 130 outputs the validation signal SV having a first logic value (for example, logic value 0). The selection circuit 140 can select the output clock signal CK1 as the final clock signal CKF according to the validation signal SV. When the supply voltage VDD is greater than or equal to the second startup voltage, the clock generating circuit 120 starts to operate to output the clock signal CK2. Under this condition, the detection circuit 130 outputs the validation signal SV having a second logic value (for example, logic value 1). The selection circuit 140 can select the output clock signal CK2 as the final clock signal CKF according to the validation signal SV. With the above arrangement, the clock generating device 100 can provide the final clock signal CKF faster during the boot process, so as to speed up the start-up time of other circuits in the system. In some embodiments, the selection circuit 140 may be a multiplexer circuit.

FIG. 1B is a schematic diagram of a clock generating device 100A according to some embodiments of the present invention. Compared with FIG. 1A , the clock generating device 100A in FIG. 1B further includes a detection circuit 150 , which can be used to confirm whether the clock generating circuit 110 starts to output the clock signal CK1 to generate the control signal SC1 . In some embodiments, the control signal SC1 can be used to enable peripheral circuits (not shown) in the system. For example, when the clock generating circuit 110 starts to output the clock signal CK1, the control signal SC1 switches from the first logic value to the second logic value. In response to the control signal SC1, a power-on control circuit in the system is enabled to start supplying power to peripheral circuits. In this way, peripheral circuits can start operating more quickly.

FIG. 2A is a schematic diagram of the detection circuit 130 in FIG. 1A or FIG. 1B according to some embodiments of the present invention. The detection circuit 130 includes a current source 210 , a switch 220 , a capacitor 230 and an inverter 240 .

A first terminal of the current source 210 receives the supply voltage VDD, and a second terminal of the current source 210 is coupled to the first terminal of the switch 220 . The second terminal of the switch 220 receives the ground voltage GND, and the control terminal of the switch 220 receives the clock signal CK2. The first end of the capacitor 230 is coupled to the second end of the current source 210, and the second end of the capacitor 230 receives the ground voltage GND. The input terminal of the inverter 240 is coupled to the first terminal of the capacitor 230, and the output terminal of the inverter 240 is used to output the validation signal SV. The current source 210 is used for providing the current signal SI. The switch 220 is used for selectively conducting according to the clock signal CK2. The capacitor 230 is charged by the current signal SI and discharged by the switch 220 to generate the detection signal SD. The inverter 240 is used for outputting the validation signal SV according to the detection signal SD.

In detail, when the clock generating circuit 120 has not generated the clock signal CK2 , the switch 220 is not turned on, and the capacitor 230 is charged by the current signal SI to generate the detection signal SD having a high level. In response to the detection signal SD, the inverter 240 outputs the validation signal SV having a low level (corresponding to logic value 0). Alternatively, when the clock generating circuit 120 starts to generate a suitable clock signal CK2, it means that the clock signal CK2 has a certain number of pulses stably. The switch 220 is sequentially turned on in response to the pulses to discharge the capacitor 230 to generate the detection signal SD having a low level. In response to the detection signal SD, the inverter 240 outputs the validation signal SV having a high level (corresponding to logic value 1). In this way, the validation signal SV can be used to indicate whether the clock generating circuit 120 is stably generating the appropriate clock signal CK2.

In this example, the capacitance C of the capacitor 230 can be used to adjust the generation time of the high-level validation signal SV, thereby setting the time from switching the output clock signal CK1 to the output clock signal CK2 (hereinafter referred to as switching time T). In some embodiments, the switching time T can be determined according to the application requirements of the clock signal CK2. For example, the switching time T can be determined according to the required frequency of the clock signal CK2.

其中，供應電壓VDD可為前述的第二啟動電壓所對應的電壓範圍，Q為電容230儲存的電荷量，I為電容230的放電電流，T _CK2為時脈訊號CK2的週期，M為預定數值。上式表示電容C在預定期間（其對應於M個時脈訊號CK2的週期）放電使得電容C的第一端之位準為地電壓GND。根據上式，可藉由調整電容230的容值C或是電流訊號SI（影響電容C的放電電流I）來設定切換時間T。 In some embodiments, the switching time T and the capacitance C conform to the following formula:

Wherein, the supply voltage VDD can be the voltage range corresponding to the aforementioned second start-up voltage, Q is the amount of charge stored in the capacitor 230, I is the discharge current of the capacitor 230, T _CK2 is the period of the clock signal CK2, and M is a predetermined value. . The above formula indicates that the capacitor C is discharged in a predetermined period (corresponding to M cycles of the clock signal CK2 ) so that the level of the first terminal of the capacitor C is the ground voltage GND. According to the above formula, the switching time T can be set by adjusting the capacitance C of the capacitor 230 or the current signal SI (affecting the discharge current I of the capacitor C).

FIG. 2B is a schematic diagram of the detection circuit 130 in FIG. 1A or FIG. 1B according to some embodiments of the present invention. The detection circuit 130 includes a counter 250 and a comparator 260 . The counter 250 is used for counting the clock signal CK2 to generate a count value CT. In some embodiments, the counter 250 can be an up counter, a down counter, a ripple counter or other types of counters. The comparator 260 is used for outputting the validation signal SV when the count value is equal to the threshold TH.

For example, the counter 250 is an up counter, which is used to count up in response to one pulse of the clock signal CK2 to generate a count value CT. When the count value CT increases to be equal to the threshold value TH, it means that the clock generating circuit 120 can output the clock signal CK2 stably. Under this condition, the comparator 260 outputs the validation signal SV with a specific logic value. Compared with FIG. 2A , in this example, the frequency and stability of the clock signal CK2 can be set by adjusting the threshold TH.

In some embodiments, the detection circuit 150 and the detection circuit 130 have similar or identical circuit arrangements. The arrangement of the detection circuit 150 can refer to FIG. 2A or FIG. 2B , so it will not be repeated here. If the detection circuit 150 is implemented using the example shown in FIG. 2A , the supply voltage VDD in the above formula can be the voltage range corresponding to the operating voltage of the clock generator circuit 110 . Alternatively, if the detection circuit 150 is implemented with the example shown in FIG. 2B , the threshold TH used by the detection circuit 150 may be different from the threshold TH used by the detection circuit 130 .

FIG. 3 is a schematic diagram of a clock generating device 300 according to some embodiments of the present invention. Compared with FIG. 1B , in this example, the validation signal SV can be used to control the clock generating circuit 110 . For example, the clock generating circuit 110 is a ring oscillator circuit with power gating, which can be enabled or disabled according to the validation signal SV.

In some embodiments, the initial value of the validation signal SV is a first logic value. In response to the validation signal SV having a first logic value, the clock generating circuit 110 is enabled to start generating the clock signal CK1 according to the supply voltage VDD. When the clock generating device 300 is powered on, the supply voltage VDD starts to climb from a zero level to a predetermined level. When the supply voltage VDD is higher than or equal to the first startup voltage, the clock generator circuit 110 starts to generate the clock signal CK1 . In response to the validation signal SV having the first logic value, the selection circuit 140 outputs the clock signal CK1 as the final clock signal CKF. When the supply voltage VDD is higher than or equal to the second startup voltage, the clock generator circuit 120 starts to generate the clock signal CK2. The detecting circuit 130 confirms that the clock generating circuit 120 can stably generate a suitable clock signal CK2, and generates a valid signal SV having a second logic value. In response to the validation signal SV having the second logic value, the selection circuit 140 switches to output the clock signal CK2 as the final clock signal CKF. On the other hand, the clock generating circuit 110 can be turned off in response to the validation signal SV having the second logic value, so as to save system power consumption. When the clock generating circuit 110 is turned off, the clock generating circuit 110 stops outputting the clock signal CK1 . Under this condition, the detection circuit 150 outputs the control signal SC1 with a first logic value.

Moreover, compared with FIG. 1B , the clock generating device 300 further includes a logic gate circuit 310 . The logic gate circuit 310 is used for generating the control signal SC2 according to the validation signal SV and the control signal SC1. The control signal SC2 can be used to control the digital circuit in the system. For example, the control signal SC2 can be used to control the power control circuit to determine whether to supply power to the digital circuit.

In some embodiments, the logic gate circuit 310 may be (but not limited to) an exclusive OR (XOR) gate circuit. When the supply voltage VDD is powered on, the clock generating circuit 110 first outputs the clock signal CK1 (compared to the clock generating circuit 120 ). Under this condition, the control signal SC1 has a second logic value and the validation signal SV has a first logic value. The logic gate circuit 310 generates a control signal SC2 having a second logic value in response to the control signal SC1 and the validation signal SV. The power control circuit can provide power to the digital circuit in response to the control signal SC2. When the clock generating circuit 120 outputs a proper clock signal CK2 , the detection circuit 130 outputs a valid signal SV having a second logic value. Under this condition, the clock generating circuit 110 is turned off to stop outputting the clock signal CK1 , and the detection circuit 150 accordingly outputs the control signal SC1 having a first logic value. In response to the validating signal SV and the control signal SC1, the logic gate circuit 310 generates the control signal SC2 having a second logic value, and the power control circuit can continuously provide power to the digital circuit.

FIG. 4A is a schematic diagram of a clock generating device 400 according to some embodiments of the present invention. Compared with the clock generator 300 in FIG. 3 , the clock generator 400 further includes a delay circuit 410 and a delay circuit 420 . The delay circuit 410 is used to delay the validation signal SV to generate the signal S1. The delay circuit 420 is used to delay the control signal SC1 to generate the signal S2. The logic gate circuit 310 is used for generating the control signal SC2 according to the signal S1 and the signal S2. In some embodiments, the delay time of the delay circuit 420 may be smaller than the delay time of the delay circuit 410 . In this example, the control signal SC2 can be used to control digital circuits related to real time clock applications. For example, the digital circuit may include a flip-flop circuit with reset function, which can be reset according to the control signal SC2 to reset the set value or parameter of the digital circuit.

To illustrate the operation of the clock generating device 400 , refer to FIG. 4B , which is a schematic diagram illustrating the timing of the clock generating device 400 in FIG. 4A according to some embodiments of the present invention. After the clock generating device 400 is powered on, at time T0 , the clock generating circuit 110 outputs the clock signal CK1 , and the selection circuit 140 outputs the clock signal CK1 as the final clock signal CKF. At time T1, the detecting circuit 150 determines that the clock generating circuit 110 can output the clock signal CK1 stably, and outputs the control signal SC1 having a second logic value (corresponding to a high level). At time T2, the clock generating circuit 120 outputs the clock signal CK2. At time T3, the detection circuit 130 judges that the clock generator circuit 120 can stably output the appropriate clock signal CK2, and outputs the validation signal SV having a second logic value (corresponding to a high level). In response to the validation signal SV, the clock generating circuit 110 is turned off to stop outputting the clock signal CK1. Under this condition, the detecting circuit 150 determines that the clock generating circuit 110 does not output the clock signal CK1 , and outputs the control signal SC1 having a first logic value (corresponding to a low level). The delay circuit 410 delays the validation signal SV to output the signal S1. The delay circuit 420 delays the control signal SC1 to output the signal S2. The logic gate circuit 310 can generate the control signal SC2 according to the signal S1 and the signal S2. With the above arrangement, as shown in FIG. 4B , the control signal SC2 has a reset period TR. During the reset period TR, the operation of the digital circuit part of the RTC circuit will be reset. In this way, the operation of the digital circuit part can be prevented from being affected by the switching process of the clock signal (for example, a glitch), thereby improving the operation stability of the overall system.

FIG. 5 is a flowchart of a clock generation method 500 according to some embodiments of the present invention. In some embodiments, the clock generation method 500 may be performed by (but not limited to) the clock generation device shown in FIG. 1A , FIG. 1B , FIG. 3 or FIG. 4 .

In operation S510, a first clock generating circuit is utilized to generate a first clock signal in response to a supply voltage, wherein the first clock generating circuit has a first start-up voltage. In operation S520, a second clock generating circuit is utilized to generate a second clock signal in response to the supply voltage, wherein the second clock generating circuit has a second startup voltage, and the first startup voltage is lower than the second startup voltage. Voltage. In operation S530, the second clock signal is detected to generate a validation signal. In operation S540, one of the first clock signal and the second clock signal is selected to be output as the final clock signal according to the validation signal.

For the description of the above operation S510 to operation S540, reference may be made to the foregoing embodiments, so the description is not repeated. The multiple operations of the above clock generation method 500 are only examples, and are not limited to be performed in the order in this example. Various operations in the clock generating method 500 may be appropriately added, replaced, omitted or performed in a different order without departing from the operation manner and scope of the various embodiments of the present application. Alternatively, one or more operations under the clock generation method 500 may be performed concurrently or partially concurrently.

To sum up, the clock generating device and the clock generating method in some embodiments of the present case can output clock signals faster, so as to speed up the time for the system to start operating. In this way, the start-up time of related circuits or chips for RTC applications can be reduced.

Although the embodiments of this case are as described above, these embodiments are not intended to limit this case. Those with ordinary knowledge in the technical field can make changes to the technical characteristics of this case according to the explicit or implied content of this case. All these changes All may fall within the scope of patent protection sought in this case. In other words, the scope of patent protection in this case shall be subject to the definition of the scope of patent application in this specification.

100, 100A: clock generator 110, 120: clock generation circuit 130, 150: Detection circuit 140: Select circuit 210: current source 220: switch 230: capacitance 240: Inverter 250: counter 260: comparator 300, 400: clock generator 310: logic gate circuit 410, 420: delay circuit 500: clock generation method CK1, CK2: clock signal CKF: final clock signal CT: count value GND: ground voltage S1, S2: signal S510, S520, S530, S540: Operation SC1, SC2: Control signal SD: detect signal SV: Validation signal T0~T3: time TH: critical value TR: during reset VDD: supply voltage

[Fig. 1A] is a schematic diagram of a clock generating device according to some embodiments of the present case; [Fig. 1B] is a schematic diagram of a clock generating device according to some embodiments of the present invention; [Fig. 2A] is a schematic drawing of the detection circuit in Fig. 1A or Fig. 1B according to some embodiments of the present case; [Fig. 2B] is a schematic drawing of the detection circuit in Fig. 1A or Fig. 1B according to some embodiments of the present case; [Figure 3] is a schematic diagram of a clock generating device according to some embodiments of this case; [Fig. 4A] is a schematic diagram of a clock generating device according to some embodiments of the present case; [FIG. 4B] is a schematic diagram of the timing sequence of the clock generating device in FIG. 4A according to some embodiments of the present invention; and [ FIG. 5 ] is a flowchart of a clock generation method according to some embodiments of the present case.

100: clock generator

110,120: clock generation circuit

130: Detection circuit

140: Select circuit

CK1, CK2: clock signal

CKF: final clock signal

SV: Validation signal

VDD: supply voltage

Claims (11)

A clock generator, comprising: A first clock generating circuit, having a first start-up voltage, and generating a first clock signal in response to a supply voltage; A second clock generating circuit, having a second start-up voltage, and generating a second clock signal in response to the supply voltage; A first detection circuit detects the second clock signal to generate a validation signal; and a selection circuit, for selecting to output one of the first clock signal and the second clock signal according to the activation signal; Wherein, the first startup voltage is lower than the second startup voltage. The clock generating device according to claim 1, wherein the validation signal is used to control the first clock generating circuit. For example, the clock generating device of claim 1 further includes: A second detection circuit detects the first clock signal to generate a first control signal. For example, the clock generating device of claim 3 further includes: A logic gate circuit is used to generate a second control signal according to the validation signal and the first control signal, wherein the second control signal is used to control a digital circuit. For example, the clock generating device of claim 3 further includes: A first delay circuit, used to delay the activation signal to generate a first signal; a second delay circuit for delaying the first control signal to generate a second signal; and a logic gate circuit for generating a second control signal according to the first signal and the second signal; Wherein, a delay time of the first delay circuit is smaller than a delay time of the second delay circuit. The clock generating device according to claim 1, wherein when the supply voltage is equal to or greater than the first start-up voltage, the first clock generating circuit starts to generate the first clock signal, and when the supply voltage is equal to or greater than the When the second startup voltage is applied, the second clock generator circuit starts to generate the second clock signal. The clock generator according to claim 1, wherein the first detection circuit includes: a current source for providing a current signal; a switch for selectively conducting according to the second clock signal; a capacitor is used to charge through the current signal and discharge through the switch to generate a detection signal; and An inverter is used for outputting the validation signal according to the detection signal. The clock generator according to claim 1, wherein the first detection circuit includes: a counter for counting the second clock signal to generate a count value; and A comparator is used for outputting the validation signal when the count value is equal to a critical value. The clock generating device according to claim 1, wherein the first clock generating circuit is a free running oscillator, and the second clock generating circuit is a crystal oscillator. A clock generation method, comprising: generating a first clock signal in response to a supply voltage by using a first clock generating circuit, the first clock generating circuit having a first start-up voltage; generating a second clock signal in response to the supply voltage by a second clock generating circuit, the second clock generating circuit having a second start-up voltage; detecting the second clock signal to generate a validation signal; and select to output one of the first clock signal and the second clock signal according to the validation signal; Wherein, the first startup voltage is lower than the second startup voltage. A clock generator, comprising: A first clock generator circuit, which generates a first clock signal when a supply voltage is greater than or equal to a first level; a second clock generator circuit for generating a second clock signal when the supply voltage is greater than or equal to a second level, wherein the first level is lower than the second level; A detection circuit detects the second clock signal to generate a validation signal; and A selection circuit selects and outputs one of the first clock signal and the second clock signal according to the activation signal.

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