TW202306169A - Systems and methods for singulation of gan-on-silicon wafers - Google Patents

Abstract

Structures and related techniques for singulating GaN-on-Si wafers are disclosed. In one aspect, a semiconductor wafer includes a silicon layer, and a gallium nitride (GaN) layer disposed on the silicon layer and defining a plurality of trenches that each extend to the silicon layer. In another aspect, the GaN layer includes one or more gallium nitride layers of different compositions. In yet another aspect, the wafer includes a plurality of dielectric layers disposed on the GaN layer. In yet another aspect, each of the plurality of trenches has a depth that is equal to a sum of a thickness of the GaN layer and a thickness of the plurality of the dielectric layers.

Description

System and method for singulation of GAN-on-silicon wafers

The described embodiments relate generally to the singulation of gallium nitride (GaN) wafers on silicon (Si), and more specifically, the present embodiments relate to methods for self-contained formation of one or more wafers on silicon wafers. A system and method for singulating individual grains of a silicon wafer with multiple GaN layers.

In semiconductor technology, gallium nitride (GaN) is a compound semiconductor material used to form various devices such as high power and/or high voltage transistors. These devices can be formed by growing epitaxial layers on silicon, silicon carbide, sapphire, gallium nitride, or other substrates. Often, such devices are formed using aluminum gallium nitride (AlGaN) and heteroepitaxial junctions of GaN. This structure is known to form a high electron mobility two-dimensional electron gas (2DEG) at the interface of the two materials. Electron gas can have a charge density in a 2DEG. There is a need to have efficient fabrication methods for GaN-on-Si wafers.

In some embodiments, a semiconductor wafer is disclosed. A semiconductor wafer includes a silicon layer, and a gallium nitride (GaN) layer disposed on the silicon layer and defining a plurality of trenches each extending into the silicon layer.

In some embodiments, the GaN layer includes one or more gallium nitride layers having different compositions.

In some embodiments, the semiconductor wafer further includes a plurality of dielectric layers disposed on the GaN layer.

In some embodiments, each of the plurality of trenches has a depth equal to the sum of the thickness of the GaN layer and the thickness of the plurality of dielectric layers.

In some embodiments, the plurality of trenches are formed at the front end of line (FEOL).

In some embodiments, the plurality of trenches are formed at a mid-line-of-line (MOL).

In some embodiments, the plurality of trenches are formed at a back end of line (BEOL).

In some embodiments, a method of forming semiconductor grains is disclosed. The method includes: forming a silicon layer, forming a gallium nitride (GaN) layer on the silicon layer, defining a plurality of grooves in the GaN layer each extending to the silicon layer, and singulating semiconductor grains along the plurality of grooves.

In some embodiments, in the disclosed methods, the GaN layer includes one or more gallium nitride layers having different compositions.

In some embodiments, in the disclosed method, the silicon layer defines the outer perimeter of the semiconductor die, and the GaN layer is recessed from the outer perimeter.

In some embodiments, the disclosed method further includes forming a plurality of dielectric layers on the GaN layer.

In some embodiments, defining the plurality of trenches is performed at the front end of line (FEOL).

In some embodiments, defining the plurality of trenches is performed at a mid-line-of-line (MOL).

In some embodiments, defining the plurality of trenches is performed at a back end of line (BEOL).

In some embodiments, a semiconductor die is disclosed. The semiconductor die includes a silicon layer defining an outer periphery of the semiconductor die, a gallium nitride (GaN) layer disposed on the silicon layer and recessed from the outer periphery.

In some embodiments, the GaN layer includes one or more gallium nitride layers having different compositions.

In some embodiments, the semiconductor die further includes a plurality of dielectric layers disposed on the GaN layer.

In some embodiments, the recess in the GaN layer is formed at the front end of line (FEOL).

In some embodiments, the recess in the GaN layer is formed at a mid-line-of-line (MOL).

In some embodiments, the recess in the GaN layer is formed at a back end of line (BEOL).

Cross References to Related Applications

This application claims a U.S. provisional application titled "Systems and Methods for Singulation of GaN-On-Silicon Wafers" filed on July 15, 2021 No. 63/203,279, and the United States of America filed on October 12, 2021 entitled "Systems and Methods for Singulation of GaN-On-Silicon Wafers" The benefit of Provisional Application No. 63/262,437, the entire contents of which are incorporated herein by reference for all purposes.

The devices, structures and related technologies disclosed herein generally relate to singulation of gallium nitride (GaN) on silicon (Si) wafers. More specifically, the devices, structures, and related techniques disclosed herein relate to the use of silicon wafers that include one or more GaN layers formed on a silicon wafer (e.g., forming a GaN-on-Si wafer) Systems and methods for granulating (eg, dicing) individual dies. In various embodiments, systems and methods for singulating individual dies from GaN-on-Si wafers enable efficient singulation of wafers while preventing chipping, delamination, and/or fracture of GaN layers, thereby Improved reliability of the die is obtained. This enables faster sawing speeds, providing efficient and economical dicing of GaN-on-Si wafers.

In some embodiments, GaN-free dicing vias may be fabricated by forming etch back along each dicing via in the shape of a trench in a GaN-on-Si wafer. This trench can be formed at any stage in the fabrication process and can be formed through all layers except the silicon substrate. At the end of the fabrication process, a sawing operation may be performed along the GaN-free dicing via, sawing through the GaN-free dicing via and only in contact with the silicon substrate. Since the saw is only in contact with the silicon substrate, there is no chipping, delamination and/or fracture of the GaN layer. In various embodiments, GaN-free dicing vias can eliminate the need for laser grooving during dicing, thereby reducing manufacturing costs while preventing die cracking. In some embodiments, GaN-free dicing vias can reduce die area by reducing the size of inactive die regions along each dicing via to prevent die cracking. In this way, the absence of GaN dicing vias can increase the number of dies that can be collected from the wafer for the same active die area, thus achieving a reduction in die cost. Various inventive embodiments are described herein, including methods, procedures, systems, apparatuses, and the like.

Several illustrative embodiments will now be described with respect to the accompanying drawings, which form a part of this disclosure. The following description provides examples only, and is not intended to limit the scope, applicability, or configuration of the disclosure. Indeed, the following description of the embodiments will provide those skilled in the art with an enabling description for implementing one or more embodiments. It being understood that various changes can be made in the function and arrangement of elements without departing from the spirit and scope of the disclosure. In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of certain inventive embodiments. It will be apparent, however, that various embodiments may be practiced without these specific details. The drawings and descriptions are not intended to be limiting. The word "example" or "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" or "example" is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

1 illustrates a plan view of a GaN-on-Si wafer 100 with no GaN dicing vias 102 in accordance with an embodiment of the present disclosure. As shown in FIG. 1 , GaN-free dicing vias 102 may be used to singulate individual die from a GaN-on-Si wafer 100 . The GaN-on-Si wafer 100 may include a silicon substrate and one or more GaN layers formed on the silicon substrate, as described in more detail below.

2A illustrates a simplified partial cross-sectional view of the GaN-on-Si wafer 100 shown in FIG. 1 in a region without GaN dicing vias 102 in accordance with an embodiment of the present disclosure. As shown in FIG. 2A , GaN-free dicing via 102 may be formed from which GaN layer 206 has been removed, leaving only silicon layer 204 in dicing via 102 . In some embodiments, the GaN-free cut vias may be referred to as trenches. In various embodiments, GaN layer 206 may include multiple gallium nitride layers having different compositions. FIG. 2A also shows a GaN-on-Si wafer with a wiring and ohmic contact layer 224 , one or more dielectric layers 208 , a passivation layer 210 , and a polyimide layer 212 . The wiring and ohmic contact layer 224 may include metal layers, such as the first metal layer 214 , which may be used for ohmic contact formation in active devices, the second metal layer 216 and the third metal layer 218 . In some embodiments, GaN-free dicing via 102 may have a depth 221 equal to the sum of the thicknesses of GaN layer 206 , dielectric layer 208 , and passivation layer 210 . Removing the GaN layer 206 in the dicing via 102 enables efficient singulation of the GaN-on-Si wafer 100 while preventing chipping, delamination, and/or fracture of the GaN layer, resulting in improved reliability of the die. This enables faster sawing speeds, providing efficient and economical dicing of GaN-on-Si wafers 100 . In various embodiments, the GaN-free dicing vias 102 may be fabricated by etching trenches along each dicing via 102 in the GaN-on-Si wafer 100 to remove portions of the GaN layer 206 . This trench can be formed at any stage in the fabrication process, as described in further detail below. In some embodiments, trenches may be formed through all layers of the GaN-on-Si wafer 100 except the silicon layer 204 .

2B illustrates a simplified partial cross-sectional view of the GaN-on-Si wafer 100 shown in FIG. 2A after a sawing operation forms dicing via cuts 226 to singulate the wafer. Individual die 209 may be formed in this manner. Individual die 209 includes a silicon layer 204 defining a perimeter 211 in which GaN layer 206 has been recessed. The sawing operation may be performed by means of a dicing saw, laser or other suitable singulation process. In some embodiments, at the end of the fabrication process, a sawing operation may be performed along the GaN-free dicing via 102 , sawing through the GaN-free dicing via and only in contact with the silicon substrate 204 . Because the saw is only in contact with the silicon substrate 204, there is no chipping, delamination and/or fracture of the GaN layer 206. More specifically, in some embodiments, the GaN-free dicing via 102 may be wider than the width of the dicing saw that forms the dicing via kerf 226 .

In various embodiments, the absence of GaN dicing vias 102 may eliminate the need for laser grooving during dicing, thereby reducing assembly costs while preventing die cracking. In some embodiments, GaN-free dicing vias 102 may reduce die area by reducing the size of inactive die regions along each dicing via to prevent die cracking. In this way, the absence of GaN dicing vias can increase the number of dies that can be collected from the wafer for the same active die area, thus achieving a reduction in die cost. As an example, using the structures and methods disclosed herein, the number of good dies per wafer can be increased by between 10% and 20% for 1 mm ² die. In various embodiments, the ratio of the size of the inactive die region along the dicing via 222 to the size of the GaN-free dicing via 220 may be used in order to maximize the number of die collected from the wafer. This ratio may be part of a process design kit (PDK) for designing integrated circuits on GaN-on-Si wafers. By reducing the size of the inactive area along the dicing via, the die-to-die spacing can be reduced, for example, from 160 um to 80 um, or to other suitable dimensions. Additionally, the width of the GaN-free dicing vias may be adjustable.

In some embodiments, GaN-free dicing vias may be formed by means of a dry etch process and/or by means of a combination of dry and wet etch processes. In various embodiments, GaN-free dicing vias may be formed at front end of line (FEOL), middle end of line (MOL), or back end of line (BEOL) of the wafer fabrication process. In some embodiments, the width of the GaN-free region defined within the dicing via may be 60 um. Those skilled in the art will appreciate that the width of the GaN-free region can be a function of the wafer thickness and the wafer saw width.

Referring now to FIGS. 3A-3E , systems and methods for forming GaN-free dicing vias at front-end-of-line (FEOL) are illustrated, in accordance with embodiments of the present disclosure. In FIG. 3A , a GaN-on-Si wafer 300 is provided and includes a GaN layer 302 formed on a Si layer 304 . Portions of GaN layer 302 may be etched away to form GaN-free trenches 308 as shown in Figure 3B. Mask 306 may be used to protect the active area of the wafer during the etching process. In some embodiments, dry etching 307 may be used to form GaN-free trenches 308 . In various embodiments, wet etching or a combination of dry and wet etching may be used to form GaN-free trenches, as described in further detail below. As shown in FIG. 3C , after the GaN-free trenches 308 have been formed, the GaN-on-Si wafer 300 can be processed through fabrication steps to add active and passive regions, including but not limited to metal layers, first, second and third respectively. Three interlayer dielectrics 310 , 312 and 314 , and a capping dielectric layer 316 . As those skilled in the art having the benefit of this disclosure understand, GaN-on-Si wafers can be processed to have as many layers as are suitable for various applications.

The GaN-on-Si wafer 300 may then be passivated by forming a silicon nitride (SiN) layer 318 on the wafer, followed by a polyimide layer 320 , as shown in FIG. 3D . The GaN-on-Si wafer may then be singulated by means of a sawing operation that cuts through the GaN-free dicing vias to form kerfs 322 as shown in Figure 3E. Because the dicing vias do not include the GaN layer and are wider than the width of the saw, the saw does not contact the GaN layer 302, thus preventing chipping and/or fracture of the GaN layer 302. This can improve the reliability of the GaN-on-Si dies collected from the wafer. Furthermore, by eliminating the GaN layer in the dicing vias, the laser grooving step can be eliminated, resulting in improved manufacturing efficiency and cost savings.

4A and 4B illustrate a method for forming a GaN-free trench 308 at the FEOL by means of a combination of dry and wet etching, according to an embodiment of the disclosure. As shown in Figure 4A, dry etching can be used to remove regions of the GaN layer and form relatively narrow GaN-free trench pairs. This may be followed by a wet etch process by which the pair of GaN-free trenches may be enlarged, as shown in Figure 4B. After the wet etch process, a single GaN-free trench remains. Next, the GaN-on-Si wafer may be processed to singulate the GaN-on-Si wafer through the fabrication steps as shown in FIG. 4C, followed by the process described in FIG. 3D and FIG. 3E.

5 illustrates a flow diagram of an example process 500 for forming GaN-free dicing vias on a GaN-on-Si wafer at the FEOL according to an embodiment of the present disclosure. At block 510, a GaN-on-Si wafer is provided. At block 520, the GaN layer in the GaN-free dicing via can be etched away. At block 530, the GaN-on-Si wafer may be processed through fabrication steps. At block 540, the GaN-on-Si wafer may be passivated by forming a SiN layer on the GaN-on-Si wafer. At block 550, the GaN-on-Si wafer may be singulated by means of sawing through GaN-free dicing vias. Process 500 enables efficient singulation of GaN-on-Si wafers and provides increased number of collected good dies per wafer because the saw is not in contact with the GaN layer, preventing chipping and/or fracture of the GaN layer. Furthermore, process 500 can provide an increased number of collected good dies per wafer because the size of inactive areas along the dicing vias can be reduced, thus saving die area and cost. It will be appreciated that process 500 is illustrative and that variations and modifications are possible. Steps described as sequential may be performed in parallel, the order of steps may be changed, and steps may be modified, combined, added, or omitted.

Referring now to FIGS. 6A-6E , systems and methods for forming GaN-free dicing vias at a mid-line-of-line (MOL) are illustrated, in accordance with embodiments of the present disclosure. As shown in Figure 6A, a GaN-on-Si wafer 600 that has been processed by FEOL may be provided. The GaN-on-Si wafer 600 may include a Si layer 604 , a GaN layer 602 formed on the Si layer 604 , and a first metal layer and a first interlayer dielectric layer 606 formed on the GaN layer 602 . The GaN layer 602 and layers above it may be etched away to form a GaN-free trench 610 as shown in Figure 6B. Mask 608 may be used to protect the active area of the wafer during the etching process. In some embodiments, dry etching 609 may be used to form GaN-free trenches 610 . In various embodiments, wet etching or a combination of dry and wet etching may be used to form GaN-free trench 610, as described in further detail below. As shown in FIG. 6C , after the GaN-free trenches 610 have been formed, the GaN-on-Si wafer 600A can be processed through fabrication steps to add active and passive regions, including but not limited to metal layers, second and third interlayer vias, respectively. Electrodes 612 and 614 , and capping dielectric layer 616 . As those skilled in the art having the benefit of this disclosure understand, GaN-on-Si wafers can be processed to have as many layers as are suitable for various applications.

The GaN-on-Si wafer 600 may then be passivated by forming a silicon nitride (SiN) layer 618 on the wafer, followed by a polyimide layer 620, as shown in FIG. 6D. The GaN-on-Si wafer may then be singulated by means of a sawing operation that cuts through the GaN-free dicing vias to form kerfs 622 as shown in Figure 6E. Because the dicing vias do not include the GaN layer and because the GaN-free trench 610 is wider than the width of the saw, the saw does not contact the GaN layer 602, thus preventing chipping and/or fracture of the GaN layer 602. This can improve the reliability of the GaN-on-Si dies collected from the wafer. Furthermore, by eliminating the GaN layer in the dicing vias, the laser grooving step can be eliminated, resulting in improved manufacturing efficiency and cost savings.

7A and 7B illustrate a method for forming a GaN-free trench 610 at a MOL by means of a combination of dry and wet etching, according to an embodiment of the disclosure. As shown in Figure 7A, dry etching can be used to remove regions of the GaN layer and form relatively small GaN-free trench pairs. This may be followed by a wet etch process wherein the pair of GaN-free trenches may be enlarged by means of a wet etch, as shown in Figure 7B, thus remaining a single GaN-free trench. After the GaN-free trenches have been formed, the GaN-on-Si wafer can be processed to singulate the GaN-on-Si wafer through the fabrication steps as shown in FIG. 7C followed by the process described in FIGS. 6D and 6E .

8 illustrates a flow diagram of an example process 800 for forming GaN-free dicing vias on a GaN-on-Si wafer at a MOL in accordance with an embodiment of the present disclosure. At block 810, a GaN-on-Si wafer that has been processed by FEOL is provided. At block 820, the GaN layer in the GaN-free dicing via can be etched away. At block 830, the GaN-on-Si wafer may be processed through the remainder of the fabrication steps. At block 840, the GaN-on-Si wafer may be passivated by forming a SiN layer on the GaN-on-Si wafer. At block 850, the GaN-on-Si wafer may be singulated by means of sawing through GaN-free dicing vias. Process 800 enables efficient singulation of GaN-on-Si wafers and provides increased number of collected good dies per wafer because the saw is not in contact with the GaN layer, preventing chipping and/or fracture of the GaN layer. Furthermore, process 800 can provide an increased number of collected good dies per wafer because the size of inactive areas along dicing vias can be reduced, thus saving die area and cost. It will be appreciated that process 800 is illustrative and that variations and modifications are possible. Steps described as sequential may be performed in parallel, the order of steps may be changed, and steps may be modified, combined, added, or omitted.

Referring now to FIGS. 9A-9D , systems and methods for forming GaN-free dicing vias after back-end-of-line (BEOL) processing are illustrated in accordance with embodiments of the present disclosure. As shown in Figure 9A, a GaN-on-Si wafer 900 may be provided that has been BEOL processed. The GaN-on-Si wafer 900 may include a Si layer 904, a GaN layer 902 formed on the Si layer 904, a metal layer and first, second and third interlayer dielectric layers 906, 912 and 914, respectively, and a capping dielectric Layer 916. The GaN layer 902 and layers above it can be etched away to form a GaN-free trench 910 as shown in FIG. 9B . Mask 908 may be used to protect the active area of the wafer during the etching process. In some embodiments, dry etching 909 may be used to form GaN-free trenches 910 . In various embodiments, wet etching or a combination of dry and wet etching may be used to form GaN-free trench 910 . As will be appreciated by those skilled in the art having the benefit of this disclosure, a GaN-on-Si wafer may include as many layers as are suitable for various applications.

As shown in FIG. 9C , after the GaN-free trenches 910 have been formed, the GaN-on-Si wafer 900 can be passivated by forming a silicon nitride (SiN) layer 918 on the wafer, followed by a polyimide layer 920. . The GaN-on-Si wafer 900 may then be singulated by means of a sawing operation that cuts through GaN-free dicing vias to form kerfs 922 as shown in FIG. 9D . Because the dicing vias do not include a GaN layer that could be chipped and/or broken by the sawing operation, the saw does not make contact with the GaN layer 902, thus preventing chipping and/or breaking of the GaN layer 902. This can improve the reliability of the GaN-on-Si dies collected from the wafer. Furthermore, by eliminating the GaN layer in the dicing vias, the laser grooving step can be eliminated, resulting in improved manufacturing efficiency and cost savings.

10A and 10B illustrate a method for forming a GaN-free trench 910 at the BEOL by means of a combination of dry and wet etching, according to an embodiment of the disclosure. As shown in Figure 10A, dry etching can be used to remove regions of the GaN layer and form relatively small pairs of GaN-free trenches. This may be followed by a wet etch process, where the pair of GaN-free trenches may be enlarged to form a single GaN-free trench by means of wet etching, as shown in Figure 10B. The GaN-on-Si wafer can then be passivated by means of a SiN layer, and a polyimide layer can be formed on the wafer, as shown in Figure 10C. The GaN-on-Si wafer can then be singulated, as depicted in Figure 9D.

11 illustrates a flow diagram of an example process 1100 for forming GaN-free dicing vias on a GaN-on-Si wafer at a MOL in accordance with an embodiment of the present disclosure. At block 1110, a GaN-on-Si wafer that has been BEOL processed is provided. At block 1120, the GaN layer in the GaN-free dicing via can be etched away. At block 1130, the GaN-on-Si wafer may be passivated by forming a SiN layer on the GaN-on-Si wafer. At block 1140, the GaN-on-Si wafer may be singulated by means of sawing through GaN-free dicing vias. Process 1100 enables efficient singulation of GaN-on-Si wafers and provides increased number of collected good dies per wafer because the saw is not in contact with the GaN layer, preventing chipping and/or fracture of the GaN layer . Furthermore, process 1100 can provide an increased number of collected good dies per wafer because the size of inactive areas along the dicing vias can be reduced, thus saving die area and cost. It will be appreciated that process 1100 is illustrative and that variations and modifications are possible. Steps described as sequential may be performed in parallel, the order of steps may be changed, and steps may be modified, combined, added, or omitted.

In some embodiments, a combination of the structures and techniques disclosed herein may be utilized in order to form GaN-free dicing vias. Although structures and methods are described and illustrated herein with respect to GaN-on-Si wafers, embodiments of the disclosure are suitable for use with other compound semiconductor wafers.

In the foregoing specification, embodiments of the disclosure have been described with reference to numerous specific details that may vary from implementation to implementation. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive. The sole and exclusive indicator of the scope of this disclosure, and what applicants desire to be the scope of this disclosure, are the literal and equivalent ranges of the set of claims issued in this application, as published in such claims specific form, including any subsequent corrections. Specific details of a particular embodiment may be combined in any suitable manner without departing from the spirit and scope of the embodiments of the present disclosure.

In addition, spatially relative terms such as "bottom" or "top" and the like may be used to describe an element and/or feature's relationship to another element and/or feature(s), such as as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and/or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "bottom" surfaces would then be oriented "above" other elements or features. The device may be otherwise oriented (eg, rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the terms "and", "or" and "one/or" may include a variety of meanings which are also expected to depend at least in part on the context in which such terms are used. Generally, "or" when used in relation to a list such as A, B or C, is intended to mean A, B and C, used here in an inclusive sense, and A, B or C, here used in an exclusive sense use on. In addition, the term "one or more" as used herein may be used to describe any feature, structure or characteristic in the singular or may be used to describe some combination of features, structures or characteristics. It should be noted, however, that this is merely an illustrative example, and claimed subject matter is not limited to this example. Furthermore, the term "at least one of" if used in connection with a listing such as A, B or C, may be construed to mean any combination of A, B and/or C, such as A, B, C, AB, AC, BC, AA, AAB, ABC, AABBCCC, etc.

Reference throughout this specification to "one example," "an example," "certain examples," or "exemplary implementations" means that a particular feature, structure, or characteristic described with respect to features and/or examples can be included in the claimed subject matter In at least one feature and/or example. Thus, appearances of the phrases "in one instance," "instances," "in some instances," or "in certain embodiments," or other similar phrases throughout this specification are not necessarily all referring to the same feature. , examples and/or limitations. Furthermore, certain features, structures or characteristics may be combined in one or more examples and/or characteristics.

In the preceding detailed description, numerous specific details have been set forth in order to provide a thorough understanding of claimed subject matter. However, those skilled in the art will understand that claimed subject matter may be practiced without these specific details. In other instances, methods and apparatus that would otherwise be known by those skilled in the art have not been described in detail so as not to obscure claimed subject matter. Thus, it is intended that claimed subject matter not be limited to the particular examples disclosed, but that such claimed subject matter may include all forms falling within the scope of the appended claims and equivalents thereof.

100: GaN-on-Si Wafer 102: No GaN dicing via/cutting via 204: silicon layer/silicon substrate 206: GaN layer 208: dielectric layer 209: Individual Die 210: passivation layer 211: Surrounding 212: polyimide layer 214: the first metal layer 216: second metal layer 218: The third metal layer 220: No GaN dicing vias 221: Depth 222: Cutting access 224: Wiring and ohmic contact layer 226: cut channel incision 300: GaN-on-Si Wafer 302: GaN layer 304: Si layer 306: mask 307: Dry etching 308: No GaN trench 310: the first interlayer dielectric 312: Second interlayer dielectric 314: The third interlayer dielectric 316: capping dielectric layer 318: silicon nitride layer 320: polyimide layer 322: incision 500: process 510: block 520: block 530: block 540: block 550: block 600: GaN-on-Si Wafers 602: GaN layer 604: Si layer 606: the first interlayer dielectric layer 608: mask 609: Dry etching 610: No GaN trench 612: Second interlayer dielectric 614: The third interlayer dielectric 616: capping dielectric layer 618: Silicon nitride layer 620: polyimide layer 622: cut 800: process 810: block 820: block 830: block 840: block 850: block 900: GaN-on-Si Wafer 902: GaN layer 904: Si layer 906: the first interlayer dielectric layer 908: mask 909: dry etching 910: No GaN trench 912: second interlayer dielectric layer 914: the third interlayer dielectric layer 916: capping dielectric layer 918: Silicon nitride layer 920: polyimide layer 922: incision 1100: process 1110: block 1120: block 1130: block 1140: block

1 illustrates a GaN-on-Si wafer with GaN-free dicing vias according to an embodiment of the present disclosure;

2A illustrates a diagram showing a side view of the GaN-on-Si wafer of FIG. 1 in accordance with an embodiment of the present disclosure. 2B illustrates a dicing via cut that may be formed by means of a sawing operation, according to an embodiment of the present disclosure;

3A-3E illustrate a method for forming a GaN-free dicing via at a front-end-of-line (FEOL) in accordance with an embodiment of the present disclosure;

4A-4C illustrate a method for forming a GaN-free trench at a FEOL by means of a combination of dry and wet etching in accordance with an embodiment of the disclosure;

5 illustrates a flow diagram of a process for forming GaN-free dicing vias on a GaN-on-Si wafer at the FEOL in accordance with an embodiment of the present disclosure;

6A-6E illustrate a method for forming a GaN-free dicing via at a mid-line-of-line (MOL) according to an embodiment of the present disclosure;

7A-7C illustrate a method for forming a GaN-free trench at a MOL by means of a combination of dry and wet etching, according to an embodiment of the present disclosure;

8 illustrates a flow diagram of a process for forming GaN-free dicing vias on a GaN-on-Si wafer at a MOL in accordance with an embodiment of the present disclosure;

9A-9D illustrate a method for forming a GaN-free dicing via at a back-end-of-line (BEOL) according to an embodiment of the present disclosure;

10A-10C illustrate a method for forming a GaN-free trench at a BEOL by means of a combination of dry and wet etching, according to an embodiment of the present disclosure; and

11 illustrates a flow diagram of a process for forming GaN-free dicing vias on a GaN-on-Si wafer at a BEOL, according to an embodiment of the present disclosure.

102: No GaN dicing via/cutting via

204: silicon layer/silicon substrate

206: GaN layer

208: dielectric layer

210: passivation layer

212: polyimide layer

214: the first metal layer

216: second metal layer

218: The third metal layer

220: No GaN dicing vias

221: Depth

222: Cutting access

224: Wiring and ohmic contact layer

Claims (20)

A semiconductor wafer comprising: a silicon layer; and A gallium nitride (GaN) layer is disposed on the silicon layer and defines a plurality of trenches each extending into the silicon layer. The semiconductor wafer of claim 1, wherein the GaN layer comprises one or more gallium nitride layers having different compositions. The semiconductor wafer according to claim 1, further comprising a plurality of dielectric layers disposed on the GaN layer. The semiconductor wafer of claim 3, wherein each of the plurality of trenches has a depth equal to a sum of a thickness of the GaN layer and a thickness of the plurality of dielectric layers. The semiconductor wafer according to claim 1, wherein the plurality of trenches are formed at a front end of line (FEOL). The semiconductor wafer according to claim 1, wherein the plurality of trenches are formed at a middle-of-line process (MOL). The semiconductor wafer according to claim 1, wherein the plurality of trenches are formed at a back end of line (BEOL). A method of forming a semiconductor grain, the method comprising: forming a silicon layer; forming a gallium nitride (GaN) layer on the silicon layer; defining a plurality of trenches in the GaN layer each extending to the silicon layer; and The semiconductor grains are singulated along the plurality of trenches. The method of claim 8, wherein the GaN layer comprises one or more gallium nitride layers having different compositions. The method of claim 8, wherein the silicon layer defines an outer periphery of the semiconductor die, and the GaN layer is recessed from the outer periphery. The method according to claim 8, further comprising forming a plurality of dielectric layers on the GaN layer. The method of claim 8, wherein defining the plurality of trenches is performed at a front end of line (FEOL). The method of claim 8, wherein defining the plurality of trenches is performed at a mid-line-of-line (MOL). The method of claim 8, wherein defining the plurality of trenches is performed at a back end of line (BEOL). A semiconductor die comprising: a silicon layer defining an outer perimeter of the semiconductor die; and A gallium nitride (GaN) layer is disposed on the silicon layer and recessed from the outer periphery. The semiconductor die of claim 15, wherein the GaN layer comprises one or more gallium nitride layers having different compositions. The semiconductor die according to claim 15, further comprising a plurality of dielectric layers disposed on the GaN layer. The semiconductor die of claim 15, wherein the grooves in the GaN layer are formed at a front end of line (FEOL). The semiconductor die of claim 15, wherein the grooves in the GaN layer are formed at a mid-line-of-line (MOL). The semiconductor die of claim 15, wherein the grooves in the GaN layer are formed at a back end of line (BEOL).

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