儘管討論了具體的配置和布置,但應該理解,這樣做僅僅是為了說明的目的。因此,在不脫離本揭露內容的範圍的情況下,可以使用其他配置和布置。此外,本揭露內容還可以用於各種其他應用。如本揭露內容中描述的功能和結構特徵可以彼此並以未在圖式中具體示出的方式組合、調整和修改,使得這些組合、調整和修改在本揭露內容的範圍內。While specific configurations and arrangements are discussed, it should be understood that this is done for illustration purposes only. Accordingly, other configurations and arrangements may be used without departing from the scope of the present disclosure. In addition, the present disclosure can also be used in various other applications. Functional and structural features as described in this disclosure may be combined, adjusted and modified with each other and in ways not specifically shown in the drawings, such that such combinations, adjustments and modifications are within the scope of this disclosure.
通常,可以至少部分地從上下文中的用法理解術語。例如,如本文所用的術語“一個或多個”至少部分取決於上下文,可用於以單數意義描述任何特徵、結構或特性,或可用於以複數意義描述特徵、結構或特徵的組合。類似地,至少部分取決於上下文,諸如“一”、“一個”或“該”的術語同樣可以被理解為表達單數用法或表達複數用法。另外,術語“基於”可以被理解為不一定旨在傳達排他性的因素集合,而是可以允許存在不一定明確描述的其他因素,這同樣至少部分地取決於上下文。In general, a term can be understood, at least in part, from its usage in context. For example, the term "one or more" as used herein may be used to describe any feature, structure or characteristic in the singular sense or may be used to describe a feature, structure or combination of characteristics in the plural sense, depending at least in part on the context. Similarly, terms such as "a", "an" or "the" may equally be read to express singular usage or to express plural usage, depending at least in part on the context. Additionally, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, but may allow for the presence of other factors not necessarily explicitly described, again depending at least in part on context.
應當容易理解的是,本揭露內容中的“在……上”、“在……上方”和“在……之上”的含義應以最寬泛的方式來解釋,使得“在……上”不僅意味著“直接在某物上”,而且還包括其間具有中間特徵或層的“在某物上”的含義,並且“在……上方”或“在……之上”不僅意味著“在某物上方”或“在某物之上”的含義,而且還可以包括其間沒有中間特徵或層的“在某物上方”或“在某物之上”的含義(即,直接在某物上)。It should be readily understood that the meanings of "on", "above" and "over" in this disclosure are to be construed in the broadest manner such that "on" Not only means "directly on something" but also "on something" with an intermediate feature or layer in between, and "over" or "over" means not only "on over" or "over something" and can also include the meaning of "over" or "over something" without intervening features or layers (i.e., directly on something ).
此外,為了便於描述,可以在本文使用諸如“在……之下”、“在……下方”、“下”、“在……上方”、“上”等的空間相對術語來描述如圖所示的一個元件或特徵與另一個元件或特徵的關係。除了圖式中所示的方向之外,空間相對術語旨在涵蓋設備在使用或操作中的不同方向。該裝置可以以其他方式定向(旋轉90度或在其他方向),並且同樣可以相應地解釋本文使用的空間相關描述詞。In addition, for the convenience of description, spatially relative terms such as "under", "below", "below", "above", "on" and the like may be used herein to describe the The relationship of one element or feature to another element or feature is shown. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
如本文所使用的,術語“基底”是指在其上添加後續材料層的材料。基底本身可以被圖案化。添加在基底頂部的材料可以被圖案化或可以保持未圖案化。此外,基底可以包括多種半導體材料,例如矽,鍺、砷化鎵、磷化銦等。可替換地,基底可以由非導電材料製成,例如玻璃、塑料或藍寶石晶圓。As used herein, the term "substrate" refers to a material on which subsequent layers of material are added. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate may include various semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic or a sapphire wafer.
如本文所使用的,術語“層”是指包括具有厚度的區域的材料部分。層可以在整個下層或上層結構上延伸,或者可以具有小於下層或上層結構範圍的範圍。此外,層可以是厚度小於連續結構的厚度的均勻或不均勻連續結構的區域。例如,層可以位於連續結構的頂表面和底表面之間或在頂表面和底表面處的任何一對橫向平面之間。層可以橫向、垂直和/或沿著錐形表面延伸。基底可以是層,其中可以包括一層或多層,和/或可以在其上、上方和/或其下具有一層或多層。層可以包括多個層。例如,互連層可以包括一個或多個導體和觸點層(其中形成有互連線和/或垂直互連接入(過孔)觸點)以及一個或多個介電質層。As used herein, the term "layer" refers to a portion of material that includes regions having a thickness. A layer may extend across the entire underlying or superstructure, or may have an extent that is less than the extent of the underlying or superstructure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any pair of transverse planes at the top and bottom surfaces. Layers may extend laterally, vertically and/or along the tapered surface. A substrate can be a layer, can include one or more layers, and/or can have one or more layers thereon, above, and/or below. Layers may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers in which interconnect lines and/or vertical interconnect access (via) contacts are formed, and one or more dielectric layers.
與邏輯裝置(例如微處理器)相比,用於儲存裝置(例如NAND快閃記憶體)的外圍電路的互補金屬氧化物半導體(CMOS)技術節點不太先進(例如,60 nm及以上),因為記憶體外圍電路需要低成本和低洩漏電流(又稱為截止狀態電流I
off)。隨著3D儲存裝置(例如,3D NAND快閃記憶體裝置)的發展,更多堆疊的層(例如,字元線)需要更多的用於操作3D儲存裝置的外圍電路,進而要求外圍電路的單元大小更小。例如,頁緩衝器的數量和/或大小需要增加以與增加的儲存單元的數量相匹配。在一些情況下,由頁緩衝器占據的晶片面積在3D NAND快閃記憶體中可能變得占主導,例如,超過總晶片面積的50%。在另一示例中,字元線驅動器中的串驅動器的數量與3D NAND快閃記憶體中的字元線的數量成比例。因此,字元線的不斷增加還增加了字元線驅動器所占據的面積,以及金屬布線的複雜性,有時甚至增加了金屬層的數量。此外,在一些3D儲存裝置中,其中將儲存單元陣列和外圍電路製造在不同的基底上並鍵合在一起,外圍電路面積的不斷增加,尤其是頁緩衝器面積的不斷增加,使得其成為減小總晶片尺寸的瓶頸。
Complementary metal-oxide-semiconductor (CMOS) technology nodes for peripheral circuits of storage devices (such as NAND flash memory) are less advanced (for example, 60 nm and above) compared to logic devices (such as microprocessors), Because the memory peripheral circuit requires low cost and low leakage current (also called off-state current I off ). With the development of 3D storage devices (for example, 3D NAND flash memory devices), more stacked layers (for example, word lines) require more peripheral circuits for operating 3D storage devices, which in turn requires the The unit size is smaller. For example, the number and/or size of page buffers needs to be increased to match the increased number of storage units. In some cases, the die area occupied by the page buffer may become dominant in 3D NAND flash memory, for example, exceeding 50% of the total die area. In another example, the number of string drivers in the word line driver is proportional to the number of word lines in the 3D NAND flash memory. Therefore, the continuous increase of word lines also increases the area occupied by word line drivers, the complexity of metal wiring, and sometimes even increases the number of metal layers. In addition, in some 3D storage devices, in which the memory cell array and peripheral circuits are fabricated on different substrates and bonded together, the increasing area of peripheral circuits, especially the increasing area of page buffers, makes it a Bottleneck for small total wafer size.
然而,遵循用於邏輯裝置的先進技術節點趨勢而按比例縮小外圍電路尺寸將導致顯著的成本增加和較高的洩漏電流,這對於儲存裝置來說是不合需要的。此外,因為3D NAND快閃記憶體裝置在某些記憶體操作(例如,編程和擦除)中需要相對高的電壓(例如,高於5V),這與可以隨著CMOS技術節點的進步而降低其工作電壓的邏輯裝置不同,因此不能降低提供給記憶體外圍電路的電壓。因此,透過遵循發展CMOS技術節點的趨勢(如普通邏輯裝置)來按比例縮小記憶體外圍電路尺寸變得不可行。However, scaling down peripheral circuit dimensions following the advanced technology node trend for logic devices would result in significant cost increases and higher leakage currents, which are undesirable for memory devices. Furthermore, since 3D NAND flash memory devices require relatively high voltages (e.g., above 5V) for certain memory operations (e.g., programming and erasing), this can be reduced with advances in CMOS technology nodes. The operating voltage of the logic device is different, so the voltage supplied to the peripheral circuits of the memory cannot be reduced. Therefore, it becomes infeasible to scale down the memory peripheral circuit size by following the trend of developing CMOS technology nodes such as common logic devices.
另一方面,對於3D NAND快閃記憶體的更高I/O速度的需求日益增加,這需要在記憶體I/O電路中使用的電晶體的更高飽和汲極電流(I
dsat,也稱為導通狀態電流I
on)。然而,隨著飽和汲極電流持續增加,通常現有記憶體外圍電路(例如I/O電路)中使用的平面電晶體將遭受高洩漏電流,這對於儲存裝置也是不合需要的。
On the other hand, the increasing demand for higher I/O speeds of 3D NAND flash memory requires higher saturation drain current (I dsat , also called is the on-state current I on ). However, as the saturated drain current continues to increase, planar transistors typically used in existing memory peripheral circuits (eg, I/O circuits) suffer from high leakage current, which is also undesirable for memory devices.
總之,諸如3D NAND快閃記憶體的儲存裝置的持續進步同時要求記憶體外圍電路的高速、低洩漏電流、高電壓和小尺寸,而不增加成本,這已經變得越來越具有挑戰性。現有記憶體外圍電路中使用的全平面電晶體解決方案或邏輯裝置中使用的先進CMOS技術節點解決方案都不能同時滿足上述要求。In conclusion, the continuous advancement of storage devices such as 3D NAND flash memory simultaneously requires high speed, low leakage current, high voltage and small size of memory peripheral circuits without increasing cost, which has become more and more challenging. Neither full-planar transistor solutions used in existing memory peripheral circuits nor advanced CMOS technology node solutions used in logic devices can simultaneously meet the above requirements.
為了解決上述問題中的一個或多個,本揭露內容介紹了一種解決方案,其中至少在一些記憶體外圍電路中,諸如I/O電路、頁緩衝器和字元線驅動器,用3D電晶體(也稱為非平面電晶體)代替傳統的平面電晶體。在一些實施方式中,由於本文公開的3D電晶體的製造製程與平面電晶體兼容,因此平面電晶體和3D電晶體在相同的製程流程中製造以實現具有3D電晶體和平面電晶體兩者的記憶體外圍電路的混合配置。To address one or more of the above problems, the present disclosure introduces a solution in which 3D transistors ( Also known as non-planar transistors) instead of traditional planar transistors. In some embodiments, since the manufacturing process of the 3D transistors disclosed herein is compatible with the planar transistors, the planar transistors and the 3D transistors are fabricated in the same process flow to realize the 3D transistors and the planar transistors. Mixed configuration of memory peripheral circuits.
與平面電晶體相比,3D電晶體可以具有更大的閘極控制面積,以用更小的亞閾值擺幅實現更好的通道控制。在截止狀態期間,由於通道完全耗盡,所以可以很好地顯著減小3D電晶體的洩漏電流。因此,使用3D電晶體代替平面電晶體的記憶體外圍電路(例如,I/O電路)可實現好得多的速度(飽和汲極電流)/洩漏電流性能。例如,根據發明人所作的一些研究,具有相同的尺寸和相同的洩漏電流的情況下,3D電晶體的飽和汲極電流可以是平面電晶體的飽和汲極電流的兩倍以上(例如,3倍)。Compared with planar transistors, 3D transistors can have larger gate control areas to achieve better channel control with smaller subthreshold swings. During the off-state, since the channel is fully depleted, it is good to significantly reduce the leakage current of the 3D transistor. Therefore, memory peripheral circuits (eg, I/O circuits) using 3D transistors instead of planar transistors can achieve much better speed (saturation drain current)/leakage current performance. For example, according to some studies done by the inventors, with the same size and the same leakage current, the saturated drain current of a 3D transistor can be more than twice (for example, 3 times) that of a planar transistor. ).
除了由於高飽和汲極電流而使開關速度增加之外,透過用3D電晶體代替平面電晶體,也可以減小記憶體外圍電路尺寸。例如,根據發明人所做的一些研究,在相同尺寸和洩漏電流下,3D電晶體的飽和汲極電流可以是平面電晶體的飽和汲極電流的兩倍以上(例如,3倍)。因此,對於尺寸減小比速度增加更合乎需要的某些記憶體外圍電路,例如頁緩衝器和字元線驅動器,外圍電路的尺寸可以減小,同時保持相同的洩漏電流和飽和汲極電流。此外,根據發明人的一些研究,減小平面電晶體的電晶體尺寸的簡單解決方案是不可行的,因為洩漏電流由於窄通道效應而急劇增加,例如,當閘極寬度低於180 nm時。In addition to the increased switching speed due to the high saturation drain current, the peripheral circuit size of the memory can also be reduced by replacing the planar transistors with 3D transistors. For example, according to some studies done by the inventors, under the same size and leakage current, the saturation drain current of a 3D transistor can be more than twice (eg, 3 times) that of a planar transistor. Therefore, for certain memory peripheral circuits where size reduction is more desirable than speed increase, such as page buffers and word line drivers, the size of the peripheral circuits can be reduced while maintaining the same leakage current and saturation drain current. Furthermore, according to some studies by the inventors, a simple solution to reduce the transistor size of planar transistors is not feasible because the leakage current increases drastically due to the narrow channel effect, for example, when the gate width is below 180 nm.
另一方面,為了滿足記憶體外圍電路的低洩漏電流、高電壓和低成本要求,與邏輯裝置相比,可以使用不太先進的CMOS技術節點(例如,14 nm以上)來製造本文公開的3D電晶體。例如,雖然先進的CMOS技術節點(例如,小於22 nm)可以減小電晶體尺寸,但是必須降低電壓(例如,降低到0.9V)以避免增加洩漏電流。然而,對於在記憶體操作期間需要在某些電壓電平下操作的記憶體外圍電路來說,電壓降低是不可接受的。此外,先進CMOS技術節點以及相關聯的製程和結構,例如用於應變控制的應力源和高介電常數(高k)/金屬閘極(HKMG),可能增加製造複雜性並降低生産成品率,因此增加成本,這可能不適合於成本敏感的記憶體外圍電路。On the other hand, in order to meet the low leakage current, high voltage, and low cost requirements of memory peripheral circuits, the 3D devices disclosed herein can be fabricated using less advanced CMOS technology nodes (e.g., above 14 nm) compared to logic devices. Transistor. For example, while advanced CMOS technology nodes (eg, less than 22 nm) can reduce transistor size, the voltage must be reduced (eg, to 0.9V) to avoid increasing leakage current. However, voltage reduction is unacceptable for memory peripheral circuits that need to operate at certain voltage levels during memory operation. Additionally, advanced CMOS technology nodes and associated processes and structures, such as stressors and high-k (high-k)/metal gate (HKMG) for strain control, can increase manufacturing complexity and reduce production yields, Thus increasing cost, it may not be suitable for cost sensitive memory peripheral circuits.
與本揭露內容的範圍一致,根據本揭露內容的一些方面,具有3D電晶體的外圍電路和儲存單元陣列可形成在不同晶圓上且以面對面方式鍵合在一起。因此,製造儲存單元陣列的熱預算不會影響外圍電路的製造。對於外圍電路和儲存單元陣列在同一晶圓上製造的現有儲存裝置,電晶體尺寸的減小受到形成儲存單元陣列的熱預算的限制。相反,在本揭露內容中,可在不受儲存單元陣列熱預算限制的情況下減小形成記憶體外圍電路的電晶體(例如,3D電晶體)的尺寸。此外,在一些實施方式中,在鍵合之後,可以將具有減小的3D電晶體尺寸的某些外圍電路(例如,字元線驅動器的串驅動器)布置為面向形成在另一基底上的儲存單元陣列的階梯結構,從而簡化金屬布線。Consistent with the scope of the present disclosure, according to some aspects of the present disclosure, peripheral circuits with 3D transistors and memory cell arrays can be formed on different wafers and bonded together in a face-to-face manner. Therefore, the thermal budget of manufacturing the memory cell array will not affect the manufacturing of peripheral circuits. For existing memory devices in which the peripheral circuitry and the memory cell array are fabricated on the same wafer, the reduction in transistor size is limited by the thermal budget of forming the memory cell array. On the contrary, in the present disclosure, the size of the transistors (eg, 3D transistors) forming the peripheral circuits of the memory can be reduced without being limited by the thermal budget of the memory cell array. Furthermore, in some embodiments, after bonding, certain peripheral circuits with reduced 3D transistor size (eg, string drivers for word line drivers) can be arranged to face memory chips formed on another substrate. The ladder structure of the cell array simplifies metal wiring.
圖1A示出了根據本揭露內容的一些方面的3D儲存裝置100的截面的示意圖。3D儲存裝置100代表經鍵合的晶片的示例。3D儲存裝置100的部件(例如,儲存單元陣列及外圍電路)可單獨形成在不同基底上且隨後接合以形成經鍵合的晶片。3D儲存裝置100可以包括第一半導體結構102,其包括儲存單元的陣列(儲存單元陣列)。在一些實施方式中,儲存單元陣列包括NAND快閃記憶體單元陣列。為了便於描述,NAND快閃記憶體單元陣列可用作描述本揭露內容中的儲存單元陣列的示例。但是,應當理解,儲存單元陣列不限於NAND快閃記憶體單元陣列,且可包括任何其他合適類型的儲存單元陣列,例如動態隨機存取記憶體(DRAM)單元陣列、靜態隨機存取記憶體(SRAM)單元陣列、NOR快閃記憶體單元陣列、相變記憶體(PCM)單元陣列、電阻性儲存單元陣列、磁性儲存單元陣列、自旋轉移矩(STT)儲存單元陣列,僅舉幾個示例,或其任何組合。FIG. 1A shows a schematic diagram of a cross-section of a 3D storage device 100 according to some aspects of the present disclosure. 3D storage device 100 represents an example of a bonded wafer. Components of the 3D storage device 100 (eg, the memory cell array and peripheral circuits) may be formed separately on different substrates and then bonded to form a bonded wafer. The 3D storage device 100 may include a first semiconductor structure 102 including an array of memory cells (memory cell array). In some embodiments, the array of storage cells includes an array of NAND flash memory cells. For ease of description, a NAND flash memory cell array can be used as an example to describe the storage cell array in this disclosure. However, it should be understood that the array of storage cells is not limited to an array of NAND flash memory cells, and may include any other suitable type of storage cell array, such as a dynamic random access memory (DRAM) cell array, a static random access memory (SRAM) SRAM) cell array, NOR flash memory cell array, phase change memory (PCM) cell array, resistive memory cell array, magnetic memory cell array, spin transfer torque (STT) memory cell array, just to name a few , or any combination thereof.
第一半導體結構102可以是NAND快閃記憶體裝置,其中以3D NAND記憶體串的陣列和/或二維(2D)NAND儲存單元的陣列的形式提供儲存單元。可以將NAND儲存單元組織成頁或指狀物,所述頁或指狀物接著被組織成若干塊,其中每個NAND儲存單元電連接到被稱為位元線(BL)的單獨線。NAND儲存單元中具有相同垂直位置的所有單元可由字元線(WL)透過控制閘極電連接。在一些實施方式中,平面包含透過同一位元線電連接的某一數量的塊。第一半導體結構102可以包括一個或多個平面,而執行所有讀取/編程(寫入)/擦除操作所需的外圍電路可以包括在第二半導體結構104中。The first semiconductor structure 102 may be a NAND flash memory device in which the storage cells are provided in the form of an array of 3D NAND memory strings and/or an array of two-dimensional (2D) NAND storage cells. NAND storage cells can be organized into pages or fingers, which are then organized into blocks, with each NAND storage cell electrically connected to a separate line called a bit line (BL). All cells having the same vertical position in a NAND memory cell can be electrically connected by a word line (WL) through a control gate. In some implementations, a plane contains a certain number of blocks electrically connected by the same bit line. The first semiconductor structure 102 may include one or more planes, while peripheral circuits required to perform all read/program (write)/erase operations may be included in the second semiconductor structure 104 .
在一些實施方式中,NAND儲存單元陣列是2D NAND儲存單元陣列,其中的每一個包括浮閘電晶體。根據一些實施方式,2D NAND儲存單元陣列包括多個2D NAND記憶體串,其中的每一個包括串聯連接的多個儲存單元(例如,32到128個儲存單元)(類似於NAND門)和兩個選擇電晶體。根據一些實施方式,每個2D NAND記憶體串布置在基底上的同一平面中(在2D中)。在一些實施方式中,NAND儲存單元陣列是3D NAND記憶體串陣列,其中的每一個在基底上方垂直延伸穿過堆疊結構(例如,記憶體堆疊體)(在3D中)。取決於3D NAND技術(例如,記憶體堆疊體中的層/級的數量),3D NAND記憶體串通常包括32到256個NAND儲存單元,其中的每一個包括浮閘電晶體或電荷捕獲電晶體。In some embodiments, the array of NAND storage cells is an array of 2D NAND storage cells, each of which includes a floating gate transistor. According to some embodiments, a 2D NAND memory cell array includes a plurality of 2D NAND memory strings, each of which includes a plurality of memory cells (eg, 32 to 128 memory cells) connected in series (similar to NAND gates) and two Select Transistor. According to some embodiments, each 2D NAND memory string is arranged in the same plane (in 2D) on the substrate. In some embodiments, the array of NAND storage cells is a 3D array of NAND memory strings, each of which extends vertically (in 3D) through a stacked structure (eg, memory stack) above a substrate. Depending on the 3D NAND technology (e.g. the number of layers/levels in the memory stack), a 3D NAND memory string typically includes 32 to 256 NAND memory cells, each of which includes a floating gate transistor or a charge trapping transistor .
如圖1A所示,3D儲存裝置100還可以包括第二半導體結構104,其包括第一半導體結構102的儲存單元陣列的外圍電路。外圍電路(又稱控制和感測電路)可包括用於促進儲存單元陣列的操作的任何合適的數位、模擬和/或混合訊號電路。例如,外圍電路可以包括頁緩衝器、解碼器(例如,行解碼器和列解碼器)、讀出放大器、驅動器(例如,字元線驅動器)、I/O電路、電荷泵、電壓源或發生器、電流或電壓基準、上述功能電路的任何部分(例如,子電路)、或電路的任何主動或被動部件(例如,電晶體、二極體、電阻器或電容器)中的一個或多個。第二半導體結構104中的外圍電路使用CMOS技術,例如,其可以用邏輯製程來實現(例如,90 nm、65 nm、60 nm、45 nm、32 nm、28 nm等的技術節點)。如上文和下文詳細描述的,與本揭露內容的範圍一致,用於製造第二半導體結構104中的外圍電路的技術節點在22 nm以上,以便減少洩漏電流、維持某些電壓電平(例如,1.2V和以上)並降低成本。As shown in FIG. 1A , the 3D storage device 100 may further include a second semiconductor structure 104 including peripheral circuits of the storage cell array of the first semiconductor structure 102 . Peripheral circuitry (also known as control and sensing circuitry) may include any suitable digital, analog, and/or mixed-signal circuitry for facilitating operation of the memory cell array. For example, peripheral circuits may include page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers (e.g., word line drivers), I/O circuits, charge pumps, voltage sources, or generators one or more of a circuit breaker, a current or voltage reference, any part of a functional circuit described above (eg, a subcircuit), or any active or passive component of a circuit (eg, a transistor, diode, resistor, or capacitor). Peripheral circuits in the second semiconductor structure 104 use CMOS technology, for example, they can be implemented with logic process (eg, technology nodes of 90 nm, 65 nm, 60 nm, 45 nm, 32 nm, 28 nm, etc.). As described in detail above and below, consistent with the scope of the present disclosure, the technology nodes used to fabricate peripheral circuits in the second semiconductor structure 104 are above 22 nm in order to reduce leakage currents, maintain certain voltage levels (e.g., 1.2V and above) and reduce cost.
如圖1A所示,3D儲存裝置100進一步包括垂直地在第一半導體結構102與第二半導體結構104之間的鍵合界面106。如下文詳細描述的,第一半導體結構102和第二半導體結構104可以分開製造(並且在一些實施方式中並行製造),使得製造第一半導體結構102和第二半導體結構104之一的熱預算不限制製造第一半導體結構102和第二半導體結構104中的另一個的製程。此外,可以透過鍵合界面106形成大量互連(例如,鍵合觸點),以在第一半導體結構102和第二半導體結構104之間進行直接的短距離(例如,微米級)電連接,而不是在諸如印刷電路板(PCB)的電路板上的長距離(例如,毫米或厘米級)晶片到晶片數據總線,從而消除晶片介面延遲並以降低的功耗實現高速I/O吞吐量。第一半導體結構102中的儲存單元陣列與第二半導體結構104中的外圍電路之間的數據傳送可透過跨越鍵合界面106的互連(例如,鍵合觸點)來執行。透過垂直集成第一半導體結構102和第二半導體結構104,可以減小晶片尺寸,並可以增加儲存單元密度。As shown in FIG. 1A , the 3D storage device 100 further includes a bonding interface 106 vertically between the first semiconductor structure 102 and the second semiconductor structure 104 . As described in detail below, the first semiconductor structure 102 and the second semiconductor structure 104 may be fabricated separately (and in some embodiments in parallel) such that the thermal budget for fabricating one of the first semiconductor structure 102 and the second semiconductor structure 104 is not the same. A process for fabricating the other of the first semiconductor structure 102 and the second semiconductor structure 104 is limited. In addition, a large number of interconnections (eg, bonding contacts) can be formed through the bonding interface 106 to make direct short-distance (eg, micron-scale) electrical connections between the first semiconductor structure 102 and the second semiconductor structure 104, Rather than a long-distance (eg, millimeter or centimeter scale) die-to-die data bus on a circuit board such as a printed circuit board (PCB), thereby eliminating die interface delays and enabling high-speed I/O throughput with reduced power consumption. Data transfer between the memory cell array in the first semiconductor structure 102 and peripheral circuits in the second semiconductor structure 104 may be performed through interconnections (eg, bonding contacts) across the bonding interface 106 . By vertically integrating the first semiconductor structure 102 and the second semiconductor structure 104, the chip size can be reduced and the memory cell density can be increased.
應當理解,堆疊的第一半導體結構102和第二半導體結構104的相對位置不受限制。圖1B示出了根據一些實施方式的另一示例性3D儲存裝置101的截面的示意圖。與圖1A中的3D儲存裝置100不同,其中包括外圍電路的第二半導體結構104在包括儲存單元陣列的第一半導體結構102上方,在圖1B中的3D儲存裝置101中,包括儲存單元陣列的第一半導體結構102在包括外圍電路的第二半導體結構104上方。然而,根據一些實施方式,鍵合界面106垂直地形成在3D儲存裝置101中的第一半導體結構102和第二半導體結構104之間,並且第一半導體結構102和第二半導體結構104透過鍵合(例如,混合鍵合)垂直地接合。混合鍵合,也稱為“金屬/介電質混合鍵合”,是一種直接鍵合技術(例如,在不使用中間層(例如焊料或黏合劑)的情況下在表面之間形成鍵合),並且可以同時獲得金屬-金屬(例如,Cu-至-Cu)鍵合和介電質-介電質(例如,SiO2-至-SiO2)鍵合。第一半導體結構102中的儲存單元陣列與第二半導體結構104中的外圍電路之間的數據傳送可透過跨越鍵合界面106的互連(例如,鍵合觸點)來執行。It should be understood that the relative positions of the stacked first semiconductor structure 102 and the second semiconductor structure 104 are not limited. FIG. 1B shows a schematic diagram of a cross-section of another exemplary 3D storage device 101 according to some embodiments. Unlike the 3D storage device 100 in FIG. 1A, in which the second semiconductor structure 104 including peripheral circuits is above the first semiconductor structure 102 including the storage cell array, in the 3D storage device 101 in FIG. 1B, the The first semiconductor structure 102 is over the second semiconductor structure 104 including peripheral circuitry. However, according to some embodiments, the bonding interface 106 is vertically formed between the first semiconductor structure 102 and the second semiconductor structure 104 in the 3D storage device 101, and the first semiconductor structure 102 and the second semiconductor structure 104 pass through the bonding (eg, hybrid bonding) to join vertically. Hybrid bonding, also known as "metal/dielectric hybrid bonding", is a direct bonding technique (i.e., forming a bond between surfaces without the use of an intermediate layer such as solder or adhesive) , and metal-metal (eg, Cu-to-Cu) bonding and dielectric-dielectric (eg, SiO2-to-SiO2) bonding can be obtained simultaneously. Data transfer between the memory cell array in the first semiconductor structure 102 and peripheral circuits in the second semiconductor structure 104 may be performed through interconnections (eg, bonding contacts) across the bonding interface 106 .
圖2示出了根據本揭露內容的一些方面的包括外圍電路的儲存裝置200的示意性電路圖。儲存裝置200可包括儲存單元陣列201和耦接到儲存單元陣列201的外圍電路202。3D儲存裝置100和101可以是其中儲存單元陣列201和外圍電路202可分別包括在第一半導體結構102和第二半導體結構104中的儲存裝置200的示例。儲存單元陣列201可以是NAND快閃記憶體單元陣列,其中儲存單元206以3D NAND記憶體串208的陣列的形式提供,每一個3D NAND記憶體串在基底(未示出)上方垂直延伸。在一些實施方式中,每個3D NAND記憶體串208包括串聯耦接且垂直堆疊的多個儲存單元206。每個儲存單元206可保持連續模擬值,例如電壓或電荷,這取決於在儲存單元206的區域內捕獲的電子的數量。每個儲存單元206可以是包括浮閘電晶體的浮閘類型的儲存單元,或者是包括電荷捕獲電晶體的電荷捕獲類型的儲存單元。FIG. 2 shows a schematic circuit diagram of a storage device 200 including peripheral circuits according to some aspects of the present disclosure. The storage device 200 may include a storage cell array 201 and a peripheral circuit 202 coupled to the storage cell array 201. The 3D storage devices 100 and 101 may be wherein the storage cell array 201 and the peripheral circuit 202 may be included in the first semiconductor structure 102 and the second semiconductor structure 102, respectively. An example of the storage device 200 in the semiconductor structure 104. The storage cell array 201 may be an array of NAND flash memory cells, where the storage cells 206 are provided in the form of an array of 3D NAND memory strings 208, each 3D NAND memory string extending vertically above a substrate (not shown). In some implementations, each 3D NAND memory string 208 includes a plurality of storage cells 206 coupled in series and stacked vertically. Each storage cell 206 may hold a continuous analog value, such as a voltage or charge, depending on the number of electrons trapped within the area of the storage cell 206 . Each storage cell 206 may be a floating gate type storage cell including a floating gate transistor, or a charge trap type storage cell including a charge trap transistor.
在一些實施方式中,每個儲存單元206是具有兩個可能記憶體狀態且因此可儲存一位元數據的單電平單元(SLC)。例如,第一記憶體狀態“0”可對應於第一電壓範圍,而第二記憶體狀態“1”可對應於第二電壓範圍。在一些實施方式中,每個儲存單元206是能夠以四個或更多個記憶體狀態儲存多於單個資料位元的多電平單元(MLC)。例如,MLC可以每單元儲存兩位元、每單元儲存三位元(也稱為三電平單元(TLC))、或每單元儲存四位元(也稱為四電平單元(QLC))。每個MLC可被編程為採用可能的標稱儲存值的範圍。在一個示例中,如果每個MLC儲存兩位元數據,則可以透過將三個可能的標稱儲存值中的一個寫入單元來編程MLC以採取從擦除狀態起的三個可能的編程電平中的一個。第四標稱儲存值可用於擦除狀態。In some implementations, each storage cell 206 is a single level cell (SLC) that has two possible memory states and can therefore store one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some embodiments, each storage cell 206 is a multi-level cell (MLC) capable of storing more than a single bit of data in four or more memory states. For example, MLCs can store two bits per cell, three bits per cell (also called tri-level cell (TLC)), or four bits per cell (also called quad-level cell (QLC)). Each MLC can be programmed to use a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLCs can be programmed to assume three possible programming levels from the erased state by writing one of three possible nominal storage values into the cell. One of the flat. A fourth nominal stored value is available for the erased state.
如圖2中所示,每個NAND記憶體串208可包括在其源極端處的源極選擇閘極(SSG)210和在其汲極端處的汲極選擇閘極(DSG)212。SSG電晶體210和DSG電晶體212可被配置為在讀取和編程操作期間啓動所選NAND記憶體串208(陣列的列)。在一些實施方式中,同一塊204中的3D NAND記憶體串208的SSG電晶體210的源極透過同一源極線(SL)214(例如,公共SL)耦接到地。根據一些實施方式,每個3D NAND記憶體串208的DSG電晶體212耦接到相應位元線216,可經由輸出總線(未示出)從所述位元線讀取或編程數據。在一些實施方式中,每個3D NAND記憶體串208被配置為透過經由一條或多條DSG線213將選擇電壓(例如,高於DSG電晶體212的閾值電壓)或不選擇電壓(例如,0V)施加到相應DSG電晶體212和/或透過經由一條或多條SSG線215將選擇電壓(例如,高於SSG電晶體210的閾值電壓)或不選擇電壓(例如,0V)施加到相應SSG電晶體210,而被選擇或不被選擇。As shown in FIG. 2 , each NAND memory string 208 may include a source select gate (SSG) 210 at its source terminal and a drain select gate (DSG) 212 at its drain terminal. SSG transistors 210 and DSG transistors 212 may be configured to enable selected NAND memory strings 208 (columns of the array) during read and program operations. In some embodiments, the sources of the SSG transistors 210 of the 3D NAND memory strings 208 in the same block 204 are coupled to ground through the same source line (SL) 214 (eg, common SL). According to some embodiments, the DSG transistor 212 of each 3D NAND memory string 208 is coupled to a corresponding bit line 216 from which data can be read or programmed via an output bus (not shown). In some implementations, each 3D NAND memory string 208 is configured to pass a selection voltage (eg, higher than the threshold voltage of the DSG transistor 212 ) or a non-selection voltage (eg, 0 V ) to the corresponding DSG transistor 212 and/or by applying a select voltage (for example, above the threshold voltage of the SSG transistor 210 ) or a deselect voltage (for example, 0V) to the corresponding SSG transistor via one or more SSG lines 215 Crystal 210 is selected or not selected.
如圖2中所示,3D NAND記憶體串208可被組織成多個塊204,其中的每個塊可具有公共源極線214。在一些實施方式中,每個塊204是用於擦除操作的基本數據單位,即,同時擦除同一塊204上的所有儲存單元206。儲存單元206可透過字元線218耦接,所述字元線選擇儲存單元206的哪一行受讀取和編程操作影響。在一些實施方式中,每條字元線218耦接到儲存單元206的行220,其是用於編程和讀取操作的基本數據單位。每條字元線218可包括在相應行220中的每個儲存單元206處的多個控制閘極(閘電極)和耦接控制閘極的閘極線As shown in FIG. 2 , 3D NAND memory string 208 may be organized into multiple blocks 204 , each of which may have a common source line 214 . In some implementations, each block 204 is the basic unit of data for an erase operation, ie, all storage units 206 on the same block 204 are erased simultaneously. The storage cells 206 may be coupled by a word line 218 that selects which row of storage cells 206 is affected by read and program operations. In some implementations, each word line 218 is coupled to a row 220 of storage cells 206 , which is the basic unit of data used for programming and reading operations. Each word line 218 may include a plurality of control gates (gate electrodes) at each memory cell 206 in a corresponding row 220 and a gate line coupled to the control gates.
。.
外圍電路202可透過位元線216、字元線218、源極線214、SSG線215和DSG線213耦接到儲存單元陣列201。如上所述,外圍電路202可包括任何合適的電路,用於透過經由字元線218、源極線214、SSG線215和DSG線213施加和感測經由位元線216往返於每個目標儲存單元206的電壓訊號和/或電流訊號來促進儲存單元陣列201的操作。外圍電路202可包括使用MOS技術形成的各種類型的外圍電路。例如,圖3示出了一些示例性外圍電路202,包括頁緩衝器304、列解碼器/位元線驅動器306、行解碼器/字元線驅動器308、電壓發生器310、控制邏輯312、暫存器314、介面(I/F)316和數據總線318。應當理解,在一些示例中,也可包括額外外圍電路202。The peripheral circuit 202 can be coupled to the memory cell array 201 through the bit line 216 , the word line 218 , the source line 214 , the SSG line 215 and the DSG line 213 . As noted above, peripheral circuitry 202 may include any suitable circuitry for applying and sensing via bit lines 216 to and from each target storage line via word lines 218 , source lines 214 , SSG lines 215 , and DSG lines 213 . The voltage signal and/or current signal of the cell 206 is used to facilitate the operation of the memory cell array 201 . The peripheral circuit 202 may include various types of peripheral circuits formed using MOS technology. For example, FIG. 3 shows some exemplary peripheral circuits 202, including page buffer 304, column decoder/bitline driver 306, row decoder/wordline driver 308, voltage generator 310, control logic 312, temporary memory 314, interface (I/F) 316 and data bus 318. It should be understood that in some examples, additional peripheral circuitry 202 may also be included.
頁緩衝器304可被配置為根據控制邏輯312的控制訊號來緩衝從儲存單元陣列201讀取或編程到其的數據。在一個示例中,頁緩衝器304可以儲存一頁編程數據(寫入數據),以編程到儲存單元陣列201的一行220中。在另一示例中,頁緩衝器304還執行編程驗證操作以確保數據已經被正確編程到耦接到所選字元線218的儲存單元206中。The page buffer 304 may be configured to buffer data read from or programmed into the memory cell array 201 according to a control signal of the control logic 312 . In one example, the page buffer 304 may store a page of program data (write data) for programming into a row 220 of the memory cell array 201 . In another example, the page buffer 304 also performs a program verify operation to ensure that data has been correctly programmed into the storage cells 206 coupled to the selected word line 218 .
行解碼器/字元線驅動器308可以被配置為由控制邏輯312控制,並且選擇或不選擇儲存單元陣列201的塊204,以及選擇或不選擇所選塊204的字元線218。行解碼器/字元線驅動器308可以進一步被配置為驅動儲存單元陣列201。例如,行解碼器/字元線驅動器308可以使用從電壓發生器310生成的字元線電壓來驅動耦接到所選字元線218的儲存單元206。在一些實施方式中,行解碼器/字元線驅動器308可包括耦接到局部字元線和字元線218的解碼器和串驅動器(驅動電晶體)。Row decoder/wordline driver 308 may be configured to be controlled by control logic 312 and select or deselect a block 204 of memory cell array 201 and select or deselect wordline 218 of a selected block 204 . The row decoder/word line driver 308 may be further configured to drive the memory cell array 201 . For example, the row decoder/wordline driver 308 may use the wordline voltage generated from the voltage generator 310 to drive the storage cell 206 coupled to the selected wordline 218 . In some implementations, row decoder/wordline driver 308 may include decoders and string drivers (drive transistors) coupled to local wordlines and wordlines 218 .
電壓發生器310可被配置為由控制邏輯312控制且生成待提供到儲存單元陣列201的字元線電壓(例如,讀取電壓、編程電壓、通過電壓、局部電壓和檢驗電壓)。在一些實施方式中,電壓發生器310是電壓源的一部分,所述電壓源提供不同外圍電路202的各種電平的電壓,如下文詳細描述。與本揭露內容的範圍一致,在一些實施方式中,由電壓發生器310提供到(例如)行解碼器/字元線驅動器308和頁緩衝器304的電壓高於足以執行記憶體操作的某些電平。例如,提供到頁緩衝器304的電壓可在2V與3.3V之間,例如3.3V,且提供到行解碼器/字元線驅動器308的電壓可大於3.3V,例如在3.3V與30V之間。The voltage generator 310 may be configured to be controlled by the control logic 312 and generate word line voltages (eg, read voltages, program voltages, pass voltages, local voltages, and verify voltages) to be provided to the memory cell array 201 . In some implementations, the voltage generator 310 is part of a voltage source that provides various levels of voltage to the various peripheral circuits 202, as described in detail below. Consistent with the scope of the present disclosure, in some embodiments, the voltage provided by voltage generator 310 to, for example, row decoder/word line driver 308 and page buffer 304 is higher than certain voltages sufficient to perform memory operations. level. For example, the voltage provided to the page buffer 304 may be between 2V and 3.3V, such as 3.3V, and the voltage provided to the row decoder/wordline driver 308 may be greater than 3.3V, such as between 3.3V and 30V .
列解碼器/位元線驅動器306可被配置為由控制邏輯312控制且透過施加從電壓發生器310生成的位元線電壓來選擇一個或多個3D NAND記憶體串208。例如,列解碼器/位元線驅動器306可施加列訊號,以用於從頁緩衝器304選擇將在讀取操作中輸出的N個資料位元集合。Column decoder/bit line driver 306 may be configured to be controlled by control logic 312 and to select one or more 3D NAND memory strings 208 by applying bit line voltages generated from voltage generator 310 . For example, column decoder/bit line driver 306 may apply a column signal for selecting a set of N data bits from page buffer 304 to be output in a read operation.
控制邏輯312可以耦接到每個外圍電路202,並且被配置為控制外圍電路202的操作。暫存器314可以耦接到控制邏輯312,並且包括用於儲存狀態信息、命令操作碼(OP碼)和用於控制每個外圍電路202的操作的命令地址的狀態暫存器、命令暫存器和地址暫存器。Control logic 312 may be coupled to each peripheral circuit 202 and configured to control the operation of peripheral circuit 202 . Registers 314 may be coupled to control logic 312 and include status registers, command registers, and command addresses for storing state information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit 202. register and address register.
介面316可耦接到控制邏輯312且被配置為將儲存單元陣列201與記憶體控制器(未示出)介面連接。在一些實施方式中,介面316充當控制緩衝器,以將從記憶體控制器和/或主機(未示出)接收的控制命令緩衝並中繼到控制邏輯312,並將從控制邏輯312接收的狀態訊息緩衝並中繼到記憶體控制器和/或主機。介面316還可經由數據總線318耦接到頁緩衝器304和列解碼器/位元線驅動器306,且充當I/O介面和數據緩衝器以將從記憶體控制器和/或主機接收的編程數據緩衝並中繼到頁緩衝器304,且將來自頁緩衝器304的讀取數據緩衝並中繼到記憶體控制器和/或主機。在一些實施方式中,介面316和數據總線318是外圍電路202的I/O電路的一部分。Interface 316 may be coupled to control logic 312 and configured to interface memory cell array 201 with a memory controller (not shown). In some implementations, interface 316 acts as a control buffer to buffer and relay control commands received from memory controller and/or host (not shown) to control logic 312 and to Status messages are buffered and relayed to the memory controller and/or host. Interface 316 is also coupled to page buffer 304 and column decoder/bit line driver 306 via data bus 318, and acts as an I/O interface and data buffer for programming received from the memory controller and/or host Data is buffered and relayed to the page buffer 304, and read data from the page buffer 304 is buffered and relayed to the memory controller and/or host. In some implementations, interface 316 and data bus 318 are part of the I/O circuitry of peripheral circuitry 202 .
與本揭露內容的範圍一致,儲存裝置200的至少一個外圍電路202可具有3D電晶體而非平面電晶體,以便同時實現高速、低洩漏電流、高電壓及小尺寸,而不增加成本。在一些實施方式中,用3D電晶體替換每個外圍電路202中的所有平面電晶體。即,外圍電路202可以根本不具有平面電晶體。在一些實施方式中,由於本文公開的3D電晶體的製造製程與平面電晶體兼容,因此平面電晶體和3D電晶體在相同的製程流程中製造以實現具有3D電晶體和平面電晶體兩者的記憶體外圍電路的混合配置。即,外圍電路202也可具有平面電晶體。例如,一個或多個外圍電路202可以具有3D電晶體,而其他外圍電路202仍然可以具有平面電晶體。應當理解,在一些示例中,3D電晶體和平面電晶體兩者可用於同一外圍電路202中。例如,圖4示出了根據本揭露內容的一些方面的平面電晶體的透視圖,圖5示出了根據本揭露內容的一些方面的3D電晶體的透視圖。Consistent with the scope of the present disclosure, at least one peripheral circuit 202 of the storage device 200 may have 3D transistors instead of planar transistors in order to simultaneously achieve high speed, low leakage current, high voltage, and small size without increasing cost. In some implementations, all planar transistors in each peripheral circuit 202 are replaced with 3D transistors. That is, the peripheral circuit 202 may not have planar transistors at all. In some embodiments, since the manufacturing process of the 3D transistors disclosed herein is compatible with the planar transistors, the planar transistors and the 3D transistors are fabricated in the same process flow to realize the 3D transistors and the planar transistors. Mixed configuration of memory peripheral circuits. That is, the peripheral circuit 202 may also have planar transistors. For example, one or more peripheral circuits 202 may have 3D transistors, while other peripheral circuits 202 may still have planar transistors. It should be understood that in some examples, both 3D transistors and planar transistors may be used in the same peripheral circuit 202 . For example, FIG. 4 shows a perspective view of a planar transistor according to some aspects of the present disclosure, and FIG. 5 shows a perspective view of a 3D transistor according to some aspects of the present disclosure.
如圖4所示,平面電晶體400可以是基底402上的MOS場效應電晶體(MOSFET),其可以包括矽(例如,單晶矽、c-Si)、矽鍺(SiGe)、砷化鎵(GaAs)、鍺(Ge)、絕緣體上矽(SOI)或任何其他合適的材料。注意,在圖4中添加了x軸和y軸,以進一步示出半導體器件(例如,平面電晶體400)的部件的空間關係。基底402包括在x方向(橫向方向或寬度方向)上橫向延伸的兩個橫向表面(例如,頂表面和底表面)。如本文所使用的,當基底(例如,基底402)在y方向上位於半導體器件(例如,平面電晶體400)的最低平面中時,在y方向(垂直方向或厚度方向)上相對於半導體器件的基底確定半導體器件的一個部件(例如,層或器件)是在另一個部件(例如,層或器件)“上”、“上方”還是“下方”(例如,層或器件)。在本揭露內容中應用了用於描述空間關係的相同概念。As shown in FIG. 4, the planar transistor 400 may be a MOS field effect transistor (MOSFET) on a substrate 402, which may include silicon (eg, single crystal silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. Note that the x-axis and y-axis have been added in FIG. 4 to further illustrate the spatial relationship of the components of the semiconductor device (eg, planar transistor 400 ). The base 402 includes two lateral surfaces (eg, top and bottom surfaces) extending laterally in the x-direction (lateral direction or width direction). As used herein, when a substrate (eg, substrate 402 ) is in the lowest plane of a semiconductor device (eg, planar transistor 400 ) in the y-direction, relative to the semiconductor device in the y-direction (vertical or thickness direction) The substrate determines whether one component (eg, layer or device) of a semiconductor device is "on," "over," or "below" (eg, layer or device) another component (eg, layer or device). The same concepts used to describe spatial relationships are applied in this disclosure.
可以在基底402中以及相鄰的平面電晶體400之間形成溝槽隔離404,例如淺溝槽隔離(STI),以減小電流洩漏。溝槽隔離404可以包括任何合適的介電材料,諸如氧化矽、氮化矽、氮氧化矽或高k介電質(例如,氧化鋁、氧化鉿、氧化鋯等)。在一些實施方式中,高k介電質材料包括具有高於氮化矽的介電常數或k值的介電常數或k值(k > 7)的任何介電質。在一些實施方式中,溝槽隔離404包括氧化矽。Trench isolation 404 , such as shallow trench isolation (STI), may be formed in the substrate 402 and between adjacent planar transistors 400 to reduce current leakage. Trench isolation 404 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric (eg, aluminum oxide, hafnium oxide, zirconium oxide, etc.). In some embodiments, a high-k dielectric material includes any dielectric having a dielectric constant or k value higher than that of silicon nitride (k > 7). In some embodiments, trench isolation 404 includes silicon oxide.
如圖4所示,平面電晶體400還可以包括基底402上的閘極結構408。在一些實施方式中,閘極結構408在基底402的頂表面上。雖然未示出,但是閘極結構408可以包括在基底402上,即在基底402的頂表面上方並與其接觸的閘極介電質。閘極結構408也可以包括在閘極介電質上的閘電極,即在閘極介電質上方並與其接觸。閘極介電質可以包括任何合適的介電質材料,諸如氧化矽、氮化矽、氮氧化矽或高k介電質。在一些實施方式中,閘極介電質包括氧化矽,即,閘極氧化物。閘電極可以包括任何合適的導電材料,例如多晶矽、金屬(例如,鎢(W)、銅(Cu)、鋁(Al)等)、金屬化合物(例如,氮化鈦(TiN)、氮化鉭(TaN)等)或矽化物。在一些實施方式中,閘電極包括摻雜多晶矽,即,閘極多晶矽。As shown in FIG. 4 , the planar transistor 400 may further include a gate structure 408 on the substrate 402 . In some embodiments, the gate structure 408 is on the top surface of the substrate 402 . Although not shown, gate structure 408 may include a gate dielectric on substrate 402 , ie, above and in contact with a top surface of substrate 402 . The gate structure 408 may also include a gate electrode on the gate dielectric, ie above and in contact with the gate dielectric. The gate dielectric may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the gate dielectric includes silicon oxide, ie, gate oxide. The gate electrode may comprise any suitable conductive material, such as polysilicon, metals (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), metal compounds (e.g., titanium nitride (TiN), tantalum nitride ( TaN) etc.) or silicide. In some embodiments, the gate electrode comprises doped polysilicon, ie, gate polysilicon.
如圖4所示,平面電晶體400還可以包括在基底402中的一對源極和汲極406。源極和汲極406可以摻雜有任何合適的P型摻雜劑,例如硼(B)或鎵(Ga),或者任何合適的N型摻雜劑,例如磷(P)或砷(As)。在平面圖中,源極和汲極406可以由閘極結構408隔開。即,根據一些實施方式,在平面圖中,閘極結構408形成在源極與汲極406之間。當施加到閘極結構408的閘電極的閘極電壓高於平面電晶體400的閾值電壓時,可以在閘極結構408下方的源極和汲極406之間橫向地形成基底402中的平面電晶體400的通道410。如圖4所示,閘極結構408可以在其中可以形成通道410的部分基底402(主動區)的頂表面上方並與其接觸。即,根據一些實施方式,閘極結構408僅與主動區的一側接觸,即,在基底402的頂表面的平面中接觸。閘極結構408還包括在閘電極和通道410之間的閘極介電質(例如,閘極氧化物,圖4中未示出)。應當理解,儘管圖4中未示出,但是平面電晶體400可以包括附加的部件,例如阱和間隔物。As shown in FIG. 4 , planar transistor 400 may also include a pair of source and drain 406 in substrate 402 . The source and drain 406 may be doped with any suitable P-type dopant, such as boron (B) or gallium (Ga), or any suitable N-type dopant, such as phosphorus (P) or arsenic (As) . In plan view, the source and drain 406 may be separated by a gate structure 408 . That is, according to some embodiments, gate structure 408 is formed between source and drain 406 in plan view. When the gate voltage applied to the gate electrode of gate structure 408 is higher than the threshold voltage of planar transistor 400, a planar transistor in substrate 402 may be formed laterally between source and drain 406 below gate structure 408. Channel 410 of crystal 400 . As shown in FIG. 4 , gate structure 408 may be over and in contact with the top surface of the portion of substrate 402 (active region) in which channel 410 may be formed. That is, according to some embodiments, the gate structure 408 is in contact with only one side of the active region, ie in the plane of the top surface of the substrate 402 . Gate structure 408 also includes a gate dielectric (eg, gate oxide, not shown in FIG. 4 ) between the gate electrode and channel 410 . It should be understood that, although not shown in FIG. 4 , planar transistor 400 may include additional components, such as wells and spacers.
如圖5所示,3D電晶體500可以是基底502上的MOSFET,其可以包括矽(例如,單晶矽、c-Si)、SiGe、GaAs、Ge、絕緣體上矽SOI或任何其他合適的材料。在一些實施方式中,基底502包括單晶矽。可以在基底502中以及在相鄰3D電晶體500之間形成諸如STI的溝槽隔離504以減少電流洩漏。溝槽隔離504可以包括任何合適的介電質材料,諸如氧化矽、氮化矽、氮氧化矽或高k介電質(例如,氧化鋁、氧化鉿、氧化鋯等)。在一些實施方式中,高k介電質材料包括具有高於氮化矽的介電常數或k值的介電常數或k值(k > 7)的任何介電質。在一些實施方式中,溝槽隔離404包括氧化矽。As shown in FIG. 5, the 3D transistor 500 can be a MOSFET on a substrate 502, which can include silicon (eg, single crystal silicon, c-Si), SiGe, GaAs, Ge, silicon-on-insulator SOI, or any other suitable material . In some embodiments, substrate 502 includes single crystal silicon. Trench isolation 504 such as an STI may be formed in the substrate 502 and between adjacent 3D transistors 500 to reduce current leakage. Trench isolation 504 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectrics (eg, aluminum oxide, hafnium oxide, zirconium oxide, etc.). In some embodiments, a high-k dielectric material includes any dielectric having a dielectric constant or k value higher than that of silicon nitride (k > 7). In some embodiments, trench isolation 404 includes silicon oxide.
如圖5所示,與平面電晶體400不同,3D電晶體500還可以包括在基底502上方的3D半導體主體505。即,在一些實施方式中,3D半導體主體505至少部分地在基底502的頂表面上方延伸,以不僅暴露3D半導體主體505的頂表面,還暴露兩個側表面。如圖5所示,例如,3D半導體主體505可以是3D結構,其也被稱為“鰭狀物”,以暴露其三個側面。如下面關於3D電晶體500的製造製程所描述的,根據一些實施方式,3D半導體主體505由基底502形成,並且因此具有與基底502相同的半導體材料。在一些實施方式中,3D半導體主體505包括單晶矽。由於通道可以形成在3D半導體主體505中,因此與基底502相對的3D半導體主體505(例如,鰭狀物)可以被視為3D電晶體500的主動區。As shown in FIG. 5 , unlike the planar transistor 400 , the 3D transistor 500 may further include a 3D semiconductor body 505 above a substrate 502 . That is, in some embodiments, the 3D semiconductor body 505 extends at least partially over the top surface of the substrate 502 to expose not only the top surface of the 3D semiconductor body 505 but also two side surfaces. As shown in FIG. 5 , for example, the 3D semiconductor body 505 may be a 3D structure, also referred to as a "fin", to expose three sides thereof. As described below with respect to the manufacturing process of the 3D transistor 500 , according to some embodiments, the 3D semiconductor body 505 is formed from the substrate 502 and thus has the same semiconductor material as the substrate 502 . In some embodiments, the 3D semiconductor body 505 includes monocrystalline silicon. Since channels may be formed in the 3D semiconductor body 505 , the 3D semiconductor body 505 (eg, fins) opposite the base 502 may be considered as the active region of the 3D transistor 500 .
圖6A示出了根據本揭露內容的一些方面的圖5中的3D電晶體500在平面A-A中的截面的側視圖。圖6B示出了根據本揭露內容的一些方面的圖5中的3D電晶體500在平面B-B中的截面的側視圖。如圖5和6B所示,3D電晶體500還可以包括在基底502上的閘極結構508。與閘極結構408僅與主動區的一側接觸,即在基底402的頂表面的平面中接觸的平面電晶體400不同,3D電晶體500的閘極結構508可以與主動區的多個側面接觸,即在3D半導體主體505的頂表面和側表面的多個平面中接觸。即,3D電晶體500的主動區,即3D半導體主體505,可以至少部分地被閘極結構508包圍。6A illustrates a side view of a cross-section of 3D transistor 500 in FIG. 5 in plane A-A, according to some aspects of the present disclosure. 6B illustrates a side view of a cross-section of 3D transistor 500 in FIG. 5 in plane B-B, according to some aspects of the present disclosure. As shown in FIGS. 5 and 6B , the 3D transistor 500 may further include a gate structure 508 on the substrate 502 . Unlike the planar transistor 400 where the gate structure 408 is in contact with only one side of the active region, i.e. in the plane of the top surface of the substrate 402, the gate structure 508 of the 3D transistor 500 can be in contact with multiple sides of the active region , ie contacts in multiple planes of the top and side surfaces of the 3D semiconductor body 505 . That is, the active region of the 3D transistor 500 , ie the 3D semiconductor body 505 , may be at least partially surrounded by the gate structure 508 .
閘極結構508可以包括在3D半導體主體505之上的閘極介電質602,例如,與3D半導體主體505的頂表面和兩個側表面接觸。閘極結構508還可以包括在閘極介電質602之上並與其接觸的閘電極604。閘極介電質602可以包括任何合適的介電質材料,例如氧化矽、氮化矽、氮氧化矽或高k介電質。在一些實施方式中,閘極介電質602包括氧化矽,即,閘極氧化物。閘電極604可以包括任何合適的導電材料,例如多晶矽、金屬(例如W、Cu、Al等)、金屬化合物(例如TiN、TaN等)或矽化物。在一些實施方式中,閘電極604包括摻雜多晶矽,即,閘極多晶矽。The gate structure 508 may comprise a gate dielectric 602 over the 3D semiconductor body 505 , eg in contact with the top surface and both side surfaces of the 3D semiconductor body 505 . The gate structure 508 may also include a gate electrode 604 over and in contact with the gate dielectric 602 . The gate dielectric 602 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the gate dielectric 602 includes silicon oxide, ie, gate oxide. The gate electrode 604 may comprise any suitable conductive material, such as polysilicon, metal (eg, W, Cu, Al, etc.), metal compound (eg, TiN, TaN, etc.), or silicide. In some embodiments, the gate electrode 604 includes doped polysilicon, ie, gate polysilicon.
如圖5和6A所示,3D電晶體500還可以包括在基底502中的一對源極和汲極506(摻雜區,又稱源電極和汲電極)。源極和汲極506可以摻雜有任何合適的P型摻雜劑,例如B或Ga,或者任何合適的N型摻雜劑,例如P或Ar。在平面圖中,源極和汲極506可以被閘極結構508隔開。即,根據一些實施方式,在平面圖中,閘極結構508形成在源極與汲極506之間。結果,當施加到閘極結構508的閘電極604的閘極電壓高於3D電晶體500的閾值電壓時,可以在由閘極結構508圍繞的源極和汲極506之間橫向地形成3D半導體主體505中的3D電晶體500的多個通道。與其中僅可以在基底402的頂表面上形成單個通道的平面電晶體400不同,在3D電晶體500中的3D半導體主體505的頂表面和側表面上可以形成多個通道。在一些實施方式中,3D電晶體500包括多閘極電晶體。即,與僅包括單個閘極的平面電晶體400不同,由於3D半導體主體505的3D結構和圍繞3D半導體主體505的多個側面的閘極結構508,3D電晶體500可以包括在3D半導體主體505的多個側面上的多個閘極。結果,與平面電晶體400相比,3D電晶體500可以具有更大的閘極控制面積,而以更小的亞閾值擺幅實現更好的通道控制。在截止狀態期間,由於通道完全耗盡,因此可以很好地顯著減小3D電晶體500的洩漏電流(I
off)。另一方面,3D電晶體500的尺寸可以從平面電晶體400顯著減小,同時仍然保持與平面電晶體400相同的電性能(例如,通道控制、亞閾值擺幅和/或洩漏電流)。
As shown in FIGS. 5 and 6A , the 3D transistor 500 may further include a pair of source and drain electrodes 506 (doped regions, also called source electrodes and drain electrodes) in the substrate 502 . The source and drain 506 may be doped with any suitable P-type dopant, such as B or Ga, or any suitable N-type dopant, such as P or Ar. In plan view, the source and drain 506 may be separated by a gate structure 508 . That is, according to some embodiments, gate structure 508 is formed between source and drain 506 in plan view. As a result, when the gate voltage applied to the gate electrode 604 of the gate structure 508 is higher than the threshold voltage of the 3D transistor 500, a 3D semiconductor can be formed laterally between the source and drain 506 surrounded by the gate structure 508 Multiple channels of 3D transistor 500 in body 505 . Unlike the planar transistor 400 in which only a single channel can be formed on the top surface of the substrate 402 , multiple channels can be formed on the top and side surfaces of the 3D semiconductor body 505 in the 3D transistor 500 . In some embodiments, the 3D transistor 500 includes a multi-gate transistor. That is, unlike the planar transistor 400 which includes only a single gate, the 3D transistor 500 can be included in the 3D semiconductor body 505 due to the 3D structure of the 3D semiconductor body 505 and the gate structure 508 surrounding multiple sides of the 3D semiconductor body 505. Multiple gates on multiple sides of the . As a result, compared to the planar transistor 400, the 3D transistor 500 can have a larger gate control area while achieving better channel control with a smaller subthreshold swing. During the off-state, the leakage current (I off ) of the 3D transistor 500 may well be significantly reduced since the channel is completely depleted. On the other hand, the size of the 3D transistor 500 can be significantly reduced from the planar transistor 400 while still maintaining the same electrical properties (eg, channel control, subthreshold swing, and/or leakage current) as the planar transistor 400 .
應當理解,雖然如上所述,3D電晶體(例如,FinFET)也用於使用先進技術節點(例如,小於22 nm)的邏輯裝置(例如,微處理器)中,但由於對邏輯裝置與記憶體外圍電路之間的電晶體的不同要求,3D電晶體500的設計也可展現邏輯裝置中使用的3D電晶體中所未見的獨特特徵。從材料角度來看,在一些實施方式中,不同於使用先進技術節點(例如,小於22 nm)的邏輯裝置中的3D電晶體(例如,FinFET),其使用HKMG(即,用於閘極介電質的高k介電質,及用於閘電極的金屬),記憶體外圍電路中的3D電晶體500使用閘極多晶矽和閘極氧化物而不是HKMG,以降低製造成本和複雜性。It should be understood that while, as noted above, 3D transistors (eg, FinFETs) are also used in logic devices (eg, microprocessors) using advanced technology nodes (eg, less than 22 nm), due to the Due to the different requirements of transistors between peripheral circuits, the design of 3D transistor 500 can also exhibit unique characteristics not seen in 3D transistors used in logic devices. From a materials perspective, in some embodiments, instead of 3D transistors (eg, FinFETs) in logic devices using advanced technology nodes (eg, less than 22 nm), HKMG (ie, for gate dielectric High-k dielectric for the dielectric, and metal for the gate electrode), the 3D transistor 500 in the memory peripheral circuit uses gate polysilicon and gate oxide instead of HKMG to reduce manufacturing cost and complexity.
從電晶體尺寸的角度來看,記憶體外圍電路中的3D電晶體500可能不會遵循使用先進技術節點(例如,小於22 nm)的邏輯裝置(例如,微處理器)的相同趨勢而按比例縮小。尺寸的差異可允許3D電晶體500在較高電壓(例如,3.3V及以上)下使用,所述較高電壓對於使用先進技術節點(例如,小於22 nm)的邏輯裝置中的3D電晶體(例如,FinFET)來說通常不使用且不合需要。尺寸上的差異也可顯著地降低記憶體外圍電路中的3D電晶體500的製造成本和複雜性。From a transistor size standpoint, 3D transistors 500 in memory peripheral circuits may not follow the same trend to scale as logic devices (eg, microprocessors) using advanced technology nodes (eg, less than 22 nm) zoom out. The difference in size may allow 3D transistor 500 to be used at higher voltages (e.g., 3.3V and above) for 3D transistors in logic devices using advanced technology nodes (e.g., less than 22 nm) ( For example, FinFETs) are generally not used and are undesirable. The size difference can also significantly reduce the manufacturing cost and complexity of the 3D transistor 500 in the memory peripheral circuit.
例如,在一些實施方式中,如圖6B所示,3D半導體主體505的寬度W大於10 nm。例如,3D半導體主體505的寬度可以在30 nm和1000 nm之間(例如,30 nm、40 nm、50 nm、60 nm、70 nm、80 nm、90 nm、100 nm、200 nm、300 nm、400 nm、500 nm、600 nm、700 nm、800 nm、900 nm、1000 nm、由這些值中的任何一個值為下限所界定的任何範圍、或者在由這些值中的任何兩個值所限定的任何範圍中)。3D電晶體500的寬度可以顯著大於(例如,一倍或多倍或者甚至一個或多個數量級)在使用先進技術節點(例如,小於22 nm)的邏輯裝置中使用的3D電晶體(例如,FinFET)的寬度。For example, in some embodiments, as shown in Figure 6B, the width W of the 3D semiconductor body 505 is greater than 10 nm. For example, the width of the 3D semiconductor body 505 can be between 30 nm and 1000 nm (e.g., 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, any range bounded by a lower limit of any one of these values, or in any range bounded by any two of these values in any range of ). The width of 3D transistor 500 may be significantly larger (eg, one or more times or even one or more orders of magnitude) than 3D transistors (eg, FinFET ) width.
在一些實施方式中,如圖6B所示,3D半導體主體505的高度H大於40 nm。例如,3D半導體主體505的高度可以在50 nm和1000 nm之間(例如,50 nm、60 nm、70 nm、80 nm、90 nm、100 nm、200 nm、300 nm、400 nm、500 nm、600 nm、700 nm、800 nm、900 nm、1000 nm,由這些值中的任何一個值為下限所界定的任何範圍,或者在由這些值中的任何兩個值所限定的任何範圍中)。3D電晶體500的高度可以顯著大於(例如,一倍或多倍或者甚至一個或多個數量級)在使用先進技術節點(例如,小於22 nm)的邏輯裝置中使用的3D電晶體(例如,FinFET)的高度。In some embodiments, as shown in Figure 6B, the height H of the 3D semiconductor body 505 is greater than 40 nm. For example, the height of the 3D semiconductor body 505 can be between 50 nm and 1000 nm (eg, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, any range bounded by the lower limit of any one of these values, or in any range bounded by any two of these values). The height of the 3D transistor 500 can be significantly larger (e.g., one or more times or even one or more orders of magnitude) than 3D transistors (e.g., FinFET )the height of.
在一些實施方式中,如圖6B中所示,閘極介電質602的厚度T大於1.8 nm。例如,閘極介電質602的厚度可以在2 nm和100 nm之間(例如,2 nm、3 nm、4 nm、5 nm、6 nm、7 nm、8 nm、9 nm、10 nm、20 nm、30 nm、40 nm、50 nm、60 nm、70 nm、80 nm、90 nm、100 nm、由這些值中的任何一個值為下限所界定的任何範圍、或者在由這些值中的任何兩個值所限定的任何範圍中)。閘極介電質602的厚度可以顯著大於(例如,一倍或多倍或者甚至一個或多個數量級)用於使用先進技術節點(例如,小於22 nm)的邏輯裝置中的3D電晶體(例如,FinFET)的厚度。結果,利用較厚的閘極介電質602,3D電晶體500可以比在使用先進技術節點(例如,小於22 nm)的邏輯裝置中使用的3D電晶體(例如,FinFET)承受更高的電壓(例如,3.3V和更高)。In some embodiments, as shown in Figure 6B, the thickness T of the gate dielectric 602 is greater than 1.8 nm. For example, the gate dielectric 602 may have a thickness between 2 nm and 100 nm (eg, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 20 nm nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, any range bounded by a lower limit of any of these values, or within any in any range bounded by two values). The thickness of the gate dielectric 602 can be significantly greater (eg, one or more times or even one or more orders of magnitude) for 3D transistors (eg, , FinFET) thickness. As a result, with thicker gate dielectric 602, 3D transistor 500 can withstand higher voltages than 3D transistors (eg, FinFETs) used in logic devices using advanced technology nodes (eg, less than 22 nm) (eg, 3.3V and higher).
在一些實施方式中,如圖6A所示,3D電晶體500的通道長度L大於30 nm。例如,3D電晶體500的通道長度可以在50 nm和1500 nm之間(例如,50 nm、60 nm、70 nm、80 nm、90 nm、100 nm、200 nm、300 nm、400 nm、500 nm、600 nm、700 nm、800 nm、900 nm、1000 nm、1100 nm、1200 nm、1300 nm、1400 nm、1500 nm、由這些值中的任何一個值為下限界定的任何範圍、或在由這些值中的任何兩個值限定的任何範圍中)。3D電晶體500的通道長度可以顯著大於(例如,一倍或多倍或者甚至一個或多個數量級)在使用先進技術節點(例如,小於22 nm)的邏輯裝置中使用的3D電晶體(例如,FinFET)的通道長度。In some embodiments, as shown in FIG. 6A , the channel length L of the 3D transistor 500 is greater than 30 nm. For example, the channel length of the 3D transistor 500 can be between 50 nm and 1500 nm (eg, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm , 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, 1100 nm, 1200 nm, 1300 nm, 1400 nm, 1500 nm, any range bounded by a lower limit of any of these values, or within in any range bounded by any two of the values). The channel length of 3D transistor 500 may be significantly larger (e.g., one or more times or even one or more orders of magnitude) than 3D transistors (e.g., FinFET) channel length.
應當理解,儘管在圖5、6A和6B中未示出,但是3D電晶體500可以包括附加部件,例如阱和間隔物。還應當理解,與在使用先進技術節點(例如,小於22 nm)的邏輯裝置中使用的3D電晶體(例如,FinFET)不同,其包括在源極和汲極處包括GaAs或SiGe(又稱應變元件)的應力源或者使用應變矽技術在通道中施加應變以便增加載流子遷移率,3D電晶體500可以由於其相對大的尺寸以及為了降低製造複雜性和成本而不包括在源極和汲極506處的應力源和/或可以不在3D半導體主體505中使用應變半導體材料。It should be understood that, although not shown in Figures 5, 6A and 6B, the 3D transistor 500 may include additional components such as wells and spacers. It should also be understood that, unlike 3D transistors (eg, FinFETs) used in logic devices using advanced technology nodes (eg, less than 22 nm), which include GaAs or SiGe at the source and drain (aka strained element) or using strained silicon technology to apply strain in the channel to increase carrier mobility, the 3D transistor 500 may not include sources and drains due to its relatively large size and to reduce manufacturing complexity and cost. Stressors at pole 506 and/or strained semiconductor material may not be used in 3D semiconductor body 505 .
還應當理解,圖5、6A和6B示出了可以在記憶體外圍電路中使用的3D電晶體(例如,FinFET)的一個示例,並且任何其他合適的3D電晶體(例如,全環閘(GAA)FET)也可以在記憶體外圍電路中使用。例如,圖7A-7I示出了根據本揭露內容的各個方面的各種3D電晶體的截面的側視圖。類似於圖5、6A和6B中的3D電晶體500,圖7A-7I中的每個3D電晶體可以是具有在基底上方的3D半導體主體和與3D半導體主體的多於一個側面接觸的閘極結構的多閘極電晶體。閘極結構可以包括閘極介電質和閘電極。例如,圖7A、7B和7C分別示出了全環閘(GAA)無矽(SON)電晶體、多獨立閘極FET(MIGET)和FinFET,其中的每一個都被認為是雙閘極電晶體。例如,圖7D、7E和7F分別示出三閘極FET、Π-閘極FET和Ω-FET,其中的每一個都被認為是三閘極電晶體。例如,圖7G、7H和7I分別示出了四閘極FET、圓柱形FET和多橋/堆疊奈米線FET,其中的每一個都被認為是環繞型閘極電晶體。如圖7A-7I中可以看到的,3D半導體主體的截面在側視圖中可以具有正方形形狀、矩形形狀(或梯形形狀)、圓形(或橢圓形形狀)或任何其他合適的形狀。應當理解,與本揭露內容的範圍一致,對於其截面具有圓形或橢圓形形狀的3D半導體主體,3D半導體主體仍然可以被認為具有多個側面,使得閘極結構與3D半導體主體的多於一個側面接觸。應當理解,在一些示例中,多個3D電晶體(例如,多個FinFET)可以共享單個3D半導體主體(例如,鰭狀物),即,形成在單個3D半導體主體上。例如,多個FinFET可以平行地布置在同一鰭狀物上,並且在共享同一鰭狀物的多個FinFET之間可以沒有形成任何溝槽隔離(例如STI)來分離FinFET。It should also be understood that Figures 5, 6A and 6B illustrate one example of a 3D transistor (eg, a FinFET) that may be used in a memory peripheral circuit, and that any other suitable 3D transistor (eg, a gate-all-around (GAA ) FET) can also be used in memory peripheral circuits. For example, FIGS. 7A-7I illustrate side views of cross-sections of various 3D transistors according to various aspects of the present disclosure. Similar to 3D transistor 500 in FIGS. 5, 6A and 6B, each 3D transistor in FIGS. 7A-7I can be a 3D semiconductor body with a 3D semiconductor body above a substrate and a gate contacting more than one side of the 3D semiconductor body. structure of multi-gate transistors. The gate structure may include a gate dielectric and a gate electrode. For example, Figures 7A, 7B, and 7C show a gate-all-around (GAA) silicon-free (SON) transistor, a multiple independent gate FET (MIGET), and a FinFET, respectively, each of which is considered a double-gate transistor . For example, Figures 7D, 7E, and 7F show a tri-gate FET, a Π-gate FET, and an Ω-FET, respectively, each of which is considered a tri-gate transistor. For example, Figures 7G, 7H, and 7I show a quad-gate FET, a cylindrical FET, and a multi-bridge/stacked nanowire FET, respectively, each of which is considered a wrap-around gate transistor. As can be seen in Figures 7A-7I, the cross-section of the 3D semiconductor body may have a square shape, a rectangular shape (or trapezoidal shape), a circular (or elliptical shape) or any other suitable shape in side view. It should be understood that, consistent with the scope of the present disclosure, for a 3D semiconductor body whose cross-section has a circular or elliptical shape, the 3D semiconductor body may still be considered to have multiple sides such that the gate structure is connected to more than one side of the 3D semiconductor body. side contact. It should be understood that in some examples multiple 3D transistors (eg multiple FinFETs) may share, ie be formed on, a single 3D semiconductor body (eg fin). For example, multiple FinFETs may be arranged in parallel on the same fin, and no trench isolation (eg, STI) may be formed between the multiple FinFETs sharing the same fin to separate the FinFETs.
如上文關於圖1A和1B所述的,3D電晶體500可以是與具有儲存單元陣列的第一半導體結構102鍵合的第二半導體結構104的外圍電路中的電晶體的一個示例。例如,圖8A示出了根據一些實施方式的示例性3D儲存裝置800的截面的側視圖。應當理解,圖8A僅用於說明性目的,並且實際上可以不一定反映實際器件結構(例如,互連)。作為以上關於圖1A描述的3D儲存裝置100的一個示例,3D儲存裝置800是包括第一半導體結構802和堆疊在第一半導體結構802之上的第二半導體結構804的鍵合晶片。根據一些實施方式,第一半導體結構802和第二半導體結構804在其間的鍵合界面806處接合。如圖8A所示,第一半導體結構802可以包括基底808,其可以包括矽(例如,單晶矽,c-Si)、SiGe、GaAs、Ge、SOI或任何其他合適的材料。As described above with respect to FIGS. 1A and 1B , the 3D transistor 500 may be one example of a transistor in a peripheral circuit of the second semiconductor structure 104 bonded to the first semiconductor structure 102 having the memory cell array. For example, Figure 8A shows a side view of a cross-section of an exemplary 3D storage device 800, according to some embodiments. It should be understood that FIG. 8A is for illustrative purposes only, and may not necessarily reflect actual device structures (eg, interconnects) in reality. As one example of the 3D storage device 100 described above with respect to FIG. 1A , the 3D storage device 800 is a bonded wafer including a first semiconductor structure 802 and a second semiconductor structure 804 stacked on top of the first semiconductor structure 802 . According to some embodiments, the first semiconductor structure 802 and the second semiconductor structure 804 are bonded at a bonding interface 806 therebetween. As shown in FIG. 8A , the first semiconductor structure 802 can include a substrate 808 , which can include silicon (eg, single crystal silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable material.
第一半導體結構802可以包括在基底808上方的器件層810。在一些實施方式中,器件層810包括第一外圍電路812(例如,頁緩衝器304、字元線驅動器308、和/或I/O電路316和318)、以及第二外圍電路814(例如,控制邏輯312、暫存器314等)。在一些實施方式中,第一外圍電路812包括多個3D電晶體816(例如,對應於3D電晶體500),且第二外圍電路814包括多個平面電晶體818(例如,對應於平面電晶體400)。溝槽隔離860和862(例如STI)和摻雜區(例如,電晶體816和818的阱、源極和汲極)也可以形成在基底808上或其中。在一些實施方式中,在平面圖中,溝槽隔離860在基底808上並且橫向地在兩個相鄰的3D電晶體816之間,並且溝槽隔離862延伸到基底808中並且橫向地在兩個相鄰的平面電晶體818之間。在一些實施方式中,溝槽隔離862和溝槽隔離860具有不同深度(例如,其底表面在y方向上處於不同平面中),因為它們分別分離不同類型的電晶體(平面電晶體818和3D電晶體816)。例如,如圖8A所示,溝槽隔離862可以具有比溝槽隔離860更大的深度。應當理解,取決於不同的製造製程,在一些示例中,溝槽隔離862和溝槽隔離860具有相同的深度(例如,其底表面在y方向上處於相同平面中)。The first semiconductor structure 802 may include a device layer 810 over a substrate 808 . In some implementations, device layer 810 includes first peripheral circuitry 812 (eg, page buffer 304, wordline driver 308, and/or I/O circuits 316 and 318), and second peripheral circuitry 814 (eg, control logic 312, scratchpad 314, etc.). In some implementations, the first peripheral circuit 812 includes a plurality of 3D transistors 816 (eg, corresponding to the 3D transistor 500 ), and the second peripheral circuit 814 includes a plurality of planar transistors 818 (eg, corresponding to the planar transistor 400). Trench isolations 860 and 862 (eg, STIs) and doped regions (eg, wells, sources, and drains of transistors 816 and 818 ) may also be formed on or in substrate 808 . In some embodiments, trench isolation 860 is on substrate 808 and laterally between two adjacent 3D transistors 816 in plan view, and trench isolation 862 extends into substrate 808 and laterally between two adjacent 3D transistors 816 . between adjacent planar transistors 818 . In some implementations, trench isolation 862 and trench isolation 860 have different depths (eg, their bottom surfaces are in different planes in the y-direction) because they separate different types of transistors (planar transistor 818 and 3D Transistor 816). For example, as shown in FIG. 8A , trench isolation 862 may have a greater depth than trench isolation 860 . It should be understood that trench isolation 862 and trench isolation 860 have the same depth (eg, their bottom surfaces are in the same plane in the y-direction) in some examples, depending on different manufacturing processes.
在一些實施方式中,第一半導體結構802進一步包括在器件層810上方的互連層820以往返於外圍電路812和814傳輸電訊號。互連層820可以包括多個互連(本文也稱為“觸點”),包括橫向互連線和垂直互連通路(VIA)觸點。如本文所使用的,術語“互連”可以廣泛地包括任何適當類型的互連,例如中段製程(MEOL)互連和後段製程(BEOL)互連。互連層820還可以包括一個或多個層間介電質(ILD)層(又稱為“金屬間介電質(IMD)層”),其中可以形成互連線和通孔觸點。即,互連層820可以包括多個ILD層中的互連線和通孔觸點。在一些實施方式中,器件層810中的器件透過互連層820中的互連彼此耦接。例如,外圍電路812可透過互連層820耦接到外圍電路814。In some embodiments, the first semiconductor structure 802 further includes an interconnect layer 820 above the device layer 810 to transmit electrical signals to and from the peripheral circuits 812 and 814 . The interconnect layer 820 may include a plurality of interconnects (also referred to herein as “contacts”), including lateral interconnect lines and vertical interconnect via (VIA) contacts. As used herein, the term "interconnect" may broadly include any suitable type of interconnect, such as mid-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. Interconnect layer 820 may also include one or more interlayer dielectric (ILD) layers (also referred to as "intermetal dielectric (IMD) layers") in which interconnect lines and via contacts may be formed. That is, the interconnect layer 820 may include interconnect lines and via contacts in multiple ILD layers. In some embodiments, devices in the device layer 810 are coupled to each other through interconnects in the interconnect layer 820 . For example, the peripheral circuit 812 can be coupled to the peripheral circuit 814 through the interconnection layer 820 .
如圖8A所示,第一半導體結構802還可以包括在鍵合界面806處並且在互連層820和器件層810上方的鍵合層822。鍵合層822可以包括多個鍵合觸點824和電隔離鍵合觸點824的介電質。鍵合觸點824可包括導電材料。鍵合層822的剩餘區域可以由介電質材料形成。鍵合層822中的鍵合觸點824和周圍介電質可以用於混合鍵合。類似地,如圖8A所示,第二半導體結構804還可以包括在第一半導體結構802的鍵合界面806處和鍵合層822上方的鍵合層826。鍵合層826可以包括多個鍵合觸點828和電隔離鍵合觸點828的介電質。鍵合觸點828可包括導電材料。鍵合層826的剩餘區域可以由介電質材料形成。鍵合層826中的鍵合觸點828和周圍介電質可用於混合鍵合。根據一些實施方式,鍵合觸點828在鍵合界面806處與鍵合觸點824接觸。As shown in FIG. 8A , the first semiconductor structure 802 may also include a bonding layer 822 at the bonding interface 806 and above the interconnect layer 820 and the device layer 810 . Bonding layer 822 may include a plurality of bonding contacts 824 and a dielectric that electrically isolates bonding contacts 824 . Bonding contacts 824 may include a conductive material. The remaining area of bonding layer 822 may be formed of a dielectric material. Bonding contacts 824 in bonding layer 822 and the surrounding dielectric may be used for hybrid bonding. Similarly, as shown in FIG. 8A , the second semiconductor structure 804 may further include a bonding layer 826 at the bonding interface 806 of the first semiconductor structure 802 and above the bonding layer 822 . Bonding layer 826 may include a plurality of bonding contacts 828 and a dielectric that electrically isolates bonding contacts 828 . Bonding contacts 828 may include a conductive material. The remaining area of bonding layer 826 may be formed of a dielectric material. Bonding contacts 828 in bonding layer 826 and the surrounding dielectric may be used for hybrid bonding. According to some implementations, bonding contacts 828 make contact with bonding contacts 824 at bonding interface 806 .
第二半導體結構804可以在鍵合界面806處以面對面的方式鍵合在第一半導體結構802的頂部上。在一些實施方式中,作為混合鍵合(也稱為“金屬/介電質混合鍵合”)的結果,鍵合界面806設置在鍵合層822和826之間,混合鍵合是一種直接鍵合技術(例如,在表面之間形成鍵合而不使用諸如焊料或黏合劑的中間層)並且可以同時獲得金屬-金屬鍵合和介電質-介電質鍵合。在一些實施方式中,鍵合界面806是鍵合層822和826相遇並鍵合的位置。實際上,鍵合界面806可以是具有一定厚度的層,其包括第一半導體結構802的鍵合層822的頂表面和第二半導體結構804的鍵合層826的底表面。The second semiconductor structure 804 may be bonded in a face-to-face manner on top of the first semiconductor structure 802 at the bonding interface 806 . In some embodiments, bonding interface 806 is disposed between bonding layers 822 and 826 as a result of hybrid bonding (also referred to as "hybrid metal/dielectric bonding"), which is a direct bond bonding techniques (eg, forming bonds between surfaces without the use of intermediate layers such as solder or adhesives) and can achieve both metal-metal and dielectric-dielectric bonding. In some embodiments, bonding interface 806 is where bonding layers 822 and 826 meet and bond. In practice, the bonding interface 806 may be a layer having a thickness including the top surface of the bonding layer 822 of the first semiconductor structure 802 and the bottom surface of the bonding layer 826 of the second semiconductor structure 804 .
在一些實施方式中,第二半導體結構804還包括鍵合層826上方的互連層830以傳輸電信號。互連層830可以包括多個互連,例如MEOL互連和BEOL互連。在一些實施方式中,互連層830中的互連還包括局部互連,諸如位元線、位元線觸點和字元線觸點。互連層830還可以包括一個或多個ILD層,其中可以形成互連線和和通孔觸點。在一些實施方式中,第一外圍電路812是頁緩衝器304,且第一外圍電路812的3D電晶體816耦接到第二半導體結構804的位元線。在一些實施方式中,第一外圍電路812是字元線驅動器308,且第一外圍電路812的3D電晶體816耦接到第二半導體結構804的字元線(例如,導電層834)。In some embodiments, the second semiconductor structure 804 also includes an interconnect layer 830 over the bonding layer 826 to transmit electrical signals. Interconnect layer 830 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in the interconnect layer 830 also include local interconnects, such as bit lines, bit line contacts, and word line contacts. Interconnect layer 830 may also include one or more ILD layers in which interconnect lines and via contacts may be formed. In some embodiments, the first peripheral circuit 812 is the page buffer 304 , and the 3D transistor 816 of the first peripheral circuit 812 is coupled to the bit line of the second semiconductor structure 804 . In some embodiments, the first peripheral circuit 812 is the wordline driver 308 , and the 3D transistor 816 of the first peripheral circuit 812 is coupled to the wordline (eg, the conductive layer 834 ) of the second semiconductor structure 804 .
在一些實施方式中,第二半導體結構804包括NAND快閃記憶體裝置,其中儲存單元以3D NAND記憶體串838陣列形式提供在互連層830和鍵合層826上方。根據一些實施方式,每個3D NAND記憶體串838垂直延伸穿過各自包括導電層834和介電質層836的多個對。堆疊且交錯的導電層834和介電質層836在本文中還被稱為堆疊結構,例如,記憶體堆疊體832。根據一些實施方式,記憶體堆疊體832中的交錯導電層834和介電質層836在垂直方向上交替。每個導電層834可包括由黏合層和閘極介電質層圍繞的閘電極(閘極線)。堆疊導電層834的閘電極可以橫向延伸為字元線,終止於記憶體堆疊體832的一個或多個階梯結構處。In some embodiments, the second semiconductor structure 804 includes a NAND flash memory device in which storage cells are provided in an array of 3D NAND memory strings 838 over the interconnect layer 830 and the bonding layer 826 . According to some embodiments, each 3D NAND memory string 838 extends vertically through a plurality of pairs each including a conductive layer 834 and a dielectric layer 836 . The stacked and interleaved conductive layers 834 and dielectric layers 836 are also referred to herein as a stack structure, eg, memory stack 832 . According to some embodiments, the alternating conductive layers 834 and dielectric layers 836 in the memory stack 832 alternate in the vertical direction. Each conductive layer 834 may include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrodes of the stacked conductive layer 834 may extend laterally as word lines terminating at one or more ladder structures of the memory stack 832 .
在一些實施方式中,每個3D NAND記憶體串838是包括半導體通道和記憶體膜的“電荷捕獲”類型的NAND記憶體串。在一些實施方式中,半導體通道包括矽,例如非晶矽、多晶矽或單晶矽。在一些實施方式中,記憶體膜是包括穿隧層、儲存層(也稱為“電荷捕獲/儲存層”)和阻擋層的複合介電質層。每個3D NAND記憶體串838可以具有圓柱形狀(例如,柱形)。根據一些實施方式,儲存膜的半導體通道、穿隧層、儲存層和阻擋層沿著從柱的中心向外表面的方向以該順序排列。在一些實施方式中,3D NAND記憶體串838還包括多個控制閘極(各自是字元線的一部分)。記憶體堆疊體832中的每個導電層834可充當3D NAND記憶體串838的每個儲存單元的控制閘極。In some embodiments, each 3D NAND memory string 838 is a "charge trapping" type of NAND memory string that includes a semiconductor channel and a memory film. In some embodiments, the semiconductor channel includes silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping/storage layer"), and a blocking layer. Each 3D NAND memory string 838 may have a cylindrical shape (eg, columnar). According to some embodiments, the semiconductor channel of the storage film, the tunneling layer, the storage layer and the barrier layer are arranged in this order along a direction from the center of the pillar to the outer surface. In some embodiments, the 3D NAND memory string 838 also includes a plurality of control gates (each being part of a word line). Each conductive layer 834 in the memory stack 832 can serve as a control gate for each memory cell of the 3D NAND memory string 838 .
在一些實施方式中,第二半導體結構804還包括設置在記憶體堆疊體832和3D NAND記憶體串838上方的半導體層848。半導體層848可以是其上形成記憶體堆疊體832和3D NAND記憶體串838的減薄基底。在一些實施方式中,半導體層848包括單晶矽。半導體層848還可包括隔離和摻雜區域(例如,用作3D NAND記憶體串838的陣列公共源極(ACS),未示出)。應當理解,3D NAND記憶體串838不限於“電荷捕獲”類型的3D NAND記憶體串,並且在其他示例中可以是“浮閘”類型的3D NAND記憶體串。半導體層848可以包括多晶矽作為“浮閘”類型的3D NAND記憶體串的源極板。In some embodiments, the second semiconductor structure 804 further includes a semiconductor layer 848 disposed over the memory stack 832 and the 3D NAND memory string 838 . The semiconductor layer 848 may be a thinned substrate on which the memory stack 832 and the 3D NAND memory string 838 are formed. In some embodiments, semiconductor layer 848 includes monocrystalline silicon. The semiconductor layer 848 may also include isolation and doped regions (eg, used as array common source (ACS) for the 3D NAND memory string 838 , not shown). It should be understood that 3D NAND memory string 838 is not limited to a "charge trapping" type of 3D NAND memory string, and may be a "floating gate" type of 3D NAND memory string in other examples. The semiconductor layer 848 may comprise polysilicon as a source plate for a "floating gate" type of 3D NAND memory string.
如圖8A所示,第二半導體結構804還可以包括半導體層848上方的焊墊輸出互連層850。焊墊輸出互連層850可以包括一個或多個ILD層中的互連,例如觸點焊墊852。焊墊輸出互連層850和互連層830可以形成在半導體層848的相對側。在一些實施方式中,例如出於焊墊輸出的目的,焊墊輸出互連層850中的互連可以在3D儲存裝置800和外部電路之間傳輸電訊號。在一些實施方式中,第二半導體結構804還包括延伸穿過半導體層848以電連接焊墊輸出互連層850以及互連層830和820的一個或多個觸點854。因此,外圍電路812和814可透過互連層830和820以及鍵合觸點828和824耦接到3D NAND記憶體串838的陣列。即,3D NAND記憶體串838的陣列可以跨越鍵合界面806耦接到3D電晶體816和平面電晶體818。此外,外圍電路812和814及3D NAND記憶體串838的陣列可透過觸點854和焊墊輸出互連層850耦接到外部電路。As shown in FIG. 8A , the second semiconductor structure 804 may also include a pad output interconnect layer 850 over the semiconductor layer 848 . Pads Output interconnect layer 850 may include interconnects in one or more ILD layers, such as contact pads 852 . The pad output interconnection layer 850 and the interconnection layer 830 may be formed on opposite sides of the semiconductor layer 848 . In some embodiments, the interconnects in the pad output interconnection layer 850 can transmit electrical signals between the 3D storage device 800 and external circuits, such as for pad output purposes. In some embodiments, the second semiconductor structure 804 also includes one or more contacts 854 extending through the semiconductor layer 848 to electrically connect the pad output interconnect layer 850 and the interconnect layers 830 and 820 . Thus, peripheral circuits 812 and 814 may be coupled to the array of 3D NAND memory strings 838 through interconnect layers 830 and 820 and bonding contacts 828 and 824 . That is, an array of 3D NAND memory strings 838 may be coupled across bonding interface 806 to 3D transistor 816 and planar transistor 818 . In addition, peripheral circuits 812 and 814 and the array of 3D NAND memory strings 838 can be coupled to external circuits through contact 854 and pad output interconnect layer 850 .
圖8B示出了根據本揭露內容的一些方面的另一示例性3D儲存裝置801的截面。應當理解,圖8B僅用於說明性目的,並且實際上可以不一定反映實際器件結構(例如,互連)。作為以上關於圖1B描述的3D儲存裝置101的一個示例, 3D儲存裝置801是包括第二半導體結構803和堆疊在第二半導體結構803之上的第一半導體結構805的鍵合晶片。類似於以上在圖8A中描述的3D儲存裝置800,3D儲存裝置801代表其中第一半導體結構805和第二半導體結構803單獨形成且在鍵合界面807處以面對面方式鍵合的鍵合晶片的示例。應當理解,以下可不重複3D儲存裝置800和801兩者中的類似結構(例如,材料、製造製程、功能等)的細節。FIG. 8B illustrates a cross-section of another exemplary 3D storage device 801 according to some aspects of the present disclosure. It should be understood that FIG. 8B is for illustrative purposes only, and may not in fact reflect actual device structures (eg, interconnects). As an example of the 3D storage device 101 described above with respect to FIG. 1B , the 3D storage device 801 is a bonded wafer including a second semiconductor structure 803 and a first semiconductor structure 805 stacked on top of the second semiconductor structure 803 . Similar to the 3D storage device 800 described above in FIG. 8A , the 3D storage device 801 represents an example of a bonded wafer in which the first semiconductor structure 805 and the second semiconductor structure 803 are formed separately and bonded in a face-to-face manner at the bonding interface 807 . It should be understood that details of similar structures (eg, materials, manufacturing processes, functions, etc.) in both 3D storage devices 800 and 801 may not be repeated below.
第二半導體結構803可以包括基底809和記憶體堆疊體811,該記憶體堆疊體811包括在基底809上方的交錯導電層813和介電質層815。在一些實施方式中,3D NAND記憶體串817的陣列各自垂直延伸穿過基底809上方的記憶體堆疊體811中的交錯導電層813和介電質層815。每個3D NAND記憶體串817可包括半導體通道和記憶體膜。3D NAND記憶體串817可以是“電荷捕獲”類型的3D NAND記憶體串或“浮閘”類型的3D NAND記憶體串。The second semiconductor structure 803 may include a substrate 809 and a memory stack 811 including alternating conductive layers 813 and dielectric layers 815 over the substrate 809 . In some embodiments, the array of 3D NAND memory strings 817 each extends vertically through the interleaved conductive layers 813 and dielectric layers 815 in the memory stack 811 above the substrate 809 . Each 3D NAND memory string 817 may include a semiconductor channel and a memory film. The 3D NAND memory string 817 may be a "charge trapping" type 3D NAND memory string or a "floating gate" type 3D NAND memory string.
在一些實施方式中,第二半導體結構803還包括在記憶體堆疊體811和3D NAND記憶體串817上方的互連層827,以往返於3D NAND記憶體串817傳輸電訊號。互連層827可以包括多個互連,包括互連線和通孔觸點。在一些實施方式中,互連層827中的互連還包括局部互連,諸如位元線、位元線觸點和字元線觸點。在一些實施方式中,第二半導體結構803還包括在鍵合界面807處和在互連層827和記憶體堆疊體811及3D NAND記憶體串817上方的鍵合層829。鍵合層829可以包括多個鍵合觸點855以及圍繞並且電隔離鍵合觸點855的介電質。In some embodiments, the second semiconductor structure 803 further includes an interconnection layer 827 above the memory stack 811 and the 3D NAND memory string 817 for transmitting electrical signals to and from the 3D NAND memory string 817 . The interconnect layer 827 may include a plurality of interconnects, including interconnect lines and via contacts. In some embodiments, the interconnects in the interconnect layer 827 also include local interconnects, such as bit lines, bit line contacts, and word line contacts. In some embodiments, the second semiconductor structure 803 further includes a bonding layer 829 at the bonding interface 807 and above the interconnect layer 827 and the memory stack 811 and the 3D NAND memory string 817 . Bonding layer 829 may include a plurality of bonding contacts 855 and a dielectric surrounding and electrically isolating bonding contacts 855 .
如圖8B所示,第一半導體結構805包括在鍵合界面807處和鍵合層829上方的另一鍵合層851。鍵合層851可以包括多個鍵合觸點853和圍繞並電隔離鍵合觸點853的介電質。根據一些實施方式,鍵合觸點853在鍵合界面807處與鍵合觸點855接觸。在一些實施方式中,第一半導體結構805還包括鍵合層851上方的互連層857以傳輸電訊號。互連層857可包括多個互連,包括互連線和通孔觸點。As shown in FIG. 8B , the first semiconductor structure 805 includes a further bonding layer 851 at the bonding interface 807 and above the bonding layer 829 . Bonding layer 851 may include a plurality of bonding contacts 853 and a dielectric surrounding and electrically isolating bonding contacts 853 . According to some embodiments, bonding contacts 853 are in contact with bonding contacts 855 at bonding interface 807 . In some embodiments, the first semiconductor structure 805 further includes an interconnection layer 857 above the bonding layer 851 for transmitting electrical signals. The interconnect layer 857 may include a plurality of interconnects, including interconnect lines and via contacts.
第一半導體結構805還可以包括互連層857和鍵合層851上方的器件層831。在一些實施方式中,器件層831包括第一外圍電路835(例如,頁緩衝器304、字元線驅動器308和/或I/O電路316和318)和第二外圍電路837(例如,控制邏輯312、暫存器314等)。在一些實施方式中,外圍電路835包括多個3D電晶體839(例如,對應於3D電晶體500),且外圍電路837包括多個平面電晶體841(例如,對應於平面電晶體400)。溝槽隔離861和863(例如,STI)以及摻雜區(例如,電晶體839和841的阱、源極和汲極)也可以形成在半導體層833(例如,減薄基底)上或其中。在一些實施方式中,在平面圖中,溝槽隔離861在半導體層833下方並且橫向地在兩個相鄰的3D電晶體839之間,並且溝槽隔離863延伸到半導體層833中並且橫向地在兩個相鄰的平面電晶體841之間。在一些實施方式中,溝槽隔離861和溝槽隔離863具有不同深度(例如,其頂表面在y方向上處於不同平面中),因為它們分別分離不同類型的電晶體(平面電晶體841和3D電晶體839)。例如,如圖8B所示,溝槽隔離863可以具有比溝槽隔離861更大的深度。應當理解,取決於不同製造製程,在一些示例中,溝槽隔離863和溝槽隔離861具有相同深度(例如,其頂表面在y方向上處於相同平面中)。The first semiconductor structure 805 may further include an interconnect layer 857 and a device layer 831 above the bonding layer 851 . In some implementations, device layer 831 includes first peripheral circuitry 835 (eg, page buffer 304, wordline driver 308, and/or I/O circuits 316 and 318) and second peripheral circuitry 837 (eg, control logic 312, temporary register 314, etc.). In some embodiments, the peripheral circuit 835 includes a plurality of 3D transistors 839 (eg, corresponding to the 3D transistor 500 ), and the peripheral circuit 837 includes a plurality of planar transistors 841 (eg, corresponding to the planar transistor 400 ). Trench isolations 861 and 863 (eg, STIs) and doped regions (eg, wells, sources and drains of transistors 839 and 841 ) may also be formed on or in semiconductor layer 833 (eg, a thinned substrate). In some embodiments, in a plan view, the trench isolation 861 is below the semiconductor layer 833 and laterally between two adjacent 3D transistors 839, and the trench isolation 863 extends into the semiconductor layer 833 and laterally between between two adjacent planar transistors 841 . In some embodiments, trench isolation 861 and trench isolation 863 have different depths (eg, their top surfaces are in different planes in the y-direction) because they separate different types of transistors (planar transistors 841 and 3D Transistor 839). For example, as shown in FIG. 8B , trench isolation 863 may have a greater depth than trench isolation 861 . It should be understood that trench isolation 863 and trench isolation 861 have the same depth (eg, their top surfaces are in the same plane in the y-direction) in some examples, depending on different manufacturing processes.
在一些實施方式中,第一外圍電路835是頁緩衝器304,且第一外圍電路835的3D電晶體839耦接到第二半導體結構803的位元線。在一些實施方式中,第一外圍電路835是字元線驅動器308,且第一外圍電路835的3D電晶體839耦接到第二半導體結構803的字元線(例如,導電層834)。In some embodiments, the first peripheral circuit 835 is the page buffer 304 , and the 3D transistor 839 of the first peripheral circuit 835 is coupled to the bit line of the second semiconductor structure 803 . In some embodiments, the first peripheral circuit 835 is the wordline driver 308 , and the 3D transistor 839 of the first peripheral circuit 835 is coupled to the wordline (eg, the conductive layer 834 ) of the second semiconductor structure 803 .
在一些實施方式中,第一半導體結構805進一步包括設置在器件層831上方的半導體層833。半導體層833可位於外圍電路835和837上方且與其接觸。半導體層833可以是其上形成電晶體839和841的減薄基底。在一些實施方式中,半導體層833包括單晶矽。半導體層833還可以包括隔離區與摻雜區。In some embodiments, the first semiconductor structure 805 further includes a semiconductor layer 833 disposed over the device layer 831 . The semiconductor layer 833 may be over and in contact with the peripheral circuits 835 and 837 . Semiconductor layer 833 may be a thinned substrate on which transistors 839 and 841 are formed. In some embodiments, the semiconductor layer 833 includes monocrystalline silicon. The semiconductor layer 833 may further include isolation regions and doped regions.
如圖8B所示,第一半導體結構805可以進一步包括半導體層833上方的焊墊輸出互連層843。焊墊輸出互連層843可以包括在一個或多個ILD層中的互連,例如,觸點焊墊845。在一些實施方式中,例如出於焊墊輸出目的,焊墊輸出互連層843中的互連可在3D儲存裝置801與外部電路之間傳輸電訊號。在一些實施方式中,第一半導體結構805進一步包括延伸穿過半導體層833以耦合焊墊出互連層843以及互連層857和827的一個或多個觸點847。結果,外圍電路835和837也可透過互連層857和827以及鍵合觸點853和855耦接到3D NAND記憶體串817的陣列。即,3D NAND記憶體串817的陣列可跨越鍵合界面807耦接到3D電晶體839和平面電晶體841。此外,外圍電路835和837以及3D NAND記憶體串817的陣列可透過觸點847和焊墊輸出互連層843電連接到外部電路。As shown in FIG. 8B , the first semiconductor structure 805 may further include a pad output interconnect layer 843 over the semiconductor layer 833 . Pads Output interconnect layer 843 may include interconnects, eg, contact pads 845 , in one or more ILD layers. In some embodiments, the interconnection in the pad output interconnection layer 843 can transmit electrical signals between the 3D storage device 801 and external circuits, such as for pad output purposes. In some embodiments, the first semiconductor structure 805 further includes one or more contacts 847 extending through the semiconductor layer 833 to couple pads out of the interconnect layer 843 and the interconnect layers 857 and 827 . As a result, peripheral circuits 835 and 837 may also be coupled to the array of 3D NAND memory strings 817 through interconnect layers 857 and 827 and bonding contacts 853 and 855 . That is, an array of 3D NAND memory strings 817 may be coupled across bonding interface 807 to 3D transistor 839 and planar transistor 841 . In addition, the peripheral circuits 835 and 837 and the array of 3D NAND memory strings 817 can be electrically connected to external circuits through the contact 847 and pad output interconnect layer 843 .
如上所述,半導體結構102中的儲存單元陣列不限於如圖8A和8B所示的NAND快閃記憶體單元陣列,並且可以包括任何其他合適的儲存單元陣列,例如DRAM單元陣列。例如,圖8C示出了根據本揭露內容的一些方面的另一示例性3D儲存裝置899的截面。應當理解,圖8C僅用於說明性目的,並且實際上可以不一定反映實際器件結構(例如,互連)。3D儲存裝置899類似於圖8A中的3D儲存裝置800,除了儲存單元陣列包括DRAM單元890的陣列,與NAND記憶體串838的陣列不同。應當理解,以下可以不重複3D儲存裝置800和899兩者中的類似結構(例如,第一半導體結構802的材料、製造製程、功能等)的細節。As mentioned above, the memory cell array in the semiconductor structure 102 is not limited to the NAND flash memory cell array as shown in FIGS. 8A and 8B , and may include any other suitable memory cell array, such as a DRAM cell array. For example, FIG. 8C illustrates a cross-section of another exemplary 3D storage device 899 in accordance with aspects of the present disclosure. It should be understood that FIG. 8C is for illustrative purposes only, and may not necessarily reflect actual device structures (eg, interconnects) in reality. 3D storage device 899 is similar to 3D storage device 800 in FIG. 8A , except that the storage cell array includes an array of DRAM cells 890 as opposed to the array of NAND memory strings 838 . It should be understood that details of similar structures in both the 3D storage devices 800 and 899 (eg, materials, manufacturing processes, functions, etc. of the first semiconductor structure 802 ) may not be repeated below.
如圖8C所示,第二半導體結構804可以在鍵合界面806處以面對面的方式鍵合在包括3D電晶體816的第一半導體結構802的頂部上。在一些實施方式中,作為混合鍵合的結果,鍵合界面806設置在鍵合層822和826之間。As shown in FIG. 8C , the second semiconductor structure 804 may be bonded face-to-face on top of the first semiconductor structure 802 including the 3D transistor 816 at the bonding interface 806 . In some embodiments, bonding interface 806 is disposed between bonding layers 822 and 826 as a result of hybrid bonding.
在一些實施方式中,3D儲存裝置899的第二半導體結構804還包括鍵合層826上方的互連層830,以便往返於DRAM單元890傳輸電訊號。互連層830可以包括多個互連,例如MEOL互連和BEOL互連。在一些實施方式中,互連層830中的互連還包括局部互連,諸如位元線觸點和字元線觸點。互連層830還可以包括一個或多個ILD層,其中可以形成互連線和通孔觸點。In some embodiments, the second semiconductor structure 804 of the 3D storage device 899 further includes an interconnection layer 830 above the bonding layer 826 for transmitting electrical signals to and from the DRAM unit 890 . Interconnect layer 830 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in the interconnect layer 830 also include local interconnects, such as bit line contacts and word line contacts. Interconnect layer 830 may also include one or more ILD layers in which interconnect lines and via contacts may be formed.
3D儲存裝置899的第二半導體結構804還可以包括在互連層830和鍵合層826上方的器件層881。在一些實施例中,器件層881包括在互連層830和鍵合層826上方的DRAM單元890的陣列。在一些實施例中,每個DRAM單元890包括DRAM選擇電晶體886和電容器888。DRAM單元890可以是由一個電晶體和一個電容器組成的1T1C單元。應當理解,DRAM單元890可以具有任何適當的配置,例如2T1C單元、3T1C單元等。在一些實施方式中,DRAM選擇電晶體886形成在半導體層848“上”,其中DRAM選擇電晶體886的全部或部分形成在半導體層848中(例如,在半導體層848的頂表面下方)和/或直接形成在半導體層848上。隔離區(例如STI)和摻雜區(例如,DRAM選擇電晶體886的源極區和汲極區)也可以形成在半導體層848中。在一些實施方式中,電容器888設置在DRAM選擇電晶體886下方。根據一些實施方式,每個電容器888包括兩個電極,其中的一個電極電連接到相應DRAM選擇電晶體886的一個節點。根據一些實施方式,每個DRAM選擇電晶體886的另一節點耦接到DRAM的位元線880。每個電容器888的另一電極可以耦接到公共極板882,例如公共地。應當理解,DRAM單元890的結構和配置不限於圖8C中的示例,並且可包括任何合適的結構和配置。例如,電容器888可以是平面電容器、堆疊電容器、多鰭電容器、圓柱電容器、溝槽電容器、或基底-平板電容器。The second semiconductor structure 804 of the 3D storage device 899 may further include a device layer 881 above the interconnection layer 830 and the bonding layer 826 . In some embodiments, device layer 881 includes an array of DRAM cells 890 over interconnect layer 830 and bonding layer 826 . In some embodiments, each DRAM cell 890 includes a DRAM select transistor 886 and a capacitor 888 . DRAM cell 890 may be a 1T1C cell consisting of a transistor and a capacitor. It should be understood that DRAM cells 890 may have any suitable configuration, such as 2T1C cells, 3T1C cells, and the like. In some embodiments, DRAM select transistor 886 is formed “on” semiconductor layer 848 , wherein all or part of DRAM select transistor 886 is formed in semiconductor layer 848 (eg, below the top surface of semiconductor layer 848 ) and/or Or directly formed on the semiconductor layer 848 . Isolation regions (eg, STI) and doped regions (eg, source and drain regions of DRAM select transistor 886 ) may also be formed in semiconductor layer 848 . In some implementations, capacitor 888 is disposed below DRAM select transistor 886 . According to some embodiments, each capacitor 888 includes two electrodes, one of which is electrically connected to a node of a corresponding DRAM select transistor 886 . According to some embodiments, the other node of each DRAM select transistor 886 is coupled to the bit line 880 of the DRAM. The other electrode of each capacitor 888 may be coupled to a common plate 882, such as a common ground. It should be understood that the structure and configuration of DRAM cell 890 is not limited to the example in FIG. 8C and may include any suitable structure and configuration. For example, capacitor 888 may be a planar capacitor, a stack capacitor, a multi-fin capacitor, a cylinder capacitor, a trench capacitor, or a substrate-plate capacitor.
在一些實施方式中,第二半導體結構804還包括設置在器件層881上方的半導體層848。半導體層848可在DRAM單元陣列890上方並與其接觸。半導體層848可以是其上形成DRAM選擇電晶體886的減薄基底。在一些實施方式中,半導體層848包括單晶矽。在一些實施方式中,半導體層848可以包括多晶矽、非晶矽、SiGe、GaAs、Ge或任何其他合適的材料。半導體層848還可以包括隔離區和摻雜區(例如,作為DRAM選擇電晶體886的源極和汲極)。In some embodiments, the second semiconductor structure 804 further includes a semiconductor layer 848 disposed over the device layer 881 . The semiconductor layer 848 may be over and in contact with the DRAM cell array 890 . Semiconductor layer 848 may be a thinned substrate upon which DRAM select transistor 886 is formed. In some embodiments, semiconductor layer 848 includes monocrystalline silicon. In some embodiments, the semiconductor layer 848 may include polysilicon, amorphous silicon, SiGe, GaAs, Ge, or any other suitable material. The semiconductor layer 848 may also include isolation regions and doped regions (eg, as the source and drain of the DRAM select transistor 886 ).
如上所述,不同於邏輯裝置,儲存裝置(例如,3D NAND快閃記憶體)需要將寬範圍的電壓提供到不同記憶體外圍電路,包括不適合於邏輯裝置(例如,微處理器)(尤其是使用先進CMOS技術節點(例如,小於22 nm))但需要用於記憶體操作的較高電壓(例如,3.3V或以上)。例如,圖9示出了根據本揭露內容的一些方面的提供有各種電壓的外圍電路的方塊圖。在一些實施方式中,儲存裝置(例如,儲存裝置200)包括低低電壓(LLV)源901、低電壓(LV)源903和高電壓(HV)源905,其中的每一個被配置為提供處於相應電平(Vdd1、Vdd2或Vdd3,其中Vdd1<Vdd2<Vdd3)的電壓。每個電壓源901、903或905可以從外部電源(例如,電池)接收處於適當電平的電壓輸入。每個電壓源901、903或905還可包括電壓轉換器和/或電壓調節器以將外部電壓輸入轉換為相應電平(Vdd1、Vdd2或Vdd3)且維持在相應電平(Vdd1、Vdd2或Vdd3)下的電壓並透過對應電源軌輸出該電壓。在一些實施方式中,儲存裝置200的電壓發生器310是電壓源901、903和905的部分。As mentioned above, unlike logic devices, storage devices (e.g., 3D NAND flash memory) need to supply a wide range of voltages to different memory peripheral circuits, including those not suitable for logic devices (e.g., microprocessors) (especially Use advanced CMOS technology nodes (eg, less than 22 nm) but require higher voltages for memory operation (eg, 3.3V or above). For example, FIG. 9 shows a block diagram of peripheral circuits supplied with various voltages according to some aspects of the present disclosure. In some embodiments, a storage device (eg, storage device 200 ) includes a low-low voltage (LLV) source 901 , a low-voltage (LV) source 903 , and a high-voltage (HV) source 905 , each of which is configured to provide The voltage of the corresponding level (Vdd1, Vdd2 or Vdd3, where Vdd1<Vdd2<Vdd3). Each voltage source 901, 903 or 905 may receive a voltage input at an appropriate level from an external power source (eg, a battery). Each voltage source 901, 903 or 905 may also include a voltage converter and/or a voltage regulator to convert the external voltage input to the corresponding level (Vdd1, Vdd2 or Vdd3) and maintain it at the corresponding level (Vdd1, Vdd2 or Vdd3 ) and outputs that voltage through the corresponding supply rail. In some embodiments, the voltage generator 310 of the storage device 200 is part of the voltage sources 901 , 903 and 905 .
在一些實施方式中,LLV源901被配置為提供0.9V與2.0V之間的電壓(例如,0.9V、0.95V、1V、1.05V、1.1V、1.15V、1.2V、1.25V、1.3V、1.35V、1.4V、1.45V、1.5V、1.55V、1.6V、1.65V、1.7V、1.75V、1.8V、1.85V、1.9V、1.95V、2.0V、由這些值中的任何一個值為下限所界定的任何範圍、或者在由這些值中的任何兩個值所限定的任何範圍中)。在一個示例中,電壓為1.2V。在一些實施方式中,LV源903被配置為提供2V和3.3V之間的電壓(例如,2V、2.1V、2.2V、2.3V、2.4V、2.5V、2.6V、2.7V、2.8V、2.9V、3V、3.1V、3.2V、3.3V、由這些值中的任何一個值為下限所界定的任何範圍、或者在由這些值中的任何兩個值所限定的任何範圍中)。在一個示例中,電壓為3.3V。在一些實施方式中,HV源905被配置為提供大於3.3V的電壓。在一個示例中,電壓在5V與30V之間(例如,5V、6V、7V、8V、9V、10V、11V、12V、13V、14V、15V、16V、17V、18V、19V、20V、21V、22V、23V、24V、25V、26V、27V、28V、29V、30V、由這些值中的任何一個值為下限所界定的任何範圍、或者在由這些值中的任何兩個值所限定的任何範圍中)。應當理解,上面關於HV源905、LV源903和LLV源901描述的電壓範圍是出於說明性目的而非限制性的,並且HV源905、LV源903和LLV源901可以提供任何其他合適的電壓範圍。然而,至少由LV源903和HV源905提供的電壓電平(例如,2V及以上)可能不適合於使用先進CMOS技術節點(例如,小於22 nm)的邏輯裝置中的3D電晶體(例如,FinFET)。In some embodiments, the LLV source 901 is configured to provide a voltage between 0.9V and 2.0V (eg, 0.9V, 0.95V, 1V, 1.05V, 1.1V, 1.15V, 1.2V, 1.25V, 1.3V , 1.35V, 1.4V, 1.45V, 1.5V, 1.55V, 1.6V, 1.65V, 1.7V, 1.75V, 1.8V, 1.85V, 1.9V, 1.95V, 2.0V, by any of these values values in any range bounded by the lower limit, or in any range bounded by any two of these values). In one example, the voltage is 1.2V. In some embodiments, the LV source 903 is configured to provide a voltage between 2V and 3.3V (eg, 2V, 2.1V, 2.2V, 2.3V, 2.4V, 2.5V, 2.6V, 2.7V, 2.8V, 2.9V, 3V, 3.1V, 3.2V, 3.3V, any range bounded by the lower limit of any one of these values, or in any range bounded by any two of these values). In one example, the voltage is 3.3V. In some implementations, the HV source 905 is configured to provide a voltage greater than 3.3V. In one example, the voltage is between 5V and 30V (eg, 5V, 6V, 7V, 8V, 9V, 10V, 11V, 12V, 13V, 14V, 15V, 16V, 17V, 18V, 19V, 20V, 21V, 22V , 23V, 24V, 25V, 26V, 27V, 28V, 29V, 30V, any range bounded by the lower limit of any one of these values, or in any range bounded by any two of these values ). It should be understood that the voltage ranges described above with respect to HV source 905, LV source 903, and LLV source 901 are for illustrative purposes and not limiting, and that HV source 905, LV source 903, and LLV source 901 may provide any other suitable voltage range. However, the voltage levels provided by at least LV source 903 and HV source 905 (eg, 2V and above) may not be suitable for 3D transistors (eg, FinFET ).
基於它們合適的電壓電平(Vdd1、Vdd2或Vdd3),記憶體外圍電路(例如,外圍電路202)可以被分類為LLV電路902、LV電路904和HV電路906,它們可以分別耦接到LLV源901、LV源903和HV源905。在一些實施方式中,HV電路906包括一個或多個驅動器,所述一個或多個驅動器透過字元線、位元線、SSG線、DSG線、源極線等耦接到儲存單元陣列(例如,儲存單元陣列201),且被配置為在執行記憶體操作(例如,讀取、編程或擦除)時透過將處於合適電平的電壓施加到字元線、位元線、SSG線、DSG線、源極線等來驅動儲存單元陣列。在一個示例中,HV電路906可包括在編程操作期間將在例如5V與30V範圍內的編程電壓(Vprog)或通過電壓(Vpass)施加到字元線的字元線驅動器(例如,行解碼器/字元線驅動器308)。在另一示例中,HV電路906可包括在擦除操作期間將在例如5V與30V範圍內的擦除電壓(Veras)施加到位元線的位元線驅動器(例如,列解碼器/位元線驅動器306)。在一些實施方式中,LV電路904包括被配置為緩衝從儲存單元陣列讀取的數據或編程到儲存單元陣列的數據的頁緩衝器(例如,頁緩衝器304)。例如,可以由LV源903向頁緩衝器提供例如3.3V的電壓。在一些實施方式中,LLV電路902包括被配置為將儲存單元陣列與記憶體控制器介面連接的I/O電路(例如,介面316和/或數據總線318)。例如,可以由LLV源901向I/O電路提供例如1.2V的電壓。Based on their appropriate voltage levels (Vdd1, Vdd2, or Vdd3), memory peripheral circuits (eg, peripheral circuit 202) can be categorized as LLV circuits 902, LV circuits 904, and HV circuits 906, which can be coupled to LLV sources, respectively. 901 , LV source 903 and HV source 905 . In some implementations, the HV circuit 906 includes one or more drivers coupled to the memory cell array (eg, , memory cell array 201), and is configured to perform a memory operation (eg, read, program, or erase) by applying a voltage at an appropriate level to a word line, a bit line, a SSG line, a DSG lines, source lines, etc. to drive the memory cell array. In one example, the HV circuit 906 may include a word line driver (eg, a row decoder) that applies a program voltage (Vprog) or a pass voltage (Vpass) in the range of, for example, 5V and 30V to the word lines during a program operation. / word line driver 308). In another example, the HV circuit 906 may include a bit line driver (e.g., column decoder/bit line driver 306). In some embodiments, LV circuit 904 includes a page buffer (eg, page buffer 304 ) configured to buffer data read from or programmed to the array of memory cells. For example, a voltage of eg 3.3V may be supplied from the LV source 903 to the page buffer. In some implementations, LLV circuitry 902 includes I/O circuitry (eg, interface 316 and/or data bus 318 ) configured to interface the array of storage cells with a memory controller. For example, a voltage of eg 1.2V may be provided by LLV source 901 to the I/O circuit.
LLV電路902、LV電路904或HV電路906中的至少一個可以包括本文公開的3D電晶體(例如,3D電晶體500)。在一些實施方式中,LLV電路902、LV電路904和HV電路906中的每一個包括3D電晶體。在一些實施方式中,LLV電路902和LV電路904中的每一個包括3D電晶體,而HV電路906包括本文公開的平面電路(例如,平面電晶體400)。此外,LLV電路902、LV電路904或HV電路906可以以本文公開的任何合適的組合用3D電晶體和/或平面電晶體實現為圖8A-8C中的外圍電路812、814、835和837。At least one of LLV circuit 902 , LV circuit 904 , or HV circuit 906 may include a 3D transistor (eg, 3D transistor 500 ) disclosed herein. In some implementations, each of LLV circuit 902 , LV circuit 904 , and HV circuit 906 includes 3D transistors. In some implementations, each of LLV circuit 902 and LV circuit 904 includes a 3D transistor, while HV circuit 906 includes a planar circuit disclosed herein (eg, planar transistor 400 ). Additionally, LLV circuit 902, LV circuit 904, or HV circuit 906 may be implemented with 3D transistors and/or planar transistors in any suitable combination disclosed herein as peripheral circuits 812, 814, 835, and 837 in FIGS. 8A-8C.
與本揭露內容的範圍一致,下面詳細描述了分別適用於LLV電路902、LV電路904和HV電路906的3D電晶體的各種設計。根據本揭露內容的一些方面,如圖10所示,儲存裝置200的LLV電路902可以由包括例如介面316和數據總線318的I/O電路來表示。I/O電路可被配置為將儲存單元陣列201與記憶體控制器介面連接。在一些實施方式中,由LLV源901向I/O電路提供0.9V和2.0V之間的電壓,例如1.2V。Consistent with the scope of the present disclosure, various designs of 3D transistors suitable for LLV circuit 902, LV circuit 904, and HV circuit 906, respectively, are described in detail below. According to some aspects of the present disclosure, as shown in FIG. 10 , the LLV circuit 902 of the storage device 200 may be represented by an I/O circuit including, for example, the interface 316 and the data bus 318 . The I/O circuitry may be configured to interface the memory cell array 201 with a memory controller. In some implementations, the I/O circuit is supplied by the LLV source 901 with a voltage between 0.9V and 2.0V, for example 1.2V.
圖11A和11B分別示出了根據本揭露內容的一些方面的圖10的I/O電路中的3D電晶體1100的透視圖和側視圖。3D電晶體1100可以是圖5、6A和6B中的3D電晶體500的一個示例,並且被設計為滿足I/O電路或任何其他合適的LLV電路902的特定要求,如下面詳細描述的。圖11B示出了圖11A中的3D電晶體1100在平面B-B中的截面的側視圖。如圖11A和11B所示,3D電晶體1100可以包括在基底1102上方的3D半導體主體1104,以及與3D半導體主體1104的多個側面(例如,頂表面和兩個側表面)接觸的閘極結構1108。應當理解,3D電晶體1100可以是任何合適的多閘極電晶體,例如,如圖7A-7I所示。在一些實施方式中,閘極結構1108包括與3D半導體主體1104的多個側面接觸的閘極介電質1107和與閘極介電質1107接觸的閘電極1109。如圖11A和11B所示,閘極結構1108的頂表面(例如,閘電極1109)是彎曲的。11A and 11B illustrate perspective and side views, respectively, of 3D transistor 1100 in the I/O circuit of FIG. 10, in accordance with aspects of the present disclosure. 3D transistor 1100 may be an example of 3D transistor 500 in FIGS. 5, 6A and 6B, and is designed to meet the specific requirements of I/O circuitry or any other suitable LLV circuitry 902, as described in detail below. FIG. 11B shows a side view of a cross-section of the 3D transistor 1100 in FIG. 11A in plane B-B. As shown in FIGS. 11A and 11B , a 3D transistor 1100 may include a 3D semiconductor body 1104 above a substrate 1102, and a gate structure in contact with multiple sides (eg, a top surface and two side surfaces) of the 3D semiconductor body 1104 1108. It should be understood that the 3D transistor 1100 may be any suitable multi-gate transistor, eg, as shown in FIGS. 7A-7I . In some embodiments, the gate structure 1108 includes a gate dielectric 1107 in contact with sides of the 3D semiconductor body 1104 and a gate electrode 1109 in contact with the gate dielectric 1107 . As shown in FIGS. 11A and 11B , the top surface of the gate structure 1108 (eg, gate electrode 1109 ) is curved.
如圖11A和11B所示,3D電晶體1100還可以包括在3D半導體主體1104中並且在平面圖中由閘極結構1108分離的一對源極和汲極1106。如圖11B所示,溝槽隔離1103(例如STI)可以形成在基底1102中,使得閘極結構1108可以形成在溝槽隔離1103上。在一些實施方式中,溝槽隔離1103還橫向地形成在相鄰的3D電晶體1100之間以減少洩漏電流。應當理解,為了易於說明,在圖11B中示出了溝槽隔離1103,但在圖11A中沒有示出。還應當理解,3D電晶體1100可以包括圖11A和11B中未示出的附加部件,例如阱和間隔物。As shown in FIGS. 11A and 11B , the 3D transistor 1100 may also include a pair of source and drain electrodes 1106 in the 3D semiconductor body 1104 and separated by a gate structure 1108 in plan view. As shown in FIG. 11B , trench isolation 1103 (eg, STI) may be formed in substrate 1102 such that gate structure 1108 may be formed on trench isolation 1103 . In some embodiments, trench isolation 1103 is also formed laterally between adjacent 3D transistors 1100 to reduce leakage current. It should be understood that trench isolation 1103 is shown in FIG. 11B but not shown in FIG. 11A for ease of illustration. It should also be understood that 3D transistor 1100 may include additional components not shown in FIGS. 11A and 11B , such as wells and spacers.
對於用在儲存裝置200的I/O電路中的3D電晶體1100,開關速度是重要的特性。特別地,當儲存裝置200是鍵合晶片時,如3D儲存裝置800和801,其可透過在兩個鍵合半導體結構之間使用直接、短距離(例如,微米級)電連接而以降低的功率消耗實現高速I/O吞吐量,形成I/O電路的電晶體的開關速度可成為I/O電路的性能瓶頸。為了提高開關速度,如上所述,需要提高電晶體的導通狀態電流(I
on或I
dsat)。然而,同時,截止狀態洩漏電流(I
off)也不能增加,這是透過平面電晶體難以實現的。
For the 3D transistor 1100 used in the I/O circuit of the storage device 200, switching speed is an important characteristic. In particular, when the storage device 200 is a bonded wafer, such as the 3D storage devices 800 and 801, it can be achieved with reduced Power consumption enables high-speed I/O throughput, and the switching speed of the transistors that form the I/O circuit can become a performance bottleneck for the I/O circuit. In order to increase the switching speed, as mentioned above, the on-state current (I on or I dsat ) of the transistor needs to be increased. However, at the same time, the off-state leakage current (I off ) cannot be increased, which is difficult to achieve through planar transistors.
例如,圖12A和12B分別示出了平面電晶體1200的透視圖和側視圖。平面電晶體1200可以是圖4中的平面電晶體400的一個示例。平面電晶體1200包括在基底1202上,即在基底1202的頂表面上方並與其接觸的閘極結構1208。閘極結構1208包括在基底1202的頂表面上方並與其接觸的平面閘極介電質1207,以及在平面閘極介電質1207上的閘電極1209。平面電晶體1200還包括在基底1202中並且在平面圖中由閘極結構1208分離的一對源極和汲極1206。溝槽隔離1203(例如,STI)形成在基底1202中並且橫向地形成在相鄰的平面電晶體1200之間。應當理解,為了便於說明,圖12B中示出了溝槽隔離1203,但圖12A中未示出。由於與3D電晶體1100相比通道和閘極的數量較少,所以平面電晶體1200的通道控制和亞閾值擺幅可能較差。結果,根據發明人所進行的研究,在相同的尺寸和洩漏電流(截止狀態電流)下,3D電晶體1100的飽和汲極電流(導通狀態電流)可以比平面電晶體1200的飽和汲極電流高幾倍(例如,超過兩倍)。另一方面,為了保持與平面電晶體1200相同的開關速度和洩漏電流,可以減小3D電晶體1100的尺寸。此外,為了進一步改善I/O電路的電性能,在3D電晶體1100的閘極結構1108中可以使用HKMG,而具有較大尺寸的平面電晶體1200並未使用它。For example, Figures 12A and 12B show a perspective view and a side view, respectively, of a planar transistor 1200. Planar transistor 1200 may be an example of planar transistor 400 in FIG. 4 . The planar transistor 1200 includes a gate structure 1208 on a substrate 1202 , ie, above and in contact with a top surface of the substrate 1202 . The gate structure 1208 includes a planar gate dielectric 1207 over and in contact with the top surface of the substrate 1202 , and a gate electrode 1209 on the planar gate dielectric 1207 . The planar transistor 1200 also includes a pair of source and drain electrodes 1206 in the substrate 1202 and separated by a gate structure 1208 in plan view. Trench isolation 1203 (eg, STI) is formed in substrate 1202 and laterally between adjacent planar transistors 1200 . It should be understood that trench isolation 1203 is shown in FIG. 12B but not shown in FIG. 12A for ease of illustration. Due to the lower number of channels and gates compared to the 3D transistor 1100, the channel control and sub-threshold swing of the planar transistor 1200 may be poor. As a result, according to the research conducted by the inventors, under the same size and leakage current (off-state current), the saturated drain current (on-state current) of the 3D transistor 1100 can be higher than that of the planar transistor 1200 Several times (for example, more than twice). On the other hand, in order to maintain the same switching speed and leakage current as the planar transistor 1200, the size of the 3D transistor 1100 can be reduced. In addition, in order to further improve the electrical performance of the I/O circuit, HKMG can be used in the gate structure 1108 of the 3D transistor 1100 , while the planar transistor 1200 with a larger size does not use it.
返回參考圖11A和11B,在一些實施方式中,儲存裝置200的I/O電路中的3D電晶體1100的閘電極1109包括金屬,例如Cu。在一些實施方式中,3D電晶體1100的閘極介電質1107包括高k介電質,諸如二氧化鉿、二氧化鋯、二氧化鈦、或具有高於氮化矽的介電常數(例如,高於3.9)的任何其他介電質。即,HKMG可以用於在儲存裝置200的I/O電路中形成3D電晶體1100的閘極結構1108。應當理解,在一些示例中,閘極多晶矽和閘極氧化物也可用作閘極結構1108。Referring back to FIGS. 11A and 11B , in some embodiments, the gate electrode 1109 of the 3D transistor 1100 in the I/O circuit of the storage device 200 includes a metal, such as Cu. In some embodiments, the gate dielectric 1107 of the 3D transistor 1100 includes a high-k dielectric, such as hafnium dioxide, zirconium dioxide, titanium dioxide, or has a higher dielectric constant than silicon nitride (eg, high any other dielectric in 3.9). That is, HKMG can be used to form the gate structure 1108 of the 3D transistor 1100 in the I/O circuit of the storage device 200 . It should be understood that gate polysilicon and gate oxide may also be used as gate structure 1108 in some examples.
在一些實施方式中,如圖11B中所示,閘極介電質1107的厚度T在1.8 nm和10 nm之間。例如,閘極介電質1107的厚度可以在2 nm和4 nm之間(例如,2 nm、2.1 nm、2.2 nm、2.3 nm、2.4 nm、2.5 nm、2.6 nm、2.7 nm、2.8 nm、2.9 nm、3 nm、3.1 nm、3.2 nm、3.3 nm、3.4 nm、3.5 nm、3.6 nm、3.7 nm、3.8 nm、3.9 nm、4 nm、由這些值中的任何一個值為下限所界定的任何範圍、或者在由這些值中的任何兩個值所限定的任何範圍中)。閘極介電質1107的厚度可大於(例如,一倍或多倍)在使用先進技術節點(例如,小於22 nm)的邏輯裝置中所使用的3D電晶體(例如,FinFET)的厚度,且可與施加到I/O電路的LLV電壓範圍相當,如上文詳細描述的,例如在0.9V與2.0V之間(例如,1.2V)。In some embodiments, as shown in FIG. 11B , the thickness T of the gate dielectric 1107 is between 1.8 nm and 10 nm. For example, the gate dielectric 1107 may have a thickness between 2 nm and 4 nm (e.g., 2 nm, 2.1 nm, 2.2 nm, 2.3 nm, 2.4 nm, 2.5 nm, 2.6 nm, 2.7 nm, 2.8 nm, 2.9 nm nm, 3 nm, 3.1 nm, 3.2 nm, 3.3 nm, 3.4 nm, 3.5 nm, 3.6 nm, 3.7 nm, 3.8 nm, 3.9 nm, 4 nm, any range bounded by a lower limit of any of these values , or in any range bounded by any two of these values). The thickness of the gate dielectric 1107 may be greater (eg, one or more times) than the thickness of 3D transistors (eg, FinFETs) used in logic devices using advanced technology nodes (eg, less than 22 nm), and Comparable to the LLV voltage range applied to the I/O circuitry, as detailed above, eg, between 0.9V and 2.0V (eg, 1.2V).
在一些實施方式中,如圖11B所示,3D半導體主體1104的寬度W在10 nm和180 nm之間。3D半導體主體1104的寬度可以指3D半導體主體1104的頂部處的寬度(例如,頂部臨界尺寸(CD)),如圖11B所示。例如,3D半導體主體1104的寬度可以在30 nm和100 nm之間(例如,30 nm、40 nm、50 nm、60 nm、70 nm、80 nm、90 nm、100 nm、由這些值中的任何一個值為下限所界定的任何範圍、或者在由這些值中的任何兩個值所限定的任何範圍中)。3D電晶體1100的寬度可以大於(例如,一倍或多倍)在使用先進技術節點(例如,小於22 nm)的邏輯裝置中使用的3D電晶體(例如,FinFET)的寬度。另一方面,3D電晶體1100的寬度可以小於在現有儲存裝置的I/O電路中使用的平面電晶體1200的寬度。應當理解,在一些示例中,3D半導體主體1104可以具有“啞鈴”形狀,其中由於3D半導體主體1104的不足以形成源極和汲極1106的相對小的寬度,3D半導體主體1104在形成源極和汲極1106的兩側處的寬度大於半導體主體1104在源極和汲極1106之間的寬度。In some embodiments, as shown in FIG. 11B , the width W of the 3D semiconductor body 1104 is between 10 nm and 180 nm. The width of the 3D semiconductor body 1104 may refer to the width at the top of the 3D semiconductor body 1104 (eg, the top critical dimension (CD)), as shown in FIG. 11B . For example, the width of the 3D semiconductor body 1104 can be between 30 nm and 100 nm (e.g., 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, by any of these values any range bounded by a lower limit of one value, or in any range bounded by any two of these values). The width of 3D transistor 1100 may be larger (eg, one or more times) than the width of 3D transistors (eg, FinFETs) used in logic devices using advanced technology nodes (eg, less than 22 nm). On the other hand, the width of the 3D transistor 1100 may be smaller than the width of the planar transistor 1200 used in the I/O circuit of the existing memory device. It should be appreciated that in some examples, the 3D semiconductor body 1104 may have a "dumbbell" shape, wherein due to the relatively small width of the 3D semiconductor body 1104 that is not sufficient to form the source and drain 1106, the 3D semiconductor body 1104 may have The width at both sides of the drain 1106 is greater than the width of the semiconductor body 1104 between the source and the drain 1106 .
在一些實施方式中,3D電晶體1100在源極和汲極1106之間的通道長度在30 nm和180 nm之間。3D電晶體1100的通道長度可以指源極和汲極1106之間的距離,即,與通道的頂表面接觸的閘極結構1104的尺寸。例如,3D電晶體1100的通道長度可以在50 nm和120 nm之間(例如,50 nm、60 nm、70 nm、80 nm、90 nm、100 nm、110 nm、120 nm、由這些值中的任何一個值為下限所界定的任何範圍、或者在由這些值中的任何兩個值所限定的任何範圍中)。3D電晶體1100的通道長度可以大於(例如,一倍或多倍)在使用先進技術節點(例如,小於22 nm)的邏輯裝置中使用的3D電晶體(例如,FinFET)的通道長度。另一方面,3D電晶體1100的通道長度可以小於在現有儲存裝置的I/O電路中使用的平面電晶體1200的通道長度。In some embodiments, the channel length of the 3D transistor 1100 between the source and the drain 1106 is between 30 nm and 180 nm. The channel length of the 3D transistor 1100 may refer to the distance between the source and drain 1106, ie, the dimension of the gate structure 1104 in contact with the top surface of the channel. For example, the channel length of 3D transistor 1100 may be between 50 nm and 120 nm (e.g., 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, from among these values any one value in any range bounded by a lower limit, or in any range bounded by any two of these values). The channel length of 3D transistor 1100 may be greater (eg, one or more times) than the channel length of 3D transistors (eg, FinFETs) used in logic devices using advanced technology nodes (eg, less than 22 nm). On the other hand, the channel length of the 3D transistor 1100 may be smaller than the channel length of the planar transistor 1200 used in the I/O circuit of the existing memory device.
在一些實施方式中,如圖11B所示,3D半導體主體1104的高度H在40 nm和300 nm之間。例如,3D半導體主體1104的高度可以在50 nm和100 nm之間(例如,50 nm、60 nm、70 nm、80 nm、90 nm、100 nm、由這些值中的任何一個值為下限所界定的任何範圍、或者在由這些值中的任何兩個值所限定的任何範圍中)。3D半導體主體1104的高度可以大於(例如,一倍或多倍)在使用先進技術節點(例如,小於22 nm)的邏輯裝置中使用的3D電晶體(例如,FinFET)的高度。In some embodiments, as shown in FIG. 11B , the height H of the 3D semiconductor body 1104 is between 40 nm and 300 nm. For example, the height of the 3D semiconductor body 1104 can be between 50 nm and 100 nm (e.g., 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, defined by any one of these values with a lower limit , or in any range bounded by any two of these values). The height of the 3D semiconductor body 1104 may be greater (eg, one or more times) than the height of 3D transistors (eg, FinFETs) used in logic devices using advanced technology nodes (eg, less than 22 nm).
在一些實施方式中,如圖11B所示,溝槽隔離1103的厚度t與3D半導體主體1104的高度相同。例如,溝槽隔離1103的厚度可以在50 nm和100 nm之間(例如,50 nm、60 nm、70 nm、80 nm、90 nm、100 nm、由這些值中的任何一個值為下限所界定的任何範圍、或者在由這些值中的任何兩個值所限定的任何範圍中)。溝槽隔離1103的厚度可以大於(例如,一倍或多倍)在使用先進技術節點(例如,小於22 nm)的邏輯裝置中使用的3D電晶體(例如,FinFET)的厚度。In some embodiments, as shown in FIG. 11B , the thickness t of the trench isolation 1103 is the same as the height of the 3D semiconductor body 1104 . For example, trench isolation 1103 may have a thickness between 50 nm and 100 nm (e.g., 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, defined by any one of these values with a lower limit , or within any range bounded by any two of these values). The thickness of trench isolation 1103 may be greater (eg, one or more times) than the thickness of 3D transistors (eg, FinFETs) used in logic devices using advanced technology nodes (eg, less than 22 nm).
根據本揭露內容的一些方面,如圖13所示,儲存裝置200的LV電路904可以由例如頁緩衝器304來表示。頁緩衝器304可被配置為緩衝從儲存單元陣列201讀取或編程到儲存單元陣列201的數據。在一些實施方式中,由LV源903向頁緩衝器304提供2V和3.3V之間的電壓,例如3.3V。根據本揭露內容的一些方面,如圖13中所示,儲存裝置200的HV電路906可由例如字元線驅動器308來表示。字元線驅動器308可以被配置為透過字元線驅動儲存單元陣列201。在一些實施方式中,由HV源905向字元線驅動器308提供大於3.3V(例如,在5V與30V之間)的電壓。According to some aspects of the present disclosure, as shown in FIG. 13 , the LV circuit 904 of the storage device 200 may be represented by, for example, a page buffer 304 . The page buffer 304 may be configured to buffer data read from or programmed into the memory cell array 201 . In some implementations, the page buffer 304 is supplied by the LV source 903 with a voltage between 2V and 3.3V, for example 3.3V. According to some aspects of the present disclosure, as shown in FIG. 13 , HV circuitry 906 of storage device 200 may be represented by, for example, word line driver 308 . The word line driver 308 may be configured to drive the memory cell array 201 through the word lines. In some implementations, the wordline driver 308 is provided by the HV source 905 with a voltage greater than 3.3V (eg, between 5V and 30V).
圖14示出了根據本揭露內容的一些方面的圖13中的字元線驅動器308和頁緩衝器304的示意性電路圖。在一些實施方式中,頁緩衝器304包括多個子頁緩衝器電路1402,各自經由相應位元線216耦接到一個3D NAND記憶體串208。即,儲存裝置200可包括分別耦接到3D NAND記憶體串208的位元線216,且頁緩衝器304可包括分別耦接到位元線216和3D NAND記憶體串208的子頁緩衝器電路1402。每個子頁緩衝器電路1402可以包括一個或多個鎖存器、開關、電源、節點(例如,數據節點和I/O節點)、電流鏡、驗證邏輯、感測電路等。在一些實施方式中,每個子頁緩衝器電路1402被配置為儲存從相應位元線216接收的感測數據,例如,對應於讀取數據的感測電流。每個子頁緩衝器電路1402可被配置為在讀取操作時還輸出所儲存的感測數據。每個子頁緩衝器電路1402還可以被配置為儲存編程數據,並且在編程操作時將所儲存的編程數據輸出到相應的位元線216。FIG. 14 shows a schematic circuit diagram of word line driver 308 and page buffer 304 in FIG. 13 in accordance with some aspects of the present disclosure. In some embodiments, the page buffer 304 includes a plurality of sub-page buffer circuits 1402 , each coupled to a 3D NAND memory string 208 via a corresponding bit line 216 . That is, the storage device 200 may include bit lines 216 respectively coupled to the 3D NAND memory strings 208, and the page buffer 304 may include subpage buffer circuits respectively coupled to the bit lines 216 and the 3D NAND memory strings 208 1402. Each subpage buffer circuit 1402 may include one or more latches, switches, power supplies, nodes (eg, data nodes and I/O nodes), current mirrors, verification logic, sensing circuits, and the like. In some implementations, each subpage buffer circuit 1402 is configured to store sense data received from a corresponding bit line 216, eg, a sense current corresponding to read data. Each sub-page buffer circuit 1402 may be configured to also output stored sense data upon a read operation. Each subpage buffer circuit 1402 may also be configured to store programming data and output the stored programming data to a corresponding bit line 216 during a programming operation.
如圖14所示,每個子頁緩衝器電路1402可以包括多個電晶體,例如下面參考圖20A和20B詳細公開的3D電晶體2000。3D電晶體2000可以是適合於在頁緩衝器304中形成子頁緩衝器電路1402的元件的3D電晶體500的一個示例。在一些實施方式中,頁緩衝器304中的3D電晶體2000耦接到位元線216。因此,頁緩衝器304中的3D電晶體2000可以透過位元線216耦接到儲存單元陣列201。As shown in FIG. 14, each subpage buffer circuit 1402 may include a plurality of transistors, such as the 3D transistor 2000 disclosed in detail below with reference to FIGS. An example of a 3D transistor 500 that is an element of the subpage buffer circuit 1402 . In some implementations, the 3D transistors 2000 in the page buffer 304 are coupled to the bit line 216 . Therefore, the 3D transistors 2000 in the page buffer 304 can be coupled to the memory cell array 201 through the bit line 216 .
在一些實施方式中,字元線驅動器308包括分別耦接到字元線218的多個串驅動器1404(又稱驅動元件)。字元線驅動器308還可以包括分別耦接到串驅動器1404的多條局部字元線1406(LWL)。每個串驅動器1404可包括耦接到解碼器(未示出)的閘極、耦接到相應局部字元線1406的源極/汲極,以及耦接到相應字元線218的另一源極/汲極。在一些記憶體操作中,解碼器可以例如透過施加大於串驅動器1404的閾值電壓的電壓訊號並向每條局部字元線1406施加電壓(例如,編程電壓、通過電壓或擦除電壓)來選擇某些串驅動器1404,使得電壓由每個所選擇的串驅動器1404施加到相應的字元線218。相反,解碼器還可以例如透過施加小於串驅動器1404的閾值電壓的電壓訊號來不選擇某些串驅動器1404,使得每個未被選擇的串驅動器1404在記憶體操作期間浮置相應的字元線218。In some implementations, the wordline driver 308 includes a plurality of string drivers 1404 (also referred to as drive elements) respectively coupled to the wordlines 218 . The word line driver 308 may also include a plurality of local word lines 1406 (LWL) respectively coupled to the string driver 1404 . Each string driver 1404 may include a gate coupled to a decoder (not shown), a source/drain coupled to a corresponding local wordline 1406, and another source coupled to a corresponding wordline 218 Pole/Drain Pole. In some memory operations, the decoder can select a certain memory, for example, by applying a voltage signal greater than the threshold voltage of the string driver 1404 and applying a voltage (e.g., a programming voltage, a pass voltage, or an erase voltage) to each local word line 1406. The string drivers 1404 are selected such that a voltage is applied by each selected string driver 1404 to the corresponding word line 218 . Conversely, the decoder can also deselect certain string drivers 1404, such as by applying a voltage signal less than the threshold voltage of the string drivers 1404, so that each unselected string driver 1404 floats the corresponding word line during memory operation. 218.
如圖14所示,每個串驅動器1404可以包括一個或多個電晶體,諸如下面參考圖21A和21B詳細公開的3D電晶體2100。3D電晶體2100可以是適合於形成字元線驅動器308中的串驅動器1404的元件的3D電晶體500的一個示例。在一些實施方式中,字元線驅動器308中的3D電晶體2100耦接到字元線218。因此,字元線驅動器308中的3D電晶體2100可以透過字元線218耦接到儲存單元陣列201。As shown in FIG. 14, each string driver 1404 may include one or more transistors, such as the 3D transistor 2100 disclosed in detail below with reference to FIGS. An example of a 3D transistor 500 of elements of the string driver 1404 . In some embodiments, the 3D transistor 2100 in the wordline driver 308 is coupled to the wordline 218 . Therefore, the 3D transistor 2100 in the word line driver 308 can be coupled to the memory cell array 201 through the word line 218 .
如圖15所示,在一些實施方式中,儲存單元陣列201被布置在多個平面1502中,每個平面具有多個塊204和其自己的頁緩衝器304。即,儲存裝置200可包括儲存單元206的多個平面1502及分別耦接到多個平面1502的多個頁緩衝器304。雖然圖15中未示出,但是應當理解,在一些示例中,每個平面1502可以具有其自己的頁緩衝器304、行解碼器/字元線驅動器308和列解碼器/位元線驅動器306的集合,使得控制邏輯312可以以同步方式或不同步方式並行地控制多個平面1502的操作,以增加儲存裝置200的操作速度。如以上關於圖2和14所描述的,應當理解,頁緩衝器304的數量和每個頁緩衝器304中的子頁緩衝器電路1402的數量可隨著由於平面1502、塊204和/或3D NAND記憶體串208(位元線216)的數量增加所導致的儲存單元的數量的增加而增加。因此,如果形成子頁緩衝器電路1402的每個電晶體的器件尺寸不減小,則頁緩衝器304的總面積就持續增加。類似地,串驅動器1404的數量可隨著由於平面1502、塊204和/或行220(字元線218)的數量增加所導致的儲存單元的數量的增加而增加。因此,如果形成串驅動器1404的每個電晶體的器件尺寸不減小,則字元線驅動器308的總面積就持續增加。As shown in FIG. 15 , in some embodiments, the storage cell array 201 is arranged in multiple planes 1502 , each plane having multiple blocks 204 and its own page buffer 304 . That is, the storage device 200 may include a plurality of planes 1502 of storage units 206 and a plurality of page buffers 304 respectively coupled to the plurality of planes 1502 . Although not shown in FIG. 15, it should be understood that in some examples, each plane 1502 may have its own page buffer 304, row decoder/word line driver 308, and column decoder/bit line driver 306. , so that the control logic 312 can control the operations of multiple planes 1502 in parallel in a synchronous or asynchronous manner, so as to increase the operation speed of the storage device 200 . As described above with respect to FIGS. 2 and 14, it should be understood that the number of page buffers 304 and the number of sub-page buffer circuits 1402 in each page buffer 304 may An increase in the number of storage cells results in an increase in the number of NAND memory strings 208 (bit lines 216 ). Therefore, if the device size of each transistor forming sub-page buffer circuit 1402 does not decrease, the total area of page buffer 304 continues to increase. Similarly, the number of string drivers 1404 may increase as the number of storage cells increases due to the increased number of planes 1502, blocks 204, and/or rows 220 (word lines 218). Thus, if the device size of each transistor forming string driver 1404 does not decrease, the overall area of word line driver 308 continues to increase.
此外,在外圍電路和儲存單元陣列在鍵合晶片中彼此垂直堆疊的3D儲存裝置100或101中,3D儲存裝置100或101的尺寸取決於第一半導體結構102或第二半導體結構104的較大尺寸。如圖16所示,隨著頁緩衝器304的面積不斷增加,具有頁緩衝器304、字元線驅動器308和其他外圍電路1600(例如,I/O電路等)的第二半導體結構104(例如,圖1A和1B所示)的尺寸可能最終變得大於具有儲存單元陣列的第一半導體結構102的尺寸,並且因此支配3D儲存裝置100或101的尺寸。結果,為了補償儲存裝置200(並且具體地,3D儲存裝置100或101)的尺寸增加,形成頁緩衝器304和字元線驅動器308的每個電晶體的器件尺寸需要在不犧牲太多性能(諸如電晶體電流洩漏)以及産品成品率和成本的情況下減小,如上所述。In addition, in the 3D storage device 100 or 101 in which the peripheral circuit and the storage cell array are vertically stacked on each other in a bonded wafer, the size of the 3D storage device 100 or 101 depends on the larger size of the first semiconductor structure 102 or the second semiconductor structure 104. size. As shown in FIG. 16 , as the area of the page buffer 304 continues to increase, the second semiconductor structure 104 (such as , shown in FIGS. 1A and 1B ) may eventually become larger than the size of the first semiconductor structure 102 with the storage cell array and thus dominate the size of the 3D storage device 100 or 101 . As a result, in order to compensate for the size increase of the storage device 200 (and in particular, the 3D storage device 100 or 101), the device size of each transistor forming the page buffer 304 and the word line driver 308 needs to be obtained without sacrificing too much performance ( conditions such as transistor current leakage) and product yield and cost are reduced, as described above.
如上所述,與用於形成現有記憶體外圍電路(例如子頁緩衝器電路和串驅動器)的平面電晶體相比,3D電晶體可以縮小器件尺寸,而不會由於較大的閘極控制面積、較高的導通狀態電流和較低的截止狀態電流而犧牲太多性能(例如洩漏電流)、以及製造複雜性和成本。例如,圖17示出了字元線驅動器或頁緩衝器中的平面電晶體的設計布局,並且作為比較,圖18示出了根據本揭露內容的一些方面的圖13中的字元線驅動器308或頁緩衝器304中的3D電晶體的設計布局。As mentioned above, compared with planar transistors used to form existing memory peripheral circuits such as sub-page buffer circuits and string drivers, 3D transistors can reduce device size without due to larger gate control area. , higher on-state current and lower off-state current at the expense of too much performance (such as leakage current), as well as manufacturing complexity and cost. For example, FIG. 17 shows a design layout of a word line driver or a planar transistor in a page buffer, and for comparison, FIG. 18 shows the word line driver 308 in FIG. 13 according to some aspects of the present disclosure. Or the design layout of the 3D transistors in the page buffer 304 .
如圖17和18所示,主動區的寬度W(即通道寬度)和/或閘極結構的長度(長度L1、L2)(即通道長度)可能透過從平面電晶體轉換到3D電晶體而受到影響。因此,可以減小字元線驅動器308或頁緩衝器304中的寬度方向上的間距(間距PW1、PW2)和/或長度方向上的間距(間距PL1、PL2)。在一些實施方式中,對於頁緩衝器304,使用平面電晶體來形成子頁緩衝器電路1402在不引入顯著的洩漏電流增加的情況下僅可實現180 nm的最小通道寬度W1。相反,根據發明人的研究,使用3D電晶體來形成子頁緩衝器電路1402,在不引入顯著的洩露電流增加的情況下,通道寬度W2可以減小到180 nm以下。例如,在相同的洩漏電流下,透過在形成子頁緩衝器電路1402時用3D電晶體代替平面電晶體,寬度方向上的間距可以減小5%到50%(例如25%),從而減小頁緩衝器304的總面積。此外,由於位元線216可以沿寬度方向排列,所以子頁緩衝器電路1402的沿寬度方向的間距的減小還可以容納更多的位元線216和3D NAND記憶體串208。As shown in Figures 17 and 18, the width W of the active region (i.e., the channel width) and/or the length of the gate structure (length L1, L2) (i.e., the channel length) may be affected by switching from planar to 3D transistors. Influence. Accordingly, the pitch in the width direction (pitch PW1 , PW2 ) and/or the pitch in the length direction (pitch PL1 , PL2 ) in the word line driver 308 or the page buffer 304 can be reduced. In some embodiments, the use of planar transistors to form sub-page buffer circuit 1402 for page buffer 304 can only achieve a minimum channel width W1 of 180 nm without introducing a significant increase in leakage current. On the contrary, according to the research of the inventors, using 3D transistors to form the sub-page buffer circuit 1402, the channel width W2 can be reduced below 180 nm without introducing a significant increase in leakage current. For example, under the same leakage current, by replacing the planar transistor with a 3D transistor when forming the subpage buffer circuit 1402, the pitch in the width direction can be reduced by 5% to 50% (for example, 25%), thereby reducing The total area of the page buffer 304. In addition, since the bit lines 216 can be arranged along the width direction, the reduction of the pitch of the subpage buffer circuit 1402 along the width direction can accommodate more bit lines 216 and 3D NAND memory strings 208 .
在一些實施方式中,對於字元線驅動器308,類似於頁緩衝器304,使用3D電晶體代替平面電晶體來形成串驅動器1404,可在不引入顯著洩漏電流增加的情況下減小通道寬度,例如從1900 nm減小到500 nm,從而減小字元線驅動器308的總面積。此外,也可透過在串驅動器1404中用3D電晶體代替平面電晶體來減小通道長度。因此,透過使用3D電晶體,可增加閘極結構至阱邊界之間的距離,從而擴大為HV電路906(例如字元線驅動器308)的重要特性的擊穿電壓(BV)的裕度。此外,由於字元線218可沿長度方向排列,所以串驅動器1404沿長度方向的間距的減小也可容納更多字元線218。串驅動器1404的尺寸減小可以允許更多的串驅動器1404面向鍵合的3D儲存裝置(例如,3D儲存裝置800和801)的階梯結構,並且因此減少金屬布線和金屬層。在一些實施方式中,對於字元線驅動器308或任何其他HV電路906,通道長度L2大於如圖18中所示的3D電晶體的通道寬度W2,其不同於形成字元線驅動器308的平面電晶體(例如,圖17中所示)。應當理解,對於字元線驅動器308或任何其他HV電路906,不同於圖18中所示的,3D電晶體的源極/汲極的寬度W2'可與3D電晶體的通道寬度(W2,即3D半導體主體/主動區在源極與汲極之間的寬度)相同,使得3D電晶體的3D半導體主體可在平面圖中不具有啞鈴形狀,而是沿通道長度方向具有均勻寬度。In some embodiments, for the word line driver 308, similar to the page buffer 304, 3D transistors are used instead of planar transistors to form the string driver 1404, which can reduce the channel width without introducing a significant increase in leakage current, For example, from 1900 nm to 500 nm, thereby reducing the total area of the word line driver 308 . In addition, the channel length can also be reduced by replacing planar transistors with 3D transistors in the string driver 1404 . Therefore, by using 3D transistors, the distance from the gate structure to the well boundary can be increased, thus increasing the breakdown voltage (BV) margin, which is an important characteristic of the HV circuit 906 (eg, the word line driver 308 ). In addition, since the word lines 218 can be arranged along the length direction, the reduction of the pitch of the string driver 1404 along the length direction can also accommodate more word lines 218 . The reduced size of string drivers 1404 may allow more string drivers 1404 to face the ladder structure of bonded 3D storage devices (eg, 3D storage devices 800 and 801 ), and thus reduce metal wiring and metal layers. In some embodiments, for the wordline driver 308 or any other HV circuit 906, the channel length L2 is greater than the channel width W2 of the 3D transistor as shown in FIG. crystals (for example, as shown in Figure 17). It should be understood that for the word line driver 308 or any other HV circuit 906, unlike that shown in FIG. The width of the 3D semiconductor body/active region between the source and the drain) is the same, so that the 3D semiconductor body of the 3D transistor may not have a dumbbell shape in plan view, but have a uniform width along the channel length.
例如,圖19示出了根據本揭露內容的一些方面的包括具有3D電晶體的串驅動器的3D儲存裝置1900的截面的側視圖。3D儲存裝置1900可以是3D儲存裝置800的一個示例。如圖19所示,3D儲存裝置1900可以包括在鍵合界面1915處以面對面的方式彼此鍵合的第一半導體結構1902和第二半導體結構1904。應當理解,在其他示例中,第一和第二半導體結構的相對位置可以切換。第一半導體結構1902可以包括堆疊結構,例如記憶體堆疊體1906,其包括交錯的字元線1905和介電質層1907。在一些實施方式中,交錯的字元線1905和介電質層1907的邊緣在記憶體堆疊體1906的一側或多側上限定一個或多個階梯結構1908。階梯結構1908可用於透過字元線觸點1912互連字元線1905。第一半導體結構1902還可以包括儲存單元陣列,諸如3D NAND記憶體串1910的陣列,每個串垂直延伸穿過記憶體堆疊體1906。For example, FIG. 19 illustrates a side view of a cross-section of a 3D storage device 1900 including a string driver with 3D transistors, according to some aspects of the present disclosure. The 3D storage device 1900 may be an example of the 3D storage device 800 . As shown in FIG. 19 , a 3D storage device 1900 may include a first semiconductor structure 1902 and a second semiconductor structure 1904 bonded to each other in a face-to-face manner at a bonding interface 1915 . It should be understood that in other examples, the relative positions of the first and second semiconductor structures may be switched. The first semiconductor structure 1902 may include a stack structure, such as a memory stack 1906 including interleaved word lines 1905 and a dielectric layer 1907 . In some embodiments, the edges of the interleaved word lines 1905 and dielectric layer 1907 define one or more stair structures 1908 on one or more sides of the memory stack 1906 . A ladder structure 1908 may be used to interconnect wordlines 1905 through wordline contacts 1912 . The first semiconductor structure 1902 may also include an array of memory cells, such as an array of 3D NAND memory strings 1910 , each string extending vertically through the memory stack 1906 .
第二半導體結構1904可以包括分別對應於字元線1905的多個串驅動器1914。每個串驅動器1914可包括用於本文中所公開的HV電路906的3D電晶體。如圖19所示,透過使用3D電晶體減小每個電晶體的尺寸,串驅動器1914可以跨越鍵合界面1915面對階梯結構1908,以允許每個字元線觸點1912電連接一對字元線1905和串驅動器1914,而不在平面圖中的階梯區域外部布線。即,所有串驅動器1914可以被直接布置在階梯結構1908的下方或上方。因此,透過在串驅動器1914中用3D電晶體代替平面電晶體,可以避免階梯區域外部的額外金屬布線和所産生的額外金屬層。應當理解,圖19中的字元線觸點1912僅用於說明性目的,且可包括3D儲存裝置1900的各種互連層和鍵合層(未示出)中的互連。如圖8A和8B所示,第一半導體結構1902和第二半導體結構1904還可以包括它們自己的互連層和鍵合層,使得串驅動器1914的3D電晶體可以透過第一和第二互連層以及第一和第二鍵合層分別耦接到字元線1905。The second semiconductor structure 1904 may include a plurality of string drivers 1914 respectively corresponding to the word lines 1905 . Each string driver 1914 may include 3D transistors for the HV circuit 906 disclosed herein. As shown in FIG. 19, by using 3D transistors to reduce the size of each transistor, the string driver 1914 can face the ladder structure 1908 across the bonding interface 1915 to allow each word line contact 1912 to electrically connect a word pair. The element line 1905 and the string driver 1914 are not wired outside the stepped area in plan view. That is, all string drivers 1914 may be arranged directly below or above the ladder structure 1908 . Therefore, by replacing the planar transistors with 3D transistors in the string driver 1914, extra metal wiring outside the step region and the resulting extra metal layers can be avoided. It should be understood that word line contacts 1912 in FIG. 19 are for illustrative purposes only and may include interconnects in various interconnect layers and bonding layers (not shown) of 3D storage device 1900 . As shown in FIGS. 8A and 8B , the first semiconductor structure 1902 and the second semiconductor structure 1904 may also include their own interconnect layers and bonding layers so that the 3D transistors of the string driver 1914 can see through the first and second interconnects. layer and the first and second bonding layers are respectively coupled to word lines 1905 .
圖20A和20B分別示出了根據本揭露內容的一些方面的圖13的頁緩衝器304中的3D電晶體2000的透視圖和側視圖。3D電晶體2000可以是圖5、6A和6B中的3D電晶體500的一個示例,並且被設計為滿足頁緩衝器304或任何其他合適的LV電路904的特定要求,如以下詳細描述的。圖20B示出了圖20A中的3D電晶體2000在平面B-B中的截面的側視圖。如圖20A和20B所示,3D電晶體2000可以包括在基底2002上方的3D半導體主體2004,以及與3D半導體主體2004的多個側面(例如,頂表面和兩個側表面)接觸的閘極結構2008。應當理解,3D電晶體2000可以是任何合適的多閘極電晶體,例如,如圖7A-7I所示。在一些實施方式中,閘極結構2008包括與3D半導體主體2004的多個側面接觸的閘極介電質2007以及與閘極介電質2007接觸的閘電極2009。如圖20A和20B所示,閘極結構2008的頂表面(例如,閘電極2009)是彎曲的。20A and 20B illustrate perspective and side views, respectively, of 3D transistor 2000 in page buffer 304 of FIG. 13 in accordance with some aspects of the present disclosure. 3D transistor 2000 may be an example of 3D transistor 500 in FIGS. 5, 6A and 6B, and is designed to meet the specific requirements of page buffer 304 or any other suitable LV circuit 904, as described in detail below. FIG. 20B shows a side view of a cross-section of the 3D transistor 2000 in FIG. 20A in plane B-B. As shown in FIGS. 20A and 20B , a 3D transistor 2000 may include a 3D semiconductor body 2004 above a substrate 2002, and a gate structure in contact with multiple sides (eg, a top surface and two side surfaces) of the 3D semiconductor body 2004 2008. It should be understood that the 3D transistor 2000 may be any suitable multi-gate transistor, eg, as shown in FIGS. 7A-7I . In some embodiments, the gate structure 2008 includes a gate dielectric 2007 in contact with sides of the 3D semiconductor body 2004 and a gate electrode 2009 in contact with the gate dielectric 2007 . As shown in FIGS. 20A and 20B , the top surface of the gate structure 2008 (eg, gate electrode 2009 ) is curved.
如圖20A和20B所示, 3D電晶體1100還可以包括3D半導體主體2004中且在平面圖中由閘極結構2008分隔開的一對源極和汲極2006。如圖20B所示,溝槽隔離2003(例如,STI)可以形成在基底2002中,使得閘極結構2008可以形成在溝槽隔離2003上。在一些實施方式中,溝槽隔離2003也橫向形成在相鄰3D電晶體2000之間以減小洩漏電流。應當理解,為了便於說明,圖20B中示出了溝槽隔離2003,但圖20A中未示出。還應當理解,3D電晶體2000可以包括圖20A和20B中未示出的附加部件,例如阱和間隔物。As shown in FIGS. 20A and 20B , the 3D transistor 1100 may also include a pair of source and drain electrodes 2006 in the 3D semiconductor body 2004 and separated by a gate structure 2008 in plan view. As shown in FIG. 20B , trench isolation 2003 (eg, STI) may be formed in substrate 2002 such that gate structure 2008 may be formed on trench isolation 2003 . In some embodiments, trench isolation 2003 is also formed laterally between adjacent 3D transistors 2000 to reduce leakage current. It should be understood that trench isolation 2003 is shown in FIG. 20B but not shown in FIG. 20A for ease of illustration. It should also be understood that 3D transistor 2000 may include additional components not shown in FIGS. 20A and 20B , such as wells and spacers.
如上所述,對於在儲存裝置200的頁緩衝器304中使用的3D電晶體2000,器件尺寸是重要的特性。另一方面,也不能增加截止狀態洩漏電流(I
off)以減少電流洩漏,這透過平面電晶體是難以實現的。此外,由於LV電路904在例如2V和3.3V之間(例如3V)的電壓下工作,因此3D電晶體2000的尺寸減小不能依賴於電壓降低,而這是透過在使用先進CMOS技術節點(例如,低於22 nm)的邏輯裝置中使用的3D電晶體難以實現的。應當理解,頁緩衝器304可以包括HV電路906和LV電路904。在一個示例中,頁緩衝器304的LV電路904可以包括3D電晶體2000,而頁緩衝器304的HV電路906可以包括平面電晶體(例如,平面電晶體400)。在另一個示例中,頁緩衝器304中的LV電路904中的一個可以包括具有類似於圖11A和11B中的結構的3D電晶體。頁緩衝器中的HV電路906中的一個包括具有類似於圖21A和21B的結構的3D電晶體。頁緩衝器中的兩個3D電晶體具有不同的結構和不同的尺寸。HV電路906中的3D電晶體的尺寸大於LV電路904中的3D電晶體的尺寸。3D電晶體的尺寸包括3D電晶體的通道長度、3D電晶體的3D半導體主體的高度、3D電晶體的3D半導體主體的寬度、或3D電晶體的面積中的至少一個。在一些實施方式中,在外圍電路中,頁緩衝器和其他電路都包括3D電晶體,頁緩衝器中的3D電晶體包括單個鰭狀物,而其他外圍電路中的3D電晶體包括多於一個鰭狀物。
As mentioned above, for the 3D transistor 2000 used in the page buffer 304 of the storage device 200, the device size is an important characteristic. On the other hand, the off-state leakage current (I off ) cannot be increased to reduce current leakage, which is difficult to achieve with planar transistors. Furthermore, since the LV circuit 904 operates at a voltage between, for example, 2V and 3.3V (eg, 3V), the size reduction of the 3D transistor 2000 cannot rely on voltage reduction, which is achieved by using advanced CMOS technology nodes (eg, , below 22 nm) is difficult to achieve with 3D transistors used in logic devices. It should be appreciated that page buffer 304 may include HV circuitry 906 and LV circuitry 904 . In one example, LV circuit 904 of page buffer 304 may include 3D transistor 2000 , while HV circuit 906 of page buffer 304 may include planar transistor (eg, planar transistor 400 ). In another example, one of the LV circuits 904 in the page buffer 304 may include a 3D transistor having a structure similar to that in FIGS. 11A and 11B . One of the HV circuits 906 in the page buffer includes a 3D transistor having a structure similar to that of FIGS. 21A and 21B . The two 3D transistors in the page buffer have different structures and different sizes. The size of the 3D transistors in the HV circuit 906 is larger than the size of the 3D transistors in the LV circuit 904 . The dimensions of the 3D transistor include at least one of the channel length of the 3D transistor, the height of the 3D semiconductor body of the 3D transistor, the width of the 3D semiconductor body of the 3D transistor, or the area of the 3D transistor. In some embodiments, in peripheral circuits, both the page buffer and other circuits include 3D transistors, the 3D transistor in the page buffer includes a single fin, and the 3D transistor in other peripheral circuits includes more than one fins.
在一些實施方式中,如圖20B中所示,閘極介電質2007的厚度T在1.8 nm與10 nm之間。例如,閘極介電質2007的厚度可以在2 nm和8 nm之間(例如,2 nm、2.1 nm、2.2 nm、2.3 nm、2.4 nm、2.5 nm、2.6 nm、2.7 nm、2.8 nm、2.9 nm、3 nm、3.1 nm、3.2 nm、3.3 nm、3.4 nm、3.5 nm、3.6 nm、3.7 nm、3.8 nm、3.9 nm、4 nm、4.5 nm、5 nm、5.5 nm、6 nm、6.5 nm、7 nm、7.5 nm、8 nm、由這些值中的任何一個值為下限所界定的任何範圍、或者在由這些值中的任何兩個值所限定的任何範圍中)。閘極介電質2007的厚度可以大於(例如,一倍或多倍)在使用先進技術節點(例如,小於22 nm)的邏輯裝置中使用的3D電晶體(例如,FinFET)的厚度,並且可以與施加到頁緩衝器304的LV電壓範圍相當,如上文詳細描述的,諸如在2V和3.3V之間(例如,3.3V)。此外,與LLV電路902中的3D電晶體1100(諸如I/O電路)相比,在一些實施方式中,3D電晶體2000的閘極介電質2007的厚度由於較高的工作電壓而較厚,例如在4 nm和8 nm之間,諸如在5 nm和8 nm之間。In some embodiments, as shown in Figure 20B, the thickness T of the gate dielectric 2007 is between 1.8 nm and 10 nm. For example, the gate dielectric 2007 may have a thickness between 2 nm and 8 nm (eg, 2 nm, 2.1 nm, 2.2 nm, 2.3 nm, 2.4 nm, 2.5 nm, 2.6 nm, 2.7 nm, 2.8 nm, 2.9 nm nm, 3 nm, 3.1 nm, 3.2 nm, 3.3 nm, 3.4 nm, 3.5 nm, 3.6 nm, 3.7 nm, 3.8 nm, 3.9 nm, 4 nm, 4.5 nm, 5 nm, 5.5 nm, 6 nm, 6.5 nm, 7 nm, 7.5 nm, 8 nm, any range bounded by the lower limit of any one of these values, or in any range bounded by any two of these values). The thickness of the gate dielectric 2007 may be greater (eg, one or more times) than the thickness of 3D transistors (eg, FinFETs) used in logic devices using advanced technology nodes (eg, less than 22 nm), and may Comparable to the LV voltage range applied to the page buffer 304 , as described in detail above, such as between 2V and 3.3V (eg, 3.3V). Additionally, compared to 3D transistors 1100 in LLV circuits 902 (such as I/O circuits), in some embodiments, the thickness of gate dielectric 2007 of 3D transistors 2000 is thicker due to the higher operating voltage , for example between 4 nm and 8 nm, such as between 5 nm and 8 nm.
在一些實施方式中,如圖20B所示,3D半導體主體2004的寬度W在10 nm和180 nm之間。3D半導體主體2004的寬度可以指3D半導體主體2004頂部(例如,頂部CD)處的寬度,如圖20B所示。例如,3D半導體主體1104的寬度可以在30 nm和100 nm之間(例如,30 nm、40 nm、50 nm、60 nm、70 nm、80 nm、90 nm、100 nm、由這些值中的任何一個值為下限所界定的任何範圍、或者在由這些值中的任何兩個值所限定的任何範圍中)。3D電晶體2000的寬度可以大於(例如,一倍或多倍)在使用先進技術節點(例如,小於22 nm)的邏輯裝置中使用的3D電晶體(例如,FinFET)的寬度。另一方面,3D電晶體2000的寬度可以小於現有儲存裝置的頁緩衝器中使用的平面電晶體的寬度,例如大於180 nm,如上所述。應當理解,在一些示例中,3D半導體主體2004可以具有“啞鈴”形狀,其中由於3D半導體主體2004的不足以形成源極和汲極2006的相對小的寬度,3D半導體主體2004在形成源極和汲極2006的兩側處的寬度大於3D半導體主體2004在源極和汲極2006之間的寬度。例如,如圖18所示,3D電晶體的源極/汲極的寬度W2'可以大於3D電晶體的通道寬度(W2,即,3D半導體主體/主動區在源極和汲極之間的寬度)。In some embodiments, as shown in Figure 20B, the width W of the 3D semiconductor body 2004 is between 10 nm and 180 nm. The width of the 3D semiconductor body 2004 may refer to the width at the top (eg, top CD) of the 3D semiconductor body 2004 , as shown in FIG. 20B . For example, the width of the 3D semiconductor body 1104 can be between 30 nm and 100 nm (e.g., 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, by any of these values any range bounded by a lower limit of one value, or in any range bounded by any two of these values). The width of 3D transistor 2000 may be larger (eg, one or more times) than the width of 3D transistors (eg, FinFETs) used in logic devices using advanced technology nodes (eg, less than 22 nm). On the other hand, the width of the 3D transistor 2000 may be smaller than the width of the planar transistor used in the page buffer of the existing storage device, for example larger than 180 nm, as mentioned above. It should be understood that in some examples, the 3D semiconductor body 2004 may have a "dumbbell" shape, wherein due to the relatively small width of the 3D semiconductor body 2004 which is insufficient to form the source and drain 2006 The width at both sides of the drain 2006 is greater than the width of the 3D semiconductor body 2004 between the source and the drain 2006 . For example, as shown in FIG. 18, the width W2' of the source/drain of the 3D transistor may be larger than the channel width of the 3D transistor (W2, that is, the width of the 3D semiconductor body/active region between the source and the drain ).
在一些實施方式中,3D電晶體2000在源極和汲極2006之間的通道長度在30 nm和180 nm之間。3D電晶體2000的通道長度可以指源極和汲極2006之間的距離,即,與通道的頂表面接觸的閘極結構2008的尺寸。例如,3D電晶體2000的通道長度可以在50 nm和120 nm之間(例如,50 nm、60 nm、70 nm、80 nm、90 nm、100 nm、110 nm、120 nm、由這些值中的任何一個值為下限所界定的任何範圍、或者在由這些值中的任何兩個值所限定的任何範圍中)。3D電晶體2000的通道長度可以大於(例如,一倍或多倍)在使用先進技術節點(例如,小於22 nm)的邏輯裝置中使用的3D電晶體(例如,FinFET)的通道長度。另一方面,3D電晶體2000的通道長度可以小於在現有儲存裝置的頁緩衝器中使用的平面電晶體的通道長度,例如大於180 nm。In some embodiments, the channel length of the 3D transistor 2000 between the source and the drain 2006 is between 30 nm and 180 nm. The channel length of the 3D transistor 2000 may refer to the distance between the source and drain 2006, ie, the dimension of the gate structure 2008 in contact with the top surface of the channel. For example, the channel length of the 3D transistor 2000 can be between 50 nm and 120 nm (e.g., 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, from among these values any one value in any range bounded by a lower limit, or in any range bounded by any two of these values). The channel length of 3D transistor 2000 may be greater (eg, one or more times) than the channel length of 3D transistors (eg, FinFETs) used in logic devices using advanced technology nodes (eg, less than 22 nm). On the other hand, the channel length of the 3D transistor 2000 may be smaller than the channel length of the planar transistor used in the page buffer of the existing storage device, eg greater than 180 nm.
在一些實施方式中,如圖20B所示,3D半導體主體2004的高度H在40 nm和300 nm之間。例如,3D半導體主體2004的高度可以在50 nm和100 nm之間(例如,50 nm、60 nm、70 nm、80 nm、90 nm、100 nm、由這些值中的任何一個值為下限所界定的任何範圍、或者在由這些值中的任何兩個值所限定的任何範圍中)。3D半導體主體2004的高度可以大於(例如,一倍或多倍)在使用先進技術節點(例如,小於22 nm)的邏輯裝置中使用的3D電晶體(例如,FinFET)的高度。In some embodiments, as shown in Figure 20B, the height H of the 3D semiconductor body 2004 is between 40 nm and 300 nm. For example, the height of the 3D semiconductor body 2004 may be between 50 nm and 100 nm (e.g., 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, defined by any one of these values with a lower limit , or in any range bounded by any two of these values). The height of the 3D semiconductor body 2004 may be greater (eg, one or more times) than the height of 3D transistors (eg, FinFETs) used in logic devices using advanced technology nodes (eg, less than 22 nm).
在一些實施方式中,如圖20B所示,溝槽隔離2003的厚度t與3D半導體主體2004的高度相同。例如,溝槽隔離2003的厚度可以在50 nm和100 nm之間(例如,50 nm、60 nm、70 nm、80 nm、90 nm、100 nm、由這些值中的任何一個值為下限所界定的任何範圍、或者在由這些值中的任何兩個值所限定的任何範圍中)。溝槽隔離2003的厚度可以大於(例如,一倍或多倍)在使用先進技術節點(例如,小於22 nm)的邏輯裝置中使用的3D電晶體(例如,FinFET)的厚度。In some embodiments, as shown in FIG. 20B , the thickness t of the trench isolation 2003 is the same as the height of the 3D semiconductor body 2004 . For example, trench isolation 2003 may have a thickness between 50 nm and 100 nm (eg, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, defined by any one of these values with a lower limit , or within any range bounded by any two of these values). The thickness of trench isolation 2003 may be greater (eg, one or more times) than the thickness of 3D transistors (eg, FinFETs) used in logic devices using advanced technology nodes (eg, less than 22 nm).
與使用先進技術節點(例如,小於22 nm)的邏輯裝置中使用的3D電晶體(例如,FinFET)相比,例如透過改變材料和/或簡化結構和製程,也可以改進3D電晶體2000的生産成品率和成本。在一些實施方式中,代替使用HKMG,儲存裝置200的頁緩衝器304中的3D電晶體2000的閘電極2009包括多晶矽,例如,摻雜有氮化物(N)的多晶矽。在一些實施方式中,3D電晶體2000的閘極介電質2007包括氧化矽。即,閘極多晶矽和閘極氧化物可以用作閘極結構2008,以降低製造複雜性和成本。在一些實施方式中,3D電晶體2000不包括在源極和汲極2006處的應力源和/或在3D半導體主體2004中不使用應變半導體材料,以降低製造複雜性和成本。Production of 3D Transistor 2000 may also be improved, for example, by changing materials and/or simplifying structure and process, compared to 3D Transistors (e.g., FinFETs) used in logic devices using advanced technology nodes (e.g., less than 22 nm) Yield and cost. In some embodiments, instead of using HKMG, the gate electrode 2009 of the 3D transistor 2000 in the page buffer 304 of the storage device 200 comprises polysilicon, eg, polysilicon doped with nitride (N). In some embodiments, the gate dielectric 2007 of the 3D transistor 2000 includes silicon oxide. That is, gate polysilicon and gate oxide can be used as the gate structure 2008 to reduce manufacturing complexity and cost. In some embodiments, the 3D transistor 2000 does not include stressors at the source and drain 2006 and/or does not use strained semiconductor material in the 3D semiconductor body 2004 to reduce manufacturing complexity and cost.
圖21A和21B分別示出了根據本揭露內容的一些方面的圖13的字元線驅動器308中的3D電晶體2100的透視圖和側視圖。3D電晶體2100可以是圖5、6A和6B中的3D電晶體500的一個示例,且被設計為滿足字元線驅動器308或任何其他合適的HV電路906的特定要求,如以下所詳細描述的。圖21B示出了圖21A中的3D電晶體2100在平面B-B中的截面的側視圖。如圖21A和21B所示,3D電晶體2100可以包括在基底2102上方的3D半導體主體2104以及與3D半導體主體2104的多個側面(例如,頂表面和兩個側表面)接觸的閘極結構2108。應當理解,3D電晶體2100可以是任何合適的多閘極電晶體,例如,如圖7A-7I所示。在一些實施方式中,閘極結構2108包括與3D半導體主體2104的多個側面接觸的閘極介電質2107和與閘極介電質2107接觸的閘電極2109。21A and 21B illustrate perspective and side views, respectively, of 3D transistor 2100 in word line driver 308 of FIG. 13 in accordance with aspects of the present disclosure. 3D transistor 2100 may be an example of 3D transistor 500 in FIGS. 5, 6A, and 6B, and is designed to meet the specific requirements of word line driver 308 or any other suitable HV circuit 906, as described in detail below. . FIG. 21B shows a side view of a cross-section of the 3D transistor 2100 in FIG. 21A in plane B-B. As shown in FIGS. 21A and 21B , a 3D transistor 2100 may include a 3D semiconductor body 2104 over a substrate 2102 and a gate structure 2108 in contact with multiple sides (eg, a top surface and two side surfaces) of the 3D semiconductor body 2104 . It should be understood that the 3D transistor 2100 may be any suitable multi-gate transistor, eg, as shown in FIGS. 7A-7I . In some embodiments, the gate structure 2108 includes a gate dielectric 2107 in contact with sides of the 3D semiconductor body 2104 and a gate electrode 2109 in contact with the gate dielectric 2107 .
如圖21A和21B所示,3D電晶體2100還可以包括在3D半導體主體2104中並在平面圖中由閘極結構2108分隔開的一對源極和汲極2106。由於施加到HV電路906中所使用的3D電晶體2100的相對高的電壓,3D電晶體2100可進一步包括3D半導體主體2104中的漂移區2110。源極和汲極2106可以與漂移區2110接觸。應當理解,在一些示例中,由於施加到3D電晶體1100和2000的較低電壓以及較少的擊穿問題,在LLV電路902和LV電路904中使用的3D電晶體1100和2000可以不包括漂移區2110。漂移區2110可以是3D半導體主體2104中的摻雜區,類似於源極和汲極2106,但是具有比源極和汲極2106小的摻雜濃度。即,源極和汲極2106可以是形成在3D電晶體2100中的輕摻雜區(即,漂移區2110)中的重摻雜區。在一些實施方式中,漂移區2110與源極和汲極2106摻雜有N型摻雜劑,使得源極和汲極2106成為輕N型摻雜區(N,即,漂移區2110)中的重N型摻雜區(N+)。為了維持施加到HV電路906中所使用的3D電晶體2100的相對高的電壓且避免擊穿,在一些實施方式中,源極/汲極2106與閘極結構2108之間的距離d1大於源極/汲極2106與3D半導體結構2104的邊緣之間的距離d2。例如,d1可以比d2大兩倍或更多倍。如圖21B所示,可以在基底2102中形成溝槽隔離2103(例如STI),使得可以在溝槽隔離2103上形成閘極結構2108。在一些實施方式中,溝槽隔離2103也橫向地形成在相鄰的3D電晶體2100之間以減少洩漏電流。應當理解,為了便於說明,圖21B中示出溝槽隔離2103,但圖21A中未示出。還應當理解,3D電晶體2100可以包括圖21A和21B中未示出的附加部件,諸如阱和間隔物。As shown in FIGS. 21A and 21B , the 3D transistor 2100 may also include a pair of source and drain electrodes 2106 in the 3D semiconductor body 2104 and separated by a gate structure 2108 in plan view. Due to the relatively high voltage applied to the 3D transistor 2100 used in the HV circuit 906 , the 3D transistor 2100 may further include a drift region 2110 in the 3D semiconductor body 2104 . The source and drain 2106 may be in contact with the drift region 2110 . It should be understood that, in some examples, the 3D transistors 1100 and 2000 used in the LLV circuit 902 and the LV circuit 904 may not include drift due to the lower voltage applied to the 3D transistors 1100 and 2000 and fewer breakdown issues. District 2110. The drift region 2110 may be a doped region in the 3D semiconductor body 2104 , similar to the source and drain 2106 , but with a lower doping concentration than the source and drain 2106 . That is, the source and drain 2106 may be heavily doped regions formed in the lightly doped region (ie, the drift region 2110 ) in the 3D transistor 2100 . In some embodiments, the drift region 2110 and the source and drain 2106 are doped with N-type dopants such that the source and drain 2106 become the N-type doped region (N, ie, the drift region 2110 ) Heavy N-type doped region (N+). In order to maintain a relatively high voltage applied to the 3D transistor 2100 used in the HV circuit 906 and avoid breakdown, in some embodiments the distance d1 between the source/drain 2106 and the gate structure 2108 is greater than the source The distance d2 between the drain 2106 and the edge of the 3D semiconductor structure 2104 . For example, d1 may be two or more times larger than d2. As shown in FIG. 21B , trench isolation 2103 (eg, STI) may be formed in substrate 2102 such that gate structure 2108 may be formed on trench isolation 2103 . In some embodiments, trench isolation 2103 is also formed laterally between adjacent 3D transistors 2100 to reduce leakage current. It should be understood that trench isolation 2103 is shown in FIG. 21B but not shown in FIG. 21A for ease of illustration. It should also be understood that 3D transistor 2100 may include additional components not shown in FIGS. 21A and 21B , such as wells and spacers.
如上所述,對於在儲存裝置200的字元線驅動器308中使用的3D電晶體2100,器件尺寸是重要的特性。另一方面,也不能增加截止狀態洩漏電流(I
off)以減少電流洩漏,而這是透過平面電晶體難以實現的。而且,由於HV電路906在例如大於3.3V(例如,在5V與30V之間)的電壓下操作,因此3D電晶體2100的尺寸減小不能依賴於電壓降低,這透過在使用先進CMOS技術節點(例如,小於22 nm)的邏輯裝置中使用的3D電晶體難以實現。
As mentioned above, for the 3D transistor 2100 used in the word line driver 308 of the storage device 200, the device size is an important characteristic. On the other hand, the off-state leakage current (I off ) cannot be increased to reduce current leakage, which is difficult to achieve with planar transistors. Also, since the HV circuit 906 operates at, for example, voltages greater than 3.3V (e.g., between 5V and 30V), the size reduction of the 3D transistor 2100 cannot rely on voltage reduction, which is achieved by using advanced CMOS technology nodes ( For example, 3D transistors used in logic devices smaller than 22 nm are difficult to realize.
在一些實施方式中,如圖21B中所示,閘極介電質2107的厚度T大於10 nm。例如,閘極介電質2107的厚度可以在20 nm和80 nm之間(例如,20 nm、21 nm、22 nm、23 nm、24 nm、25 nm、26 nm、27 nm、28 nm、29 nm、30 nm、31 nm、32 nm、33 nm、34 nm、35 nm、36 nm、37 nm、38 nm、39 nm、40 nm、45 nm、50 nm、55 nm、60 nm、65 nm、70 nm、75 nm、80 nm、由這些值中的任何一個值為下限所界定的任何範圍、或者在由這些值中的任何兩個值所限定的任何範圍中)。閘極介電質2107的厚度可顯著大於(例如,一個或多個數量級)在使用先進技術節點(例如,小於22 nm)的邏輯裝置中使用的3D電晶體(例如,FinFET)的厚度,且可與施加到字元線驅動器308的HV電壓範圍相當,如上文詳細描述的,例如大於3.3V(例如,在5V與30V之間)。此外,與LLV電路902中的3D電晶體1100(諸如I/O電路)以及LV電路904中的3D電晶體2000(諸如頁緩衝器304)相比,在一些實施方式中,3D電晶體2100的閘極介電質2107的厚度由於較高的工作電壓而較厚。In some embodiments, as shown in Figure 21B, the thickness T of the gate dielectric 2107 is greater than 10 nm. For example, the gate dielectric 2107 may have a thickness between 20 nm and 80 nm (e.g., 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm nm, 30 nm, 31 nm, 32 nm, 33 nm, 34 nm, 35 nm, 36 nm, 37 nm, 38 nm, 39 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, any range bounded by the lower limit of any one of these values, or in any range bounded by any two of these values). The thickness of the gate dielectric 2107 can be significantly greater (eg, by one or more orders of magnitude) than the thickness of 3D transistors (eg, FinFETs) used in logic devices using advanced technology nodes (eg, less than 22 nm), and Comparable to the range of HV voltages applied to the word line driver 308, as detailed above, eg, greater than 3.3V (eg, between 5V and 30V). Furthermore, compared to the 3D transistor 1100 in the LLV circuit 902 (such as the I/O circuit) and the 3D transistor 2000 in the LV circuit 904 (such as the page buffer 304), in some embodiments, the 3D transistor 2100 The gate dielectric 2107 is thicker due to the higher operating voltage.
在一些實施方式中,如圖21B所示,3D半導體主體2104的寬度W大於100 nm。3D半導體主體2104的寬度可以指3D半導體主體2104的頂部(例如,頂部CD)處的寬度,如圖21B所示。例如,3D半導體主體2104的寬度可以在300 nm和1000 nm之間(例如,300 nm、400 nm、500 nm、600 nm、700 nm、800 nm、900 nm、1000 nm、由這些值中的任何一個值為下限所界定的任何範圍、或者在由這些值中的任何兩個值所限定的任何範圍中)。3D電晶體2100的寬度可以顯著大於(例如,一個或多個數量級)在使用先進技術節點(例如,小於22 nm)的邏輯裝置中使用的3D電晶體(例如,FinFET)的寬度。另一方面,3D電晶體2100的寬度可以小於現有儲存裝置的字元線驅動器中使用的平面電晶體的寬度,例如1900 nm,如上所述。此外,與LLV電路902中的3D電晶體1100(諸如I/O電路)以及LV電路904中的3D電晶體2000(諸如頁緩衝器304)相比,在一些實施方式中,3D電晶體2100的3D半導體主體2104的寬度由於較高的工作電壓而較大。應當理解,在一些示例中,與3D半導體主體1104和2004在平面圖中具有啞鈴形狀的一些示例不同,由於3D半導體主體1104可以具有足以形成源極和汲極2106的相對大的寬度,因此3D半導體主體2104可以在平面圖中不具有啞鈴形狀,即具有均勻的寬度。In some embodiments, as shown in FIG. 21B , the width W of the 3D semiconductor body 2104 is greater than 100 nm. The width of the 3D semiconductor body 2104 may refer to the width at the top (eg, top CD) of the 3D semiconductor body 2104, as shown in FIG. 21B. For example, the width of the 3D semiconductor body 2104 can be between 300 nm and 1000 nm (e.g., 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, by any of these values any range bounded by a lower limit of one value, or in any range bounded by any two of these values). The width of 3D transistor 2100 may be significantly greater (eg, by one or more orders of magnitude) than the width of 3D transistors (eg, FinFETs) used in logic devices using advanced technology nodes (eg, less than 22 nm). On the other hand, the width of the 3D transistor 2100 can be smaller than the width of the planar transistor used in the word line driver of the existing memory device, for example, 1900 nm, as mentioned above. Furthermore, compared to 3D transistor 1100 in LLV circuit 902 (such as I/O circuit) and 3D transistor 2000 in LV circuit 904 (such as page buffer 304), in some embodiments, the 3D transistor 2100 The width of the 3D semiconductor body 2104 is larger due to the higher operating voltage. It should be appreciated that in some examples, unlike some examples in which 3D semiconductor bodies 1104 and 2004 have a dumbbell shape in plan view, since 3D semiconductor body 1104 may have a relatively large width sufficient to form source and drain 2106, the 3D semiconductor The body 2104 may not have a dumbbell shape in plan view, ie, have a uniform width.
在一些實施方式中,3D電晶體2100在源極與汲極2106之間的通道長度大於120 nm。3D電晶體2100的通道長度可以指源極和汲極2106之間的距離,即,與通道的頂表面接觸的閘極結構2108的尺寸。例如,3D電晶體2100的通道長度可以在500 nm和1200 nm之間(例如,500 nm、600 nm、700 nm、800 nm、900 nm、1000 nm、1100 nm、1200 nm、由這些值中的任何一個值為下限所界定的任何範圍、或者在由這些值中的任何兩個值所限定的任何範圍中)。3D電晶體2100的通道長度可以顯著大於(例如,一個或多個數量級)在使用先進技術節點(例如,小於22 nm)的邏輯裝置中使用的3D電晶體(例如,FinFET)的通道長度。另一方面,3D電晶體2100的通道長度可以小於在現有儲存裝置的字元線驅動器中使用的平面電晶體的通道長度,例如900 nm。此外,與LLV電路902中的3D電晶體1100(諸如I/O電路)以及LV電路904中的3D電晶體2000(諸如頁緩衝器304)相比,在一些實施方式中,3D電晶體2100的通道長度由於較高的工作電壓而較大。In some embodiments, the channel length of the 3D transistor 2100 between the source and the drain 2106 is greater than 120 nm. The channel length of the 3D transistor 2100 may refer to the distance between the source and drain 2106, ie, the dimension of the gate structure 2108 in contact with the top surface of the channel. For example, the channel length of the 3D transistor 2100 can be between 500 nm and 1200 nm (e.g., 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, 1100 nm, 1200 nm, from among these values any one value in any range bounded by a lower limit, or in any range bounded by any two of these values). The channel length of 3D transistor 2100 may be significantly greater (eg, by one or more orders of magnitude) than the channel length of 3D transistors (eg, FinFETs) used in logic devices using advanced technology nodes (eg, less than 22 nm). On the other hand, the channel length of the 3D transistor 2100 may be smaller than the channel length of the planar transistor used in the word line driver of the existing memory device, for example, 900 nm. Furthermore, compared to the 3D transistor 1100 in the LLV circuit 902 (such as the I/O circuit) and the 3D transistor 2000 in the LV circuit 904 (such as the page buffer 304), in some embodiments, the 3D transistor 2100 The channel length is larger due to the higher operating voltage.
在一些實施方式中,如圖21B所示,3D半導體主體2104的高度H大於50 nm。例如,3D半導體主體2104的高度可以在300 nm和500 nm之間(例如,300 nm、350 nm、400 nm、450 nm、500 nm、由這些值中的任何一個值為下限所界定的任何範圍、或者在由這些值中的任何兩個值所限定的任何範圍中)。3D半導體主體2104的高度可以顯著大於(例如,一個或多個數量級)在使用先進技術節點(例如,小於22 nm)的邏輯裝置中使用的3D電晶體(例如,FinFET)的高度。此外,與LLV電路902中的3D電晶體1100(諸如I/O電路)以及LV電路904中的3D電晶體2000(諸如頁緩衝器304)相比,在一些實施方式中,3D電晶體2100的3D半導體主體2104的高度由於較高的工作電壓而較大。In some embodiments, as shown in Figure 2 IB, the height H of the 3D semiconductor body 2104 is greater than 50 nm. For example, the height of the 3D semiconductor body 2104 can be between 300 nm and 500 nm (e.g., 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, any range bounded by a lower limit for any of these values , or in any range bounded by any two of these values). The height of the 3D semiconductor body 2104 may be significantly greater (eg, one or more orders of magnitude) than the height of 3D transistors (eg, FinFETs) used in logic devices using advanced technology nodes (eg, less than 22 nm). Furthermore, compared to the 3D transistor 1100 in the LLV circuit 902 (such as the I/O circuit) and the 3D transistor 2000 in the LV circuit 904 (such as the page buffer 304), in some embodiments, the 3D transistor 2100 The height of the 3D semiconductor body 2104 is greater due to the higher operating voltage.
在一些實施方式中,如圖21B所示,溝槽隔離2103的厚度t小於,例如不大於3D半導體主體2104高度的三分之一(1/3)。例如,溝槽隔離2103的厚度可以在100 nm和200 nm之間(例如,100 nm、110 nm、120 nm、130 nm、140 nm、150 nm、160 nm、170 nm、180 nm、190 nm、200 nm、由這些值中的任何一個值為下限所界定的任何範圍、或者在由這些值中的任何兩個值所限定的任何範圍中)。溝槽隔離2103的厚度可以大於(例如,一倍或多倍)在使用先進技術節點(例如,小於22 nm)的邏輯裝置中使用的3D電晶體(例如,FinFET)的厚度。此外,與LLV電路902中的3D電晶體1100(諸如I/O電路)以及LV電路904中的3D電晶體2000(諸如頁緩衝器304)相比,在一些實施方式中,3D電晶體2100的溝槽隔離2103的厚度由於較高的工作電壓而較小。In some embodiments, as shown in FIG. 21B , the thickness t of the trench isolation 2103 is less than, eg, not greater than one third (1/3) of the height of the 3D semiconductor body 2104 . For example, trench isolation 2103 may have a thickness between 100 nm and 200 nm (eg, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, 200 nm, any range bounded by the lower limit of either of these values, or in any range bounded by any two of these values). The thickness of trench isolation 2103 may be greater (eg, one or more times) than the thickness of 3D transistors (eg, FinFETs) used in logic devices using advanced technology nodes (eg, less than 22 nm). Furthermore, compared to 3D transistor 1100 in LLV circuit 902 (such as I/O circuit) and 3D transistor 2000 in LV circuit 904 (such as page buffer 304), in some embodiments, the 3D transistor 2100 The thickness of the trench isolation 2103 is smaller due to the higher operating voltage.
與使用先進技術節點(例如,小於22 nm)的邏輯裝置中使用的3D電晶體(例如,FinFET)相比,3D電晶體2100的産品成品率和成本也可以例如透過改變材料和/或簡化結構和製程而得到改善。在一些實施方式中,代替使用HKMG,儲存裝置200的字元線驅動器308中的3D電晶體2100的閘電極2109包括多晶矽,例如,摻雜有P型摻雜劑或N型摻雜劑的多晶矽,並且3D電晶體2100的閘極介電質2107包括摻雜有氮(N2)的氧化矽。在一些實施方式中,3D電晶體2100的閘極介電質2107包括氧化矽。即,閘極多晶矽和閘極氧化物可以用作閘極結構2108以降低製造複雜性和成本。在一些實施方式中,3D電晶體2100在源極和汲極2106處不包括應力源和/或在3D半導體主體2104中不使用應變半導體材料,以降低製造複雜性和成本。Product yield and cost of the 3D transistor 2100 can also be improved, for example, by changing materials and/or simplifying the structure compared to 3D transistors (e.g., FinFETs) used in logic devices using advanced technology nodes (e.g., less than 22 nm). and process improvements. In some embodiments, instead of using HKMG, the gate electrode 2109 of the 3D transistor 2100 in the word line driver 308 of the storage device 200 comprises polysilicon, for example, polysilicon doped with P-type dopants or N-type dopants , and the gate dielectric 2107 of the 3D transistor 2100 includes silicon oxide doped with nitrogen (N2). In some embodiments, the gate dielectric 2107 of the 3D transistor 2100 includes silicon oxide. That is, gate polysilicon and gate oxide can be used as the gate structure 2108 to reduce manufacturing complexity and cost. In some embodiments, the 3D transistor 2100 includes no stressors at the source and drain 2106 and/or uses no strained semiconductor material in the 3D semiconductor body 2104 to reduce manufacturing complexity and cost.
與本揭露內容的範圍一致,外圍電路202可以包括具有3D電晶體1100的LLV電路902(例如,介面316的I/O電路和數據總線318)、具有3D電晶體2000的LV電路904(例如,頁緩衝器304的一部分)、以及具有3D電晶體2100的HV電路906(例如,字元線驅動器308)。LLV源901可以耦接到LLV電路902並且被配置為向3D電晶體1100提供Vdd1,LV源903可以耦接到LV電路904並且被配置為向3D電晶體2000提供Vdd2,並且HV源905可以耦接到HV電路906並且被配置為向3D電晶體2100提供Vdd3,其中Vdd3 > Vdd2 > Vdd1。例如在字元線驅動器308中的3D電晶體2100可以透過字元線218耦接到儲存單元陣列201,並且例如在頁緩衝器304中的3D電晶體2000可以透過位元線216耦接到儲存單元陣列201。由於不同的工作電壓,3D電晶體2100的閘極介電質厚度T可以大於3D電晶體2000的閘極介電質厚度,其又可以大於3D電晶體1100的閘極介電質厚度。應當理解,如上詳細描述的,由於施加到3D電晶體2100的較高工作電壓,3D電晶體2100的其他大小/尺寸可以大於3D電晶體2000和/或3D電晶體2100的大小/尺寸,諸如通道長度L、3D半導體主體的高度H、3D半導體主體的寬度W等。在一些實施方式中,不同於LLV電路902和LV電路904的3D電晶體1100和2000,HV電路906的3D電晶體2100還包括漂移區2110,其具有比源極/汲極2106的摻雜濃度低的摻雜濃度,以便維持Vdd3的比Vdd2和Vdd1高的電壓。在一些實施方式中,與具有多晶矽閘極和閘極氧化物的閘極結構2008和2108的3D電晶體2000和2100不同,3D電晶體1100具有HKMG的閘極結構1108,以實現比3D電晶體2000和2100更快的開關速度。Consistent with the scope of this disclosure, peripheral circuitry 202 may include LLV circuitry 902 with 3D transistors 1100 (e.g., I/O circuitry of interface 316 and data bus 318), LV circuitry 904 with 3D transistors 2000 (e.g., part of page buffer 304 ), and HV circuit 906 (eg, word line driver 308 ) with 3D transistor 2100 . LLV source 901 may be coupled to LLV circuit 902 and configured to provide Vdd1 to 3D transistor 1100, LV source 903 may be coupled to LV circuit 904 and configured to provide Vdd2 to 3D transistor 2000, and HV source 905 may be coupled to connected to the HV circuit 906 and configured to provide Vdd3 to the 3D transistor 2100, where Vdd3 > Vdd2 > Vdd1. For example, 3D transistor 2100 in word line driver 308 may be coupled to storage cell array 201 through word line 218, and 3D transistor 2000, for example in page buffer 304 may be coupled to storage cell array 201 through bit line 216. cell array 201 . Due to different operating voltages, the gate dielectric thickness T of the 3D transistor 2100 may be greater than that of the 3D transistor 2000 , which may be greater than that of the 3D transistor 1100 . It should be understood that other sizes/dimensions of 3D transistor 2100 may be larger than 3D transistor 2000 and/or the size/dimensions of 3D transistor 2100 due to the higher operating voltage applied to 3D transistor 2100, such as channel The length L, the height H of the 3D semiconductor body, the width W of the 3D semiconductor body, etc. In some embodiments, unlike the 3D transistors 1100 and 2000 of the LLV circuit 902 and the LV circuit 904, the 3D transistor 2100 of the HV circuit 906 further includes a drift region 2110 having a higher doping concentration than the source/drain 2106 Low doping concentration in order to maintain a higher voltage of Vdd3 than Vdd2 and Vdd1. In some embodiments, unlike the 3D transistors 2000 and 2100 having the gate structures 2008 and 2108 of polysilicon gate and gate oxide, the 3D transistor 1100 has the gate structure 1108 of HKMG to achieve a higher ratio than the 3D transistor 1100. 2000 and 2100 faster switching speed.
圖25示出了根據本揭露內容的一些方面的具有儲存裝置的系統2500的方塊圖。系統2500可以是行動電話、桌上型電腦、筆記型電腦、平板電腦、車載電腦、遊戲控制台、影印機、定位設備、可穿戴電子設備、智能感測器、虛擬現實(VR)設備、增強現實(AR)設備或其中具有儲存的任何其他合適的電子設備。如圖25所示,系統2500可包括主機2508和具有一個或多個儲存裝置2504和記憶體控制器2506的記憶體系統2502。主機2508可以是電子設備的處理器,例如中央處理單元(CPU),或者片上系統(SoC),例如應用處理器(AP)。主機2508可被配置為將數據發送到儲存裝置2504或從其接收數據。FIG. 25 illustrates a block diagram of a system 2500 with storage, according to some aspects of the present disclosure. System 2500 can be a mobile phone, desktop computer, notebook computer, tablet computer, vehicle computer, game console, photocopier, pointing device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented Reality (AR) device or any other suitable electronic device having storage therein. As shown in FIG. 25 , system 2500 may include a host 2508 and a memory system 2502 having one or more storage devices 2504 and a memory controller 2506 . The host 2508 may be a processor of an electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). Host 2508 may be configured to send data to or receive data from storage device 2504 .
儲存裝置2504可以是本文所公開的任何儲存裝置,例如3D儲存裝置100和101、儲存裝置200、3D儲存裝置800、801和1900。在一些實施方式中,每個儲存裝置2504包括具有3D電晶體的外圍電路,如上文詳細描述的。The storage device 2504 may be any storage device disclosed herein, such as the 3D storage devices 100 and 101 , the storage device 200 , and the 3D storage devices 800 , 801 and 1900 . In some embodiments, each storage device 2504 includes peripheral circuitry with 3D transistors, as described in detail above.
根據一些實施方式,記憶體控制器2506耦接到儲存裝置2504和主機2508,並且被配置為控制儲存裝置2504。記憶體控制器2506可管理儲存在存儲裝置2504中的數據並與主機2508通訊。在一些實施方式中,記憶體控制器2506被設計用於在低占空比環境中操作,如安全數位(SD)卡、緊湊型快閃記憶體(CF)卡、通用串行總線(USB)快閃記憶體驅動器、或用於在諸如個人電腦、數位相機、行動電話等電子設備中使用的其他介質。在一些實施方式中,記憶體控制器2506被設計用於在高占空比環境SSD或嵌入式多媒體卡(eMMC)中操作,高占空比環境SSD或嵌入式多媒體卡用作行動設備(諸如智慧型手機、平板電腦、筆記型電腦等)和企業儲存陣列的數據儲存。記憶體控制器2506可被配置為控制儲存裝置2504的操作,例如讀取、擦除和編程操作。記憶體控制器2506還可被配置為管理關於儲存在或待儲存在儲存裝置2504中的數據的各種功能,包括(但不限於)壞塊管理、垃圾收集、邏輯到物理地址轉換、損耗均衡等。在一些實施方式中,記憶體控制器2506還被配置為針對從儲存裝置2504讀取或向其寫入的數據來處理糾錯碼(ECC)。也可以由記憶體控制器2506執行任何其他合適的功能,例如,對儲存裝置2504編程。記憶體控制器2506可以根據特定通訊協議與外部設備(例如,主機2508)通訊。例如,記憶體控制器2506可以透過各種介面協議中的至少一種與外部設備通訊,所述介面協議諸如USB協議、MMC協議、外圍部件互連(PCI)協議、PCI-Express(PCI-E)協議、高級技術附件(ATA)協議、串行-ATA協議、並行-ATA協議、小型電腦小型介面(SCSI)協議、增強的小型磁碟介面(ESDI)協議、集成驅動電子(IDE)協議、火線協議等。According to some implementations, memory controller 2506 is coupled to storage device 2504 and host 2508 and is configured to control storage device 2504 . The memory controller 2506 can manage data stored in the storage device 2504 and communicate with the host 2508 . In some implementations, memory controller 2506 is designed to operate in low duty cycle environments such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) Flash memory drives, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some implementations, the memory controller 2506 is designed to operate in a high duty cycle environment SSD or embedded multimedia card (eMMC) used as a mobile device such as smartphones, tablets, laptops, etc.) and enterprise storage arrays for data storage. The memory controller 2506 may be configured to control operations of the storage device 2504, such as read, erase, and program operations. Memory controller 2506 may also be configured to manage various functions related to data stored or to be stored in storage device 2504, including (but not limited to) bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. . In some implementations, memory controller 2506 is also configured to process error correction code (ECC) on data read from or written to storage device 2504 . Any other suitable function may also be performed by memory controller 2506 , such as programming storage device 2504 . The memory controller 2506 can communicate with external devices (eg, the host 2508 ) according to a specific communication protocol. For example, the memory controller 2506 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI-Express (PCI-E) protocol , Advanced Technology Attachment (ATA) Protocol, Serial-ATA Protocol, Parallel-ATA Protocol, Small Computer Small Interface (SCSI) Protocol, Enhanced Small Disk Interface (ESDI) Protocol, Integrated Drive Electronics (IDE) Protocol, FireWire Protocol wait.
記憶體控制器2506和一個或多個儲存裝置2504可以集成到各種類型的儲存裝置中,例如,包括在相同的封裝中,諸如通用快閃記憶體(UFS)封裝或eMMC封裝。即,記憶體系統2502可以被實現和封裝到不同類型的終端電子産品中。在如圖26A中所示的一個示例中,記憶體控制器2506和單個儲存裝置2504可集成到記憶卡2602中。記憶卡2602可以包括PC卡(PCMCIA,個人電腦記憶卡國際協會)、CF卡、智能媒體(SM)卡、記憶棒、多媒體卡(MMC、RS-MMC、MMCmicro)、SD卡(SD、miniSD、microSD、SDHC)、UFS等。記憶卡2602可進一步包括將記憶卡2602與主機(例如,圖25中的主機2508)耦接的記憶卡連接器2604。在如圖26B所示的另一示例中,記憶體控制器2506和多個儲存裝置2504可以被集成到SSD 2606中。SSD 2606還可以包括將SSD 2606與主機(例如,圖25中的主機2508)耦接的SSD連接器2608。在一些實施方式中,SSD 2606的儲存容量和/或操作速度大於記憶卡2602的儲存容量和/或操作速度。Memory controller 2506 and one or more storage devices 2504 may be integrated into various types of storage devices, eg, included in the same package, such as a universal flash (UFS) package or an eMMC package. That is, the memory system 2502 can be implemented and packaged into different types of end electronic products. In one example as shown in FIG. 26A , memory controller 2506 and a single storage device 2504 may be integrated into memory card 2602 . Memory card 2602 can include PC card (PCMCIA, Personal Computer Memory Card International Association), CF card, smart media (SM) card, memory stick, multimedia card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), UFS, etc. Memory card 2602 may further include memory card connector 2604 to couple memory card 2602 with a host (eg, host 2508 in FIG. 25 ). In another example as shown in FIG. 26B , memory controller 2506 and multiple storage devices 2504 may be integrated into SSD 2606 . SSD 2606 may also include SSD connector 2608 that couples SSD 2606 to a host (eg, host 2508 in FIG. 25 ). In some implementations, the storage capacity and/or operating speed of SSD 2606 is greater than the storage capacity and/or operating speed of memory card 2602 .
圖22A-22J示出了根據本揭露內容的一些方面的用於形成3D電晶體的製造過程。圖23示出了根據本揭露內容的一些方面的用於形成示例性3D儲存裝置的方法2300的流程圖。圖24A示出了根據本揭露內容的一些方面的用於形成3D電晶體的方法2400的流程圖。圖24B示出了根據本揭露內容的一些方面的用於形成3D電晶體的另一種方法2401的流程圖。圖23中示出的3D儲存裝置的示例包括圖8A-8C中示出的3D儲存裝置800、801和899。圖22A-22J、24A和24B中示出的3D電晶體的示例包括圖5、11A、20A和21A中示出的3D電晶體500、1100、2000和2100。將一起描述圖22A-22J、23、24A和24B。應當理解,方法2300、2400和2401中所示的步驟不是詳盡無遺的,並且也可以在所示步驟中的任何步驟之前、之後或之間執行其他步驟。此外,一些步驟可以同時執行,或者以與圖23、24A和24B所示的不同的順序執行。22A-22J illustrate a fabrication process for forming a 3D transistor according to some aspects of the present disclosure. FIG. 23 shows a flowchart of a method 2300 for forming an exemplary 3D storage device in accordance with aspects of the present disclosure. FIG. 24A shows a flowchart of a method 2400 for forming a 3D transistor according to some aspects of the present disclosure. FIG. 24B shows a flowchart of another method 2401 for forming a 3D transistor according to some aspects of the present disclosure. Examples of the 3D storage device shown in FIG. 23 include the 3D storage devices 800 , 801 , and 899 shown in FIGS. 8A-8C . Examples of the 3D transistors shown in FIGS. 22A-22J , 24A, and 24B include the 3D transistors 500 , 1100 , 2000 , and 2100 shown in FIGS. 5 , 11A, 20A, and 21A. 22A-22J, 23, 24A, and 24B will be described together. It should be understood that the steps shown in methods 2300, 2400, and 2401 are not exhaustive, and other steps may also be performed before, after, or between any of the steps shown. Furthermore, some steps may be performed simultaneously, or in a different order than that shown in Figures 23, 24A, and 24B.
參考圖23,方法2300開始於步驟2302,其中在第一基底上形成包括儲存單元陣列的第一半導體結構。在一些實施方式中,為了形成儲單存元陣列,形成3D NAND記憶體串的陣列。例如,如圖8B所示,在基底809上形成3D NAND記憶體串817的陣列。方法2300進行到步驟2304,如圖23所示,其中在NAND記憶體串的陣列上方形成包括多個第一鍵合觸點的第一鍵合層。例如,如圖8B所示,在3D NAND記憶體串817的陣列上方形成包括鍵合觸點855的鍵合層829。Referring to FIG. 23, the method 2300 begins at step 2302, wherein a first semiconductor structure including a memory cell array is formed on a first substrate. In some embodiments, to form the array of memory cells, an array of 3D NAND memory strings is formed. For example, as shown in FIG. 8B , an array of 3D NAND memory strings 817 is formed on a substrate 809 . Method 2300 proceeds to step 2304, as shown in FIG. 23, wherein a first bonding layer including a plurality of first bonding contacts is formed over the array of NAND memory strings. For example, as shown in FIG. 8B , a bonding layer 829 including bonding contacts 855 is formed over the array of 3D NAND memory strings 817 .
方法2300進行到步驟2306,如圖23所示,其中在第二基底上形成包括外圍電路的第二半導體結構,該外圍電路包括3D電晶體。凹式閘極電晶體可以包括突出到第二基底中的凹式閘極結構。為了形成第二半導體結構,從第二基底形成3D半導體主體,並且形成與3D半導體主體的多個側面接觸的閘極結構。The method 2300 proceeds to step 2306, as shown in FIG. 23, wherein a second semiconductor structure including peripheral circuits including 3D transistors is formed on a second substrate. The recessed gate transistor may include a recessed gate structure protruding into the second substrate. To form the second semiconductor structure, a 3D semiconductor body is formed from the second substrate, and a gate structure is formed in contact with sides of the 3D semiconductor body.
3D半導體主體可以使用各種製造製程來形成。在一些實施方式中,為了形成3D半導體主體,如圖24A所示,在步驟2402,在第二基底中圍繞第二基底的一部分形成溝槽隔離。基底可以是矽基底。3D semiconductor bodies can be formed using various fabrication processes. In some embodiments, to form a 3D semiconductor body, as shown in FIG. 24A , at step 2402 , a trench isolation is formed in the second substrate around a portion of the second substrate. The substrate may be a silicon substrate.
如圖22A所示,例如使用濕式/乾式蝕刻和氧化矽的薄膜沉積,在矽基底2202中形成溝槽隔離2204,例如STI。可以使用例如化學機械拋光(CMP)來平坦化溝槽隔離2204的頂表面。溝槽隔離2204可以將矽基底2202劃分成其中可以分別形成多個3D電晶體的多個區域。在形成溝槽隔離2204之前,可以形成犧牲層2206以覆蓋其中要形成3D電晶體的3D半導體主體的區域。在一些實施方式中,使用一個或多個薄膜沉積製程(包括但不限於化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其任何組合)來沉積不同於矽基底2202和溝槽隔離2204的犧牲材料層,例如氮化矽。然後,可以使用微影和濕式/乾式蝕刻對沉積的犧牲材料層進行圖案化,以形成犧牲層2206。因此,在矽基底2202的被犧牲層2206覆蓋的部分中不能形成溝槽隔離2204。結果,如圖22A所示,溝槽隔離2204圍繞矽基底2202的被犧牲層2206覆蓋的一部分。儘管未示出,但是隨後可以在矽基底2202中形成阱。阱可以使用光刻來圖案化並在溝槽隔離2204之間對準,隨後離子注入N型摻雜劑和/或P型摻雜劑。As shown in FIG. 22A, trench isolations 2204, such as STI, are formed in a silicon substrate 2202, eg, using wet/dry etching and thin film deposition of silicon oxide. The top surface of trench isolation 2204 may be planarized using, for example, chemical mechanical polishing (CMP). The trench isolation 2204 can divide the silicon substrate 2202 into a plurality of regions in which a plurality of 3D transistors can be respectively formed. Before forming the trench isolation 2204, a sacrificial layer 2206 may be formed to cover the region of the 3D semiconductor body where the 3D transistor is to be formed. In some embodiments, one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, are used to deposit films other than The sacrificial material layer of the silicon substrate 2202 and the trench isolation 2204, such as silicon nitride. The deposited layer of sacrificial material may then be patterned using lithography and wet/dry etching to form sacrificial layer 2206 . Therefore, trench isolation 2204 cannot be formed in the portion of silicon substrate 2202 covered by sacrificial layer 2206 . As a result, as shown in FIG. 22A , the trench isolation 2204 surrounds a portion of the silicon substrate 2202 covered by the sacrificial layer 2206 . Although not shown, wells may subsequently be formed in the silicon substrate 2202 . Wells may be patterned and aligned between trench isolations 2204 using photolithography, followed by ion implantation of N-type dopants and/or P-type dopants.
如圖24A所示,在步驟2404,對溝槽隔離進行回蝕刻以暴露第二基底的部分的至少一部分。如圖22B所示,根據一些實施方式,透過例如使用濕式/乾式蝕刻來回蝕刻溝槽隔離2204以暴露被犧牲層2206覆蓋並且被溝槽隔離2204圍繞的矽基底2202的部分中的至少一部分(例如,在圖22A中)而在溝槽隔離2204中形成凹槽。結果,根據一些實施方式,在凹陷(回蝕刻)之後,矽基底2202的暴露部分現在成為3D半導體主體2208,其在矽基底2202和溝槽隔離2204的所得頂表面上方。As shown in FIG. 24A, at step 2404, the trench isolation is etched back to expose at least a portion of the portion of the second substrate. As shown in FIG. 22B , according to some embodiments, trench isolation 2204 is etched back and forth, for example using wet/dry etching, to expose at least a portion of the portion of silicon substrate 2202 covered by sacrificial layer 2206 and surrounded by trench isolation 2204 ( For example, in FIG. 22A ), grooves are formed in trench isolation 2204 . As a result, after recessing (etch back), the exposed portion of the silicon substrate 2202 is now a 3D semiconductor body 2208 over the resulting top surface of the silicon substrate 2202 and trench isolation 2204 , according to some embodiments.
如圖22A、22B和24A所示,代替在形成溝槽隔離之後形成3D半導體主體,可以在形成溝槽隔離之前形成3D半導體主體,如圖22H、22I和24B所示。在一些實施方式中,為了形成3D半導體主體,如圖24B所示,在步驟2403,在第二基底中圍繞第二基底的一部分形成溝槽。如圖22H所示,例如透過使用乾式/濕式蝕刻來蝕刻矽基底2202而在矽基底2202中形成溝槽2209。在一些實施方式中,在蝕刻之前形成犧牲層2206以覆蓋要形成3D半導體主體2208的矽基底2202的部分。結果,根據一些實施方式,矽基底2202的一部分被溝槽2209圍繞。As shown in Figures 22A, 22B and 24A, instead of forming the 3D semiconductor body after forming the trench isolation, the 3D semiconductor body may be formed before forming the trench isolation, as shown in Figures 22H, 22I and 24B. In some embodiments, to form a 3D semiconductor body, as shown in FIG. 24B , at step 2403 , a trench is formed in the second substrate around a portion of the second substrate. As shown in FIG. 22H, trenches 2209 are formed in the silicon substrate 2202, for example, by etching the silicon substrate 2202 using dry/wet etching. In some embodiments, a sacrificial layer 2206 is formed prior to etching to cover the portion of the silicon substrate 2202 where the 3D semiconductor body 2208 is to be formed. As a result, according to some embodiments, a portion of the silicon substrate 2202 is surrounded by the trench 2209 .
如圖24B所示,在步驟2405,沉積隔離材料以部分填充溝槽,從而暴露第二基底的部分中的至少一部分。如圖22I所示,透過使用一個或多個薄膜沉積製程(包括但不限於CVD、PVD、ALD或其任何組合)將諸如氧化矽的隔離材料沉積到溝槽2209中,在溝槽2209中形成溝槽隔離2204(例如,圖22H所示)。為了形成3D半導體主體2208,可以控制沉積速率和/或持續時間以部分填充溝槽2209,從而暴露矽基底2202的部分中的至少一部分。結果,根據一些實施方式,在形成溝槽隔離2204之後,矽基底2202的暴露部分現在成為3D半導體主體2208,其在矽基底2202和溝槽隔離2204的所得頂表面上方。As shown in FIG. 24B, at step 2405, an isolation material is deposited to partially fill the trench, thereby exposing at least a portion of the portion of the second substrate. As shown in FIG. 22I , an isolating material such as silicon oxide is deposited into trench 2209 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Trench isolation 2204 (eg, shown in FIG. 22H ). To form 3D semiconductor body 2208 , the deposition rate and/or duration may be controlled to partially fill trench 2209 , thereby exposing at least a portion of portions of silicon substrate 2202 . As a result, after formation of trench isolation 2204 , the exposed portion of silicon substrate 2202 now becomes 3D semiconductor body 2208 over the resulting top surface of silicon substrate 2202 and trench isolation 2204 , according to some embodiments.
返回參考圖22C,在形成3D半導體主體2208之後,無論其是在形成溝槽隔離2204之前還是之後形成,例如透過濕式/乾式蝕刻去除犧牲層2206(例如,圖22B和22I中所示)。Referring back to FIG. 22C , after forming the 3D semiconductor body 2208 , whether it is formed before or after forming the trench isolation 2204 , the sacrificial layer 2206 is removed, eg, by wet/dry etching (eg, as shown in FIGS. 22B and 22I ).
在一些實施方式中,為了形成閘極結構,如圖24A和24B所示,在步驟2406,隨後在3D半導體主體的多個側面上形成閘極介電質層和閘電極層。如圖22D所示,在3D半導體主體2208的多個側面上形成閘極介電質層2210,例如氧化矽層或高k介電質層。在一些實施方式中,使用一個或多個薄膜沉積製程(包括但不限於CVD、PVD、ALD或其任何組合)將介電質材料層沉積到3D半導體主體2208的所有暴露表面上。在閘極介電質層2210是氧化矽層的一些實施方式中,使用乾式/濕式氧化來氧化3D半導體主體2208中的暴露表面處的矽的部分以形成閘極介電質層2210。In some embodiments, to form the gate structure, as shown in Figures 24A and 24B, at step 2406, a gate dielectric layer and a gate electrode layer are subsequently formed on the sides of the 3D semiconductor body. As shown in FIG. 22D , a gate dielectric layer 2210 , such as a silicon oxide layer or a high-k dielectric layer, is formed on various sides of the 3D semiconductor body 2208 . In some embodiments, a layer of dielectric material is deposited onto all exposed surfaces of the 3D semiconductor body 2208 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. In some embodiments where the gate dielectric layer 2210 is a silicon oxide layer, dry/wet oxidation is used to oxidize portions of the silicon at exposed surfaces in the 3D semiconductor body 2208 to form the gate dielectric layer 2210 .
如圖22E所示,在閘極介電質層2210之上形成諸如摻雜多晶矽層或金屬層的閘電極層2212。在一些實施方式中,使用一個或多個薄膜沉積製程(包括但不限於CVD、PVD、ALD或其任何組合)在閘極介電質層2210之上沉積半導體或導電材料層。在閘電極層2212是多晶矽層的一些實施方式中,執行原位摻雜以摻雜多晶矽層,或者在沉積之後執行諸如離子注入之類的摻雜製程以摻雜多晶矽層。As shown in FIG. 22E , a gate electrode layer 2212 such as a doped polysilicon layer or a metal layer is formed on the gate dielectric layer 2210 . In some embodiments, a layer of semiconductor or conductive material is deposited over gate dielectric layer 2210 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In some embodiments where the gate electrode layer 2212 is a polysilicon layer, in-situ doping is performed to dope the polysilicon layer, or a doping process such as ion implantation is performed after deposition to dope the polysilicon layer.
在一些實施方式中,為了形成閘極結構,如圖24A和24B所示,在步驟2408,圖案化閘電極層以形成閘電極。如圖22F所示,例如使用微影和濕式/乾式蝕刻來圖案化閘電極層2212(例如圖22E所示)以形成閘電極2214。In some embodiments, to form the gate structure, as shown in Figures 24A and 24B, at step 2408, the gate electrode layer is patterned to form the gate electrode. As shown in FIG. 22F , gate electrode layer 2212 (eg, as shown in FIG. 22E ) is patterned to form gate electrode 2214 , eg, using lithography and wet/dry etching.
如圖24A和24B所示,在步驟2410,在3D半導體主體中形成源極和汲極。在一些實施方式中,為了形成源極和汲極,對3D半導體主體的未被閘極結構覆蓋的部分進行摻雜。如圖22G所示,透過例如使用離子注入摻雜3D半導體主體2208的未被閘電極2214覆蓋的部分,在3D半導體主體2208中形成一對源極和汲極2216。結果,根據一些實施方式,源極和汲極2216沒有直接形成在閘電極2214下方以允許在源極和汲極2216之間形成通道。儘管未示出,但在一些實施方式中,例如透過乾式/濕式蝕刻來去除閘極介電質層2210的覆蓋源極和汲極2216的部分,以暴露源極和汲極2216的其上可形成源極和汲極觸點(未示出)的部分。As shown in Figures 24A and 24B, at step 2410, a source and a drain are formed in the 3D semiconductor body. In some embodiments, the portion of the 3D semiconductor body not covered by the gate structure is doped in order to form the source and drain. A pair of source and drain electrodes 2216 are formed in the 3D semiconductor body 2208 by doping the portion of the 3D semiconductor body 2208 not covered by the gate electrode 2214, eg, using ion implantation, as shown in FIG. 22G. As a result, source and drain 2216 are not formed directly under gate electrode 2214 to allow a channel to form between source and drain 2216, according to some embodiments. Although not shown, in some embodiments, portions of the gate dielectric layer 2210 overlying the source and drain electrodes 2216 are removed, such as by dry/wet etching, to expose the upper portions of the source and drain electrodes 2216. Portions of source and drain contacts (not shown) may be formed.
根據一些實施方式,由此形成具有3D半導體主體2208、閘電極2214、閘極介電質層2210以及源極和汲極2216的3D電晶體。應當理解,由於上述用於形成3D電晶體的製造製程與用於形成平面電晶體的製造製程兼容,因此在一些示例中,可以使用上述相同的製造製程來形成具有與3D電晶體相同的溝槽隔離深度或不同的溝槽隔離深度的平面電晶體。在一個示例中,圖24A中描述的製造製程可以用於形成具有相同溝槽隔離深度的3D電晶體和平面電晶體。相同的溝槽隔離深度可以由在形成3D半導體主體2208之前形成溝槽隔離2204來確定。在另一示例中,圖24B中描述的製造製程可以用於形成具有不同溝槽隔離深度的3D電晶體和平面電晶體。According to some embodiments, a 3D transistor having a 3D semiconductor body 2208 , a gate electrode 2214 , a gate dielectric layer 2210 , and a source and drain 2216 is thus formed. It should be understood that since the fabrication process described above for forming a 3D transistor is compatible with the fabrication process used to form a planar transistor, in some examples, the same fabrication process described above can be used to form a 3D transistor with the same trench Planar transistors with isolation depth or different trench isolation depths. In one example, the fabrication process described in FIG. 24A can be used to form 3D transistors and planar transistors with the same trench isolation depth. The same trench isolation depth may be determined by forming trench isolation 2204 before forming 3D semiconductor body 2208 . In another example, the fabrication process described in FIG. 24B can be used to form 3D transistors and planar transistors with different trench isolation depths.
為了形成具有相同溝槽隔離深度的3D電晶體和平面電晶體,如圖22A-22G所示,可以在第一區域2201中形成3D電晶體,並在相同矽基底2202的第二區域2203中形成平面電晶體。如圖22A所示,可以在第一區域2201和第二區域2203兩者中形成溝槽隔離2204,例如STI,以便在上面關於圖22A詳細描述的相同製造製程中分別形成3D電晶體和平面電晶體。因此,用於3D電晶體的溝槽隔離2204和用於平面電晶體的溝槽隔離2204可以具有相同的深度。如圖22B所示,溝槽隔離2204的回蝕刻可以僅在第一區域2201中執行,而不在第二區域2203中執行。即,根據一些實施方式,當在第一區域2201中形成用於3D電晶體的溝槽隔離2204的凹槽時,第二區域2203中的用於平面電晶體的溝槽隔離2204保持不變而無凹槽。在一些實施方式中,在回蝕刻第一區域2201中的溝槽隔離2204之前,圖案化蝕刻遮罩以覆蓋第二區域2203並且僅暴露第一區域2201,以保護第二區域2203中的溝槽隔離2204。如圖22C所示,第一區域2201和第二區域2203兩者中的犧牲層2206可以在以上關於圖22C詳細描述的相同製造製程中去除。如圖22D所示,第二區域2203中的平面電晶體的閘極介電質層2211可以在與如以上關於圖22D詳細描述的用於形成第一區域2201中的3D電晶體的閘極介電質層2210的相同製造製程中形成。如圖22E所示,閘電極層2212可以在與以上關於圖22E詳細描述的相同的製造製程中形成在第一區域2201和第二區域2203兩者中的閘極介電質層2210和2211之上。如圖22F所示,在與如以上關於圖22F詳細描述的用於圖案化第一區域2201中的3D電晶體的閘電極2214的相同製造製程中,可以從閘電極層2212圖案化第二區域2203中的平面電晶體的閘電極2215。如圖22G所示,第二區域2203中的平面電晶體的一對源極和汲極2217可以在與如以上關於圖22G詳細描述的用於形成第一區域2201中的3D電晶體的一對源極和汲極2216的相同製造製程中形成。根據一些實施方式,由此在用於形成具有3D半導體主體2208、閘電極2214、閘極介電質層2210以及源極和汲極2216的3D電晶體的相同製程流程(除了圖22B中的回蝕刻製程)中形成具有閘電極2215、閘極介電質層2211以及源極和汲極2217的平面電晶體。In order to form 3D transistors and planar transistors with the same trench isolation depth, as shown in FIGS. planar transistor. As shown in FIG. 22A, trench isolations 2204, such as STIs, may be formed in both the first region 2201 and the second region 2203 to form 3D transistors and planar transistors, respectively, in the same fabrication process described in detail above with respect to FIG. 22A. crystals. Therefore, trench isolation 2204 for 3D transistors and trench isolation 2204 for planar transistors may have the same depth. As shown in FIG. 22B , the etch back of the trench isolation 2204 may be performed only in the first region 2201 and not in the second region 2203 . That is, according to some embodiments, when the trench isolation 2204 for the 3D transistor is formed in the first region 2201, the trench isolation 2204 for the planar transistor in the second region 2203 remains unchanged and No grooves. In some embodiments, before etching back the trench isolation 2204 in the first region 2201, the etch mask is patterned to cover the second region 2203 and only expose the first region 2201 to protect the trenches in the second region 2203 Quarantine 2204. As shown in Figure 22C, the sacrificial layer 2206 in both the first region 2201 and the second region 2203 can be removed in the same fabrication process as described in detail above with respect to Figure 22C. As shown in FIG. 22D, the gate dielectric layer 2211 of the planar transistor in the second region 2203 can be formed in the same manner as the gate dielectric layer 2211 used to form the 3D transistor in the first region 2201 as described in detail above with respect to FIG. 22D. The dielectric layer 2210 is formed in the same manufacturing process. As shown in FIG. 22E, a gate electrode layer 2212 may be formed between the gate dielectric layers 2210 and 2211 in both the first region 2201 and the second region 2203 in the same manufacturing process as described in detail above with respect to FIG. 22E. superior. As shown in FIG. 22F , the second region can be patterned from the gate electrode layer 2212 in the same fabrication process as described in detail above with respect to FIG. 22F for patterning the gate electrode 2214 of the 3D transistor in the first region 2201 Gate electrode 2215 of the planar transistor in 2203. As shown in FIG. 22G , the pair of source and drain electrodes 2217 of the planar transistor in the second region 2203 can be formed in the same way as the pair of 3D transistors in the first region 2201 as described in detail above with respect to FIG. 22G The source and drain 2216 are formed in the same manufacturing process. According to some embodiments, the same process flow for forming a 3D transistor having a 3D semiconductor body 2208, a gate electrode 2214, a gate dielectric layer 2210, and a source and a drain 2216 is thus used (except for the loop in FIG. 22B An etching process) forms a planar transistor with a gate electrode 2215 , a gate dielectric layer 2211 , and a source and a drain 2217 .
還應當理解,例如對於具有不同施加電壓的外圍電路(例如,LLV電路902、LV電路904和HV電路906)而言,具有不同隔離溝槽深度的3D電晶體可以透過在回蝕刻溝槽隔離2204時改變凹槽深度來形成。如圖22J所示,透過回蝕刻第一區域2201和第三區域2205中的溝槽隔離2204的不同凹槽深度,矽基底2202的第三區域2205中的3D半導體主體2219可以具有與圖22D中的第一區域2201中的3D半導體主體2208不同的凹槽深度。在一些實施方式中,3D半導體主體2219是HV電路906中的3D電晶體的一部分,並且3D半導體主體2208是LLV電路902和/或LV電路904中的3D電晶體的一部分,並且用於形成3D半導體主體2219的第一凹槽深度大於用於形成3D半導體主體2208的第二凹槽深度。在一個示例中,第一凹槽深度可以在300 nm和400 nm之間,而第二凹槽深度可以在50 nm和100 nm之間。It should also be understood that 3D transistors with different isolation trench depths can see through the etch-back trench isolation 2204 for peripheral circuits (eg, LLV circuit 902 , LV circuit 904 , and HV circuit 906 ) with different applied voltages, for example. When changing the groove depth to form. As shown in FIG. 22J, by etching back the different groove depths of the trench isolation 2204 in the first region 2201 and the third region 2205, the 3D semiconductor body 2219 in the third region 2205 of the silicon substrate 2202 can have the same structure as that in FIG. 22D. The 3D semiconductor body 2208 in the first region 2201 has different groove depths. In some embodiments, 3D semiconductor body 2219 is part of a 3D transistor in HV circuit 906 and 3D semiconductor body 2208 is part of a 3D transistor in LLV circuit 902 and/or LV circuit 904 and is used to form a 3D The first groove depth of the semiconductor body 2219 is greater than the second groove depth used to form the 3D semiconductor body 2208 . In one example, the first groove depth may be between 300 nm and 400 nm, and the second groove depth may be between 50 nm and 100 nm.
參考圖23,方法2300進行到步驟2308,其中在外圍電路上方形成包括多個第二鍵合觸點的第二鍵合層。例如,如圖8B所示,包括鍵合觸點853的鍵合層851形成在外圍電路835中的3D電晶體839上方。方法2300進行到步驟2310,如圖23中所示,其中第一半導體結構和第二半導體結構以面對面方式鍵合,使得儲存單元陣列跨越鍵合界面耦接到外圍電路。鍵合可以是混合鍵合。在一些實施方式中,第二半導體結構在鍵合之後在第一半導體結構上方。在一些實施方式中,第一半導體結構在鍵合之後在第二半導體結構上方。Referring to FIG. 23 , method 2300 proceeds to step 2308 where a second bonding layer including a second plurality of bonding contacts is formed over the peripheral circuitry. For example, as shown in FIG. 8B , a bonding layer 851 including bonding contacts 853 is formed over the 3D transistor 839 in the peripheral circuit 835 . Method 2300 proceeds to step 2310, as shown in FIG. 23, wherein the first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner such that the memory cell array is coupled to peripheral circuitry across the bonding interface. Bonding can be mixed bonding. In some embodiments, the second semiconductor structure is over the first semiconductor structure after bonding. In some embodiments, the first semiconductor structure is over the second semiconductor structure after bonding.
如圖8A所示,將具有3D NAND記憶體串838的第二半導體結構804上下翻轉。面向下的鍵合層826與面向上的鍵合層822鍵合,即以面對面的方式,從而形成鍵合界面806。在一些實施方式中,在鍵合之前,對鍵合表面應用處理製程,例如等離子體處理、濕式處理和/或熱處理。在鍵合之後,鍵合層826中的鍵合觸點828和鍵合層822中的鍵合觸點824彼此對準並接觸,使得3D NAND記憶體串838可以耦接到器件層810(例如,外圍電路812和814)。類似地,如圖8B中所示,將具有外圍電路835和837的第一半導體結構805上下翻轉。面向下的鍵合層851與面向上的鍵合層829鍵合,即以面對面的方式,從而形成鍵合界面807。在鍵合之後,鍵合層851中的鍵合觸點853和鍵合層829中的鍵合觸點855彼此對準並且接觸,使得3D NAND記憶體串817可以耦接到器件層831(例如,外圍電路835和837)。As shown in FIG. 8A , the second semiconductor structure 804 with the 3D NAND memory strings 838 is turned upside down. Downward-facing bonding layer 826 is bonded, ie, face-to-face, to upward-facing bonding layer 822 , thereby forming bonding interface 806 . In some embodiments, a treatment process, such as plasma treatment, wet treatment, and/or heat treatment, is applied to the bonding surface prior to bonding. After bonding, bonding contacts 828 in bonding layer 826 and bonding contacts 824 in bonding layer 822 are aligned and contact each other such that 3D NAND memory string 838 can be coupled to device layer 810 (eg , peripheral circuits 812 and 814). Similarly, as shown in FIG. 8B , the first semiconductor structure 805 with peripheral circuits 835 and 837 is turned upside down. The downward-facing bonding layer 851 is bonded, ie face-to-face, to the upward-facing bonding layer 829 , thereby forming a bonding interface 807 . After bonding, bonding contacts 853 in bonding layer 851 and bonding contacts 855 in bonding layer 829 are aligned and contact each other so that 3D NAND memory string 817 can be coupled to device layer 831 (eg , peripheral circuits 835 and 837).
方法2300進行到步驟2312,如圖23所示,其中在鍵合之後,在第一和第二基底中的一個基底上方的第一和第二基底中的另一基底被減薄。如圖8A所示,由於具有3D NAND記憶體串838的第二半導體結構804的基底在具有外圍電路812和814的第一半導體結構802的基底上方,因此使用CMP和/或蝕刻製程減薄第二半導體結構804的基底以形成半導體層848。類似地,如圖8B所示,由於具有外圍電路835和837的第一半導體結構805的基底在具有3D NAND記憶體串817的第二半導體結構803的基底上方,所以使用CMP和/或蝕刻製程減薄第一半導體結構805的基底以形成半導體層833。Method 2300 proceeds to step 2312, as shown in FIG. 23, where after bonding, the other of the first and second substrates over one of the first and second substrates is thinned. As shown in FIG. 8A, since the base of the second semiconductor structure 804 having the 3D NAND memory string 838 is above the base of the first semiconductor structure 802 having the peripheral circuits 812 and 814, the first semiconductor structure 802 is thinned using CMP and/or etching processes. The base of the second semiconductor structure 804 to form a semiconductor layer 848 . Similarly, as shown in FIG. 8B, since the substrate of the first semiconductor structure 805 having peripheral circuits 835 and 837 is above the substrate of the second semiconductor structure 803 having 3D NAND memory strings 817, CMP and/or etching processes are used. The base of the first semiconductor structure 805 is thinned to form a semiconductor layer 833 .
方法2300進行到步驟2314,如圖23所示,其中在減薄的第一或第二基底上形成互連層。如圖8A所示,在半導體層848(減薄的頂部基底)上方形成焊墊輸出互連層850。類似地,如圖8B所示,在半導體層833(減薄的頂部基底)上方形成焊墊輸出互連層843。Method 2300 proceeds to step 2314, as shown in FIG. 23, where an interconnect layer is formed on the thinned first or second substrate. As shown in FIG. 8A , pad output interconnect layer 850 is formed over semiconductor layer 848 (thinned top substrate). Similarly, as shown in FIG. 8B , pad output interconnect layer 843 is formed over semiconductor layer 833 (thinned top substrate).
根據本揭露內容的一方面,一種3D儲存裝置包括:第一半導體結構,包括儲存單元陣列;第二半導體結構,包括外圍電路;以及鍵合界面,在第一半導體結構和第二半導體結構之間。外圍電路包括3D電晶體。儲存單元陣列跨越鍵合界面耦接到外圍電路。According to an aspect of the present disclosure, a 3D storage device includes: a first semiconductor structure including a storage cell array; a second semiconductor structure including peripheral circuits; and a bonding interface between the first semiconductor structure and the second semiconductor structure . Peripheral circuits include 3D transistors. The memory cell array is coupled to peripheral circuits across the bonding interface.
在一些實施方式中,3D電晶體是多閘極電晶體。In some embodiments, the 3D transistor is a multi-gate transistor.
在一些實施方式中,多閘極電晶體包括FinFET。In some embodiments, the multi-gate transistors include FinFETs.
在一些實施方式中,多閘極電晶體包括GAA FET。In some embodiments, the multi-gate transistor includes a GAA FET.
在一些實施方式中,3D電晶體包括3D半導體主體以及與3D半導體主體的多個側面接觸的閘極結構。閘極結構可以包括閘極介電質和閘電極。In some embodiments, a 3D transistor includes a 3D semiconductor body and a gate structure in contact with multiple sides of the 3D semiconductor body. The gate structure may include a gate dielectric and a gate electrode.
在一些實施方式中,外圍電路包括第一外圍電路和第二外圍電路,3D電晶體包括第一外圍電路的第一3D電晶體和第二外圍電路的第二3D電晶體,並且第一外圍電路的第一3D電晶體接收第一電壓,並且第二外圍電路的第二3D電晶體接收大於第一電壓的第二電壓。In some embodiments, the peripheral circuit includes a first peripheral circuit and a second peripheral circuit, the 3D transistor includes a first 3D transistor of the first peripheral circuit and a second 3D transistor of the second peripheral circuit, and the first peripheral circuit The first 3D transistor of the second peripheral circuit receives a first voltage, and the second 3D transistor of the second peripheral circuit receives a second voltage greater than the first voltage.
在一些實施方式中,外圍電路還包括第三外圍電路,3D電晶體還包括第三外圍電路的第三3D電晶體,並且第三外圍電路的第三3D電晶體接收大於第二電壓的第三電壓。In some embodiments, the peripheral circuit further includes a third peripheral circuit, the 3D transistor further includes a third 3D transistor of the third peripheral circuit, and the third 3D transistor of the third peripheral circuit receives a third voltage greater than the second voltage. Voltage.
在一些實施方式中,第一外圍電路包括I/O電路,第二外圍電路包括頁緩衝器的至少一部分,且第三外圍電路包括字元線驅動器。In some embodiments, the first peripheral circuit includes I/O circuitry, the second peripheral circuit includes at least a portion of the page buffer, and the third peripheral circuit includes a word line driver.
在一些實施方式中,第一半導體結構還包括耦接到儲存單元陣列的多條位元線和多條字元線,第二外圍電路的第二3D電晶體透過位元線中的至少一條耦接到儲存單元陣列,並且第三外圍電路的第三3D電晶體透過字元線中的至少一條耦接到儲存單元陣列。In some embodiments, the first semiconductor structure further includes a plurality of bit lines and a plurality of word lines coupled to the storage cell array, and the second 3D transistor of the second peripheral circuit is coupled to the second peripheral circuit through at least one of the bit lines. connected to the storage unit array, and the third 3D transistor of the third peripheral circuit is coupled to the storage unit array through at least one of the word lines.
在一些實施方式中,第三3D電晶體的閘極介電質的厚度大於第二3D電晶體的閘極介電質的厚度,並且第二3D電晶體的閘極介電質的厚度大於第一3D電晶體的閘極介電質的厚度。In some embodiments, the thickness of the gate dielectric of the third 3D transistor is greater than the thickness of the gate dielectric of the second 3D transistor, and the thickness of the gate dielectric of the second 3D transistor is greater than that of the first 3D transistor. The thickness of the gate dielectric of a 3D transistor.
在一些實施方式中,第三3D電晶體還包括漂移區、源極和汲極,並且漂移區的摻雜濃度小於源極和汲極的摻雜濃度。In some embodiments, the third 3D transistor further includes a drift region, a source and a drain, and the doping concentration of the drift region is smaller than that of the source and the drain.
在一些實施方式中,第一3D電晶體的閘電極包括金屬,並且第一3D電晶體的閘極介電質包括高k介電質。In some embodiments, the gate electrode of the first 3D transistor includes a metal, and the gate dielectric of the first 3D transistor includes a high-k dielectric.
在一些實施方式中,第一3D電晶體或第二3D電晶體的3D半導體主體在平面圖中具有啞鈴形狀。In some embodiments, the 3D semiconductor body of the first 3D transistor or the second 3D transistor has a dumbbell shape in plan view.
在一些實施方式中,閘電極包括多晶矽。In some embodiments, the gate electrode includes polysilicon.
在一些實施方式中,閘極介電質包括氧化矽。In some embodiments, the gate dielectric includes silicon oxide.
在一些實施方式中,3D半導體主體的寬度大於10 nm。在一些實施方式中,3D半導體主體的寬度在30 nm和1000 nm之間。In some embodiments, the width of the 3D semiconductor body is greater than 10 nm. In some embodiments, the width of the 3D semiconductor body is between 30 nm and 1000 nm.
在一些實施方式中,3D半導體主體的高度大於40 nm。在一些實施方式中,3D半導體主體的高度在50 nm和1000 nm之間。In some embodiments, the height of the 3D semiconductor body is greater than 40 nm. In some embodiments, the height of the 3D semiconductor body is between 50 nm and 1000 nm.
在一些實施方式中,3D半導體主體的通道長度大於30 nm。在一些實施方式中,3D半導體主體的通道長度在50 nm和1500 nm之間。In some embodiments, the channel length of the 3D semiconductor body is greater than 30 nm. In some embodiments, the channel length of the 3D semiconductor body is between 50 nm and 1500 nm.
在一些實施方式中,閘極介電質的厚度大於1.8 nm。在一些實施方式中,閘極介電質的厚度在2 nm和100 nm之間。In some embodiments, the thickness of the gate dielectric is greater than 1.8 nm. In some embodiments, the thickness of the gate dielectric is between 2 nm and 100 nm.
在一些實施方式中,3D電晶體不包括應力源。In some embodiments, the 3D transistor does not include stressors.
在一些實施方式中,外圍電路不包括平面電晶體。In some implementations, the peripheral circuitry does not include planar transistors.
在一些實施方式中,外圍電路還包括平面電晶體。In some embodiments, the peripheral circuit further includes planar transistors.
在一些實施方式中,外圍電路還包括另一3D電晶體、另一平面電晶體、在3D電晶體與另一3D電晶體之間的第一溝槽隔離,以及在平面電晶體與另一平面電晶體之間的第二溝槽隔離。In some embodiments, the peripheral circuit further includes another 3D transistor, another planar transistor, a first trench isolation between the 3D transistor and the other 3D transistor, and a first trench isolation between the planar transistor and the other planar transistor. Second trench isolation between transistors.
在一些實施方式中,第一溝槽隔離和第二溝槽隔離具有相同深度。In some embodiments, the first trench isolation and the second trench isolation have the same depth.
在一些實施方式中,第一溝槽隔離和第二溝槽隔離具有不同深度。In some embodiments, the first trench isolation and the second trench isolation have different depths.
在一些實施方式中,第二溝槽隔離具有比第一溝槽隔離大的深度。In some embodiments, the second trench isolation has a greater depth than the first trench isolation.
在一些實施方式中,第一半導體結構還包括第一鍵合層,第一鍵合層包括多個第一鍵合觸點,第二半導體結構還包括第二鍵合層,第二鍵合層包括多個第二鍵合觸點,並且第一鍵合觸點與第二鍵合觸點在鍵合界面處接觸。In some embodiments, the first semiconductor structure further includes a first bonding layer, the first bonding layer includes a plurality of first bonding contacts, the second semiconductor structure further includes a second bonding layer, and the second bonding layer A plurality of second bonding contacts are included, and the first bonding contacts contact the second bonding contacts at a bonding interface.
在一些實施方式中,儲存單元陣列包括3D NAND記憶體串陣列。In some embodiments, the array of storage cells includes an array of 3D NAND memory strings.
根據本揭露內容的另一方面,一種系統包括被配置為儲存數據的儲存裝置。該儲存裝置包括:第一半導體結構,包括儲存單元陣列;第二半導體結構,包括外圍電路;以及鍵合界面,位於第一半導體結構和第二半導體結構之間。外圍電路包括3D電晶體。儲存單元陣列跨越鍵合界面耦接到外圍電路。所述系統還包括記憶體控制器,所述記憶體控制器耦接到儲存裝置且被配置為透過外圍電路控制儲存單元陣列。According to another aspect of the present disclosure, a system includes a storage device configured to store data. The storage device includes: a first semiconductor structure including a storage unit array; a second semiconductor structure including a peripheral circuit; and a bonding interface located between the first semiconductor structure and the second semiconductor structure. Peripheral circuits include 3D transistors. The memory cell array is coupled to peripheral circuits across the bonding interface. The system also includes a memory controller coupled to the storage device and configured to control the storage unit array through a peripheral circuit.
在一些實施方式中,所述系統還包括主機,所述主機耦接到記憶體控制器且被配置為發送或接收數據。In some implementations, the system also includes a host coupled to the memory controller and configured to send or receive data.
根據本揭露內容的又一方面,公開了一種用於形成3D儲存裝置的方法。在第一基底上形成包括儲存單元陣列的第一半導體結構。在第二基底上形成包括外圍電路的第二半導體結構。外圍電路包括3D電晶體。第一半導體結構和第二半導體結構以面對面的方式鍵合,使得儲存單元陣列跨越鍵合界面耦接到外圍電路。According to yet another aspect of the present disclosure, a method for forming a 3D storage device is disclosed. A first semiconductor structure including a memory cell array is formed on a first substrate. A second semiconductor structure including peripheral circuitry is formed on the second substrate. Peripheral circuits include 3D transistors. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, so that the storage cell array is coupled to the peripheral circuit across the bonding interface.
在一些實施方式中,為了形成第二半導體結構,從第二基底形成3D半導體主體,並且形成與3D半導體主體的多個側面接觸的閘極結構。In some embodiments, to form the second semiconductor structure, a 3D semiconductor body is formed from the second substrate, and a gate structure is formed in contact with a plurality of sides of the 3D semiconductor body.
在一些實施方式中,為了形成3D半導體主體,在第二基底中圍繞第二基底的一部分形成溝槽隔離,並且回蝕刻溝槽隔離以暴露第二基底的所述部分中的至少一部分。In some embodiments, to form the 3D semiconductor body, trench isolations are formed in the second substrate around a portion of the second substrate, and the trench isolations are etched back to expose at least a portion of the portion of the second substrate.
在一些實施方式中,為了形成3D半導體主體,在第二基底中圍繞第二基底的一部分形成溝槽,並且沉積隔離材料以部分地填充溝槽以暴露第二基底的所述部分中的至少一部分。In some embodiments, to form the 3D semiconductor body, a trench is formed in the second substrate surrounding a portion of the second substrate, and an isolation material is deposited to partially fill the trench to expose at least a portion of the portion of the second substrate .
在一些實施方式中,為了形成閘極結構,在3D半導體主體的多個側面上依序形成閘極介電質層和閘電極層,並且圖案化閘電極層以形成閘電極。In some embodiments, to form the gate structure, a gate dielectric layer and a gate electrode layer are sequentially formed on multiple sides of the 3D semiconductor body, and the gate electrode layer is patterned to form a gate electrode.
在一些實施方式中,閘極介電質層包括氧化矽,並且閘電極層包括多晶矽。In some embodiments, the gate dielectric layer includes silicon oxide, and the gate electrode layer includes polysilicon.
在一些實施方式中,為了形成第二半導體結構,在3D半導體主體中形成源極和汲極。In some embodiments, to form the second semiconductor structure, a source and a drain are formed in the 3D semiconductor body.
在一些實施方式中,為了形成源極和汲極,對3D半導體主體的未被閘電極覆蓋的部分進行摻雜。In some embodiments, the portion of the 3D semiconductor body not covered by the gate electrode is doped in order to form the source and drain.
在一些實施方式中,為了形成第一半導體結構,形成多個3D NAND記憶體串。In some embodiments, to form the first semiconductor structure, a plurality of 3D NAND memory strings are formed.
在一些實施方式中,為了形成第一半導體結構,在儲存單元陣列上方形成包括多個第一鍵合觸點的第一鍵合層。在一些實施方式中,為了形成第二半導體結構,在外圍電路上方形成包括多個第二鍵合觸點的第二鍵合層。在一些實施方式中,在鍵合之後,第一鍵合觸點與第二鍵合觸點在鍵合界面處接觸。In some embodiments, to form the first semiconductor structure, a first bonding layer including a plurality of first bonding contacts is formed over the array of memory cells. In some embodiments, to form the second semiconductor structure, a second bonding layer including a plurality of second bonding contacts is formed over the peripheral circuitry. In some embodiments, after bonding, the first bonding contact contacts the second bonding contact at the bonding interface.
在一些實施方式中,在鍵合之後在第一和第二基底中的一個基底上方的第一和第二基底中的另一基底被減薄,並且在經減薄的第一或第二基底上形成互連層。In some embodiments, the other of the first and second substrates over one of the first and second substrates is thinned after bonding, and the thinned first or second substrate form the interconnect layer.
在一些實施方式中,鍵合包括混合鍵合。
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。
In some embodiments, bonding comprises hybrid bonding.
The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.