TW202301686A - Semiconductor device - Google Patents

Abstract

The present invention provides a semiconductor device that is particularly useful as a power device and has reduced element resistance. Provided is a semiconductor device that comprises: an oxide semiconductor layer that includes at least one source region; and a source electrode that is arranged on the source region. The source region comprises at least: an n+ semiconductor layer; and an n++ semiconductor layer that is arranged on the n+ semiconductor layer and has a greater carrier density than the n+ semiconductor layer. The n++ semiconductor layer is an epitaxial layer.

Description

Semiconductor device

The present invention relates to a semiconductor device usable as a power element or the like.

Gallium oxide (Ga ₂ O ₃ ) has a wide energy gap of 4.8-5.3 eV at room temperature, and is a transparent semiconductor that hardly absorbs visible light and ultraviolet light. Therefore, it is especially expected to be used for optical/electronic components operating in the deep ultraviolet region and for transparent electronic materials. In recent years, people have been developing photosensors based on gallium oxide (Ga ₂ O ₃ ), Light-emitting diodes (LEDs) and transistors (see Non-Patent Document 1). According to Patent Document 4, the energy gap can be controlled by using gallium oxide, indium, aluminum, or a combination thereof as a mixed crystal, and an attractive material system can be constituted as an InAlGaO-based semiconductor. Here, the InAlGaO-based semiconductor system means In _X Al _Y Ga _Z O ₃ (0≤X≤2, 0≤Y≤2, 0≤Z≤2, X+Y+Z=1.5～2.5), which can be regarded as The same material system containing gallium oxide.

Gallium oxide (Ga ₂ O ₃ ) has five crystal structures of α, β, γ, σ, and ε, and generally, the most stable structure is β-Ga ₂ O ₃ . However, β-Ga ₂ O ₃ has a β-gallia structure, and thus is not necessarily suitable for use in semiconductor devices, unlike crystal systems generally used for electronic materials and the like. In addition, the growth of the β-Ga ₂ O ₃ thin film requires a high substrate temperature and a high degree of vacuum, so there is also a problem that the production cost increases. Also, as described in Non-Patent Document 2, in β-Ga ₂ O ₃ , even if the dopant (Si) has a high concentration (for example, 1×10 ¹⁹ /cm ³ or more), after ion implantation, if the concentration is not increased by 800 ℃ ~ 1100 ℃ high temperature annealing, also can not be used as a donor. On the other hand, α-Ga ₂ O ₃ is suitable for use in optical/electronic devices because it has _the same crystal structure as the sapphire substrate that has been used in general, and _because it has a wider energy gap than element is particularly useful, so a semiconductor device using α-Ga ₂ O ₃ as a semiconductor is currently expected.

Patent _Documents 1 and 2 describe a semiconductor device in which β- _Ga2O3 is used as a semiconductor, and two layers consisting of a Ti layer and an Au layer, and three layers consisting of a Ti layer, an Al layer, and an Au layer are used , or four layers consisting of a Ti layer, an Al layer, a Ni layer and an Au layer as an electrode that can obtain ohmic characteristics suitable for the semiconductor. Also, Patent Document 3 describes a semiconductor device in which β- _Ga2O3 is used as a semiconductor, and _any one of Au, Pt, or a laminate of Ni and Au is used as an electrode capable of obtaining Schottky characteristics suitable for the semiconductor. . However, when the electrodes described in Patent Documents 1 to 3 are applied to a semiconductor device using α-Ga ₂ O ₃ as a semiconductor, they may not function as a Schottky electrode or an ohmic electrode, or the metal electrode may be separated from the semiconductor film. Problems such as delamination and loss of semiconductor characteristics. Furthermore, when the electrode configurations described in Patent Documents 1 to 3 are applied to, for example, a source electrode of a MOSFET, there is a problem that the source contact resistance and the source resistance cannot be sufficiently reduced. [Prior Art Document] [Patent Document]

[Patent Document 1] Japanese Unexamined Patent Publication No. 2005-260101 [Patent Document 2] Japanese Unexamined Patent Publication No. 2009-81468 [Patent Document 3] Japanese Unexamined Patent Publication No. 2013-12760 [Patent Document 4] International Publication No. 2014/050793 [Non-patent literature]

[Non-Patent Document 1] Jun Liang Zhao et al, "UV and Visible Electroluminescence From a Sn:Ga2O3/n+-Si Heterojunction by Metal-Organic Chemical Vapor Deposition", IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO.5 MAY 2011 [Non-Patent Document 2] Kohei Sasaki et al, "Si-Ion Implantation Doping in β-Ga2O3 and d Its Application to Fabrication of Low-Resistance Ohmic Contacts", Applied Physics Express 6 (2013) 086502

[Problem to be Solved by the Invention]

An object of the present invention is to provide a semiconductor element with reduced element resistance. [Means to solve the problem]

The inventors of the present application made detailed studies to achieve the above object, and as a result, found that in a semiconductor device including an oxide semiconductor layer including at least a source region and a source electrode disposed on the source region, the source region includes at least an n + -type semiconductor device. A semiconductor layer and an n++ type semiconductor layer disposed on the n+ type semiconductor layer and having a carrier density greater than that of the n+ type semiconductor layer, such a semiconductor device, compared with the case where the n++ type semiconductor layer is not provided, its element resistance is reduced; so The obtained semiconductor device can solve the above-mentioned conventional problems. In addition, the inventors of the present application, having learned the above-mentioned findings, made further studies and completed the present invention.

That is, the present invention relates to the following inventions. [1] A semiconductor device comprising an oxide semiconductor layer including at least a source region, and a source electrode arranged on the source region, wherein the source region includes at least an n+ type semiconductor layer and is arranged on the n+ type semiconductor layer. An n++ type semiconductor layer on the layer with a higher carrier density than the n+ type semiconductor layer. [2] The semiconductor device according to [1], wherein the n+ type semiconductor layer and the n++ type semiconductor layer have the same crystal structure. [3] The semiconductor device according to [1] or [2], wherein the n+ type semiconductor layer and the n++ type semiconductor layer have the same main component. [4] The semiconductor device according to any one of [1] to [3], wherein the n++ type semiconductor layer is an epitaxial layer. [5] The semiconductor device according to [4], wherein the n++ type semiconductor layer is epitaxially doped. [6] The semiconductor device according to any one of [1] to [5], wherein the carrier density of the n++ type semiconductor layer is 1.0×10 ¹⁹ /cm ³ or more. [7] The semiconductor device according to any one of [1] to [6], wherein the carrier density of the n+ type semiconductor layer is in the range of 1.0×10 ¹⁷ /cm ³ to less than 1.0×10 ¹⁹ /cm ³ . [8] The semiconductor device according to any one of [1] to [7], wherein the n++ type semiconductor layer has a thickness in the range of 1 nm to 1 μm. [9] The semiconductor device according to any one of [1] to [8], wherein the n+ type semiconductor layer is thicker than the n++ type semiconductor layer. [10] The semiconductor device according to any one of [1] to [9], wherein the mobility of the n+ type semiconductor layer is greater than the mobility of the n++ type semiconductor layer. [11] The semiconductor device according to any one of [1] to [10], wherein the n+ type semiconductor layer is an epitaxial layer. [12] The semiconductor device according to any one of [1] to [11], wherein the oxide semiconductor layer further includes a channel layer on which a gate electrode is arranged via a gate insulating film. [13] The semiconductor device according to [12], wherein the lower end of the n++ type semiconductor layer is located above the lower end of the gate insulating film. [14] The semiconductor device according to [12] or [13], wherein the distance from the outer end of the gate insulating film to the inner end of the n + -type semiconductor layer is 10 μm or less. [15] The semiconductor device according to [12], wherein the channel layer has a trench, and at least a part of the gate electrode is embedded in the trench. [16] The semiconductor device according to any one of [1] to [15], which is a transistor. [17] The semiconductor device according to any one of [1] to [16], which is a power element. [18] A power conversion device using the semiconductor device according to any one of [1] to [17]. [19] A control system using the semiconductor device according to any one of [1] to [18]. [Effect of Invention]

According to the present invention, it is possible to provide a semiconductor device with reduced element resistance.

The semiconductor device of the present invention includes an oxide semiconductor layer including at least a source region, and a source electrode arranged on the source region, and the semiconductor device is characterized in that the source region includes at least an n+ type semiconductor layer and is arranged on An n++ type semiconductor layer on the n+ type semiconductor layer and having a higher carrier density than the n+ type semiconductor layer.

The aforementioned oxide semiconductor layer is not particularly limited as long as it does not hinder the object of the present invention. In an embodiment of the present invention, the aforementioned semiconductor layer preferably contains a crystalline oxide semiconductor as a main component. Examples of the crystalline oxide semiconductor include metal oxides containing one or two or more metals selected from the group consisting of aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium. . In the embodiment of the present invention, the aforementioned crystalline oxide semiconductor preferably contains at least one metal selected from aluminum, indium, and gallium, more preferably at least gallium, most preferably α-Ga ₂ O ₃ or a mixture thereof crystal. According to the embodiments of the present invention, for example, even when a semiconductor with a large energy gap such as gallium oxide or its mixed crystal is used, the insulation withstand voltage can be improved and the device resistance, especially the contact resistance, can be reduced. The crystal structure of the aforementioned oxide semiconductor layer is not particularly limited as long as it does not hinder the object of the present invention. Examples of the crystal structure of the oxide semiconductor layer include corundum structure, β-gallia structure, hexagonal crystal structure (e.g. ε-type structure, etc.), rectangular crystal structure (e.g. κ-type structure, etc.), cubic crystal structure, or tetragonal crystal structure. structure etc. In an embodiment of the present invention, the aforementioned crystalline oxide semiconductor preferably has a corundum structure, a β-gallia structure or a hexagonal crystal structure (such as an ε-type structure, etc.), and more preferably has a corundum structure. In addition, the so-called "main component" is an atomic ratio, and preferably contains 50% or more of the above-mentioned crystalline oxide semiconductor, more preferably 70% or more, with respect to all the components of the above-mentioned oxide semiconductor layer. More preferably, it contains 90% or more, and may be 100%. Also, the thickness of the oxide semiconductor layer is not particularly limited, and may be 1 μm or less, or 1 μm or more, but in the embodiment of the present invention, it is preferably 10 μm or more. The surface area of the aforementioned semiconductor film is not particularly limited, and may be greater than or equal to 1 mm ² or less than 1 mm ² , but is preferably 10 mm ² to 300 cm ² , more preferably 100 mm ² to 100 cm ² . In addition, the aforementioned semiconductor layer is usually single crystal, but may be polycrystalline. In addition, the aforementioned oxide semiconductor layer usually includes two or more semiconductor layers. The aforementioned oxide semiconductor layer includes, for example, an n+ type semiconductor layer, an n-type semiconductor layer (drift layer), a p-type semiconductor layer (current blocking layer), an n-type semiconductor layer (channel layer), and an n+ type semiconductor layer as a source region. type semiconductor layer and n++ type semiconductor layer. In addition, the carrier density of the aforementioned oxide semiconductor layer can be appropriately set by adjusting the amount of doping.

The aforementioned oxide semiconductor layer preferably contains a dopant. The above-mentioned dopant is not particularly limited and may be known. In the implementation mode of the present invention, especially in the case where the aforementioned semiconductor layer contains gallium-containing crystalline oxide as the main component, preferred examples of the aforementioned dopant include, for example: tin, germanium, silicon, titanium, zirconium , n-type dopants such as vanadium or niobium, or p-type dopants such as magnesium, calcium, zinc, etc. In an embodiment of the present invention, the aforementioned n-type dopant is preferably at least one selected from Sn, Ge and Si. The content of the dopant in the composition of the semiconductor layer is preferably at least 0.00001 atomic %, more preferably 0.00001 atomic % to 20 atomic %, most preferably 0.00001 atomic % to 10 atomic %. More specifically, the concentration of the dopant can generally be about 1×10 ¹⁶ /cm ³ to 1×10 ²² /cm ³ , and the concentration of the dopant can also be lower than about 1×10 ¹⁷ /cm ³ low concentration. Furthermore, according to the present invention, a dopant may be contained at a high concentration of about 1×10 ²⁰ /cm ³ or more. In the embodiment of the present invention, it is preferable to contain the dopant at a carrier concentration of 1×10 ¹⁷ /cm ³ or more.

The source region is not particularly limited as long as it includes at least an n+ type semiconductor layer and an n++ type semiconductor layer disposed on the n+ type semiconductor layer and having a higher carrier density than the n+ type semiconductor layer. In addition, the carrier density can be obtained using a known method. As a method for obtaining the aforementioned carrier density, for example, SIMS (Secondary Ion Mass Spectrometry), SCM (Scanning Capacitance Microscopy), SMM (Scanning Microwave Microscopy), and SRA (Spreading Resistance Measurement) wait. The main components of the n+ type semiconductor layer and the n++ type semiconductor layer may be the same or different. In an embodiment of the present invention, preferably, the main component of the aforementioned n+ type semiconductor layer is the same as the main component of the aforementioned n++ type semiconductor layer. In addition, in the embodiment of the present invention, the aforementioned n+ type semiconductor layer and the aforementioned n++ type semiconductor layer preferably have the same crystal structure, more preferably the aforementioned n+ type semiconductor layer and the aforementioned n++ type semiconductor layer have a corundum structure. In addition, here, the so-called "main component", for example, when the main component of the aforementioned n+ type semiconductor layer is gallium oxide, as long as the atomic ratio of gallium in all metal elements in the aforementioned n+ type semiconductor layer is 50% or more Contains gallium. In the embodiment of the present invention, the atomic ratio of gallium in all metal elements in the aforementioned n+ type semiconductor layer is preferably more than 70%, more preferably more than 90%, or 100%. In an embodiment of the present invention, the aforementioned n++ type semiconductor layer is preferably an epitaxial layer, more preferably the aforementioned n++ type semiconductor layer is epitaxially doped. By using the aforementioned preferred n++ type semiconductor layer, the contact resistance can be reduced more favorably. Here, the so-called epitaxial doping is not doping by ion implantation, but doping by epitaxial growth, for example. As the n-type dopant contained in the aforementioned n+ type semiconductor layer and/or the aforementioned n++ type semiconductor layer, for example: at least one n-type dopant selected from tin, germanium, silicon, titanium, zirconium, vanadium and niobium Sundries etc. In an embodiment of the present invention, the aforementioned n-type dopant is preferably at least one selected from Sn, Ge and Si. The carrier density of the n++ type semiconductor layer is not particularly limited as long as it is higher than the carrier density of the n+ type semiconductor layer. In an embodiment of the present invention, the carrier density of the aforementioned n++ type semiconductor layer is preferably above 1.0×10 ¹⁹ /cm ³ , more preferably above 6.0×10 ¹⁹ /cm ³ . By setting the carrier density of the n++ type semiconductor layer to such a preferable value, the contact resistance can be reduced more favorably. Also, the carrier density of the aforementioned n+ type semiconductor layer is not particularly limited. In an embodiment of the present invention, the carrier density of the aforementioned n+ type semiconductor layer is preferably in the range of 1.0×10 ¹⁷ /cm ³ to less than 1.0×10 ¹⁹ /cm ³ . By setting the carrier density of the n+ type semiconductor layer within the above preferred range, the source resistance can be reduced more favorably. In addition, in the embodiments of the present invention, the method of doping the aforementioned n+ type semiconductor layer is not particularly limited, and may be diffusion or ion implantation, or epitaxial growth. In an embodiment of the present invention, the mobility of the aforementioned n+ type semiconductor layer is preferably greater than the mobility of the aforementioned n++ type semiconductor layer. The thickness of the n++ type semiconductor layer is not particularly limited as long as it does not hinder the object of the present invention. In the embodiment of the present invention, the thickness of the aforementioned n++ type semiconductor layer is preferably in the range of 1 nm˜1 μm, more preferably in the range of 10 nm˜100 nm. In an embodiment of the present invention, the thickness of the aforementioned n+ type semiconductor layer is preferably greater than the thickness of the aforementioned n++ type semiconductor layer. By making the above-mentioned n+ type semiconductor layer and the above-mentioned n++ type semiconductor layer into the above-mentioned preferred combination, the source contact resistance and source electrode resistance in the above-mentioned semiconductor device can be reduced more favorably, so the above-mentioned semiconductor device with further reduced element resistance can be realized. device.

The aforementioned oxide semiconductor layer can be formed using known means. Examples of the means for forming the semiconductor layer include CVD, MOCVD, MOVPE, atomization CVD, atomization/epitaxy, MBE, HVPE, pulse growth, and ALD. In an embodiment of the present invention, the aforementioned semiconductor layer is preferably formed by MOCVD, atomization CVD, atomization/epitaxy or HVPE, more preferably atomization CVD or atomization/epitaxy. In the aforementioned atomization CVD method or atomization/epitaxy method, for example, using the atomization CVD device shown in Figure 7, the raw material solution is atomized (atomization step), the droplets are floated, and after atomization, the carrier gas is carried The obtained atomized liquid droplets are held and transported onto a substrate (transportation step), and then the atomized liquid droplets are thermally reacted in the vicinity of the substrate, thereby depositing a layer on the substrate containing a crystalline oxide semiconductor as a main component. A semiconductor film (film forming step), whereby the aforementioned semiconductor layer is formed.

(atomization step) The atomization step is to atomize the aforementioned raw material solution. The atomization means of the aforementioned raw material solution is not particularly limited as long as the aforementioned raw material solution can be atomized, and conventional means can be used. In the embodiment of the present invention, the atomization means using ultrasonic waves is preferred. The atomized liquid droplets obtained by using ultrasonic waves have an initial velocity of zero and float in the air, so it is better. For example, it is not blown in the form of a spray, but can float in the space as a mist transported by gas, so it will not be due to collision. Excellent energy for damage. The droplet size is not particularly limited, and may be a droplet of about several mm, preferably 50 μm or less, more preferably 100 nm to 10 μm.

(raw material solution) The raw material solution is not particularly limited as long as it contains a material capable of forming a semiconductor film by atomization or droplet formation, and may be an inorganic material or an organic material. In the embodiment of the present invention, the aforementioned raw material is preferably a metal or a metal compound, and more preferably contains one or more selected from the group consisting of aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium. 2 or more metals.

In an embodiment of the present invention, as the aforementioned raw material solution, one obtained by dissolving or dispersing the aforementioned metal in an organic solvent or water in the form of a complex or a salt can be preferably used. The form of the complex includes, for example, an acetylacetone complex, a carbonyl complex, an ammonia complex, a hydride complex, and the like. As the form of the salt, for example: organic metal salts (such as acetate metal salts, oxalate metal salts, citrate metal salts, etc.), metal sulfide salts, nitration metal salts, phosphorus oxide metal salts, halide metal salts (such as Chloride metal salts, bromide metal salts, iodide metal salts, etc.) etc.

Moreover, it is preferable to mix additives, such as a hydrohalic acid or an oxidizing agent, in the said raw material solution. Examples of the hydrohalic acid include hydrobromic acid, hydrochloric acid, and hydroiodic acid. Among them, hydrobromic acid or hydroiodic acid is preferred because they can more efficiently suppress the generation of abnormal particles. Examples of the oxidizing agent include hydrogen peroxide (H ₂ O ₂ ), sodium peroxide (Na ₂ O ₂ ), barium peroxide (BaO ₂ ), benzoyl peroxide (C ₆ H ₅ CO) ₂ O Class ₂ peroxides, hypochlorous acid (HClO), perchloric acid, nitric acid, ozone water, peracetic acid or organic peroxides such as nitrobenzene, etc.

A dopant may also be contained in the aforementioned raw material solution. Doping can be performed favorably by making a raw material solution contain a dopant. The aforementioned dopant is not particularly limited as long as it does not hinder the object of the present invention. Examples of the aforementioned dopant include n-type dopant such as tin, germanium, silicon, titanium, zirconium, vanadium, or niobium, or Mg, H, Li, Na, K, Rb, Cs, Fr, Be, Ca , Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Ti, Pb, N, or P and other p-type dopants, etc. The content of the aforementioned dopant can be appropriately set by using a calibration curve showing the concentration of the dopant in the raw material versus the expected carrier density.

The solvent of the raw material solution is not particularly limited, and may be an inorganic solvent such as water, an organic solvent such as alcohol, or a mixed solvent of an inorganic solvent and an organic solvent. In an embodiment of the present invention, the aforementioned solvent is preferably water, more preferably water or a mixed solvent of water and alcohol.

(shipping steps) In the transporting step, the aforementioned atomized liquid droplets are carried by a carrier gas and transported into the film forming chamber. The carrier gas is not particularly limited as long as it does not hinder the object of the present invention. Preferred examples include inert gases such as oxygen, ozone, nitrogen, and argon, and reducing gases such as hydrogen and synthesis gas. Also, the type of carrier gas may be one type, or two or more types, and a dilution gas with a reduced flow rate (for example, a 10-fold dilution gas, etc.) may be further used as the second carrier gas. In addition, the carrier gas supply point may be not only one point but two or more points. The flow rate of the carrier gas is not particularly limited, but is preferably 0.01-20 L/min, more preferably 1-10 L/min. In the case of the diluent gas, the flow rate of the diluent gas is preferably from 0.001 to 2 L/min, more preferably from 0.1 to 1 L/min.

(film formation step) In the film forming step, the aforementioned semiconductor film is formed on the substrate by thermally reacting the atomized liquid droplets in the vicinity of the aforementioned substrate. The thermal reaction is not particularly limited as long as the atomized liquid droplets are reacted with heat, and the reaction conditions and the like are not particularly limited as long as they do not hinder the object of the present invention. In this step, the above-mentioned thermal reaction is usually carried out at a temperature above the evaporation temperature of the solvent, preferably below a temperature that is not too high (for example, 1000° C.), more preferably below 650° C., and most preferably between 300° C. and 650° C. . Also, as long as the thermal reaction does not hinder the purpose of the present invention, it can be carried out under any environment under vacuum, under a non-oxygen environment (such as under an inert gas environment, etc.), under a reducing gas environment, and under an oxygen environment, but preferably The system is carried out in an inert gas environment or an oxygen environment. Moreover, it can carry out under any conditions of atmospheric pressure, pressurization, and reduced pressure, and it is preferable to carry out under atmospheric pressure in embodiment of this invention. In addition, the film thickness can be set by adjusting the film forming time.

(substrate) The base is not particularly limited as long as it can support the semiconductor film. The material of the aforementioned substrate is not particularly limited as long as it does not hinder the object of the present invention, and may be a known substrate, an organic compound, or an inorganic compound. The shape of the above-mentioned substrate may be any shape, and it is effective for all shapes, for example: plate shape such as flat plate or disc, fiber shape, rod shape, column shape, prism shape, cylindrical shape, spiral shape, spherical shape, ring shape etc. In the embodiment of the present invention, it is preferably a substrate. The thickness of the substrate is not particularly limited in the embodiments of the present invention.

The substrate is not particularly limited as long as it is plate-shaped and serves as a support for the semiconductor film. It may be an insulator substrate, a semiconductor substrate, or a metal substrate or a conductive substrate, but the aforementioned substrate is preferably an insulator substrate, and a substrate having a metal film on its surface is also preferable. As the aforementioned substrate, for example, an underlying substrate comprising a substrate material having a corundum structure as a main component, an underlying substrate comprising a substrate material having a β-gallia structure as a main component, a substrate material comprising a hexagonal crystal structure as a main component, etc. composition of the underlying substrate, etc. Here, "main component" refers to the substrate material having the above-mentioned specific crystal structure preferably containing 50% or more, more preferably containing 70% or more, and even more preferably Contains more than 90%, can also be 100%.

The substrate material is not particularly limited as long as it does not hinder the object of the present invention, and known materials can be used. As the aforementioned substrate material having a corundum structure, for example, α-Al ₂ O ₃ (sapphire substrate) or α-Ga ₂ O ₃ , and a-plane sapphire substrate, m-plane sapphire substrate, r-plane More preferable examples include a sapphire substrate, a c-plane sapphire substrate, or an α-type gallium oxide substrate (a-plane, m-plane, or r-plane). The underlying substrate with a substrate material having a β-gallia structure as a main component, for example: a β-Ga ₂ O ₃ substrate, or a substrate containing Ga ₂ O ₃ and Al ₂ O ₃ with more than 0 wt% of Al ₂ O ₃ and Mixed crystal substrates below 60wt%. Furthermore, examples of the base substrate mainly composed of a substrate material having a hexagonal crystal structure include SiC substrates, ZnO substrates, and GaN substrates.

In the embodiment of the present invention, annealing treatment may also be performed after the aforementioned film forming step. The annealing treatment temperature is not particularly limited as long as it does not hinder the object of the present invention, but it is usually 300°C to 650°C, preferably 350°C to 550°C. Also, the annealing treatment time is generally 1 minute to 48 hours, preferably 10 minutes to 24 hours, more preferably 30 minutes to 12 hours. In addition, the annealing treatment can be performed under any circumstances as long as the object of the present invention is not hindered. It can be in a non-oxygen environment or in an oxygen environment. The non-oxygen environment includes, for example, an inert gas environment (such as a nitrogen environment) or a reducing gas environment. In the embodiment of the present invention, it is preferably in an inert gas environment, more preferably in a nitrogen environment.

Also, in the embodiment of the present invention, the aforementioned semiconductor film may be directly provided on the aforementioned substrate, or the aforementioned semiconductor film may be provided via other layers such as a stress relaxation layer (such as a buffer layer, an ELO layer, etc.), a lift-off sacrifice layer, or the like. The formation method of each layer is not particularly limited, and a known method can also be used, but in the embodiment of the present invention, atomization CVD method is preferred.

In an embodiment of the present invention, the aforementioned semiconductor film may be used in a semiconductor device as the aforementioned semiconductor layer after being peeled off from the aforementioned substrate or the like by conventional means, or may be used directly as the aforementioned semiconductor layer in a semiconductor device.

The aforementioned source electrode is not particularly limited as long as it has conductivity and does not hinder the object of the present invention. The constituent material of the aforementioned source electrode may be a conductive inorganic material or a conductive organic material. In an embodiment of the present invention, the material of the aforementioned source electrode is preferably metal. As the metal, for example, at least one metal selected from Groups 4 to 10 of the Periodic Table is suitable. Examples of metals of Group 4 of the periodic table include titanium (Ti), zirconium (Zr), hafnium (Hf), and the like. Examples of metals in Group 5 of the periodic table include vanadium (V), niobium (Nb), tantalum (Ta), and the like. Examples of metals of Group 6 of the periodic table include chromium (Cr), molybdenum (Mo), and tungsten (W). Examples of metals of Group 7 of the periodic table include manganese (Mn), tungsten (Tc), rhenium (Re), and the like. Examples of metals in Group 8 of the periodic table include iron (Fe), ruthenium (Ru), osmium (Os), and the like. Examples of metals of Group 9 of the periodic table include cobalt (Co), rhodium (Rh), iridium (Ir), and the like. The metal of Group 10 of the periodic table includes, for example, nickel (Ni), palladium (Pd), platinum (Pt) and the like. In an embodiment of the present invention, the aforementioned source electrode preferably includes at least one metal selected from titanium (Ti), tantalum (Ta) and tungsten (W). Moreover, in an embodiment of the present invention, the aforementioned source electrode may also include a conductive metal oxide. Examples of the conductive metal oxide contained in the source electrode include metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and zinc indium oxide (IZO). The aforementioned source electrode may be composed of a single layer, or may include multiple metal layers. When the aforementioned source electrode comprises multiple metal layers, for example, it is preferable to use Group 4 metals of the Periodic Table for the first and third layers, and Group 13 metals of the Periodic Table (for example, Al, etc.) for the first and third layers. Layer 2 between layers 3 and 3. The reliability of the ohmic characteristic between the source electrode/source region can be further improved by using the source electrode with such a preferable structure. The method for forming the aforementioned source electrode is not particularly limited. Specific examples of the method for forming the source electrode include a dry method, a wet method, and the like. As a dry method, sputtering, vacuum deposition, CVD etc. are mentioned, for example. As a wet method, screen printing, die coating, etc. are mentioned, for example.

In an embodiment of the present invention, the oxide semiconductor layer further includes a channel layer, and preferably a gate electrode is disposed on the channel layer via the gate insulating film. The constituent material of the aforementioned channel layer may be the same as the constituent material of the aforementioned oxide semiconductor layer. Also, the conductivity type of the aforementioned channel layer is not particularly limited, and may be n-type or p-type. When the conductivity type of the channel layer is n-type, examples of the material constituting the channel layer include α-Ga ₂ O ₃ or mixed crystals thereof. Also, when the conductivity type of the aforementioned channel layer is p-type, as the constituent material of the aforementioned channel layer, it is preferable to include, for example, α- _Ga2O3 containing a p-type dopant or its mixed crystal, and a compound selected from the 9th column of the periodic table _. Metal oxides of at least one metal in the group (for example, α-Ir ₂ O ₃ , α-Cr ₂ O ₃ , α-Rh ₂ O ₃ ), and the like. In addition, the metal oxide containing at least one metal selected from Group 9 of the periodic table may also be a mixed crystal with other metal oxides such as Ga ₂ O ₃ .

The constituent material of the aforementioned gate insulating film is not particularly limited, and may be a known material. As the material of the aforementioned gate insulating film, for example, _SiO2 film, polysilicon film, phosphorus-doped _SiO2 film (PSG film), boron-doped _SiO2 film, phosphorus-boron-doped _SiO2 film (BPSG film), etc. )wait. Examples of methods for forming the gate insulating film include CVD, atmospheric pressure CVD, plasma CVD, and atomization CVD. In an embodiment of the present invention, the method for forming the aforementioned gate insulating film is preferably an atomization CVD method or an atmospheric pressure CVD method. In addition, the constituent material of the aforementioned gate electrode is not particularly limited, and may be a known electrode material. As a constituent material of the said gate electrode, the constituent material of the said source electrode etc. are mentioned, for example. The method for forming the aforementioned gate electrode is not particularly limited. As a method of forming the aforementioned gate electrode, specifically, a dry method, a wet method, and the like are exemplified. As a dry method, sputtering, vacuum deposition, CVD etc. are mentioned, for example. As a wet method, screen printing, die coating, etc. are mentioned, for example. In the embodiment of the present invention, the lower end of the n++ layer is located above the lower end of the gate insulating film, so that the element resistance of the semiconductor device can be better reduced, so it is preferable. Also, in an embodiment of the present invention, the distance from the outer end of the gate insulating film to the inner end of the n+ type semiconductor layer is preferably 10 μm or less, more preferably 5 μm or less. By forming such a preferable configuration, the source resistance can be further reduced.

The semiconductor device of the present invention can be used for various semiconductor elements, and especially can be used for power elements. In addition, semiconductor elements can be classified into lateral elements (horizontal elements) in which electrodes are formed on one side of the semiconductor layer and current flows in a direction perpendicular to the film thickness direction of the semiconductor layer, and lateral elements in which electrodes are formed on both the surface and the back surface of the semiconductor layer. A vertical element (vertical element) that has electrodes on each side and current flows in the film thickness direction of the semiconductor layer. In the embodiment of the present invention, the above-mentioned semiconductor element can be preferably used regardless of whether it is a horizontal element or a vertical element. , which is preferably used for vertical components. Examples of the aforementioned semiconductor elements include metal semiconductor field effect transistors (MESFETs), high electron mobility transistors (HEMTs), metal oxide film semiconductor field effect transistors (MOSFETs), static induction transistors (SIT), and junction field transistors. Transistor (JFET) or Insulated Gate Bipolar Transistor (IGBT). In an embodiment of the present invention, the aforementioned semiconductor device is preferably a MOSFET, a SIT, a JFET or an IGBT, more preferably a MOSFET or an IGBT.

Hereinafter, preferred examples of the aforementioned semiconductor devices will be described using the drawings, but the present invention is not limited to these embodiments. In addition, in the semiconductor device exemplified below, as long as the object of the present invention is not hindered, other layers (such as an insulator layer, a semi-insulator layer, a conductor layer, a semiconductor layer, a buffer layer, or other intermediate layers, etc.) may be further included. A buffer layer (buffer layer) and the like may be appropriately omitted.

FIG. 1 shows the main part of a metal oxide semiconductor field effect transistor (MOSFET) which is one of the preferred embodiments of the present invention. The MOSFET shown in Fig. 1 has a drain electrode 5c, an n+ type semiconductor layer 3, an n-type semiconductor layer 7 as a drift layer, a p-type semiconductor layer 2 as a current blocking layer, a channel layer 6, and an n+ type semiconductor layer as a source region. The semiconductor layer 1a and the n++ type semiconductor layer 1b, the gate insulating film 4, the gate electrode 5a and the source electrode 5b. The aforementioned n++ type semiconductor layer 1b is an epitaxial layer formed on the aforementioned n+ type semiconductor layer 1a by epitaxial growth. Here, the aforementioned n+ type semiconductor layer 3 , n − type semiconductor layer 7 , channel layer 6 , p type semiconductor layer 2 , n+ type semiconductor layer 1 a and n++ type semiconductor layer 1 b constitute an oxide semiconductor layer 8 . The carrier density of the n+ type semiconductor layer 1a is in the range of 1.0×10 ¹⁸ /cm ³ to less than 1.0×10 ¹⁹ /cm ³ . Furthermore, the carrier density of the n++ type semiconductor layer 1b is above 1.0×10 ¹⁹ /cm ³ , preferably in the range of 1.0×10 ¹⁹ /cm ³ to 1.0×10 ²⁰ /cm ³ . In addition, the aforementioned p-type semiconductor layer 2 may be a high-resistance layer (for example, a resistivity of 1.0×10 ¹⁰ Ω·cm or more). In the embodiment of the present invention, the epitaxial layer formed by epitaxially doping the n++ type semiconductor layer 1b is used as the source region 1, so a high concentration (for example, above 1.0×10 ¹⁹ /cm ³ ) can be realized. n++ type semiconductor layer 1b. Therefore, even if a material such as gallium oxide (especially α-Ga ₂ O ₃ ) is used, which is difficult to increase the carrier density by ion implantation, the source contact resistance can be reduced. In addition, in the embodiment of the present invention, an n+ type semiconductor layer and an n++ type semiconductor layer 1 b epitaxially grown on the n+ type semiconductor layer are used as the source region 1 . By forming such a structure, the source resistance of the whole source region can be reduced. In addition, in the embodiment of the present invention, it is preferable to make the mobility of the n+ type semiconductor layer greater than the mobility of the n++ type semiconductor layer. According to such a preferable structure, the source resistance of the said source region can be reduced more favorably. In addition, in the embodiment of the present invention, the distance a from the outer end of the gate insulating film 4 to the inner end of the n+ type semiconductor layer 1a is preferably 10 μm or less, more preferably 5 μm or less. By forming such a preferable configuration, the source resistance can be further reduced. In addition, as another preferred implementation, in the semiconductor device shown in FIG. 1 , at least a part of the n+ type semiconductor layer 1 a and/or the n++ type semiconductor layer 1 b is buried in the channel layer 6 . An example of the case where the n+ type semiconductor layer 1a and the n++ type semiconductor layer 1b are buried in the channel layer 6 is shown in FIG. 13 . According to the structure shown in FIG. 13 , the electric field applied to the gate insulating film is less prone to electric field concentration, and the reliability of the gate insulating film can be further improved. Also, an example of the case where the n+ type semiconductor layer 1a is buried in the channel layer 6 is shown in FIG. 14 .

FIG. 2 shows the main part of a metal oxide semiconductor field effect transistor (MOSFET) which is one of the preferred embodiments of the present invention. The MOSFET in FIG. 2 is different from the MOSFET in FIG. 1 in that the channel layer 6 has a trench, and at least a part of the gate electrode 5a is embedded in the trench. In the embodiment of the present invention, as the aforementioned source region 1, the n++ type semiconductor layer 1b is an epitaxial layer that has undergone epitaxial doping, so a higher concentration (for example, above 1.0×10 ¹⁹ /cm ³ ) can be realized. n++ type semiconductor layer 1b. Therefore, even if a material such as gallium oxide (especially α-Ga ₂ O ₃ ) is used that is difficult to increase its concentration by ion implantation, the source contact resistance can be reduced. In addition, in the embodiment of the present invention, an n+ type semiconductor layer and an n++ type semiconductor layer 1 b epitaxially grown on the n+ type semiconductor layer are used as the source region 1 . By forming such a structure, the source resistance of the whole source region can be further reduced. In addition, in the embodiment of the present invention, it is preferable to make the mobility of the n+ type semiconductor layer greater than the mobility of the n++ type semiconductor layer. According to such a preferable structure, the source resistance of the said source region can be reduced more favorably.

The formation means of each layer in FIG. 1 and FIG. 2 is not particularly limited as long as it does not hinder the object of the present invention, and known means can be used. Examples include methods of patterning by photolithography after film formation by vacuum deposition, CVD, sputtering, and various coating techniques, or direct patterning using printing techniques.

Hereinafter, the present invention will be described in more detail using a preferred example of manufacturing the semiconductor device shown in FIG. 1 . FIG. 3( a ) shows a laminated structure in which n+ type semiconductor layer 3 , n− type semiconductor layer 7 and p type semiconductor layer 2 are sequentially stacked on substrate 9 . The aforementioned p-type semiconductor layer 2 may be a high-resistance layer. The aforementioned p-type semiconductor layer 2 is patterned using known patterning techniques. The channel layer 6, the n+ type semiconductor layer 1a as the source region, and the n++ type semiconductor layer 1b are formed on the laminate in FIG. 3(a) to obtain the laminate in FIG. 3(b). In addition, the n+-type semiconductor layer 1a and the n++-type semiconductor layer 1b are patterned by etching using a known etching technique after forming a film using, for example, an epitaxial growth method such as atomization CVD. Then, the gate insulating film 4 and the gate electrode 5a are formed on the laminated body of FIG. 3(b), whereby the laminated body of FIG. 3(c) is obtained. The aforementioned gate insulating film 4 and gate electrode 5a can be processed into the shapes shown in FIG.

Next, the source electrode 5b is formed on the laminate shown in FIG. 3(c) using a known film-forming method to obtain the laminate shown in FIG. 4(d). Examples of the film-forming method of the source electrode 5b include the above-mentioned dry method, wet method, and the like. Then, after removing the substrate 9 in the laminated body in FIG. 4( d ), the drain electrode 5 c is formed using a known film forming method, thereby obtaining the semiconductor device in FIG. 4( e ). In the semiconductor device of FIG. 4(e), as described above, the source region 1 includes an n+ type semiconductor layer 1a and an n++ type semiconductor layer 1b disposed on the n+ type semiconductor layer 1a, and the n++ type semiconductor layer is an epitaxial layer, so Lower component resistance (especially source contact resistance).

The effect of the semiconductor device according to the embodiment of the present invention was verified using device simulation. In addition, the semiconductor device for simulation verification is the semiconductor device shown in FIG. 1 . The carrier densities of the n+ type semiconductor layer and the n++ type semiconductor layer are respectively 1.0×10 ¹⁸ /cm ³ and 2.0×10 ¹⁹ /cm ³ , and the mobility of the n+ type semiconductor layer and the n++ type semiconductor layer are respectively 20 cm ² / Vs and 0.0001 cm ² /Vs were calculated under the condition that the thicknesses of the n+ type semiconductor layer and the n++ type semiconductor layer were respectively 150 nm and 50 nm. In addition, the calculation was performed assuming that both the constituent materials of the n+ type semiconductor layer and the n++ type semiconductor layer were gallium oxide. Figure 12 shows the results. Figure 12(a) shows the current density distribution when the gate voltage is 20V and the drain voltage is 1V, and Figure 12(b) is the same, showing the current flow line when the gate voltage is 20V and the drain voltage is 1V. From Figure 12(a) and Figure 12(b), it is clear that when the carrier density of the n++ type semiconductor layer is greater than the carrier density of the n+ type semiconductor layer and the mobility of the n+ type semiconductor layer is greater than the mobility of the n++ type semiconductor layer , the contact resistance can be better reduced.

In addition, as this example, in order to confirm the effect of the n++ layer, a semiconductor device having a structure equivalent to the semiconductor device shown in FIG. 1 was produced as a trial in accordance with the above procedure. The structure of Example 1 is as follows. An n-type semiconductor layer composed of tin-doped α-Ga ₂ O ₃ is used as the n-type semiconductor layer 3, and an n+ type semiconductor layer composed of tin-doped α-Ga ₂ O ₃ is used as the n+ type semiconductor layer 1a , Use the n++ type semiconductor layer (carrier density above 1.0×10 ¹⁸ /cm ³ ) composed of tin-doped α-Ga ₂ O ₃ epitaxially grown on the aforementioned n+ type semiconductor layer as the n++ type semiconductor layer 1b. Also, an electrode having a three-layer structure in which a Ti layer, an Al layer, and a Ti layer were sequentially formed was used as a source electrode. Also, as Comparative Example 1, a semiconductor device was fabricated in the same manner as in Example 1 except that no n++ type semiconductor layer was provided. The IV measurement results of the semiconductor devices fabricated in Example 1 and Comparative Example 1 are shown in FIGS. 5 and 6 . As is clear from FIGS. 5 and 6 , in the semiconductor device according to the embodiment of the present invention, element resistance (especially source contact resistance) is reduced. Also, for reference, the n++ type semiconductor layer in Example 1 has a greater effect of reducing contact resistance than the case where the n++ layer is formed by ion implantation. This is the first new insight obtained since trying to manufacture a semiconductor device using gallium oxide (especially α-Ga ₂ O ₃ ). Especially in the case of using α-Ga ₂ O ₃ , it is difficult to perform an activation treatment at a high temperature after ion implantation. Therefore, it can be seen that the case of doping by epitaxial growth can lower the source electrode more favorably than the case of ion implantation. contact resistance and source resistance.

The above-mentioned semiconductor device according to the embodiment of the present invention can be applied to a power conversion device such as an inverter or a converter in order to exhibit the above-mentioned function. More specifically, it can be used as a diode built into an inverter or a converter, a thyristor as a switching element, a power transistor, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) )wait. 8 is a block configuration diagram showing an example of a control system using a semiconductor device according to an embodiment of the present invention, and FIG. 9 is a circuit diagram of the control system, which is particularly suitable for a control system mounted on an electric vehicle.

As shown in FIG. 8 , the control system 500 has a battery (power source) 501, a step-up converter 502, a step-down converter 503, an inverter 504, a motor (driven object) 505, and a drive control unit 506. car. The battery 501 is composed of storage batteries such as nickel-metal hydride batteries or lithium-ion batteries. It stores power through charging at charging stations or regenerative energy during deceleration, and can output direct current necessary for the operation of the electric vehicle's operating system and electrical system. Voltage. The step-up converter 502 is, for example, a voltage conversion device equipped with a chopping circuit, which boosts the DC voltage supplied from the battery 501, for example, 200 V to, for example, 650 V through switching operation of the chopping circuit, and outputs it to the operation of a motor or the like. system. The step-down converter 503 is also a voltage conversion device equipped with a chopper circuit in the same way, but it steps down the DC voltage supplied from the battery 501, for example, 200V to, for example, about 12V, so that it can be output to a power supply including power windows, power steering, or Electrical systems such as on-board power equipment.

The inverter 504 converts the DC voltage supplied from the boost converter 502 into a three-phase AC voltage by switching operation, and outputs it to the motor 505 . The motor 505 is a three-phase AC motor that constitutes the operating system of the electric vehicle, and is driven to rotate by the three-phase AC voltage output from the inverter 504, and then transmits its rotational driving force through a transmission (not shown) or the like. to the wheels of electric vehicles.

On the other hand, using various sensors not shown in the figure, measured values such as the number of rotations of the wheels, the torque, and the pedaling amount (acceleration amount) of the accelerator are measured from the running electric vehicle, and these measured signals are input to the drive. control unit 506 . At the same time, the output voltage value of the inverter 504 is also input into the driving control unit 506 . The drive control unit 506 has the function of a controller with a calculation unit such as a central processing unit (CPU, Central Processing Unit) and a data storage unit such as a memory, and uses the input measurement signal to generate a control signal and output it to the feedback signal as a feedback signal. The commutator 504 is used to control the switching operation with the switching element. In this way, the AC voltage given to the motor 505 by the inverter 504 is instantly corrected, so that the operation control of the electric vehicle can be correctly performed, and safe and comfortable operation of the electric vehicle can be realized. In addition, the voltage output to the inverter 504 can also be controlled by giving the feedback signal from the driving control unit 506 to the boost converter 502 .

FIG. 9 removes the circuit configuration of the step-down converter 503 in FIG. 8 , that is, only shows the circuit configuration for driving the motor 505 . As shown in the figure, the semiconductor device of the present invention is used for a boost converter 502 and an inverter 504 as a Schottky barrier diode, for example, and is thereby applied to switching control. In the step-up converter 502 , it is incorporated in a chopper circuit for chopping control, and in the inverter 504 is incorporated in a switching circuit including an IGBT for switching control. In addition, in the output of the battery 501, the current is stabilized through the inductor (coil, etc.), and capacitors (electrolytic capacitors, etc.) Stabilization of voltage.

Also, as shown by the dotted line in FIG. 9, the drive control unit 506 is provided with a calculation unit 507 made of a central processing unit (CPU, Central Processing Unit) and a memory unit 508 made of a non-volatile memory. The signal input to the drive control unit 506 is sent to the calculation unit 507, and necessary calculations are performed to generate feedback signals corresponding to each semiconductor element. In addition, the storage unit 508 temporarily stores the calculation results from the calculation unit 507, or stores physical constants and functions required for drive control in the form of a table, and outputs them to the calculation unit 507 as appropriate. The calculation unit 507 and the memory unit 508 can adopt known configurations, and their processing capabilities and the like can also be selected arbitrarily.

As shown in FIG. 8 or FIG. 9, in the control system 500, in the switching operation of the boost converter 502, the buck converter 503, and the inverter 504, thyristors and power transistors used as diodes or switching elements are used. , IGBT, MOSFET, etc. By using gallium oxide (Ga ₂ O ₃ ), especially corundum-type gallium oxide (α-Ga ₂ O ₃ ) as a material in such semiconductor devices, switching characteristics can be greatly improved. Furthermore, by applying the semiconductor device and the like of the present invention, excellent switching characteristics can be expected, and further miniaturization and cost reduction of the control system 500 can be realized. That is, the effect of the present invention can be expected for the boost converter 502, the buck converter 503, and the inverter 504, any one of these or a combination of any two or more, or a type that also includes the drive control unit 506 In any of the states, the effects of the present invention can be expected. In addition, the above-mentioned control system 500 can not only apply the semiconductor device of the present invention to the control system of an electric vehicle, but also can be applied to step up/down the power from a DC power supply, or convert power from a DC power supply to become a Control systems for all purposes such as AC. In addition, a power source such as a solar cell can also be used as the battery.

FIG. 10 is a block configuration diagram showing an example of a control system for a semiconductor device using an embodiment of the present invention. FIG. 11 is a circuit diagram of the same control system, which is a control system suitable for installation in basic equipment or home appliances that operate with power from an AC power source.

As shown in Figure 10, the control system 600 is input by the power supplied by an external, for example, three-phase AC power supply (power supply) 601, which has an AC/DC converter 602, an inverter 604, a motor (driven object) 605, The drive control unit 606 can be installed in various devices (described later). The three-phase AC power source 601 is, for example, a power generation facility of a power company (thermal power plant, hydroelectric power plant, geothermal power plant, nuclear power plant, etc.), and its output is stepped down by a substation and supplied as an AC voltage. Also, for example, it is installed in a building or in a nearby facility in the form of a self-owned generator, and is supplied with a cable. The AC/DC converter 602 is a voltage conversion device for converting an AC voltage into a DC voltage, and converts the 100V or 200V AC voltage supplied by the three-phase AC power supply 601 into a predetermined DC voltage. Specifically, through voltage conversion, it is converted into a commonly used expected DC voltage such as 3.3V, 5V or 12V. When the driving target is a motor, it is converted to 12V. In addition, a single-phase AC power supply may be used instead of a three-phase AC power supply. In this case, as long as the AC/DC converter is used as a single-phase input, the same system configuration can be achieved.

The inverter 604 converts the DC voltage supplied by the AC/DC converter 602 into a three-phase AC voltage through switching operation, and outputs it to the motor 605 . The type of the motor 605 varies depending on the control object. In the case of an electric vehicle, it is a three-phase AC motor used to drive wheels. In the case of factory equipment, it is a three-phase AC motor used to drive pumps and various power sources. In the case of home appliances, a three-phase AC motor used to drive a compressor, etc., is rotationally driven by the three-phase AC voltage output from the inverter 604, and the rotational driving force is transmitted to a drive not shown in the figure. object.

In addition, for example, in home appliances, there are also many driving objects that can directly supply the DC voltage output from the AC/DC converter 302 (such as computers, LED lighting equipment, video equipment, audio equipment, etc.). An inverter 604 is required, and as shown in FIG. 10 , a DC voltage is supplied from an AC/DC converter 602 to a driving target. In this case, for example, a DC voltage of 3.3 V is supplied to a computer or the like, and a DC voltage of 5 V is supplied to an LED lighting device or the like.

On the other hand, by using various sensors not shown in the figure, actual measurement values such as the number of rotations and torque of the driven object, or the temperature and flow rate of the surrounding environment of the driven object are measured, and these measurement signals are input. The drive control unit 606 . At the same time, the output voltage value of the inverter 604 is also input into the driving control unit 606 . Based on these measurement signals, the drive control unit 606 gives a feedback signal to the inverter 604 to control the switching operation performed by the switching element. Thereby, the operation control of the driven object can be correctly performed by instantaneously correcting the AC voltage given to the motor 605 by the inverter 604, thereby achieving stable operation of the driven object. Also, as described above, in the case where the driving object can be driven by DC voltage, feedback control may be performed on the AC/DC converter 602 instead of feedback to the inverter.

FIG. 11 shows the circuit configuration of FIG. 10 . As shown in the figure, the semiconductor device of the present invention is used, for example, as a Schottky barrier diode for an AC/DC converter 602 and an inverter 604, thereby being applied to switch control. The AC/DC converter 602 uses, for example, Schottky barrier diodes to form a bridge-like circuit, and performs DC conversion by converting negative voltage components of the input voltage into positive voltages for rectification. Furthermore, in the inverter 604, switching control is performed by incorporating a switching circuit in the IGBT. In addition, a capacitor (such as an electrolytic capacitor) is interposed between the AC/DC converter 602 and the inverter 604 to stabilize the voltage.

Moreover, as shown by the dotted line in FIG. 11 , the drive control unit 606 is provided with a calculation unit 607 constituted by a central processing unit and a memory unit 608 constituted by a non-volatile memory. The signal input to the drive control unit 606 is sent to the calculation unit 607 to perform necessary calculations, thereby generating feedback signals corresponding to each semiconductor element. In addition, the storage unit 608 temporarily stores the calculation results from the calculation unit 607, or stores physical constants or functions required for drive control in the form of a table, and outputs them to the calculation unit 607 appropriately. The calculation unit 607 and the memory unit 608 can adopt known configurations, and their processing capabilities and the like can also be selected arbitrarily.

In such a control system 600, similar to the control system 500 shown in FIG. 8 or FIG. 9, the diode or switching element is also used in the rectification operation and switching operation of the AC/DC converter 602 and the inverter 604. Thyristor, power transistor, IGBT, MOSFET, etc. By using gallium oxide (Ga ₂ O ₃ ), especially corundum-type gallium oxide (α-Ga ₂ O ₃ ) as a material in these semiconductor devices, switching characteristics are improved. Furthermore, by applying the semiconductor film or semiconductor device of the present invention, excellent switching characteristics can be expected, and further miniaturization and cost reduction of the control system 600 can be achieved. That is, the effects of the present invention can be expected for both the AC/DC converter 602 and the inverter 604 , and the effects of the present invention can be expected for any one of them or a combination thereof, or a configuration that also includes the drive control unit 606 .

10 and 11 illustrate the motor 605 as the driving target, but the driving target is not limited to mechanically operating devices, and many devices requiring AC voltage may be used as the target. The control system 600 can be applied as long as the power is input from an AC power source to drive the driving object, and basic equipment (such as power equipment such as buildings and factories, communication equipment, traffic control equipment, water purification equipment, system equipment, and labor-saving equipment) can be used. , trains, etc.) or home appliances (for example, refrigerators, washing machines, computers, LED lighting equipment, video equipment, audio equipment, etc.) as objects, and the control system 600 is equipped to drive and control these objects. [industrial availability]

The semiconductor device of the present invention can be applied to all fields of semiconductors (such as compound semiconductor electronic devices, etc.), electronic parts/electrical equipment parts, optical/electrophotographic related devices, industrial parts, etc., and is especially useful for power devices.

1: Source area 1a: n+ type semiconductor layer 1b: n++ type semiconductor layer 2: p-type semiconductor layer 3: n-type semiconductor layer 4: Gate insulating film 5a: Gate electrode 5b: Source electrode 5c: Drain electrode 6: Channel layer 7: n-type semiconductor layer 8: Oxide semiconductor layer 9: Substrate 21: Film forming device (atomization CVD device) 22a: Carrier gas source 22b: Carrier gas (dilution) source 23a: Flow regulating valve 23b: Flow regulating valve 24: Fog generation source 24a: stock solution 24b: Raw material fine particles 25: container 25a: water 26:Ultrasonic vibrator 27: Film forming room 28: Heating plate 29: Supply pipe 30: Substrate 500: control system 501: battery (power supply) 502: Boost Converter 503: Buck converter 504: Inverter 505: Motor (drive object) 506: Drive control department 507: Calculation Department 508: memory department 600: Control system 601: Three-phase AC power supply (power supply) 602:AC/DC Converter 604: Inverter 605: Motor (driving object) 606: Drive control department 607: Calculation Department 608: memory department

FIG. 1 is a diagram schematically showing a metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the present invention. FIG. 2 is a diagram schematically showing a metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the present invention. FIG. 3 is a diagram schematically showing preferred manufacturing steps of a metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the present invention. FIG. 4 is a diagram schematically showing preferred manufacturing steps of a metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the present invention. Fig. 5 is a graph showing the results of I-V measurement in Examples. Fig. 6 is a graph showing the results of I-V measurement in Comparative Example. Fig. 7 is a configuration diagram of an atomization CVD apparatus used in an embodiment of the present invention. FIG. 8 is a block configuration diagram showing an example of a control system for a semiconductor device using an embodiment of the present invention. FIG. 9 is a circuit diagram showing an example of a control system of a semiconductor device using an embodiment of the present invention. FIG. 10 is a block configuration diagram showing an example of a control system for a semiconductor device using an embodiment of the present invention. FIG. 11 is a circuit diagram showing an example of a control system of a semiconductor device using an embodiment of the present invention. Fig. 12 is a graph showing simulation results in an embodiment of the present invention. FIG. 13 is a diagram schematically showing a metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the present invention. FIG. 14 is a diagram schematically showing a metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the present invention.

1: Source area

1a: n+ type semiconductor layer

1b: n++ type semiconductor layer

2: p-type semiconductor layer

3: n-type semiconductor layer

4: Gate insulating film

5a: Gate electrode

5b: Source electrode

5c: Drain electrode

6: Channel layer

7: n-type semiconductor layer

8: Oxide semiconductor layer

Claims (19)

A semiconductor device comprising an oxide semiconductor layer including at least a source region, and a source electrode disposed on the source region, wherein, The aforementioned source region at least includes an n+ type semiconductor layer and an n++ type semiconductor layer disposed on the n+ type semiconductor layer and having a higher carrier density than the n+ type semiconductor layer. The semiconductor device according to claim 1, wherein said n+ type semiconductor layer has the same crystal structure as said n++ type semiconductor layer. The semiconductor device according to claim 1 or 2, wherein said n+ type semiconductor layer has the same main component as said n++ type semiconductor layer. The semiconductor device according to any one of claims 1 to 3, wherein the n++ type semiconductor layer is an epitaxial layer. The semiconductor device according to claim 4, wherein the n++ type semiconductor layer is epitaxially doped. The semiconductor device according to any one of claims 1 to 5, wherein the carrier density of the n++ type semiconductor layer is above 1.0×10 ¹⁹ /cm ³ . The semiconductor device according to any one of claims 1 to 6, wherein the carrier density of the n+ type semiconductor layer is in the range of 1.0×10 ¹⁷ /cm ³ to less than 1.0×10 ¹⁹ /cm ³ . The semiconductor device according to any one of claims 1 to 7, wherein the thickness of the n++ type semiconductor layer is in the range of 1 nm to 1 μm. The semiconductor device according to any one of claims 1 to 8, wherein the thickness of the n+ type semiconductor layer is greater than the thickness of the n++ type semiconductor layer. The semiconductor device according to any one of claims 1 to 9, wherein the mobility of the n+ type semiconductor layer is greater than the mobility of the n++ type semiconductor layer. The semiconductor device according to any one of claims 1 to 10, wherein the n+ type semiconductor layer is an epitaxial layer. The semiconductor device according to any one of claims 1 to 11, wherein the oxide semiconductor layer further includes a channel layer, and a gate electrode is disposed on the channel layer via a gate insulating film. The semiconductor device according to claim 12, wherein the lower end of the n++ type semiconductor layer is located above the lower end of the gate insulating film. The semiconductor device according to claim 12 or 13, wherein the distance from the outer end of the gate insulating film to the inner end of the n+ type semiconductor layer is 10 μm or less. The semiconductor device according to claim 12, wherein the channel layer has a trench, and at least a part of the gate electrode is buried in the trench. The semiconductor device according to any one of claims 1 to 15, which is a transistor. The semiconductor device according to any one of claims 1 to 16, which is a power element. A power conversion device using the semiconductor device according to any one of claims 1 to 17. A control system using the semiconductor device according to any one of claims 1 to 18.

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