TW202248660A - System and method for z-pat defect-guided statistical outlier detection of semiconductor reliability failures - Google Patents

Abstract

A system and method for Z-PAT defect-guided statistical outlier detection of semiconductor reliability failures includes receiving electrical test bin data with semiconductor die data for a plurality of wafers in a lot generated by a statistical outlier detection subsystem configured to perform Z-direction Part Average Testing (Z-PAT) on test data generated by an electrical test subsystem after fabrication of the plurality of wafers in the lot, receiving characterization data for the plurality of wafers in the lot generated by a semiconductor fab characterization subsystem during the fabrication of the plurality of wafers in the lot, determining a statistical correlation between the electrical test bin data and the characterization data at a same x, y position on each of the plurality of wafers in the lot, and locating defect data signatures on the plurality of wafers in the lot based on the statistical correlation.

Description

System and method for defect-guided statistical outlier detection in Z-direction partial average test for semiconductor reliability faults

The present invention relates generally to semiconductor devices and, more particularly, to a system and method for defect-guided statistical outlier detection for Z-direction partial average testing (Z-PAT) of semiconductor reliability failures .

The fabrication of semiconductor devices typically requires hundreds or thousands of processing steps to form a functional device. During these processing steps, various characterization measurements (eg, inspection and/or metrology measurements) may be performed to identify defects and/or monitor various parameters on the device. Electrical testing may be performed in place of or in addition to the various characterization measurements to verify or evaluate the functionality of the device. However, while some detected defects and metrology errors can be so significant as to clearly indicate a device failure, smaller variations can cause early reliability failures of the device after exposure to an operating environment. Risk-averse users of semiconductor devices such as automotive, military, aerospace, and medical applications are now looking for failure rates in the parts-per-billion (PPB) range beyond current parts-per-million (PPM) levels . As the demand for semiconductor devices in automotive, military, aerospace and medical applications continues to increase, evaluating the reliability of semiconductor die is key to meeting these industry requirements. Accordingly, it would be desirable to provide systems and methods for reliability defect detection.

According to one or more embodiments of the invention, a system is disclosed. In one illustrative embodiment, the system includes a controller communicatively coupled to at least one semiconductor fab characterization subsystem. In another illustrative embodiment, the controller includes one or more processors configured to execute programmed instructions that cause the one or more processors to receive via a defect guidance related subsystem Electrical test grid data. In another illustrative embodiment, the electrical test bin data includes semiconductor die data for a plurality of wafers in a batch. In another illustrative embodiment, the electrical test bin data is generated by a statistical outlier detection subsystem configured to perform a Z-direction partial average test (Z-PAT) on the test data. In another illustrative embodiment, an electrical test subsystem is configured to generate the test data by testing the plurality of wafers in the lot after fabrication by the semiconductor fab characterization subsystem. In another illustrative embodiment, the controller includes one or more processors configured to execute programmed instructions that cause the one or more processors to receive via the defect guidance related subsystem Characterized data. In another illustrative embodiment, the characterization data for the plurality of wafers in the lot is generated by the semiconductor fab characterization subsystem during fabrication of the plurality of wafers in the lot. In another illustrative embodiment, the controller includes one or more processors configured to execute programmed instructions that cause the one or more processors to direct an associated subsystem through the defect to determine A statistical correlation between the electrical test bin data and the characterization data at a same x, y location on each of the plurality of wafers in the lot. In another illustrative embodiment, the controller includes one or more processors configured to execute programmed instructions that cause the one or more processors to direct associated subsystems through the defect based on The statistics are correlated to locate defect data signatures on the plurality of wafers in the lot.

According to one or more embodiments of the invention, a method is disclosed. In one illustrative embodiment, the method may include, but is not limited to, receiving electrical test bin data via a defect guidance correlation subsystem. In another illustrative embodiment, the electrical test bin data includes semiconductor die data for a plurality of wafers in a lot. In another illustrative embodiment, the electrical test bin data is generated by a statistical outlier detection subsystem configured to perform a Z-direction partial average test (Z-PAT) on the test data. In another illustrative embodiment, an electrical test subsystem is configured to generate the test data by testing the plurality of wafers in the lot after manufacture by a semiconductor fab characterization subsystem. In another illustrative embodiment, the method may include, but is not limited to, receiving characterization data via the defect guidance correlation subsystem. In another illustrative embodiment, the characterization data for the plurality of wafers in the lot is generated by the semiconductor fab characterization subsystem during the manufacture of the plurality of wafers in the lot. In another illustrative embodiment, the method may include, but is not limited to, determining, via the defect guidance correlation subsystem, a defect at the same x, y location on each of the plurality of wafers in the lot. A statistical correlation between the electrical test bin data and the characterization data. In another illustrative embodiment, the method may include, but is not limited to, locating, via the defect guidance correlation subsystem, defect data signatures on the plurality of wafers in the lot based on the statistical correlation.

According to one or more embodiments of the invention, a system is disclosed. In an illustrative embodiment, the system includes a semiconductor fab characterization subsystem. In another illustrative embodiment, the semiconductor fab characterization subsystem is configured to manufacture a plurality of wafers in a lot. In another illustrative embodiment, the semiconductor fab characterization subsystem is configured to generate characterization data for the plurality of wafers in the lot during the fabrication of the plurality of wafers in the lot . In another illustrative embodiment, the system includes an electrical test subsystem. In another illustrative embodiment, the electrical test subsystem is configured to generate test data for the plurality of wafers in the lot after fabrication by the semiconductor fab characterization subsystem. In another illustrative embodiment, the system includes a controller communicatively coupled to at least one of the semiconductor fab characterization subsystems. In another illustrative embodiment, the controller includes one or more processors configured to execute programmed instructions that cause the one or more processors to receive via a defect guidance related subsystem Electrical test grid information. In another illustrative embodiment, the electrical test bin data includes semiconductor die data for the plurality of wafers in the lot. In another illustrative embodiment, the electrical test bin data is generated by a statistical outlier detection subsystem configured to perform Z-direction partial average testing (Z-PAT). In another illustrative embodiment, the controller includes one or more processors configured to execute programmed instructions that cause the one or more processors to receive via the defect guidance related subsystem The characterization data. In another illustrative embodiment, the controller includes one or more processors configured to execute programmed instructions that cause the one or more processors to direct an associated subsystem through the defect to determine A statistical correlation between the electrical test bin data and the characterization data at a same x, y location on each of the plurality of wafers in the lot. In another illustrative embodiment, the controller includes one or more processors configured to execute programmed instructions that cause the one or more processors to direct associated subsystems through the defect based on The statistics are correlated to locate defect data signatures on the plurality of wafers in the lot.

It is to be understood that both the foregoing general description and the following detailed description are illustrative and explanatory only and are not necessarily restrictive of the invention. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the general description serve to explain the principles of the invention.

Cross References to Related Applications This application claims priority to U.S. Provisional Application No. 63/208,014, filed June 8, 2021, which is incorporated herein by reference in its entirety.

Reference will now be made in detail to the disclosed subject matter illustrated in the accompanying drawings. The invention has been particularly shown and described with respect to certain embodiments and specific features thereof. The embodiments set forth herein should be considered as illustrative rather than restrictive. It will be readily apparent to those skilled in the art that various changes and modifications in form and detail can be made without departing from the spirit and scope of the invention.

The fabrication of semiconductor devices typically requires hundreds or thousands of processing steps to form a functional device. During these processing steps, various characterization measurements (eg, inspection and/or metrology measurements) may be performed to identify defects and/or monitor various parameters on the device. Electrical testing may be performed in place of or in addition to the various characterization measurements to verify or evaluate the functionality of the device.

However, while some detected defects and metrology errors can be so significant as to clearly indicate a device failure, smaller variations can cause early reliability failures of the device after exposure to an operating environment. Defects that occur during the manufacturing process can have a wide-ranging impact on the performance of devices in the field. For example, a "killer" defect in a design at a known or unknown location can cause the device to fail immediately. For example, killer defects in unknown locations can be particularly problematic because they are prone to reliability escapes in the test gap, where a semiconductor device may fail functionally after processing but due to testing limitations, the device manufacturer cannot make This decision. As another example, minor defects may have little or no effect on the performance of the device over the lifetime of the device. As another example, a class of defects known as Latent Reliability Defects (LRDs) may not cause failure during manufacturing/testing or may not cause immediate device failure during operation, but may cause failure during operation when used in a working environment. Early life failure of the device. It should be noted herein that the term "manufacturing process" together with respective variations of the term such as "manufacturing line" and the like, may be considered equivalent for the purposes of the present invention.

Risk-averse users of semiconductor devices such as automotive, military, aerospace, and medical applications are now looking for failure rates in the parts-per-billion (PPB) range beyond current parts-per-million (PPM) levels . As the demand for semiconductor devices in automotive, military, aerospace and medical applications continues to increase, evaluating the reliability of semiconductor die and identifying sources of reliability failures are key to meeting these industry requirements. Accordingly, it would be desirable to provide systems and methods for reliability defect detection.

Semiconductor devices with quality critical roles may undergo electrical testing during wafer sorting and final testing after separation and packaging. Additionally, semiconductor devices may be subjected to methods configured to determine systematic defects occurring at the same x, y location on multiple wafers in a given lot. In conventional semiconductor wafer processing methods, an x and y dimension locates die positions on a wafer and a z dimension refers to individual wafers stacked on top of each other in a cassette.

Most automotive semiconductor companies have adopted Partial Average Testing (PAT), primarily to help them meet the stringent requirements of the automotive industry and the growing number of high-end mobile devices. Reliability studies have shown that semiconductor portions with outlier electrical characteristics tend to be higher contributors to long-term quality and reliability problems. For example, a device that initially passes all manufacturing tests but may be considered an "outlier" compared to the rest of the same population is more likely to fail in the field. The PAT method proactively identifies such outliers to exclude from production shipments.

PAT methods may include, but are not limited to, Geographic Partial Average Testing (G-PAT) (for example, it involves testing a good die in a bad area), Parametric Partial Average Testing (P-PAT) (for example, it involves a threshold or a parameter signal outside the standard but within specification limits), composite partial averaging test (C-PAT) (for example, which involves multiple repairs on a die), inline defective partial averaging test (I-PAT), and Z Directional Partial Average Test (Z-PAT). It should be noted herein that a system and method for I-PAT is described in US Patent Publication No. US 2018/0328868 A1 published on November 15, 2018. Additionally, it should be noted herein that the systems and methods for I-PAT are described in U.S. Patent No. 10,761,128, issued September 1, 2020, and U.S. Application No. 17/101,856, filed November 23, 2020. The entire contents are incorporated herein.

Z-PAT involves partial average testing in the z direction and has traditionally relied on test data only. If the same x, y position is tested badly on multiple wafers in the same lot, the semiconductor supplier can ink the die that tested "good" in electrical test. This inking or "overkill" is based on observation. Many systemic factors that exhibit quality problems at a particular location on a wafer are frequently repeated at that die location on each wafer in the lot.

In one non-limiting example, a particle adhering to a chuck of a wafer processing tool can cause a persistent raised protrusion on the front side at that location. In another non-limiting example, an etch process "dead spot" problem may include dies at the very center of the wafer that are never etched. In another non-limiting example, a processing tool may continuously deposit particles at a specific location around the edge of the wafer. It should be noted herein that the above examples are illustrative and not intended to be limiting with respect to wafer position system issues.

FIG. 1 illustrates a system 100 for detecting semiconductor reliability failures according to one or more embodiments of the present invention.

In some embodiments, system 100 includes a semiconductor fab characterization subsystem 102 . Semiconductor fab characterization subsystem 102 may include a plurality of characterization tools configured to perform characterization measurements on semiconductor devices within a lot (eg, semiconductor wafer 104 or wafers 104 for purposes of the present invention). For example, the plurality of characterization tools may include, but is not limited to, one or more in-line defect inspection tools and/or metrology tools configured to characterize a semiconductor device. As another example, characterization measurements may include, but are not limited to, in-line defect detection measurements and/or metrology measurements. For example, inspection measurements may include baseline inspections (eg, sampling-based inspections), screening inspections of critical semiconductor device layers, or the like. For the purposes of the present invention, "characterization" may refer to in-line defect detection or in-line metrology. It should be noted herein that the online defect detection tool and/or the metrology tool may perform a standard characterization procedure or a non-standard (eg, proprietary) characterization procedure.

Characterization may be performed during (e.g., before, between, and/or after) steps in the manufacture of one or more semiconductor devices (e.g., wafer 104) in a lot via a plurality of semiconductor manufacturing processes performed by a plurality of semiconductor manufacturing tools Measure. For example, one or more semiconductor fab characterization subsystems 102 may include, but are not limited to, configured to fabricate semiconductor devices (included in several (eg, tens, hundreds, thousands) One or more processing tools of 1, 2, . . . N layers of fabrication after the step.

In some embodiments, system 100 includes an electrical testing subsystem 106 . Semiconductor fab characterization subsystem 102 provides wafer 104 and/or die material to electrical test subsystem 106 . Electrical test subsystem 106 may be configured to output test data 108 including data after probing the lot 104 , denoted lot 108 . For example, electrical testing subsystem 106 may include, but is not limited to, one or more electrical testing tools, one or more stress testing tools, or the like. Electrical test subsystem 106 may be configured to test semiconductor devices manufactured by performing one or more semiconductor fabrication processes through semiconductor fab characterization subsystem 102 . For the purposes of the present invention, "testing" is understood to mean at the end of a manufacturing process (such as an Electrical Wafer Sorting (EWS) process or the like), at the end of packaging and/or at the end of final testing ( Procedures for electrical evaluation of device functionality, such as after burn-in procedures and other quality inspection procedures. It is noted herein that non-qualifying semiconductor die or wafers may be isolated from good semiconductor die or wafers and/or marked for further testing. The data representing the lot of probed wafers 108 may be in the form of a probe map, or may be used to generate a probe map.

In some embodiments, the system 100 includes a statistical outlier detection subsystem 110 . The electrical test subsystem 106 can output the test data 108 to the statistical outlier detection subsystem 110 . Statistical outlier detection subsystem 110 may output outlier data or electrical test bin data 112 , wherein electrical test bin data 112 includes semiconductor die data for wafers 104 in the lot. For example, statistical outlier detection subsystem 110 may include and/or be configured to perform a Z-PAT method. As another example, statistical outlier detection subsystem 110 may include and/or be configured to perform other PAT methods or other known statistical outlier determination techniques.

FIG. 2 illustrates a method or process 200 for detecting semiconductor reliability failures in accordance with one or more embodiments of the present invention. It should be noted herein that the steps of the method or procedure 200 may be implemented in whole or in part by the system 100 shown in FIG. 1 . However, it should be further appreciated that the method or process 200 is not limited to the system 100 shown in FIG. 1 , as additional or alternative system-level embodiments may perform all or part of the steps of the method or process 200 .

In a step 202, a semiconductor device is received from a semiconductor foundry characterization subsystem. In some embodiments, the semiconductor fab characterization subsystem 102 is configured to manufacture a batch of wafers 104 . For example, semiconductor fab characterization subsystem 102 may include, but is not limited to, configured to fabricate semiconductor devices, including those fabricated after a number (eg, tens, hundreds, thousands) of steps performed by a number of semiconductor fabrication processes. 1, 2, ... N layers) one or more processing tools.

In a step 204, an electrical test subsystem is used to test the semiconductor device to generate test data. In some embodiments, the electrical test subsystem 106 receives the batch of wafers 104 . For example, electrical testing subsystem 106 may perform electrical testing and/or stress testing to generate test data 108 .

In a step 206, the test data is transmitted to a statistical outlier detection subsystem. In some embodiments, the electrical testing subsystem 106 sends the test data 108 to the statistical outlier detection subsystem 110 .

In a step 208, the test data is processed using the statistical outlier detection subsystem to generate electrical test bin data. In some embodiments, statistical outlier detection subsystem 110 may determine the lot of selected wafers based on known electrically failed dies on the lot of other wafers 104 in test data 108 received from electrical test subsystem 106 The location and/or system extension of the speculative electrical failure die on 104 .

In a step 210, electrical test bin data reclassified based on the characterization data are received via the statistical outlier detection subsystem. In some embodiments, at least some of the semiconductor die data in electrical test bin data 112 are reclassified using one or more steps of method or procedure 500 or 800 described in further detail herein. It is noted herein that at least one of semiconductor device fabrication, characterization, and/or testing may be determined based on reclassification of electrical test bin data 112 and/or newly discovered defects during performance of method or procedure 500 or 800. one or more adjustments. For example, one or more adjustments may modify a manufacturing process or method, a characterization process or method, a testing process or method, or the like, provided in a feedback loop to a component within the semiconductor fab characterization subsystem 102 . For example, a manufacturing procedure or method, a characterization procedure or method, a testing procedure or method, etc. may be adjusted based on reclassification of the electrical test bucket data 112 and/or newly discovered defects during execution of the method or procedure 500 or 800 (e.g., via one or more control signals).

3A and 3B generally illustrate a probe map 300 of a batch of wafers 108 in accordance with one or more embodiments of the present invention.

Referring now to FIG. 3A , wafers 108 in a selection lot include good dies 302 and electrical failed dies 304 , wherein electrical failed dies 304 include indicators of probing problems in electrical test bin data 112 . In the non-limiting example depicted in FIG. 3A , nine of the twenty-four wafers 108 in the probe map 300 (eg, W1, W4, W6, W8, W12, W16, W20, W22, W24) were at Clusters of electrically faulty die 304 are exhibited in the same x, y location on the respective wafers.

Referring now to FIG. 3B , the statistical outlier detection subsystem 110 performs Z-PAT on the lot 108 of wafers. During Z-PAT, due to the similarity of the die 306 in x, y position to a known electrically failed die 304, a rule set (e.g. its Inking of die 306 as a potential electrical failure may be defined on a per fab basis, or may be determined for multiple fabs. For example, the threshold value may represent an overkill limit that depends on the number of electrically faulty die 304 observed by the electrical test subsystem 106 . In the event that the threshold value is exceeded, due to the potential electrical failure die 306 being believed to contain a defect due to a location associated with a known electrical failure die 304, the statistical outlier detection subsystem 110 may use the ink Potential electrical failure dies 306 are marked in the same x, y locations as known electrical failure dies 304 on other wafers 108 . For example, the remaining 15 wafers (eg, W2, W3, W5, W7, W9, W10, W11, W13, W14, W15, W17, W18, W19, W21, W23) of the 24 wafers 108 may include ink-coatable Potential electrical failure dies 306 in the same x, y location are noted. For example, the electrical test subsystem 106 may not have sufficiently caught the escape due to it being a Latent Reliability Defect (LRD) and/or due to a gap in test coverage.

The Z-PAT method listed above has several disadvantages. For example, the Z-PAT approach listed above can result in excessive yield loss or overkill due to the relatively rare occurrences of presumed failures that would actually manifest as reliability failures or customer returns despite the risk-averse semiconductor supply in the automotive sector. Businesses will usually make this sacrifice. As another example, the Z-PAT methods listed above often do not provide enough information about the root cause of a failure to allow semiconductor fabrication engineers to prevent it from occurring in the future (or at least generate a baseline to monitor frequency of occurrence), resulting in Adjustments to system 100 and/or method or process 200 are reactive rather than proactive. Therefore, any method that provides insight into the causal failure mechanism and/or the propagation of this failure mechanism to other wafers enables better decision making to reduce overkill.

Embodiments of the present invention are directed to a system and method for Z-PAT defect-guided statistical outlier detection for semiconductor reliability failures. Embodiments of the present invention are also directed to identifying potential reliability and/or test gaps at the same x,y location on multiple wafers representing a lot using characterization data such as in-line defect inspection data and/or metrology data Defect Z-PAT defect signature. Embodiments of the present invention are also directed to identifying Z-PAT defect signatures using a statistical outlier algorithm. Embodiments of the present invention are also directed to automatically notifying the factory engineer of the existence of the Z-PAT defect signature. Embodiments of the present invention are also directed to characterizing Z-PAT defect signatures using spatial signature analysis methods. Embodiments of the present invention are also directed to characterizing Z-PAT defect signatures using machine learning methods. Embodiments of the present invention are also directed to identifying the presence or absence of Z-PAT defect signatures within a given lot. Embodiments of the present invention are also directed to identifying Z-PAT defect signatures on adjacent lots. Embodiments of the present invention are also directed to identifying Z-PAT defect signatures that are not detected by Z-PAT based electrical testing. Embodiments of the present invention are also directed to reducing overkill by using Z-PAT defect signatures to more precisely define the range of affected die/wafers. Embodiments of the present invention are also directed to quickly identifying potential root causes based on learning from previously characterized Z-PAT defect signatures. Embodiments of the present invention also aim at retrospective identification of Z-PAT defect signatures to use stored online defect data to guide warranty and/or recall work.

FIG. 4 illustrates a system 400 for Z-PAT defect-guided statistical outlier detection for semiconductor reliability failures according to one or more embodiments of the present invention. It is noted herein that system 400 may allow semiconductor manufacturers to more accurately identify die with a higher risk of early life reliability failures or test coverage gaps, and/or allow suppliers to better Dies from wafers containing systematic defects occurring at the same x, y location on multiple wafers in a given lot are processed.

In some embodiments, system 400 includes one or more components of system 100 . System 400 may include semiconductor fab characterization subsystem 102 configured to fabricate and characterize semiconductor wafer 104 . System 400 may include electrical test subsystem 106 configured to receive wafer 104 and perform electrical tests to generate test data 108 . System 400 may include statistical outlier detection subsystem 110 configured to receive test data 108 and output outlier data 112 after applying the Z-PAT method.

In some embodiments, system 400 includes a defect reduction subsystem 402 . The defect reduction subsystem 402 may be configured to receive a number of semiconductor fabrication processes performed by a plurality of semiconductor fabrication tools during the fabrication of one or more semiconductor devices (eg, wafer 104) (eg, before steps, between steps) and/or after step) extracted characterization data 404 (e.g., characterization measurements, including (but not limited to) in-line defect detection measurements and/or metrology measurements), wherein the characterization data 404 includes wafers in the lot 104 semiconductor grain data.

Defect reduction subsystem 402 may be configured to generate filtered characterization data 406 (or, for purposes of the present invention, filtered data 406 ), which is a subset of characterization data 404 . Filtered characterization data 406 may be generated by one or more I-PAT methods or procedures. It should be noted herein that a system and method for I-PAT is described in US Patent Publication No. US 2018/0328868 A1 published on November 15, 2018. Additionally, it should be noted herein that the systems and methods for I-PAT are described in U.S. Patent No. 10,761,128, issued September 1, 2020, and U.S. Application No. 17/101,856, filed November 23, 2020. The entire contents were previously incorporated herein. As such, defect reduction subsystem 402 may be considered an I-PAT analyzer for the purposes of the present invention.

In some embodiments, system 400 includes a defect guidance correlation subsystem 408 . Defect reduction subsystem 402 may be configured to output filtered characterization data 406 to defect guidance correlation subsystem 408 . The defect guidance correlation subsystem 408 may be configured to output improved electrical die bin data 410 (e.g., with improved semiconductor die data) to interested parties (e.g., manufacturing engineers), and/or may be configured to regenerate The classified electrical die bin data 412 (eg, with reclassified semiconductor die data) is output to the statistical outlier detection subsystem 110 . For example, the improved electrical die bin data 410 may be determined and/or regenerated by deterministic and/or statistical thresholding methods or procedures, spatial signature analysis methods or procedures, advanced deep learning or machine learning methods or procedures, etc. 412 Classified electrical grain cell data. In general, machine learning techniques can be any technique known in the art, including (but not limited to) supervised learning, unsupervised learning, or other learning-based procedures such as (but not limited to) linear regression, neural networks, or deep Neural networks, heuristic-based models, or the like. After determining the improved electrical die cell data 410 and/or the reclassified electrical die cell data 412 and/or the reclassified electrical die cell data 412, the improved electrical die cell data 410 can be automatically executed And/or reclassified electrical die bin data 412 (including Z-PAT defect signatures) is exported to interested parties (eg, fab engineers) and/or to the statistical outlier detection subsystem 110 .

It should be noted herein that the improved electrical die bin data 410 and/or the reclassified electrical die bin data 412 can more precisely define the number of affected die/wafers by using Z-PAT defect signatures. range to reduce overkill. Additionally, it should be noted herein that the improved electrical die bin data 410 and/or the reclassified electrical die bin data 412 may be responsive to the identification of the presence or absence of Z-PAT defect signatures within a given lot. Additionally, it should be noted herein that the improved electrical die bin data 410 and/or the reclassified electrical die bin data 412 may be responsive to the identification of Z-PAT defect signatures on adjacent lots. Additionally, it should be noted herein that the improved electrical die bin data 410 and/or the reclassified electrical die bin data 412 can respond to signing Z-PAT defects not detected by electrical test based Z-PAT identification. Furthermore, it should be noted herein that the improved electrical die bin data 410 and/or the reclassified electrical die bin data 412 can be used to quickly identify potential root causes based on learning from previously characterized Z-PAT defect signatures. Additionally, it should be noted herein that the improved electrical die bin data 410 and/or the reclassified electrical die bin data 412 can be used for identification of retrospective Z-PAT defect signatures to guide warranties using stored online defect data and/or recall jobs.

It should be noted herein that the characterization data 404 can be run through a recipe run of a fab-wide defect management subsystem 414 (e.g., a fab yield management subsystem) to filter the characterization data 404 so that the defect guidance related subsystem 408 can handle some The analyzed characterized data 404 and/or filtered data 406 (eg, when the characterized data 404 first passes through the defect reduction subsystem 402).

Although an embodiment of the invention is shown extracting characterization data 404 from semiconductor fab characterization subsystem 102 and using defect reduction subsystem 402 prior to generating filtered characterization data 406 and providing it to defect guidance correlation subsystem 408 It is processed, but it should be noted herein that the characterization data 404 can be provided as raw data from the semiconductor fab characterization subsystem 102 directly to the defect guidance correlation subsystem 408 . As such, defect reduction subsystem 402 may not be considered a required component of system 400 for purposes of the present disclosure. Therefore, the above description should not be construed as limiting the scope of the present invention but as illustration only.

Although the embodiments of the present invention depict the defect guidance related subsystem 408 separate from the defect reduction subsystem 402, it should be noted herein that the defect guidance related subsystem 408 can be integrated into the defect reduction subsystem 402 and vice versa. More generally, although embodiments of the invention depict subsystems 102, 106, 110, 402, 408 as separate or independent subsystems within system 400, it should be noted herein that subsystems 102, 106, 110, 402 One or more of , 408 may be combined or integrated subsystems. Therefore, the above description should not be construed as limiting the scope of the present invention but as illustration only.

FIG. 5 illustrates a method or procedure 500 for Z-PAT defect-guided statistical outlier detection for semiconductor reliability failures according to one or more embodiments of the present invention. It should be noted herein that the steps of the method or procedure 500 may be implemented in whole or in part by the system 400 shown in FIG. 4 . However, it should be further appreciated that the method or process 500 is not limited to the system 400 depicted in FIG. 4 , as additional or alternative system-level embodiments may perform all or part of the steps of the method or process 500 .

In a step 502, semiconductor device characterization data is received from a semiconductor fab characterization subsystem. In some embodiments, semiconductor fab characterization subsystem 102 is configured to perform characterization measurements during fabrication of one or more wafers 104 . For example, semiconductor fab characterization subsystem 102 may include, but is not limited to, one or more in-line defect detection and/or metrology tools configured to characterize semiconductor devices. For example, one or more outputs may include, but are not limited to, baseline inspections (eg, sampling-based inspections), screening inspections at critical semiconductor device layers, or the like. For the purposes of the present invention, "characterization" may refer to in-line defect detection or in-line metrology.

In a step 504, the characterization data is processed through a defect reduction subsystem to generate filter data. In some embodiments, defect reduction subsystem 402 may receive characterization data 404 and generate filtered characterization data 406 . Defect reduction subsystem 402 may include or be configured to perform the I-PAT method. As such, defect reduction subsystem 402 may be considered an I-PAT analyzer for the purposes of the present invention.

In a step 506, the filtering data and/or characterization data are transmitted to a defect guidance correlation subsystem. In some embodiments, filtered characterization data 406 is transferred from defect reduction subsystem 402 to defect guidance related subsystem 408 and/or characterization data 404 is transferred from semiconductor fab characterization subsystem 102 to defect guidance Related subsystems 408 . It should be noted herein that step 504 may be optional, wherein the characterization data 404 is directly transmitted to the defect guidance correlation subsystem 408 such that the filtered characterization data 406 is not used by the defect guidance correlation subsystem 408 .

In a step 508, the electrical test bin data is received by the defect guidance related subsystem. In some embodiments, the electrical test bucket data 112 is generated by one or more components of the system 100 through one or more steps of the method or procedure 200 .

In a step 510, a statistical correlation between the electrical test bin data and the filter data or signature data is determined via the defect guidance correlation subsystem. In some embodiments, filtered characterization data 406 and/or characterization data 404 are overlaid on electrical test bin data 112 by defect guidance correlation subsystem 408 . For example, filtered characterization data 406 may be determined by defect reduction subsystem 402 (eg, in electrical test bin data 112 ) based on its association with the particular Z-PAT system failure mechanism under study. As another example, all of the characterization data 404 can be overlaid on the electrical test bin data 112 .

In a step 512, defect data signatures are located on the semiconductor device based on statistical correlation via the defect guidance correlation subsystem. In some embodiments, if a statistical correlation is found after filtering characterization data 406 and/or characterization data 404 overlaid on electrical test bin data 112, system 400 (e.g., defect guidance correlation subsystem 408 or system Other components of 400) look for similar defect/metric signatures on the lot 104 processed before and after the lot 104 is studied.

In a step 514, at least some of the semiconductor die data of the electrical test bin data is reclassified by the defect guidance correlation subsystem based on the defect data signature. In some embodiments, the system 400 (e.g., the defect guidance related subsystem 408 or other components of the system 400) reclassifies the bins associated with the die 302/304/306 under consideration, depending on the results and the handling logic applied. . For example, statistical outlier detection subsystem 110 may confirm that a bin contains a fault found in electrical fault die 304 . As another example, a bin may be changed to indicate that the failure found by the statistical outlier detection subsystem 110 in either the known electrical failure die 304 or the potential electrical failure die 306 is a good die 302 . As another example, a bin may be changed to indicate that a good die 302 may or does contain a fault and therefore should be considered a potential electrical fault die 306 or a known electrical fault die 304 .

In a step 516, the reclassified electrical test bin data is transmitted via the defect guidance related subsystem. In some embodiments, the modified electrical test bin data 410 is transmitted or otherwise provided to various parties (eg, factory engineers) by the defect guidance related subsystem 408 . For example, the modified electrical test bin data 410 may include information on whether to ink a die (e.g., a believed good die 302 and/or a potential electrical fault die) using the same x, y position as the known electrical fault die 304 306) recommendations. For example, recommendations may be made based on a rule set that includes a threshold for fully inking (eg, it may be defined on a per-fab basis, or may be determined for multiple fabs).

In a step 518, the new defect data signature is transmitted via the defect guidance related subsystem. In some embodiments, the new defect data signature may be transmitted or otherwise provided to the statistical outlier detection subsystem 110 by the defect guidance correlation subsystem 408 as part of the reclassified electrical die bin data 412 . For example, the statistical outlier detection subsystem 110 may use the new defect data signature to adjust the resulting electrical test bin data 112 when processing subsequent wafer lots 104 . As another example, the statistical outlier detection subsystem 110 can output the new defect data signature to the semiconductor fab characterization subsystem 102 to adjust components or methods or procedures of the semiconductor fab characterization subsystem 102 . It should be noted herein that instead of or in addition to statistical outlier detection subsystem 110 , semiconductor fab characterization subsystem 102 may directly receive new defect data signatures.

In a step 520, a representation of the statistical correlation is displayed. In some embodiments, filtered characterization data 406 and/or an overlay of characterization data 404 is presented on a graphical user interface over electrical test bin data 112 . For example, a representation can be a quantitative representation (such as a list of data, a table, or the like) or a qualitative representation (such as a graph, chart, image, video, or the like) of an overlay of data and corresponding metrics. Suggestions for improvements to various steps performed by method or process 200 and/or 500 may accompany the representation.

6A and 6B generally illustrate a probe map 300 of the lot 108 according to one or more embodiments of the present invention. In FIGS. 6A and 6B , filtered characterization data 406 and/or characterization data 404 are overlaid on detection map 300 as defect data 600 for a particular failure mechanism. Both the characterization data 404 and the electrical test wafer 108 (e.g., W1, W4, W6, W8, W12, W16, W20, W22, W24) with the electrical test failed die 304 and the rest of the wafers 108 in the lot A statistical correlation is performed between the bin data 112 .

Referring now to FIG. 6A , defect guidance correlation subsystem 408 determines that one or more defects of a particular failure mechanism are affected wafer 108 (e.g., W1, W4, Root cause of failure on W6, W8, W12, W16, W20, W22, W24). In this non-limiting example, the defect guidance related subsystem 408 determines that the electrical test subsystem 106 sufficiently captures escapes based on overlay such that there is no need to ink the die 302 on other wafers 108 .

Referring now to FIG. 6B , defect guidance correlation subsystem 408 determines that one or more defects of a particular failure mechanism are affected wafer 108 (e.g., W1, W4, Root cause of failure on W6, W8, W12, W16, W20, W22, W24). In this non-limiting example, the defect guidance related subsystem 408 determines that the electrical test subsystem 106 did not adequately capture the escape based on overlay and that the die 302 must be inked on the other wafer 108 . For example, the electrical test subsystem 106 may not have sufficiently caught the escape due to it being a Latent Reliability Defect (LRD) and/or due to a gap in test coverage.

It should be noted herein that the above examples represent two non-limiting examples of possible boundaries determined by the defect steering correlation subsystem 408 . For example, defect guidance related subsystem 408 may determine based on filtered characterization data 406 and/or characterization data 404 that only a minority of wafers 108 contain escapes or defects even though wafers 108 do not contain corresponding electrical test bin data 112 . However, it should be noted herein that if the system 400 and method or process 500 are applied conservatively, the system 400 and method or process 500 may tend to target entire groups of pairs having the same x, y position across the lot 108 for a particular failure mechanism. Die 302 is inked regardless of the number of escapes. Therefore, the above description should not be construed as limiting the scope of the present invention but as illustration only.

Although embodiments of the present invention depict defect data 600 comprising only filtered characterization data 406 and/or characterization data 404 for specific fault mechanisms overlaid on detection map 300, it should be noted herein that the overlay is not limited to The specific failure mechanism and any (or all) additional filtered characterization data 406 and/or characterization data 404 may be overlaid on the detection map 300 . Therefore, the above description should not be construed as limiting the scope of the present invention but as illustration only.

Although the embodiment of the invention depicts defect data 600 overlaid on electrical test bin data 112, it should be noted herein that system 400 can be configured to actively seek identification independent of the presence of electrical test bin data 112 Undetected repetitive spatial signatures in defectivity across wafer 104 . For example, this may be performed by or within defect guidance related subsystem 408 , defect reduction subsystem 402 , or a yield management system included in or associated with system 400 . Therefore, the above description should not be construed as limiting the scope of the present invention but as illustration only.

In this regard, the system 400 and method or process 500 can be configured to reduce potential yield loss or overkill by inking fewer good dies that are not part of presumed potential reliability issues, which can lead to Additional income for semiconductor suppliers.

Additionally, the system 400 and method or process 500 can be configured to provide information about the root cause of failure mechanisms (failures in the same location on multiple wafers), providing valuable feedback to a quality engineer and/or Semiconductor fabrication facilities to drive root cause elimination in future processed wafers.

Additionally, system 400 and method or process 500 may be configured to identify Z-PAT signatures on adjacent lots, including identifying other wafers that may be affected by the same root cause (e.g., other wafers than the lot under consideration) , which can lead to improved quality by reducing escapes on lots not identified by traditional Z-PAT ink scribbles. For example, identifying Z-PAT signatures on adjacent lots may provide the nuance to catch problems at an early stage of their gradual growth/propagation by providing the nuance through defect data not available through the electrical test bin data 112 .

Additionally, the system 400 and method or process 500 can be configured to actively identify wafer probes and/or other Z-PAT signatures that are entirely undetected by final testing.

7A and 7B illustrate a block diagram of a system 700 according to one or more embodiments of the invention. It is noted herein that system 700 may be configured to perform processing steps to fabricate and/or analyze semiconductor devices and/or components (eg, semiconductor dies) on semiconductor devices, as described herein. Additionally, it should be noted herein that system 700 may comprise all or a portion of system 100 and/or system 400, as described herein.

In some embodiments, system 700 includes semiconductor fab characterization subsystem 102 and electrical testing subsystem 106 .

In some embodiments, semiconductor fab characterization subsystem 102 includes one or more characterization tools configured to output characterization measurements within (or as) characterization data 404 . For example, characterization measurements may include, but are not limited to, baseline inspections (eg, sampling-based inspections), screening inspections at critical semiconductor device layers, or the like. For the purposes of the present invention, "characterization metrology" may refer to in-line defect detection and/or in-line metrology.

In one non-limiting example, semiconductor fab characterization subsystem 102 may include at least one inspection tool 702 (e.g., in-line sample analysis) for detecting defects in one or more layers of a sample 704 (e.g., wafer 104). tool). Semiconductor fab characterization subsystem 102 may generally include any number or type of inspection tools 702 . For example, detection means 702 may comprise an optical detection means configured to detect light based on the use of light from any source such as, but not limited to, a laser source, a lamp source, an x-ray source, or a broadband plasma source The samples are interrogated 704 to detect defects. As another example, a detection tool 702 may be configured to interrogate a sample 704 based on the use of one or more particle beams, such as, but not limited to, an electron beam, an ion beam, or a neutral particle beam Particle beam inspection tool for detecting defects. For example, inspection means 702 may include a transmission electron microscope (TEM) or a scanning electron microscope (SEM). For the purposes of the present invention, it is noted herein that the at least one inspection tool 702 may be a single inspection tool 702 or may represent a group of inspection tools 702 .

It should be noted herein that sample 704 may be one of a plurality of semiconductor wafers, wherein each semiconductor wafer of the plurality of semiconductor wafers is comprised in a number (e.g., tens, hundreds, several A plurality of (such as 1, 2, ... N) layers manufactured after the thousand) step, wherein each layer of the plurality of layers comprises a plurality of semiconductor crystal grains, wherein each semiconductor crystal grain of the plurality of semiconductor crystal grains comprises a plurality of blocks. In addition, it should be noted herein that the sample 704 may be one of a plurality of semiconductor dies arranged in a 2.5D lateral combination of a bare die on a substrate inside an advanced die package or a 3D die package Semiconductor die packaging.

For the purposes of the present invention, the term "defect" may refer to a physical defect found by an in-line inspection tool, a metrology outlier, or any other physical characteristic of a semiconductor device that should be considered an anomaly. A defect can be considered as any deviation of a fabricated layer or a fabricated pattern in a layer from a designed characteristic, including but not limited to physical, mechanical, chemical or optical properties. Additionally, a defect can be viewed as any deviation in the alignment or bonding of components in a manufactured semiconductor die package. Furthermore, a defect can be of any size relative to a semiconductor die or features thereon. In this way, a defect can be smaller than a semiconductor die (eg, at the scale of one or more patterned features), or can be larger than a semiconductor die (eg, as part of a wafer-scale scratch or pattern). For example, a defect may include a deviation in the thickness or composition of a sample layer before or after patterning. As another example, a defect may include a deviation in the size, shape, orientation, or position of a patterned feature. As another example, a defect may include defects associated with photolithography and/or etching steps, such as, but not limited to, bridges (or lack thereof), pits, or holes between adjacent structures. As another example, a defect may include a damaged portion of a sample 704, such as, but not limited to, a scratch or a wafer. For example, the severity of a defect (such as the length of a scratch, the depth of a pit, the quantity measurement or polarity of the defect, or the like) may be important and should be considered. As another example, a defect may include a foreign particle introduced into sample 704 . As another example, a defect may be a misaligned and/or misbonded packaged component on sample 704 . Therefore, it should be understood that the examples of disadvantages in the present invention are for illustration only and should not be construed as limiting.

In another non-limiting example, semiconductor fab characterization subsystem 102 may include at least one metrology tool 706 (eg, an online sample analysis tool) for measuring one or more properties of sample 704 or one or more layers thereof . For example, a metrology tool 706 can characterize properties such as, but not limited to, layer thickness, layer composition, critical dimension (CD), overlay, or photolithography processing parameters (e.g., illumination intensity or dose during a photolithography step) ). Accordingly, a metrology tool 706 can provide information about the sample 704, one or more layers of the sample 704, or one or more semiconductor dies of the sample 704 that can be related to the probability of manufacturing defects that can lead to reliability problems of the resulting fabricated device. manufacturing information. For the purposes of the present invention, it is noted herein that at least one metrology tool 706 may be a single metrology tool 706 or may represent a group of metrology tools 706 .

In some embodiments, semiconductor fab characterization subsystem 102 includes at least one semiconductor fabrication tool or processing tool 708 . It is noted herein that during fabrication of sample 704 , sample 704 may be moved between one or more detection tools 702 , one or more metrology tools 706 , and one or more processing tools 708 . For example, processing tool 708 may include any tool known in the art, including but not limited to an etcher, scanner, stepper, cleaner, or the like. For example, a fabrication process may include fabricating a plurality of dies (eg, a semiconductor wafer or the like) distributed across the surface of a sample, where each die includes layers of patterned material forming a device component. Each patterned layer may be formed by processing tool 708 through a series of steps including material deposition, lithography, etching to produce a pattern of interest and/or one or more exposure steps (e.g., by a scanner, stepper, or similar implementation). As another example, processing tool 708 may include any tool known in the art configured to package and/or combine semiconductor die into a 2.5D and/or 3D semiconductor die package. For example, the fabrication process may include, but is not limited to, aligning semiconductor die and/or electrical components on the semiconductor die. Additionally, a fabrication process may include, but is not limited to, bonding via hybrid (eg, die-to-die, die-to-wafer, wafer-to-wafer, or the like) solder, an adhesive, fasteners, or the like. or bonding semiconductor die and/or electrical components to the semiconductor die. For the purposes of the present invention, it is noted herein that at least one processing tool 708 may be a single processing tool 708 or may represent a group of processing tools 708 . It should be noted herein that for the purposes of the present invention, the term "manufacturing process" together with the respective variations of the term (such as "production line" and "manufacturing line", "manufacturer" and "manufacturer" or the like) may be considered as such effect.

In some embodiments, system 700 includes electrical test subsystem 106 for testing the functionality of one or more portions of a manufactured device. For example, electrical test subsystem 106 may be configured to generate test data 108 . It is noted herein that after fabrication of sample 704 is complete, sample 704 may be moved from semiconductor fab characterization subsystem 102 to electrical test subsystem 106 .

In one non-limiting example, electrical test subsystem 106 may include any number or type of electrical test tools 710 to perform a preliminary probing at a wafer level. For example, preliminary probing may not be designed to attempt to force failures at the wafer level.

In another non-limiting example, electrical testing subsystem 106 may include any number or type of stress testing tools 712 to test, inspect, or otherwise characterize one or more of a manufacturing device at any point in the manufacturing cycle the nature of the part. For example, stress testing tool 712 may include, but is not limited to, a pre-fired electrical wafer sort and final test (such as an e-test) or a post-fired electrical test configured to heat sample 704 (such as an oven or other heat source), cooling the sample 704 (such as a freezer or other cold source), operating the sample 704 at a wrong voltage (such as a power supply), or the like.

In some embodiments, semiconductor fab characterization subsystems 102 (e.g., inspection tools 702, metrology tools 706, or the like), electrical test subsystems 106 (e.g., including electrical test tools 710 and/or stress test tools 712 or or the like) to identify defects before or after one or more process steps (e.g., lithography, etching, alignment, bonding, or the like) are performed by one or more processing tools 708 for semiconductor A layer of interest within a die and/or semiconductor die package. Accordingly, defect detection at various stages of the manufacturing process may be referred to as in-line defect detection.

In some embodiments, system 700 includes a controller 714 . Controller 714 may communicate with semiconductor fab characterization subsystems 102 (e.g., including inspection tools 702 or metrology tools 706), electrical test subsystems 106 (eg, including electrical test tools 710 or stress test tools 712), or Any of the like components of system 700 are communicatively coupled. It should be noted herein that the embodiment depicted in FIG. 7A and the embodiment depicted in FIG. 7B may be considered part of the same system 700 or part of a different system 700 for purposes of the present disclosure. Additionally, it should be noted herein that the components within the system 700 depicted in FIG. 7A and the components within the system 700 depicted in FIG. 7B may communicate directly or through the controller 714 .

Controller 714 may include one or more processors 716 configured to execute programmed instructions maintained on memory 718, such as a memory medium, memory device, or the like. Controller 714 may be configured to perform one or all steps of method or procedure 200, method or procedure 500, and/or method or procedure 800 (eg, as described herein). As such, subsystems 110 , 402 and/or 408 may be stored in controller 714 and/or configured for execution by controller 714 . It should be noted herein, however, that subsystems 110, 402, and/or 408 may be separate from controller 714 and configured to communicate with controller 714 (eg, directly or communicatively coupled to a server or controller of controller 714). server, where a server or controller may include a processor and memory, and other communicatively coupled components as described in this disclosure).

One or more processors 716 may include any processor or processing element known in the art. For the purposes of the present invention, the terms "processor" or "processing element" may be broadly defined to include processors having one or more processing or logic elements (e.g., one or more graphics processing units (GPUs), microprocessing units (MPUs) , a system on a chip (SoC), one or more application specific integrated circuit (ASIC) devices, one or more field programmable gate arrays (FPGA), or one or more digital signal processors (DSP)). In this sense, one or more processors 716 may include any device configured to execute algorithms and/or instructions, such as program instructions stored in memory. In one embodiment, the one or more processors 716 may be embodied as a desktop computer, mainframe computer system, workstation, video computer, parallel processor, network computer, or configured to perform operations configured to operate or Any other computer system of a program that operates with components of systems 100, 400, and/or 700, as described herein.

Memory 718 may include any storage medium known in the art suitable for storing program instructions executable by associated respective processor(s) 716 . For example, memory 718 may include a non-transitory memory medium. As another example, memory 718 may include, but is not limited to, a read only memory (ROM), a random access memory (RAM), a magnetic or optical memory device (such as an optical disc), a magnetic tape , a solid state hard disk or the like. It should be further noted that memory 718 may be housed in a common controller housing with one or more processors 716 . In one embodiment, the memory 718 may be remotely located relative to the physical location of the respective one or more processors 716 . For example, each of the one or more processors 716 can access a remote memory (eg, a server) accessible through a network (eg, the Internet, an intranet, or the like).

In another embodiment, system 700 includes a user interface 720 coupled (eg, physically, electrically, communicatively, or the like) to controller 714 . For example, user interface 720 may be a separate device coupled to controller 714 . As another example, user interface 720 and controller 714 may be located within a common or common housing. However, it should be noted herein that the controller 714 may not include, need, or be coupled to the user interface 720 .

User interface 720 may include, but is not limited to, one or more desktop computers, laptop computers, tablet computers, and the like. User interface 720 may include a display for displaying data of systems 100, 400, and/or 700 to a user. The display of user interface 720 may comprise any display known in the art. For example, the display may include, but is not limited to, a liquid crystal display (LCD), an organic light emitting diode (OLED) based display, or a CRT display. Those skilled in the art will recognize that any display device capable of being integrated with user interface 720 is suitable for implementation in the present invention. In another embodiment, a user may input selections and/or commands in response to information displayed to the user via a user input device of the user interface 720 .

It should be noted herein that one or more of the systems 100, 400, 700 may be configured to operate using an electronic wafer identification (ID) tag, tag, designator, or the like. For example, an electronic wafer ID may be assigned to facilitate correlation of wafer-based bin data, characterization data (eg, in-line defect inspection data and/or metrology data), packaging test data, or the like.

FIG. 8 shows a method or procedure 800 depicting steps for fabricating, characterizing, and/or testing a semiconductor device in accordance with one or more embodiments of the present invention. It should be noted herein that the steps of the method or procedure 800 may be implemented in whole or in part by the system 700 depicted in FIGS. 7A and 7B . However, it should be further appreciated that the method or procedure 800 is not limited to the system 700 depicted in FIGS. 7A and 7B , as additional or alternative system-level embodiments may perform all or part of the steps of the method or procedure 800 .

In a step 802, a semiconductor device is fabricated. In some embodiments, a semiconductor device (eg, wafer 104 ) is fabricated via a plurality of semiconductor fabrication processes. For example, semiconductor fab characterization subsystem 102 may include, but is not limited to, configured to fabricate semiconductor devices, including those fabricated after a number (eg, tens, hundreds, thousands) of steps performed by a number of semiconductor fabrication processes. 1, 2, ... N layers) or one or more processing tools 708 .

In a step 804, characterization measurements are acquired during fabrication of the semiconductor device. In some embodiments, the characterization measurements are obtained by the semiconductor fab characterization subsystem 102 . For example, during the fabrication of one or more semiconductor devices (eg, wafer 104 ) via the plurality of semiconductor fabrication processes performed by the plurality of processing tools 708 (eg, before, between, and/or after steps), the Characterization measurements are performed using a plurality of characterization tools, such as detection tool 702 and/or metrology tool 706 .

In a step 806, the semiconductor device is provided to an electrical test subsystem. In some embodiments, the electrical test subsystem 106 receives the batch of wafers 104 . For example, electrical testing subsystem 106 may perform electrical testing and/or stress testing to generate test data 108 .

In a step 808, the characterization measurements are transmitted to a defect reduction subsystem or a defect steering correlation subsystem. In some embodiments, system 700 is configured to overlay characterization data 404 and/or filter characterization data 406 on electrical test bin data 112 via one or more steps of method or procedure 500 . For example, defect reduction subsystem 402 may be configured to receive characterization data 404 and generate filtered characterization data 406 via one or more steps of method or procedure 500 (eg, performed by one or more components of system 400 ). As another example, defect guidance correlation subsystem 408 may be configured to receive characterization data 404 and/or filter characterization data 406 . The defect guidance correlation subsystem 408 can be configured to overlay the characterization data 404 and/or filter the characterization data 406 on the electrical test bin data 112 .

In a step 810, control signals for adjustment are generated based on the reclassified electrical test bin data. In some embodiments, after overlaying the characterization data 404 and/or filtering the characterization data 406 on the electrical test bin data 112, the defect guidance correlation subsystem 408 performs a test on at least some of the electrical test bin data 112 Reclassification. Additionally, the defect guidance correlation subsystem 408 may newly discover defects based on overlays. It is noted herein that at least one of semiconductor device fabrication, characterization, and/or testing may be determined based on reclassification of electrical test bin data 112 and/or newly discovered defects during performance of method or procedure 500 or 800. one or more adjustments. For example, one or more adjustments may modify a manufacturing process or method, a characterization process or method, a testing process or method, or the like, provided in a feedback loop to a component within the semiconductor fab characterization subsystem 102 . For example, a manufacturing procedure or method, a characterization procedure or method, a testing procedure or method, or the like may be adjusted based on reclassification of the electrical test bucket data 112 and/or newly discovered defects during execution of the method or procedure 500 or 800 (eg via one or more control signals).

Adjustments are transmitted via a feedback loop (eg for adjusting future semiconductor devices). The control signals may adjust components of the system 100 or 400 and corresponding methods or procedures based on the reclassified electrical test bin data 112 . For example, improvements may be directed to adjusting one or more components of system 100 and/or steps of method or procedure 200 . For example, improvements may be directed to adjusting one or more components of semiconductor fab characterization subsystem 102 . As another example, improvements may be directed to adjusting one or more components of system 400 and/or steps of method or procedure 500 . As such, manufacturing and/or characterization procedures can be improved to result in reduced costs to the manufacturer (eg, time, money, or the like) while maintaining a desired level of quality (eg, PPB failure rate).

It should be noted herein that the methods or procedures 200, 500 and 800 are not limited by the steps and/or sub-steps presented. The methods or procedures 200, 500, and 800 may include more or fewer steps and/or sub-steps. The methods or procedures 200, 500, and 800 may perform steps and/or sub-steps concurrently. The methods or procedures 200, 500, and 800 may perform steps and/or sub-steps sequentially, including in the order provided or in an order other than that provided. Therefore, the above description should not be construed as limiting the scope of the present invention but as illustration only.

In one non-limiting example of the systems and methods described in this disclosure, for reliability sensitive devices, semiconductor fab characterization subsystem 102 may initiate screening tests at 4 to 8 key test steps to obtain characterization Data 404 , screening inspection is performed on each die of each lot 104 of a given semiconductor device. The characterization data 404 can be automatically forwarded to a plant-wide defect management subsystem 414 and/or a defect reduction subsystem 402 (e.g., an I-PAT analyzer or the like), which can weight and aggregate defect rates to arrive at an The die defectivity score, wherein the die-based defectivity score is forwarded as filtered characterization data 406 to the appropriate fab database.

After fab processing is complete, wafer 104 may undergo wafer sort electrical testing and separation via electrical test subsystem 106 . After separation, the dies are packaged and subjected to several electrical and stress tests to generate test data 108 . After all tests, the statistical outlier detection subsystem 110 applies a statistical outlier algorithm to the test data 108 (including, but not limited to, Z-PAT, for example). When instances of Z-PAT outliers are identified by the statistical outlier detection subsystem 110, the electrical test bin data 112 of the corresponding die will be sent to the defect guidance correlation subsystem 408 for analysis.

The defect guidance correlation subsystem 408 can use the characterization data 404 and/or filter the characterization data 406 to overlay the electrical test bin data 112 . Based on the overlay, the defect guidance correlation subsystem 408 can determine whether the defect was correctly found by the electrical test subsystem 106 in the electrical fault wafer 304 on the wafer 104, whether the electrical test subsystem 106 detected the defect by declaring the corresponding die as Whether a good die 302 misses a defect on the selected wafer 104 or the electrical test subsystem 106 incorrectly characterizes the wafer 104 as having a presumed electrical fault die 306 . Defect Guidance Correlation Subsystem 408 may determine whether ink should be applied to the die and provide this information to interested parties (eg, as Modified Electrical Die Bin Data 410) or at least to Statistical Outlier Detection Subsystem 110 ( For example as reclassified electrical die cell data 412).

As such, the systems and methods of the present invention can provide greater sampling (e.g., 100% inspection of all wafers in all lots rather than three wafers/lot or other subsets of wafers and lots) 10% inspection) while improving electrical testing and/or defect testing by identifying potential reliability and/or test gap defects. The systems and methods of the present invention can provide improved insight that will help automotive semiconductor device manufacturers reduce reliability failures in the PPM to PPB range. Semiconductor failure is the number one failure in the automotive manufacturing industry, and as the semiconductor content of automobiles increases, such as with the implementation of autonomous driving and electric vehicles, the problem will become more serious. Similarly, reliability issues are becoming increasingly important in industrial, biomedical, defense, aerospace, hyperscale data centers, and the like. Identifying test coverage gaps will make us aware of the limitations of electrical testing methods, and thus drive the adoption of in-line defect screening inspections to mitigate these issues.

An advantage of the present invention is directed to a system and method for Z-PAT defect-guided statistical outlier detection for semiconductor reliability failures. An advantage of the present invention is also directed to identifying potential reliability and/or test gap defects at the same x,y location on multiple wafers representing a lot using characterization data such as in-line defect inspection data and/or metrology data The Z-PAT defect signature. An advantage of the present invention is also directed to identifying Z-PAT defect signatures using a statistical outlier algorithm. The advantage of the present invention is also aimed at automatically notifying the factory engineer of the existence of the Z-PAT defect signature. An advantage of the present invention is also directed to characterizing Z-PAT defect signatures using spatial signature analysis methods. An advantage of the present invention is also directed to characterizing Z-PAT defect signatures using machine learning methods. An advantage of the present invention is also directed to identifying the presence or absence of Z-PAT defect signatures within a given lot. An advantage of the present invention is also directed to identifying Z-PAT defect signatures on adjacent lots. An advantage of the present invention is also directed to identifying Z-PAT defect signatures that are not detected by Z-PAT based on electrical testing. An advantage of the present invention is also directed to reducing overkill by using Z-PAT defect signatures to more precisely define the range of affected die/wafers. An advantage of the present invention is also directed to rapid identification of potential root causes based on learning from previously characterized Z-PAT defect signatures. The advantages of the present invention are also directed to the retrospective identification of Z-PAT defect signatures to use the stored online defect data to guide warranty and/or recall efforts.

The subject matter described herein sometimes depicts different components contained within, or connected with, other components. It is to be understood that such depicted architectures are illustrative only, and that in fact many other architectures can be implemented which achieve the same functionality. In a conceptual sense, any arrangement of components to achieve the same functionality is effectively "associated" such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as "associated with" each other such that the desired functionality is achieved, regardless of architectures or intermediary components. Likewise, any two components so associated can also be considered to be "connected" or "coupled" to each other to achieve the desired functionality, and any two components capable of being so associated can also be considered to be "coupled" to each other to achieve the desired functionality. Specific examples of "couplable" include, but are not limited to, physically interactable and/or physically interactable components and/or wirelessly interactable and/or wirelessly interactable components and/or logically interactable and/or logically interactable components.

It is believed that the invention and its many attendant advantages will be understood from the foregoing description, and it will be appreciated that various changes in form, construction and arrangement of components may be made without departing from the invention or sacrificing all of its material advantages. The forms described are for illustration only and such variations are intended to be covered and encompassed by the following claims. In addition, it should be understood that the present invention is defined by the claims of the appended applications.

100: system 102:Semiconductor Fab Characterization Subsystem 104: Semiconductor wafer 106:Electrical test subsystem 108: Test data/wafer 110: Statistical outlier detection subsystem 112: Abnormal value data/electrical test storage cell data 200: Method/Procedure 202: Step 204: step 206: Step 208: Step 210: step 300: Detection map 302: Good grain 304: Electrical fault grain 306: Potential Electrical Failure Die 400: system 402: Defect reduction subsystem 404: Featured data 406:Characterized data 408: Defect guidance related subsystems 410: Electrical grain storage data 412: Electrical grain storage data 414: Defect management subsystem of the whole manufacturing plant 500: Method/Procedure 502: Step 504: step 506: Step 508: Step 510: step 512: Step 514: step 516: step 518:Step 520: step 600: Defect data 700: system 702: detection tools 704:sample 706: Measuring tool 708: processing tool 710: Electrical test tools 712:Stress testing tool 714: Controller 716: Processor 718:Memory 720: user interface 800: Method/Procedure 802: step 804: step 806: Step 808:Step 810: step W1 to W24: Wafer

Those skilled in the art can better understand many advantages of the present invention by referring to the accompanying drawings, in which: 1 is a block diagram of a system for detecting semiconductor reliability failures according to one or more embodiments of the present invention; 2 is a flowchart illustrating one of the steps performed in a method or program for detecting semiconductor reliability failures in accordance with one or more embodiments of the present invention; FIG. 3A is a diagram illustrating a detection diagram of a semiconductor reliability failure detected according to one or more embodiments of the present invention; FIG. 3B is a diagram illustrating detection and prediction of semiconductor reliability failures according to one or more embodiments of the present invention; 4 is a block diagram of a system for Z-direction partial average test (Z-PAT) defect-guided statistical outlier detection for semiconductor reliability faults according to one or more embodiments of the present invention; 5 is a flow chart illustrating steps performed in a method or program for Z-PAT defect-guided statistical outlier detection for semiconductor reliability faults according to one or more embodiments of the present invention; Figure 6A is a diagram illustrating a detection of a detected semiconductor reliability fault overlaying characterization data according to one or more embodiments of the present invention; FIG. 6B is a diagram illustrating a detection of a detected semiconductor reliability fault overlaying characterization data according to one or more embodiments of the present invention; 7A is a block diagram of a system for fabricating, characterizing and/or testing semiconductor devices according to one or more embodiments of the present invention; 7B is a block diagram of a system for fabricating, characterizing and/or testing semiconductor devices according to one or more embodiments of the present invention; and 8 is a flow diagram illustrating one of the steps performed in a method or process for fabricating, characterizing, and/or testing a semiconductor device in accordance with one or more embodiments of the present invention.

100: system

102:Semiconductor Fab Characterization Subsystem

104: Semiconductor wafer

106:Electrical test subsystem

108: Test data/wafer

110: Statistical outlier detection subsystem

112: Abnormal value data/electrical test storage cell data

400: system

402: Defect reduction subsystem

404: Featured data

406:Characterized data

408: Defect guidance related subsystems

410: Electrical grain storage data

412: Electrical grain storage data

414: Defect management subsystem of the whole manufacturing plant

Claims (29)

A system comprising: A controller communicatively coupled to at least one semiconductor fab characterization subsystem, wherein the controller includes one or more processors configured to execute program instructions causing the one or more processes device: receiving electrical test cell data via a defect guidance related subsystem, wherein the electrical test cell data includes semiconductor die data for a plurality of wafers in a lot, wherein the electrical test cell data is configured to The test data is generated by a statistical outlier detection subsystem performing Z-direction partial average testing (Z-PAT), wherein an electrical test subsystem is configured to perform a Z-direction partial average test (Z-PAT) by testing the generating the test data for the plurality of wafers in the batch; receiving characterization data via the defect guidance related subsystem, wherein the characterization data for the plurality of wafers in the lot is provided by the semiconductor foundry characterization subsystem during manufacture of the plurality of wafers in the lot produce; determining via the defect guidance correlation subsystem a statistical correlation between the electrical test bin data and the characterization data at a same x, y location on each of the plurality of wafers in the lot; and A defect data signature is located on the plurality of wafers in the lot based on the statistical correlation via the defect guidance correlation subsystem. The system of claim 1, wherein the one or more processors are further configured to execute program instructions that cause the one or more processors to: processing the characterization data via a defect reduction subsystem configured to perform in-line defect partial average testing (I-PAT) to produce a subset of the characterization data as filtered characterization data, wherein the The defect reduction subsystem is configured to generate the filtered characterization data by performing I-PAT on the characterization data before the defect guidance related subsystem receives the filtered characterization data. The system of claim 1, wherein the one or more processors are further configured to execute program instructions that cause the one or more processors to: overlaying the characterization data on the electrical test cell data to determine the statistical correlation between the electrical test cell data and the characterization data via the defect guidance related subsystem, wherein the electrical test cell data Overlaying of the characterization data on occurs at the same x, y location on each of the plurality of wafers in the lot. The system of claim 1, wherein the one or more processors are further configured to execute program instructions that cause the one or more processors to: At least some of the semiconductor die data in the electrical test bin data are reclassified via the defect guidance related subsystem based on the defect data signatures. The system of claim 4, wherein the at least some semiconductor die data is reclassified as a good die, a known electrical failure die, or a potential electrical failure die. The system of claim 5, wherein the one or more processors are further configured to execute program instructions that cause the one or more processors to: transferring the reclassified semiconductor die data via the defect guidance related subsystem as improved electrical test bin data, wherein the improved electrical test bin data is included for the plurality of wafers having the same number in the lot Ink on selected wafers of the plurality of wafers in the lot to reclassify as a good die or a potential electrical failure die at the x,y position of a known electrical failure die on other wafers One or more suggestions for the semiconductor die data of the die. The system of claim 6, wherein the one or more processors are further configured to execute program instructions that cause the one or more processors to: The reclassified semiconductor die data is transmitted to the statistical outlier detection subsystem via the defect guidance related subsystem. The system of claim 4, wherein the one or more processors are further configured to execute program instructions that cause the one or more processors to: One or more adjustments to at least one of fabrication, characterization and/or testing of subsequent wafers in a subsequent batch are determined based on the reclassified semiconductor die data in the electrical test bin data. The system of claim 8, wherein the one or more processors are further configured to execute program instructions that cause the one or more processors to: One or more control signals are generated based on the one or more adjustments to at least one of fabrication, characterization and/or testing of the subsequent plurality of wafers in the subsequent batch. The system of claim 1, wherein the controller is communicatively coupled to the electrical testing subsystem. A method comprising: receiving electrical test cell data via a defect guidance related subsystem, wherein the electrical test cell data includes semiconductor die data for a plurality of wafers in a lot, wherein the electrical test cell data is configured to The test data is generated by a statistical outlier detection subsystem performing Z-Directional Partial Average Testing (Z-PAT), wherein an electrical test subsystem is configured to characterize the subsystem by testing the generating the test data for the plurality of wafers in the batch; Receiving characterization data via the defect guidance related subsystem, wherein the characterization data of the plurality of wafers in the lot is produced by the semiconductor foundry characterization subsystem of the plurality of wafers in the lot Generated during; determining via the defect guidance correlation subsystem a statistical correlation between the electrical test bin data and the characterization data at a same x, y location on each of the plurality of wafers in the lot; and A defect data signature is located on the plurality of wafers in the lot based on the statistical correlation via the defect guidance correlation subsystem. The method as claimed in item 11, further comprising: processing the characterization data via a defect reduction subsystem configured to perform in-line defect partial average testing (I-PAT) to produce a subset of the characterization data as filtered characterization data, wherein the The defect reduction subsystem is configured to generate the filtered characterization data by performing I-PAT on the characterization data before the defect guidance related subsystem receives the filtered characterization data. The method as claimed in item 11, further comprising: overlaying the characterization data on the electrical test cell data to determine the statistical correlation between the electrical test cell data and the characterization data via the defect guidance related subsystem, wherein the electrical test cell data Overlaying of the characterization data on occurs at the same x, y location on each of the plurality of wafers in the lot. The method as claimed in item 11, further comprising: At least some of the semiconductor die data in the electrical test bin data are reclassified via the defect guidance related subsystem based on the defect data signatures. The method of claim 14, wherein the at least some semiconductor die data is reclassified as a good die, a known electrical failure die, or a potential electrical failure die. The method as claimed in item 15, further comprising: transferring the reclassified semiconductor die data via the defect guidance related subsystem as improved electrical test bin data, wherein the improved electrical test bin data is included for the plurality of wafers having the same number in the lot Ink on selected wafers of the plurality of wafers in the lot to reclassify as a good die or a potential electrical failure die at the x,y position of a known electrical failure die on other wafers One or more suggestions for the semiconductor die data of the die. The method of claim 16, further comprising: The reclassified semiconductor die data is transmitted to the statistical outlier detection subsystem via the defect guidance related subsystem. The method of claim 14, further comprising: Determining one or more adjustments to at least one of fabrication, characterization and/or testing of a subsequent plurality of wafers in a subsequent lot based on the reclassified semiconductor die data in the electrical test bin data . The method of claim 18, further comprising: One or more control signals are generated based on the one or more adjustments to at least one of fabrication, characterization and/or testing of the subsequent plurality of wafers in the subsequent batch. A system comprising: A semiconductor fab characterization subsystem, wherein the semiconductor fab characterization subsystem is configured to manufacture a plurality of wafers in a lot, wherein the semiconductor fab characterization subsystem is configured to manufacture a plurality of wafers in the lot characterization data of the wafers in the lot generated during the manufacturing of the wafers; an electrical test subsystem, wherein the electrical test subsystem is configured to generate test data for the plurality of wafers in the lot after fabrication by the semiconductor fab characterization subsystem; and a controller communicatively coupled to at least the semiconductor fab characterization subsystem, wherein the controller includes one or more processors configured to execute programmed instructions causing the one or more processing device: receiving electrical test cell data via a defect guidance related subsystem, wherein the electrical test cell data includes semiconductor die data for the plurality of wafers in the lot, wherein the electrical test cell data is configured to Generated by a statistical outlier detection subsystem performing Z-direction partial average testing (Z-PAT); receiving the characterization data via the defect guidance related subsystem; determining, via the defect guidance correlation subsystem, a statistical correlation between the electrical test bin data and the characterization data at a same x, y location on each of the plurality of wafers in the lot; and A defect data signature is located on the plurality of wafers in the lot based on the statistical correlation via the defect guidance correlation subsystem. The system of claim 20, wherein the one or more processors are further configured to execute program instructions that cause the one or more processors to: processing the characterization data via a defect reduction subsystem configured to perform in-line defect partial average testing (I-PAT) to produce a subset of the characterization data as filtered characterization data, wherein the The defect reduction subsystem is configured to generate the filtered characterization data by performing I-PAT on the characterization data before the defect guidance related subsystem receives the filtered characterization data. The system of claim 20, wherein the one or more processors are further configured to execute program instructions that cause the one or more processors to: overlaying the characterization data on the electrical test cell data to determine the statistical correlation between the electrical test cell data and the characterization data via the defect guidance related subsystem, wherein the electrical test cell data Overlaying of the characterization data on occurs at the same x, y location on each of the plurality of wafers in the lot. The system of claim 20, wherein the one or more processors are further configured to execute program instructions that cause the one or more processors to: At least some of the semiconductor die data in the electrical test bin data are reclassified via the defect guidance related subsystem based on the defect data signatures. The system of claim 23, wherein the at least some semiconductor die data is reclassified as a good die, a known electrical failure die, or a potential electrical failure die. The system of claim 24, wherein the one or more processors are further configured to execute program instructions that cause the one or more processors to: transferring the reclassified semiconductor die data via the defect guidance related subsystem as improved electrical test bin data, wherein the improved electrical test bin data is included for the plurality of wafers having the same number in the lot Ink on selected wafers of the plurality of wafers in the lot to reclassify as a good die or a potential electrical failure die at the x,y position of a known electrical failure die on other wafers One or more suggestions for the semiconductor die data of the die. The system of claim 25, wherein the one or more processors are further configured to execute program instructions that cause the one or more processors to: The reclassified semiconductor die data is transmitted to the statistical outlier detection subsystem via the defect guidance related subsystem. The system of claim 23, wherein the one or more processors are further configured to execute program instructions that cause the one or more processors to: Determining one or more adjustments to at least one of fabrication, characterization and/or testing of a subsequent plurality of wafers in a subsequent lot based on the reclassified semiconductor die data in the electrical test bin data . The system of claim 27, wherein the one or more processors are further configured to execute program instructions that cause the one or more processors to: One or more control signals are generated based on the one or more adjustments to at least one of fabrication, characterization and/or testing of the subsequent plurality of wafers in the subsequent batch. The system of claim 20, wherein the controller is communicatively coupled to the electrical testing subsystem.

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