TW202247647A - Time schedule controller and display device - Google Patents

Abstract

The invention relates to the technical field of 3D display data processing, and discloses a time schedule controller. The device comprises an MCU, a 3D module, a receiving module and an output module. The MCU is connected with a first input end of the 3D module, the receiving module is connected with a second input end of the 3D module, and an output end of the 3D module is connected with the output module. The MCU is configured to receive eyeball coordinates and send the eyeball coordinates to the 3D module. The receiving module is configured to receive image data and transmit the image data to the 3D module. The 3D module is configured to generate pixel driving signals according to eyeball coordinates and image data. The output module is configured to output the pixel driving signal to the display screen. According to the time schedule controller provided by the invention, the user experience is improved to a certain extent. The invention further discloses a display device.

Description

Timing controller and display device

This application claims the priority of the Chinese patent application with the application number 2021105680995 and the title of the invention "a timing controller and display device" submitted to the China Intellectual Property Office on May 25, 2021, the entire contents of which are incorporated in this application by reference middle. The present application relates to the technical field of 3D display data processing, for example, to a timing controller and a display device.

At present, the data processing of electronic devices is usually performed by the central processing unit (CPU). Since the amount of 3D data is much larger than that of 2D data, problems such as delays and freezes will occur when the CPU processes 3D data, which will affect the user experience. .

In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is presented below. This summary is not intended to be an extensive overview or to identify key/critical elements or to delineate the scope of these embodiments, but rather serves as a prelude to the detailed description that follows.

Embodiments of the present disclosure provide a timing controller and a display device to solve the above technical problems.

In some embodiments, the timing controller includes: an MCU, a 3D module, a receiving module and an output module, the MCU is connected to the first input terminal of the 3D module, and the receiving module is connected to the second input terminal of the 3D module connected, the output terminal of the 3D module is connected with the output module, wherein, MCU configured to receive eyeball coordinates and send the eyeball coordinates to the 3D module; A receiving module configured to receive image data and send the image data to the 3D module; A 3D module configured to generate pixel driving signals according to eyeball coordinates and image data; The output module is configured to output the pixel driving signal to the display screen.

In some embodiments, the display device includes the timing controller as described above.

The timing controller and display device provided by the embodiments of the present disclosure can achieve the following technical effects: To a certain extent, the user experience is improved.

The foregoing general description and the following description are exemplary and explanatory only and are not intended to limit the application.

In order to understand the characteristics and technical content of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. The attached drawings are only for reference and description, and are not intended to limit the embodiments of the present disclosure. In the following technical description, for convenience of explanation, numerous details are given to provide a full understanding of the disclosed embodiments. However, at least one embodiment can be practiced without these details. In other instances, well-known structures and devices may be shown simplified in order to simplify the drawings.

Usually, the display screen (or display panel) has a timing controller (Timing Controller, TCON), also called TCON board or screen driver board, which is used to receive red, green and blue (RGB) data signals, clock signals and control signals, etc. Input signals, and then convert these input signals into signals that can drive the display screen.

An embodiment of the present disclosure provides a timing controller, which will be described below.

FIG. 1 shows a schematic structural diagram of a timing controller in an embodiment of the present disclosure.

As shown in the figure, the timing controller 600 may include: a microprocessor (MCU, Microcontroller Unit) 10, a three-dimensional 3D module 20, a receiving module 30 and an output module 40, the first connection between the MCU 10 and the 3D module 20 The input end is connected, the receiving module 30 is connected to the second input end of the 3D module 20, and the output end of the 3D module 20 is connected to the output module, wherein, The MCU 10 is configured to receive eyeball coordinates and send the eyeball coordinates to the 3D module 20; The receiving module 30 is configured to receive image data and send the image data to the 3D module 20; The 3D module 20 is configured to generate pixel driving signals according to eyeball coordinates and image data; The output module 40 is configured to output the pixel driving signal to the display screen.

The embodiment of the present disclosure improves the existing timing controller. A hardware unit for computing image data is added to the timing controller. The CPU does not need to participate in any computing of image data, and the computing of image data is controlled by timing The implementation of dedicated hardware devices such as controllers improves the efficiency to a certain extent. Using the timing controller provided by the embodiments of the present disclosure for 3D display can increase the processing rate, reduce the delay, and improve the user's viewing experience.

In some embodiments, the 3D module 20 may include two input pins and one output pin, the output pin of the MCU 10 may be connected to one input pin of the 3D module 20, and the output pin of the receiving module 30 It can be connected with another input pin of the 3D module 20 , and the input pin of the output module 40 is connected with the output pin of the 3D module 20 .

In some embodiments, the input terminal of the timing controller 600 may be connected to the application processor AP, and the AP provides image data. Optionally, the image data may be a movie frame acquired by an image sensor, or a virtual movie frame generated by the AP.

In some embodiments, the image profiles may include left-eye image profiles and right-eye image profiles.

In some embodiments, the MCU may be connected to the image sensor, or to the processing unit of the image sensor, to obtain the user's eye coordinates. Optionally, the eyeball coordinates may include horizontal and vertical coordinates x and y values in the screen coordinate system, and may also include a depth value z from the eyeball to the screen. The eyeball coordinates may include the coordinates of the left eye and the coordinates of the right eye.

In some embodiments, the output module 40 may transmit signals in a peer-to-peer (P2P, Peer-to-peer) manner, or in other manners.

In some embodiments, the 3D module 20 and the output module 40 can be connected to the MCU 10 through a bus. Optionally, the bus may be an AXI (Advanced extensible Interface) bus or the like.

FIG. 2 shows another schematic structural diagram of the timing controller in the embodiment of the present disclosure.

As shown in the figure, in some embodiments, the MCU 10 may include a processing unit 100 and a first interface 101, wherein, The first interface 101 may be configured to receive eye coordinates; The processing unit 100 may be configured to send the eyeball coordinates to the 3D module 20 .

In some embodiments, the first interface 101 may be an integrated circuit bus (IIC, Inter-Integrated Circuit) interface.

In some embodiments, the processing unit 100 can control the first interface 101 to obtain eye coordinates, and control the first interface 101 to send the eye coordinates to the 3D module 20 .

Fig. 3 shows another schematic structural diagram of the timing controller in the embodiment of the present disclosure.

As shown in the figure, in some embodiments, the MCU 10 may further include: a second interface 102, the second interface 102 may be connected to the memory 104, and the memory 104 may pre-store optical data; The processing unit 100 may also be configured to send a read command to the second interface 102; The second interface 102 may be configured to obtain optical data from the memory 104 according to a read command, and send the optical data to the 3D module 20; The 3D module 20 can be configured to generate pixel driving signals according to eyeball coordinates, optical data and image data.

In some embodiments, the processing unit 100 may send a read command to the second interface 102 after each power-on.

In some embodiments, the optical data may include a corresponding relationship between pixels on the display screen (each pixel may include multiple sub-pixels, each sub-pixel may also include multiple composite sub-pixels, etc.) and gratings. Optionally, the grating may include a lenticular grating or the like. The corresponding relationship may include the number of compound sub-pixels in each grating, the horizontal position arrangement, the vertical position arrangement and the like.

In some embodiments, the optical data may be received from the application processor AP, or obtained from other means. The first interface 101 may be connected to an application processor AP to receive optical data sent by the AP.

In some embodiments, the second interface 102 may be a Serial Peripheral Interface (SPI, Serial Peripheral Interface).

In some embodiments, the memory 104 may be a non-volatile storage medium Flash. Optionally, when the second interface 102 is an SPI interface, the memory 104 may be a SPI Flash storage device.

In some embodiments, the first interface 101 may also be configured to receive optical data; The processing unit 100 may also be configured to send a write command to the second interface 102; The second interface 102 can also be configured to acquire optical data according to a write command and store the optical data in the memory 104 .

Fig. 4 shows another schematic structural diagram of the timing controller in the embodiment of the present disclosure.

As shown in the figure, in some embodiments, the timing controller 600 may also include an image transmission interface unit 50 connected to the input end of the receiving module 30, The image transmission interface unit 50 may be configured to receive the image data in the first protocol format and convert it into the second protocol format before sending it to the receiving module 30 .

In some embodiments, the image transmission interface unit 50 may be a Mobile Industry Processor Interface (MIPI, Mobile Industry Processor Interface). Optionally, it may be a MIPI display interface (DSI, Display Serial Interface).

Fig. 5 shows another schematic structural diagram of the timing controller in the embodiment of the present disclosure.

As shown in the figure, in some embodiments, the MCU 10 may further include a third interface 103, The third interface 103 may be configured to send initialization data to the image transmission interface unit; The image transmission interface unit 50 may also be configured to perform initialization according to initialization data.

In some embodiments, the third interface 103 may be an IIC interface.

In some embodiments, the image transmission interface unit 50 may further include an initialization interface configured to receive initialization data.

In some embodiments, the initialization interface of the image transmission interface unit 50 may be an IIC interface configured to receive initialization data. Optionally, the IIC interface of the image transmission interface unit 50 may be an IIC slave interface IIC-s, the third interface 103 may be an IIC master master interface IIC-m, and the first interface 101 may be a slave interface IIC -s.

In some embodiments, the MCU 10 can also be configured to send mode control information to the 3D module 20, and the 3D module 20 can be configured to output the corresponding mode according to the eyeball coordinates, optical data, mode control information and image data. Pixel drive signal.

In some embodiments, the mode control information may include at least one of the following: 2D mode, calibration mode, 3D mode; The 3D module 20 can be configured to output the received image data after pixel expansion according to the number of composite sub-pixels of each pixel in the 2D mode; output the pre-stored standard image in the calibration mode; in the 3D mode After the received image data is determined according to the eyeball coordinates and optical data, the pixel arrangement of the left and right eyes is determined and then output.

Fig. 6 shows another schematic structural diagram of the timing controller in the embodiment of the present disclosure.

As shown in the figure, in some embodiments, the 3D module 20 may include a register 201, a selection unit 202, a standard graphic unit 203, and a 3D algorithm unit 204, and the register 201 is connected to the selection unit 202 and the 3D algorithm respectively. Unit 204 is connected to, The selection unit 202 may be configured to receive the mode control information of the register 201 to select and connect to the standard graphics unit 203 or the 3D algorithm unit 204; The standard map unit 203 can be configured to output a pre-stored standard map in the calibration mode; The 3D algorithm unit 204 may be configured to output the received image data according to the eyeball coordinates and optical data to determine the pixel arrangement of the left and right eyes in the 3D mode, and output the received image data in the 2D mode according to each The composite sub-pixel quantity of the pixel is output after pixel expansion.

In some embodiments, the processing unit 100 can configure the value of the 3D mode in the register 201 to be 1 through the bus, which means that the 3D module 20 needs to work in the 3D mode. When the 3D module 20 determines that the value of the 3D mode is 1 , the 3D algorithm unit 204 performs 3D calculation on the image data. Optionally, the specific 3D operation may be implemented by using an existing 3D algorithm.

In some embodiments, the processing unit 100 can configure the value of the calibration mode in the temporary register 201 to be 1 and the value of the 3D mode to be 0 through the bus configuration, which means that the 3D module 20 needs to work in the calibration mode, and the standard image unit 203 is in the calibration mode. When the value of the calibration mode is judged to be 1, the pre-stored standard map is output.

In some embodiments, the processing unit 100 can configure the value of the calibration mode in the register 201 to be 0 and the value of the 3D mode to be 0 through the bus configuration, which means that the 3D module 20 needs to work in the 2D mode, and the 3D algorithm unit 204 When it is judged that the value of the calibration mode is 0 and the value of the 3D mode is 0, each pixel of the image data is copied and output to the output module 40 .

In some embodiments, in the 2D mode, the 3D algorithm unit 204 can copy each pixel of the image data N times and output it to the output module 40 . The number of duplications is related to the number of composite sub-pixels included in each sub-pixel. For example: each pixel includes three sub-pixels, and each sub-pixel includes 4 composite sub-pixels. In the 2D mode, each sub-pixel of the image data can be copied 4 times and then output to the output module 240 .

In some embodiments, the selection unit 202 may be implemented using a switch circuit. Optionally, the selection unit 202 may include three input pins A, B, and C, wherein, the input pin A is a 3D mode, the input pin B is a calibration mode, the input pin C is a 2D mode, and the three pins The high and low levels of the pin can determine which module is connected to the output pin. For example: pin A input high level, pin B and pin C low level, the selection unit 202 and 3D algorithm unit 204 conduction (3D mode); pin B input high level, pin A and pin C low level, the selection unit 202 is connected to the standard image unit 203 (calibration mode); pin C input is high level, pin A and pin B are low level, the selection unit 202 is connected to the 3D algorithm unit 204 (2D model).

In some embodiments, the processing of the 2D mode can also be implemented by a functional unit independent of the 3D algorithm unit 204 .

In some embodiments, each functional module and unit in the embodiments of the present disclosure may be implemented by means of hardware circuits and the like.

An embodiment of the present disclosure also provides a display device, including the above timing controller 600 .

Fig. 7 shows a schematic structural diagram of a display device in an embodiment of the present disclosure.

As shown, in some embodiments, the display device may include a timing controller 600 .

Optionally, a display screen 800 may also be included, and the timing controller 600 may output pixel driving signals to the display screen 800 to drive the display of the display screen.

The timing controller and the display device provided by the embodiments of the present disclosure can be used in liquid crystal display screens (LCD, Liquid Crystal Display), light-emitting diodes (LED, Light-Emitting Diode) and other devices.

The timing controller and the display device provided by the embodiments of the present disclosure can be used in 2D, 3D and other display devices.

In some embodiments, the display device may further include other components for supporting the normal operation of the display device, such as at least one of components such as a communication interface, a frame, and a control circuit.

The above description and drawings sufficiently illustrate the embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, procedural, and other changes. The examples merely represent possible variations. Individual components and functions are optional unless explicitly required, and the order of operations may vary. Portions and features of some embodiments may be included in or substituted for those of other embodiments. The scope of the disclosed embodiments includes the full scope of the claimed items, and all available equivalents of the claimed items. When used in this application, although the terms "first", "second", etc. may be used in this application to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without changing the meaning of the description, a first element may be called a second element, and likewise, a second element may be called a first element, as long as all occurrences of "first element" are renamed consistently and all occurrences of "Second component" can be renamed consistently. Both the first element and the second element are elements, but may not be the same element. Also, the terms used in the present application are only used to describe the embodiments and are not used to limit the claimed items. As used in the examples and description of the claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well unless the context clearly indicates otherwise . Similarly, the term "and/or" as used in this application is meant to include any and all possible combinations of one or more of the associated listed ones. In addition, when used in this application, the term "comprise" and its variants "comprises" and/or comprising (comprising) etc. refer to stated features, integers, steps, operations, elements, and/or The presence of an element does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, elements and/or groupings of these. Without further limitations, an element qualified by the statement "comprising a..." does not preclude the presence of additional identical elements in the process, method or apparatus comprising that element. Herein, each embodiment may focus on the differences from other embodiments, and reference may be made to each other for the same and similar parts of the various embodiments. For the method, product, etc. disclosed in the embodiment, if it corresponds to the method part disclosed in the embodiment, then the relevant part can refer to the description of the method part.

Those skilled in the art can appreciate that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed by hardware or software may depend on the specific application and design constraints of the technical solution. Those skilled in the art may implement the described functions using different methods for each specific application, but such implementation should not be considered as exceeding the scope of the disclosed embodiments. Those skilled in the art can clearly understand that for the convenience and brevity of description, the working process of the above-described system, device and unit can refer to the corresponding process in the foregoing method embodiment, and details are not repeated here.

In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of units may only be a logical function division. In actual implementation, there may be other division methods, for example, multiple units or elements may be combined or integrated. to another system, or some features may be ignored, or not implemented. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms. A unit described as a separate component may or may not be physically separated, and a component displayed as a unit may or may not be a physical unit, that is, it may be located in one place, or may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiments of the present disclosure may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.

In the drawings, the width, length, thickness, etc. of structures such as elements or layers may be exaggerated in consideration of clarity and descriptiveness. When a structure such as an element or layer is said to be "disposed on" (or "mounted on", "laid on", "attached to", "coated on" and similar descriptions) another element or layer is "on" or "on" ”, the element or layer may be directly “disposed on” or “on” the other element or layer mentioned above, or there may be an intermediate element or layer between the above-mentioned another element or layer , or even partly embedded in another element or layer above.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to embodiments of the disclosure. In this regard, each block in the flowchart or block diagram may represent a module, program segment, or part of code that includes at least one Executable instructions. In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks in succession may, in fact, be executed substantially concurrently, or they may sometimes be executed in the reverse order, depending upon the functionality involved. In the descriptions corresponding to the flowcharts and block diagrams in the drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no difference between different operations or steps. specific order. For example, two consecutive operations or steps may, in fact, be performed substantially concurrently, or they may sometimes be performed in the reverse order, depending upon the functionality involved. Each block in the block diagrams and/or flowcharts, and combinations of blocks in the block diagrams and/or flowcharts, can be implemented by a dedicated hardware-based system that performs the specified functions or actions, or can be It is realized by a combination of special-purpose hardware and computer instructions.

10: Microprocessor 100: processing unit 101: The first interface 102: Second interface 103: The third interface 104: memory 20:3D module 201: scratchpad 202: Select unit 203:Standard graph unit 204: 3D algorithm unit 30: Receiving module 40: Output module 50: Image transmission interface unit 600: Timing controller 800: display screen

At least one embodiment is exemplified through the corresponding drawings, and these exemplifications and drawings do not constitute a limitation to the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements. does not constitute a proportional limit, and where: Figure 1 shows a schematic structural diagram of a timing controller in an embodiment of the present disclosure; Figure 2 shows another schematic structural diagram of a timing controller in an embodiment of the present disclosure; Figure 3 shows another schematic structural diagram of the timing controller in the embodiment of the present disclosure; Figure 4 shows another schematic structural diagram of a timing controller in an embodiment of the present disclosure; Fig. 5 shows another schematic structural diagram of a timing controller in an embodiment of the present disclosure; Figure 6 shows another schematic structural diagram of a timing controller in an embodiment of the present disclosure; Fig. 7 shows a schematic structural diagram of a display device in an embodiment of the present disclosure.

10: Microprocessor

20:3D module

30: Receiving module

40: Output module

600: timing controller

Claims (10)

A timing controller, comprising: a microprocessor MCU, a 3D module, a receiving module and an output module, the MCU is connected to the first input end of the 3D module, the receiving module is connected to the 3D module The second input terminal of the group is connected, and the output terminal of the 3D module is connected with the output module, wherein, The MCU is configured to receive eye coordinates and send the eye coordinates to the 3D module; The receiving module is configured to receive image data and send the image data to the 3D module; The 3D module is configured to generate a pixel driving signal according to the eyeball coordinates and the image data; The output module is configured to output the pixel driving signal to a display screen. The timing controller according to claim 1, wherein the MCU includes a processing unit and a first interface, The first interface is configured to receive eye coordinates; The processing unit is configured to send the eyeball coordinates to the 3D module. The timing controller according to claim 2, wherein the MCU further includes a second interface, the second interface is connected to a memory, and the memory pre-stores optical data; The processing unit is further configured to send a read command to the second interface; The second interface is configured to obtain the optical data from the memory according to the read command, and send the optical data to the 3D module; The 3D module is configured to generate a pixel driving signal according to the eye coordinates, the optical data and the image data. The timing controller according to claim 3, wherein, The first interface is further configured to receive optical data; The processing unit is further configured to send a write command to the second interface; The second interface is further configured to acquire the optical data according to the write command and store the optical data in the memory. The timing controller according to claim 2, further comprising an image transmission interface unit connected to the input end of the receiving module, The image transmission interface unit is configured to receive image data in a first protocol format and convert it into a second protocol format before sending it to the receiving module. The timing controller according to claim 5, wherein the MCU further includes a third interface, The third interface is configured to send initialization data to the image transmission interface unit; The image transmission interface unit is further configured to perform initialization according to the initialization data. The timing controller according to claim 1, wherein the MCU is further configured to send mode control information to the 3D module, and the 3D module is configured to be based on the eye coordinates, the optical data, The mode control information and the image data output a pixel driving signal in a corresponding mode. The timing controller according to claim 7, wherein the mode control information includes at least one of the following: 2D mode, calibration mode, and 3D mode; The 3D module is configured to output the received image data after pixel expansion according to the number of composite sub-pixels of each pixel in 2D mode; output the pre-stored standard image in calibration mode; The received image data is output after determining the pixel arrangement of the left and right eyes according to the eyeball coordinates and the optical data. The sequence controller according to claim 8, wherein the 3D module includes a temporary register, a selection unit, a standard image unit, and a 3D algorithm unit, and the temporary register is connected to the selection unit and the 3D algorithm unit respectively , The selection unit is configured to receive the mode control information of the temporary register and select to connect with the standard graphics unit or the 3D algorithm unit; The standard map unit is configured to output a pre-stored standard map in calibration mode; The 3D algorithm unit is configured to output the received image data according to eyeball coordinates and optical data to determine the pixel arrangement of the left and right eyes in 3D mode, and output the received image data in 2D mode according to each The composite sub-pixel quantity of the pixel is output after pixel expansion. A display device, comprising the timing controller according to any one of claims 1 to 9.

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