TW202247498A - Bonding structures and methods for forming the same - Google Patents
Bonding structures and methods for forming the same Download PDFInfo
- Publication number
- TW202247498A TW202247498A TW110117829A TW110117829A TW202247498A TW 202247498 A TW202247498 A TW 202247498A TW 110117829 A TW110117829 A TW 110117829A TW 110117829 A TW110117829 A TW 110117829A TW 202247498 A TW202247498 A TW 202247498A
- Authority
- TW
- Taiwan
- Prior art keywords
- silver
- substrate
- bonding
- forming
- adhesive layer
- Prior art date
Links
Images
Landscapes
- Laminated Bodies (AREA)
- Electroluminescent Light Sources (AREA)
- Adhesive Tapes (AREA)
- Adhesives Or Adhesive Processes (AREA)
Abstract
Description
本揭露有關於一種接合結構及其形成方法,且特別關於一種具有銀部件的接合結構及其形成方法。The present disclosure relates to a bonding structure and a method of forming the same, and more particularly to a bonding structure with silver components and a method of forming the same.
發光二極體(light emitting diode, LED)的封裝製程包括:切割晶圓、固晶、連線、封膠等步驟。其中固晶(die bonding)製程需在較低的溫度進行以避免LED元件損毀,同時要求固晶結構良好的導熱性,使LED封裝具有較佳的散熱效果,以確保LED元件的發光效率。此外,固晶接合界面需有足夠的機械強度與可靠度。The packaging process of light-emitting diodes (light emitting diodes, LEDs) includes steps such as wafer dicing, die bonding, wiring, and glue sealing. Among them, the die bonding process needs to be carried out at a lower temperature to avoid damage to the LED components. At the same time, the die bonding structure is required to have good thermal conductivity, so that the LED package has a better heat dissipation effect to ensure the luminous efficiency of the LED components. In addition, the die bonding interface needs to have sufficient mechanical strength and reliability.
習知針對LED晶粒與其封裝基板之接合採用導熱膠黏著(adhesive)方法。其接合溫度較低,但接合界面導熱性不佳而無法承受較高的LED操作溫度。為了增加固晶接合界面的導熱性,近年來開始採用熔點250℃以下之銲錫合金軟銲(soldering)接合。其接合溫度亦不高,但接合後LED產品無法承受較高的操作溫度。因此開始使用熔點278℃之Au20Sn高溫銲錫合金軟銲接合。其固晶接合結構雖具有良好的導熱性與耐溫性,但其接合溫度高達300℃以上,會導致LED元件在高溫軟銲接合製程中失效。在此高溫軟銲接合後,在冷卻至室溫的期間,熱應力會導致接合界面破裂,因此良率不佳,且材料成本較高。Conventionally, a heat-conducting adhesive method is used for the bonding of the LED die and its packaging substrate. Its bonding temperature is low, but the thermal conductivity of the bonding interface is not good enough to withstand the high LED operating temperature. In order to increase the thermal conductivity of the die bonding interface, in recent years, solder alloys with a melting point below 250°C have been used for soldering. The bonding temperature is not high, but LED products cannot withstand high operating temperature after bonding. Therefore, Au20Sn high-temperature solder alloy with a melting point of 278°C has been used for soft soldering. Although its die bonding structure has good thermal conductivity and temperature resistance, its bonding temperature is as high as 300° C., which will cause LED components to fail during the high temperature soldering process. After this high temperature solder bonding, during cooling to room temperature, thermal stress can cause cracks at the bonded interface, resulting in poor yield and high material cost.
另一些習知技術採用Au-Sn共晶接合(eutectic bonding)。先在LED晶粒背面及其封裝基板表面鍍純Au層,再於其上鍍純Sn層。隨後加熱至Au-Sn二元相圖的共晶點以上的溫度,使藍寶石晶粒與LED封裝基板之間的純Au層與純Sn層產生共晶反應,形成富Au與富Sn之共晶合金界面結構。其LED封裝雖然具有良好的導熱性與耐溫性,但因為接合溫度過高,容易造成LED失效及其封裝毀損,材料成本亦偏高。此外,針對微型發光二極體(micro-LED)或迷你發光二極體(mini-LED),由於其晶片極小,習知較高溫的固晶接合技術在接合後冷卻至室溫時,晶片移位將導致晶片與基板無法對齊接合。Other known technologies use Au-Sn eutectic bonding. First, a pure Au layer is plated on the back of the LED crystal grain and the surface of the packaging substrate, and then a pure Sn layer is plated on it. Then heated to a temperature above the eutectic point of the Au-Sn binary phase diagram, so that the pure Au layer and the pure Sn layer between the sapphire crystal grain and the LED packaging substrate have a eutectic reaction, forming a eutectic of Au-rich and Sn-rich alloy interface structure. Although its LED package has good thermal conductivity and temperature resistance, but because the bonding temperature is too high, it is easy to cause LED failure and package damage, and the material cost is also high. In addition, for micro-LEDs (micro-LEDs) or mini-LEDs (mini-LEDs), due to the extremely small size of the wafers, it is known that when the wafers are cooled to room temperature after bonding, the wafers will not move. This will cause the die to be bonded out of alignment with the substrate.
奈米孿晶薄膜已被應用在接合製程中。中華民國發明專利第I6865724號揭示一種電鍍銅奈米孿晶薄膜的電連接機構及方法,其在0.8MPa至3MPa壓力及200℃至350℃溫度進行兩個分別覆蓋金屬層的氧化物基板的接合。此習知技術雖可在0.8MPa至3MPa的低壓進行接合,然而其在接合前必須先對奈米孿晶薄膜進行化學機械拋光(chemical mechanical polishing, CMP)以減少表面粗糙度,不僅製程繁複且會破壞奈米孿晶薄膜。中華民國發明專利第I521104號揭示一種先在基板上電鍍銅晶種層再電鍍鎳奈米孿晶薄膜,之後將二基板接合的封裝結構及方法;以及中華民國發明專利第I519681號揭示一種在半導體晶片、電路板或導電基板表面電鍍金奈米孿晶薄膜,之後相互接合的結構及方法。Nano-twinned films have been used in bonding processes. Invention Patent No. I6865724 of the Republic of China discloses an electrical connection mechanism and method for electroplated copper nano-twinned films, which bond two oxide substrates respectively covered with metal layers at a pressure of 0.8MPa to 3MPa and a temperature of 200°C to 350°C . Although this conventional technology can be bonded at a low pressure of 0.8MPa to 3MPa, it must first perform chemical mechanical polishing (CMP) on the nano-twinned film to reduce surface roughness before bonding, which is not only complicated and will destroy the nano-twinned film. Invention Patent No. I521104 of the Republic of China discloses a packaging structure and method for first electroplating a copper seed layer on a substrate and then electroplating a nickel nano-twin film, and then bonding the two substrates; and Invention Patent No. I519681 of the Republic of China discloses a semiconductor The invention relates to a structure and method for electroplating gold nano twin film on the surface of a wafer, a circuit board or a conductive substrate, and then bonding each other.
然而,習知技術均採用50rpm甚至1500rpm的高速旋轉電鍍方法,製程及薄膜品質均控制不易,孿晶間距較大,且其[111]優選結晶方位低於90%。中華民國發明專利第I432613號顯示其孿晶結構的X光繞射(XRD)圖中仍有明顯的Cu(222)結晶方位;中華民國發明專利第I507548號顯示其孿晶結構的X光繞射圖中仍有明顯的Au(222)結晶方位,其[111]優選結晶方位甚至會低到僅50%。However, the conventional technology adopts a high-speed spin plating method of 50 rpm or even 1500 rpm, the process and film quality are not easy to control, the twin spacing is relatively large, and the [111] preferred crystallographic orientation is less than 90%. Invention Patent No. I432613 of the Republic of China shows that there are still obvious Cu(222) crystal orientations in the X-ray diffraction (XRD) diagram of its twin structure; Invention Patent No. I507548 of the Republic of China shows the X-ray diffraction of its twin structure There is still an obvious Au (222) crystallographic orientation in the figure, and its [111] preferred crystallographic orientation is even as low as only 50%.
此外,元件或接點尺寸會受到電鍍製程的限制。詳細而言,一般小於2微米的元件或接點無法以電鍍方法製作,且電鍍製程產生的電鍍廢液亦有環保顧慮。再者,直接電鍍奈米孿晶薄膜於基板上,基板與奈米孿晶薄膜之間的接合力不足,會導致薄膜剝落從而影響薄膜整體可靠度。綜合以上問題,現有的接合技術仍面臨許多挑戰。In addition, the component or contact size will be limited by the plating process. In detail, generally, components or contacts smaller than 2 microns cannot be produced by electroplating, and the electroplating waste liquid produced in the electroplating process also has environmental concerns. Furthermore, direct electroplating of the nano-twinned film on the substrate will result in insufficient bonding force between the substrate and the nano-twinned film, which will cause the film to peel off and affect the overall reliability of the film. In view of the above problems, the existing bonding technology still faces many challenges.
本揭露的一些實施例提供一種接合結構,包括:第一基板,具有相反的第一表面以及第二表面;發光元件,於第一表面上;黏著層,於第二表面上;第二基板,與第一基板的第二表面相對設置;導電層,於第二基板上並朝向第二表面;以及銀部件,於黏著層與導電層之間,其中銀部件包括銀奈米孿晶結構,且銀奈米孿晶結構具有平行排列孿晶界,其中平行排列孿晶界包括90%以上的[111]結晶方位。Some embodiments of the present disclosure provide a bonding structure, including: a first substrate having opposite first and second surfaces; a light emitting element on the first surface; an adhesive layer on the second surface; a second substrate, Set opposite to the second surface of the first substrate; the conductive layer is on the second substrate and faces the second surface; and the silver component is between the adhesive layer and the conductive layer, wherein the silver component includes a silver nano twin structure, and The silver nanotwin structure has parallel twin boundaries, and the parallel twin boundaries include more than 90% of the [111] crystallographic orientations.
在一些實施例中,銀部件的至少80%為銀奈米孿晶結構。In some embodiments, at least 80% of the silver feature is silver nanotwinned.
在一些實施例中,銀部件的厚度至少為3.0微米。In some embodiments, the thickness of the silver features is at least 3.0 microns.
在一些實施例中,銀奈米孿晶結構的厚度至少為2.0微米。In some embodiments, the thickness of the silver nanotwinned structure is at least 2.0 microns.
在一些實施例中,平行排列孿晶界的間距為1奈米至100奈米。In some embodiments, the distance between the parallel aligned twin boundaries is 1 nm to 100 nm.
在一些實施例中,黏著層的厚度為0.01微米至1微米。In some embodiments, the adhesive layer has a thickness of 0.01 micron to 1 micron.
在一些實施例中,黏著層包括鈦、鉻、鈦鎢或其組合。In some embodiments, the adhesion layer includes titanium, chromium, titanium-tungsten, or combinations thereof.
在一些實施例中,第一基板為具有發光元件的藍寶石(Sapphire)基板。In some embodiments, the first substrate is a sapphire substrate with a light emitting element.
在一些實施例中,第二基板包括印刷電路板、金屬散熱板、陶瓷基板或其組合。In some embodiments, the second substrate includes a printed circuit board, a metal heat sink, a ceramic substrate, or a combination thereof.
在一些實施例中,陶瓷基板包括氧化鋁、氮化鋁、氮化矽或其組合。In some embodiments, the ceramic substrate includes aluminum oxide, aluminum nitride, silicon nitride, or combinations thereof.
在一些實施例中,更包括過渡晶粒層,於黏著層以及銀部件之間。In some embodiments, a transition die layer is further included between the adhesive layer and the silver component.
本揭露的另一些實施例提供一種形成接合結構的方法,包括:提供第一基板,第一基板具有相反的第一表面以及第二表面;在第一基板的第一表面上形成發光元件;在第一基板的第二表面上形成黏著層;在黏著層上形成銀部件;提供第二基板,第二基板上形成有導電層;以及將銀部件與導電層相對接合,其中銀部件包括銀奈米孿晶結構,且銀奈米孿晶結構具有平行排列孿晶界,其中平行排列孿晶界具有90%以上的[111]結晶方位。Some other embodiments of the present disclosure provide a method for forming a bonding structure, including: providing a first substrate, the first substrate has a first surface opposite to a second surface; forming a light emitting element on the first surface of the first substrate; An adhesive layer is formed on the second surface of the first substrate; a silver component is formed on the adhesive layer; a second substrate is provided, and a conductive layer is formed on the second substrate; and the silver component is relatively bonded to the conductive layer, wherein the silver component includes silver nano The nano-twin structure, and the silver nano-twin structure has parallel twin boundaries, and the parallel twin boundaries have more than 90% [111] crystallographic orientations.
在另一些實施例中,銀部件的至少80%為銀奈米孿晶結構,且其中平行排列孿晶界的間距為1奈米至100奈米。In some other embodiments, at least 80% of the silver feature is silver nanotwinned structure, and wherein the spacing between parallel twinned grain boundaries is 1 nm to 100 nm.
在另一些實施例中,銀部件的厚度至少為3.0微米,且其中銀奈米孿晶結構的厚度至少為2.0微米。In other embodiments, the thickness of the silver feature is at least 3.0 microns, and wherein the thickness of the silver nanotwinned structure is at least 2.0 microns.
在另一些實施例中,形成黏著層以及銀部件的步驟包括濺鍍或蒸鍍。In other embodiments, the step of forming the adhesive layer and the silver component includes sputtering or evaporation.
在另一些實施例中,在100℃至200℃的溫度下執行銀部件與導電層的接合。In other embodiments, the bonding of the silver component to the conductive layer is performed at a temperature of 100°C to 200°C.
在另一些實施例中,在3MPa至30MPa的壓力下執行銀部件與導電層的接合。In other embodiments, the bonding of the silver component to the conductive layer is performed at a pressure of 3 MPa to 30 MPa.
在另一些實施例中,黏著層包括鈦、鉻、鈦鎢或其組合。In other embodiments, the adhesion layer includes titanium, chromium, titanium-tungsten, or combinations thereof.
在另一些實施例中,第一基板為具有發光元件的藍寶石(Sapphire)基板,且第二基板包括印刷電路板、金屬散熱板、陶瓷基板或其組合。In some other embodiments, the first substrate is a sapphire substrate with light emitting elements, and the second substrate includes a printed circuit board, a metal heat sink, a ceramic substrate or a combination thereof.
在另一些實施例中,更包括在黏著層以及銀部件之間形成過渡晶粒層。In other embodiments, a transition grain layer is formed between the adhesive layer and the silver component.
以下內容提供了很多不同的實施例或範例,用於實施本發明實施例的不同部件。組件和配置的具體範例描述如下,以簡化本發明實施例。當然,這些僅僅是範例,並非用以限定本發明實施例。舉例來說,敘述中若提及第一部件形成於第二部件之上,可能包含第一和第二部件直接接觸的實施例,也可能包含額外的部件形成於第一和第二部件之間,使得第一和第二部件不直接接觸的實施例。另外,本發明實施例可能在許多範例中重複元件符號及/或字母。這些重複是為了簡化和清楚的目的,其本身並非代表所討論各種實施例及/或配置之間有特定的關係。The following content provides many different embodiments or examples for implementing different components of the embodiments of the present invention. Specific examples of components and configurations are described below to simplify embodiments of the invention. Of course, these are just examples, not intended to limit the embodiments of the present invention. For example, if the description mentions that the first component is formed on the second component, it may include an embodiment where the first and second components are in direct contact, or it may include an additional component formed between the first and second components , such that the first and second components are not in direct contact. In addition, the embodiments of the present invention may repeat element symbols and/or letters in many examples. These repetitions are for the purposes of simplicity and clarity and do not in themselves imply a specific relationship between the various embodiments and/or configurations discussed.
以下描述實施例的一些變化。在不同圖式和說明的實施例中,相似的元件符號被用來標示相似的元件。可以理解的是,在方法的前、中、後可以提供額外的步驟,且一些所敘述的步驟可在所述方法的其他實施例被取代或刪除。Some variations of the embodiment are described below. In the different drawings and described embodiments, like reference numerals are used to designate like elements. It is understood that additional steps may be provided before, during, and after the method, and that some recited steps may be substituted or deleted in other embodiments of the method.
此外,其中可能用到與空間相對用詞,例如「在......下方」、「下方」、「較低的」、「在......上方」、「上方」等類似用詞,是為了便於描述圖式中一個(些)部件或特徵與另一個(些)部件或特徵之間的關係。空間相對用詞用以包括使用中或操作中的裝置之不同方位,以及圖式中所描述的方位。當裝置被轉向不同方位時(旋轉90度或其他方位),其中所使用的空間相對形容詞也將依轉向後的方位來解釋。In addition, space-relative terms may be used, such as "below", "below", "lower", "above", "above", etc. Words are used to facilitate the description of the relationship between one (some) component or feature and another (some) component or feature in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation, as well as orientations depicted in the drawings. When the device is turned to a different orientation (rotated 90 degrees or otherwise), the spatially relative adjectives used therein shall also be interpreted in accordance with the turned orientation.
此處所使用的用語「約」、「近似」等類似用語描述數字或數字範圍時,該用語意欲涵蓋的數值是在合理範圍內包含所描述的數字,例如在所描述的數字之+/-10%之內,或本發明所屬技術領域中具有通常知識者理解的其他數值。例如,用語「約5nm」涵蓋從4.5nm至5.5nm的尺寸範圍。When the terms "about", "approximately" and similar terms are used herein to describe a number or range of numbers, the term is intended to cover values that include the stated number within a reasonable range, such as +/-10 of the stated number. %, or other values understood by those skilled in the art to which the present invention pertains. For example, the term "about 5 nm" encompasses a size range from 4.5 nm to 5.5 nm.
再者,說明書與請求項中所使用的序數例如”第一”、”第二”、”第三”等之用詞,以修飾請求項之元件,其本身並不意含及代表該請求元件有任何之前的序數,也不代表某一請求元件與另一請求元件的順序、或是製造方法上的順序,該些序數的使用僅用來使具有某命名的一請求元件得以和另一具有相同命名的請求元件能作出清楚區分。Furthermore, the ordinal numbers used in the description and claims, such as "first", "second", "third", etc., are used to modify the elements of the claim, which do not imply and represent that the element of the claim has Any previous ordinal numbers do not represent the order of a claimed element with another claimed element, or the order of the manufacturing method, and the use of these ordinal numbers is only used to enable a claimed element with a certain designation to have the same Named request elements make a clear distinction.
本揭露的實施例提供一種接合結構,包括:兩基板之間的銀部件,以及基板與銀部件之間的黏著層。黏著層可以使基板與銀部件之間具有較佳的接合力以避免剝落,且黏著層可以減少基板的結晶方位對銀部件的影響。此外,銀部件具有至少80%的銀奈米孿晶結構,且銀奈米孿晶結構具有90%以上[111]結晶方位的平行排列孿晶界。由於銀以及孿晶結構的特性,使本揭露可以在100℃至200℃的低溫進行直接接合製程,以確保封裝製程的良率及接合結構的接合強度。再者,接合界面不會因為高溫熱應力而導致破裂,從而提高產品的可靠性。尤其針對微型發光二極體或迷你發光二極體,此低溫接合不會導致晶片移位。An embodiment of the present disclosure provides a bonding structure, including: a silver component between two substrates, and an adhesive layer between the substrate and the silver component. The adhesive layer can provide a better bonding force between the substrate and the silver component to avoid peeling off, and the adhesive layer can reduce the influence of the crystallographic orientation of the substrate on the silver component. In addition, the silver component has at least 80% silver nanotwin structure, and the silver nanotwin structure has more than 90% [111] crystallographic orientations of parallel aligned twin boundaries. Due to the characteristics of silver and the twin structure, the present disclosure can perform direct bonding process at a low temperature of 100° C. to 200° C. to ensure the yield rate of the packaging process and the bonding strength of the bonding structure. Furthermore, the bonding interface will not be cracked due to high temperature thermal stress, thereby improving the reliability of the product. Especially for micro-LEDs or mini-LEDs, this low-temperature bonding does not cause chip displacement.
根據一些實施例,第1A至1D圖繪示接合結構在不同製造階段的剖面圖。參照第1A圖,提供第一基板10,第一基板10包括相反的第一表面S1以及第二表面S2。在一些實施例中,第一基板10可以為具有發光元件(如以下所述)的藍寶石(Sapphire)基板,並包括氧化鋁(Al
2O
3)。
1A-1D illustrate cross-sectional views of bonding structures at different stages of fabrication, according to some embodiments. Referring to FIG. 1A, a
繼續參照第1A圖,在第一基板10的第一表面S1上形成發光元件20,並且在第一基板10的第二表面S2上形成黏著層12。在一些實施例中,發光元件20包括發光二極體(LED)、迷你發光二極體(mini-LED)、微型發光二極體(micro-LED)或其組合。在一些實施例中,黏著層12包括鈦、鉻、鈦鎢或其組合。黏著層可以提供基板與隨後形成的銀部件(參照第1B圖)之間較佳的接合力,同時具有晶格緩衝的效果。黏著層12的厚度可以為0.01微米至1微米,例如0.05微米至0.1微米。若黏著層12的厚度大於例如1微米,則會導致發光元件的發光效率降低;若黏著層12的厚度小於例如0.01微米,則無法提供基板與後續形成的銀部件之間足夠的接合力。Continuing to refer to FIG. 1A , the
在一些實施例中,可以藉由濺鍍的方式將黏著層12形成在第一基板10的第二表面S2上。濺鍍採用單槍濺鍍或多槍共鍍。濺鍍電源可以使用例如DC、DC plus、RF、高功率脈衝磁控濺鍍(high-power impulse magnetron sputtering, HIPIMS)等。黏著層12的濺鍍功率可以為例如約100W至約200W。濺鍍製程的溫度為室溫,但濺鍍製程期間溫度會上升約50℃至約200℃。黏著層12的沉積速率可以為例如約0.1nm/s至約0.3nm/s。濺鍍製程的背景壓力小於1 x 10
-5torr,工作壓力可以為例如約1 x 10
-3torr至1 x 10
-2torr。氬氣流量約10sccm至約20sccm。載台轉速可以為例如約5rpm至約20rpm。濺鍍製程基板施加偏壓約-100V至約-200V。應當理解,上述濺鍍製程參數可以依照實際應用適當調整,本揭露不以此為限。
In some embodiments, the
在另一些實施例中,可以藉由蒸鍍的方式將黏著層12形成在第一基板10的第二表面S2上。蒸鍍製程的背景壓力小於1 x 10
-5torr,工作壓力可以為例如約1 x 10
-4torr至約5 x 10
-4torr。氬氣流量約2sccm至約10sccm。載台轉速可以為例如約5rpm至約2 rpm。黏著層12的蒸鍍速率可以為例如約1nm/s至約5.0nm/s。應當理解,上述蒸鍍製程參數可以依照實際應用適當調整,本揭露不以此為限。
In other embodiments, the
參照第1B圖,在黏著層12的上形成銀部件50。在一些實施例中,銀部件50包括銀奈米孿晶結構14,且銀奈米孿晶結構14具有奈米等級的平行排列孿晶界(Σ3+Σ9)。在銀部件50的剖面圖中,利用電子背向散射繞射(electron backscatter diffraction, EBSD)分析,其孿晶界(Σ3)與類孿晶界(Σ9)總和佔整體晶界40%以上。此外,平行排列孿晶界具有90%以上(例如大於90%或大於95%)的[111]結晶方位,並且孿晶界的間距可以為1奈米至100奈米,較佳為2奈米至50奈米。Referring to FIG. 1B , a
繼續參照第1B圖,在一些實施例中,銀部件50的厚度T1至少為2.0微米,例如約3微米至約10微米。銀奈米孿晶結構14的厚度T2至少為1.5微米,例如約2.0微米至約10微米。銀奈米孿晶結構14包括平行堆疊的銀奈米孿晶柱16。在一些實施例中,銀奈米孿晶柱16的直徑可以為0.1微米至10微米,較佳為0.3微米至1.0微米。Continuing to refer to FIG. 1B , in some embodiments, the thickness T1 of the
繼續參照第1B圖,在一些實施例中,除了銀奈米孿晶結構14之外,銀部件50也包括過渡晶粒層22。最初在黏著層12上形成銀部件50時,銀部件50並不會立即形成具有平行排列孿晶界的銀奈米孿晶結構14,而會形成不含有平行排列孿晶界的過渡晶粒層22。在一些實施例中,過渡晶粒層22的厚度例如為0.1微米至約1微米。Continuing to refer to FIG. 1B , in some embodiments, the
在一些實施例中,可以藉由濺鍍的方式將銀部件50形成在黏著層12上。在一些實施例中,濺鍍採用單槍濺鍍或多槍共鍍。濺鍍電源可以使用例如DC、DC plus、RF、高功率脈衝磁控濺鍍(HIPIMS)等。銀部件50的濺鍍功率可以為例如約100W至約200W。濺鍍製程的溫度為室溫,然而濺鍍製程期間溫度會上升約50℃至約200℃。濺鍍製程的背景壓力小於1 x 10
-5torr,工作壓力可以為例如約1 x 10
-3torr至1 x 10
-2torr。氬氣流量約10sccm至約20sccm。載台轉速可以為例如約5rpm至約20rpm。濺鍍製程基板施加偏壓約-100V至約-200V。銀部件50的沉積速率可以為例如0.5nm/s至約3nm/s。應當理解,上述濺鍍製程參數可以依照實際應用適當調整,本揭露不以此為限。
In some embodiments, the
在另一些實施例,可以藉由蒸鍍的方式將銀部件50形成在黏著層12上。在一些實施例中,蒸鍍製程的背景壓力小於1 x 10
-5torr,工作壓力可以為例如約1 x 10
-4torr至約5 x 10
-4torr。氬氣流量約2sccm至約10sccm。載台轉速可以為例如約5rpm至約20rpm。銀部件50的沉積速率可以為例如0.5nm/s至約3nm/s。額外地,在蒸鍍製程期間可以對銀奈米孿晶結構14施加離子撞擊,其電壓約10V至約200V且電流約0.1A至約1A。應當理解,上述蒸鍍製程參數可以依照實際應用適當調整,本揭露不以此為限。
In other embodiments, the
相較於濺鍍或蒸鍍,電鍍製程會有元件或接點尺寸的限制。詳細而言,一般小於2微米的元件或接點無法以電鍍方法製造。然而,即使是尺寸在2微米以下的元件或接點可以輕易地利用濺鍍或蒸鍍製造。Compared with sputtering or evaporation, the electroplating process has limitations in the size of components or contacts. Specifically, components or contacts generally smaller than 2 microns cannot be fabricated by electroplating. However, even components or contacts with dimensions below 2 microns can be easily fabricated by sputtering or evaporation.
本揭露的黏著層可以增進後續金屬膜層與基板的接合力以避免剝落。若直接濺鍍奈米孿晶薄膜於基板上,由於奈米孿晶薄膜與基板結合力不足,薄膜厚度僅能達到約2微米。The adhesive layer of the present disclosure can improve the bonding force between the subsequent metal film layer and the substrate to avoid peeling off. If the nano-twinned thin film is directly sputtered on the substrate, the film thickness can only reach about 2 microns due to insufficient bonding force between the nano-twinned thin film and the substrate.
此外,若直接在基板上形成奈米孿晶薄膜,則薄膜會受到基板的結晶方位影響。詳細而言,只有在(111)方位的基板上可以形成高孿晶密度的奈米孿晶薄膜,而在非(111)方位的基板上所形成的奈米孿晶結構則僅有很低的孿晶密度。然而,本揭露的黏著層對於在不同方位的基板上形成孿晶結構具有晶格緩衝的功效。詳細而言,無論基板的結晶方位,所形成的奈米孿晶皆具有90%以上的[111]結晶方位。In addition, if the nano-twinned film is directly formed on the substrate, the film will be affected by the crystal orientation of the substrate. Specifically, nanotwinned thin films with high twinning density can be formed only on (111)-oriented substrates, while nanotwinned structures formed on non-(111)-oriented substrates have only low twinning density. density. However, the adhesive layer of the present disclosure has the effect of lattice buffering for the formation of twin structures on substrates with different orientations. In detail, regardless of the crystal orientation of the substrate, the formed nanotwins have more than 90% [111] crystal orientation.
參照第1C圖,提供第二基板30。在第二基板30上形成有導電層40,並將導電層40以及銀部件50相對設置以進行後續的接合(參照第1D圖)。在一些實施例中,第二基板30包括印刷電路板、金屬散熱板、陶瓷基板或其組合。導電層40可以由金屬形成,金屬可以包括例如銅、金、銀或其組合。在一些實施例中,導電層40的厚度可以為10微米至100微米。詳細而言,陶瓷基板包括氧化鋁、氮化鋁、氮化矽或其組合。在第二基板30為印刷電路板的實施例中,導電層40為形成在印刷電路板上的銅電路。在第二基板30為陶瓷基板的實施例中,導電層40為額外沉積在陶瓷基板上的銅、金、銀或其組合。在第二基板30為金屬散熱板的實施例中,導電層40與第二基板30為一體的,而非單獨形成的兩個部件。Referring to FIG. 1C, a
應當理解,第1C圖所示的結構僅為示例,第二基板30上可以額外包括各種被動及主動裝置(未示出),例如:電阻、電容、電感、二極體、場效電晶體(field effect transistors, FETs)、金屬氧化物半導體場效電晶體(metal-oxide semiconductor FETs, MOSFETs)、互補式金屬氧化物半導體(complementary metal-oxide semiconductor, CMOS)電晶體、雙極性接面電晶體(bipolar junction transistors, BJTs)、橫向擴散MOS(laterally diffused MOS, LDMOS)電晶體、高壓電晶體、高頻電晶體、其他合適的裝置或其組合。It should be understood that the structure shown in FIG. 1C is only an example, and various passive and active devices (not shown) may be additionally included on the
參照第1D圖,將銀部件50與導電層40相對接合以形成接合結構100。銀部件50包括銀奈米孿晶結構14,且銀奈米孿晶結構14具有奈米等級的平行排列孿晶界(Σ3+Σ9)。在銀部件50的剖面圖中,利用電子背向散射繞射(EBSD)分析,其孿晶界(Σ3)與類孿晶界(Σ9)總和佔整體晶界40%以上。此外,平行排列孿晶界具有90%以上(例如大於90%或大於95%)的[111]結晶方位,並且孿晶界的間距可以為1奈米至100奈米,較佳為2奈米至50奈米。Referring to FIG. 1D , the
在一些實施例中,銀部件50的厚度至少為2.0微米,例如約3.0微米至約10微米。銀奈米孿晶結構14的厚度至少為1.5微米,例如約2.0微米至約10微米。銀奈米孿晶結構14包括平行堆疊的銀奈米孿晶柱16。在一些實施例中,銀奈米孿晶柱16的直徑可以為0.1微米至10微米,較佳為0.3微米至1.0微米。In some embodiments,
在實務上,不論電鍍、濺鍍或蒸鍍,當奈米孿晶薄膜厚度大於2微米時,奈米孿晶薄膜與基板的接合力已經明顯劣化並且極易剝落。本揭露在形成奈米孿晶薄膜之前,先在基板上形成黏著層,可以確保奈米孿晶薄膜具有大於10微米以上的厚度,且奈米孿晶薄膜與基板仍保持良好的接合力。In practice, regardless of electroplating, sputtering or vapor deposition, when the thickness of the nano-twinned film is greater than 2 microns, the bonding force between the nano-twinned film and the substrate has obviously deteriorated and is easily peeled off. In the present disclosure, before forming the nano-twin film, an adhesive layer is formed on the substrate to ensure that the nano-twin film has a thickness greater than 10 micrometers, and the nano-twin film and the substrate still maintain good bonding force.
此外,當奈米孿晶薄膜厚度低於2微米時,在後續接合製程中,奈米孿晶薄膜會快速與接合材料反應殆盡。形成的界面介金屬化合物與基板並無接合力而導致界面脫落,在應用上不具意義。In addition, when the thickness of the nano-twinned film is less than 2 microns, the nano-twinned film will quickly react with the bonding material in the subsequent bonding process. The formed interfacial intermetallic compound has no bonding force with the substrate and causes the interface to fall off, which is meaningless in application.
在一些實施例中,可以在100℃至300℃的溫度(例如約100℃至約150℃或約120℃至約180℃),並且在3MPa至30MPa的壓力(例如約5MPa至約10MPa或約15MPa至約20MPa)執行銀部件50與導電層40的接合。在銀部件50與導電層40接合之後,接合結構100仍保有奈米孿晶結構的特性。In some embodiments, at a temperature of 100°C to 300°C (eg, about 100°C to about 150°C or about 120°C to about 180°C), and at a pressure of 3MPa to 30MPa (eg, about 5MPa to about 10MPa or about 15 MPa to about 20 MPa) to perform bonding of the
本揭露使用3MPa至30MPa的壓力範圍,不論基板或銀奈米孿晶均可以保持完好無損。習知技術雖可在0.8MPa至3MPa的低壓進行接合製程,然而其在接合前必須先對奈米孿晶薄膜進行化學機械拋光(CMP)以減少表面粗糙度,不僅製程繁複且會破壞奈米孿晶薄膜。本揭露在不損害基板及銀奈米孿晶的情況下,相較於習知技術施加較大約3MPa至約30MPa的壓力,使銀奈米孿晶表面的凸起結構進行奈米等級的塑性變形,以達到緊密接觸目標的效果。其不僅解決銀奈米孿晶表面粗糙度的問題,更免除習知技術必須額外進行繁複的化學機械拋光或其他表面處理的步驟,從而可以大幅提升產能及良率。In the present disclosure, using a pressure range of 3 MPa to 30 MPa, both the substrate and the silver nanotwins can remain intact. Although the conventional technology can carry out the bonding process at a low pressure of 0.8MPa to 3MPa, it must first perform chemical mechanical polishing (CMP) on the nano twin film to reduce the surface roughness before bonding, which is not only complicated but also damages the nano-twin film. Twin film. In this disclosure, under the condition of not damaging the substrate and the silver nano twins, compared with the conventional technology, a pressure of about 3 MPa to about 30 MPa is applied, so that the convex structure on the surface of the silver nano twins undergoes nanoscale plastic deformation , in order to achieve the effect of close contact with the target. It not only solves the problem of the surface roughness of silver nano twins, but also eliminates the need for additional complicated chemical mechanical polishing or other surface treatment steps in the conventional technology, so that the production capacity and yield can be greatly improved.
此外,習知技術的銅奈米孿晶硬度高達4GPa,約為本揭露銀奈米孿晶硬度的2倍。如果要利用本揭露的奈米等級的凸起結構塑性變形機制解決銅奈米孿晶表面粗糙度的問題,必須施加100MPa以上的壓力,將造成基板及銅奈米孿晶的損壞。In addition, the hardness of the copper nanotwins in the conventional technology is as high as 4GPa, which is about twice the hardness of the silver nanotwins disclosed in this disclosure. If the plastic deformation mechanism of the nano-scale protrusion structure disclosed in this disclosure is to be used to solve the problem of the surface roughness of the copper nano-twins, a pressure of more than 100 MPa must be applied, which will cause damage to the substrate and the copper nano-twins.
再者,銀的電阻率為1.63 μΩ•cm,低於銅(1.69 μΩ•cm)、金(2.2 μΩ•cm)及鎳(6.90 μΩ•cm)。銀的疊差能(stacking fault energy)為25 mJ/m 2,亦低於銅(70 mJ/m 2)、金(45 mJ/m 2)及鎳(225 mJ/m 2)。因此銀相較於銅、金及鎳更容易形成孿晶。相較於習知技術使用電鍍形成銅奈米孿晶薄膜,在本揭露實施例的濺鍍奈米孿晶薄膜製程中,銀的擴散速率較銅快10倍以上。銀的熔點較銅低約100℃,可以在較低溫的環境進行後續的接合製程。 Furthermore, the resistivity of silver is 1.63 μΩ•cm, which is lower than that of copper (1.69 μΩ•cm), gold (2.2 μΩ•cm) and nickel (6.90 μΩ•cm). The stacking fault energy of silver is 25 mJ/m 2 , which is also lower than that of copper (70 mJ/m 2 ), gold (45 mJ/m 2 ) and nickel (225 mJ/m 2 ). Therefore, silver is more likely to form twins than copper, gold and nickel. Compared with the conventional technique of forming copper nano twin films by electroplating, in the process of sputtering nano twin films of the disclosed embodiment, the diffusion rate of silver is more than 10 times faster than that of copper. The melting point of silver is about 100°C lower than that of copper, so the subsequent bonding process can be performed in a lower temperature environment.
本揭露可以相較習知技術在更低的溫度下進行接合製程,使半導體裝置不受接合製程高溫的影響。詳細而言,相較於銀奈米孿晶結構,銅奈米孿晶結構需要在較高的溫度(例如高於200℃)進行接合製程。其可能會損害裝置,並且在接合完成冷卻至室溫時,由於材料收縮造成微小接點對位失敗。In the present disclosure, the bonding process can be performed at a lower temperature than the conventional technology, so that the semiconductor device is not affected by the high temperature of the bonding process. In detail, compared with the silver nano-twin structure, the copper nano-twin structure needs to be bonded at a higher temperature (for example, higher than 200° C.). It can damage the device and cause tiny joints to fail in alignment due to material shrinkage when the bond is completed and cooled to room temperature.
此外,銀奈米孿晶硬度僅大約2GPa,較銅奈米孿晶軟,在後續與其他材料接合時的表面粗糙度影響較小。銀奈米孿晶薄膜較銅奈米孿晶薄膜不易氧化,可以較銅奈米孿晶薄膜獲得更完美的接合界面。這些特性均可顯示本揭露實施例之銀奈米孿晶結構結構有較佳的市場應用優勢。尤其針對低溫晶圓接合與覆晶組裝等半導體產業需求。In addition, the hardness of silver nanotwins is only about 2GPa, which is softer than copper nanotwins, and the surface roughness has less influence on subsequent bonding with other materials. Silver nano-twinned films are less prone to oxidation than copper nano-twinned films, and can obtain a more perfect bonding interface than copper nano-twinned films. These characteristics all show that the silver nano-twin structure of the disclosed embodiment has better advantages in market application. Especially for the needs of the semiconductor industry such as low-temperature wafer bonding and flip-chip assembly.
孿晶組織的形成是由於材料內部累積應變能驅動部分區域之原子均勻剪移(shear)至與其所在晶粒內部未剪移原子形成相互鏡面對稱之晶格位置。孿晶包括:退火孿晶(annealing twin)與機械孿晶(mechanical twin)兩種。其相互對稱之界面即為孿晶界(twin boundary)。The formation of the twin structure is due to the fact that the accumulated strain energy in the material drives the atoms in some regions to uniformly shear (shear) to form a mirror-symmetric lattice position with the unsheared atoms inside the grain. Twins include: annealing twins and mechanical twins. The interface of mutual symmetry is the twin boundary.
孿晶主要發生在晶格排列最緊密之面心立方(face centered cubic, FCC)或六方最密堆排(hexagonal closed-packed, HCP)結晶材料。除了晶格排列最緊密結晶構造條件,通常疊差能(stacking fault energy)越小的材料越容易產生孿晶。例如,鋁雖為面心立方結晶構造材料,但其疊差能大約為200 erg/cm 2,極少出現孿晶。 Twins mainly occur in face-centered cubic (FCC) or hexagonal closed-packed (HCP) crystalline materials with the closest lattice arrangement. In addition to the conditions of the tightest crystal lattice arrangement, generally the smaller the stacking fault energy, the easier it is for a material to produce twins. For example, although aluminum is a face-centered cubic crystal structure material, its stacking energy is about 200 erg/cm 2 , and twins rarely appear.
孿晶界為調諧(Coherent)結晶構造,屬於低能量之Σ3與Σ9特殊晶界。結晶方位均為{111}面。相較於一般退火再結晶所形成的高角度晶界,孿晶界的界面能約為一般高角度晶界的5%(請參考:George E.Dieter, Mechanical Metallurgy, McGRAW-HILL Book Company, 1976, P.135-141)。The twin boundary is a tuned (Coherent) crystal structure, which belongs to the low-energy Σ3 and Σ9 special grain boundaries. The crystal orientations are all {111} planes. Compared with the high-angle grain boundaries formed by general annealing and recrystallization, the interface energy of twin grain boundaries is about 5% of that of general high-angle grain boundaries (please refer to: George E. Dieter, Mechanical Metallurgy, McGRAW-HILL Book Company, 1976 , P.135-141).
由於孿晶界較低的界面能,可以避免成為氧化、硫化及氯離子腐蝕的路徑。因此展現較佳的抗氧化性與耐腐蝕性。此外,此種孿晶之對稱晶格排列對電子傳輸的阻礙較小。因而展現較佳的導電性與導熱性。由於孿晶界對差排移動的阻擋,使材料仍可維持高強度。此兼具高強度與高導電性的特性在銅薄膜已獲得證實(請參考:L.Lu, Y.Shen, X.Chen, L.Qian, and K.Lu, Ultrahigh Strength and High Electrical Conductivity in Copper, Science, vol.304, 2004, p.422-426)。Due to the low interface energy of the twin boundary, it can avoid being the path of oxidation, sulfidation and chloride ion corrosion. Therefore, it exhibits better oxidation resistance and corrosion resistance. In addition, the symmetrical lattice arrangement of such twins has less hindrance to electron transport. Therefore, it exhibits better electrical and thermal conductivity. Due to the blocking of dislocation movement by the twin boundaries, the material can still maintain high strength. This characteristic of high strength and high electrical conductivity has been confirmed in copper film (please refer to: L.Lu, Y.Shen, X.Chen, L.Qian, and K.Lu, Ultrahigh Strength and High Electrical Conductivity in Copper , Science, vol.304, 2004, p.422-426).
就高溫穩定性而言,由於孿晶界較低的界面能,其孿晶界較一般高角度晶界穩定。孿晶界本身在高溫狀態不易移動,也會對其所在晶粒周圍的高角度晶界產生固鎖作用,使這些高角度晶界無法移動。因而整體晶粒在高溫不會有明顯的晶粒成長現象以維持材料的高溫強度。In terms of high-temperature stability, due to the lower interface energy of the twin boundary, its twin boundary is more stable than the general high-angle grain boundary. The twin boundary itself is not easy to move at high temperature, and it will also have a locking effect on the high-angle grain boundaries around the grains where it is located, making these high-angle grain boundaries unable to move. Therefore, the overall grain will not have obvious grain growth phenomenon at high temperature to maintain the high temperature strength of the material.
就通電流的可靠性而言,由於原子經由低能量孿晶界或跨越孿晶界的擴散速率較低。在使用電子產品時,高密度電流所伴隨線材內部原子移動也較為困難。如此解決線材在通電流時常發生的電遷移(Electromigration)問題。在銅薄膜已有報導證實孿晶可抑制材料電遷移現象(請參考:K.C.Chen, W.W.Wu, C.N.Liao, L.J.Chen, and K.N.Tu, Observation of Atomic Diffusion at Twin-Modified Grain Boundaries in Copper, Science, vol.321, 2008, p.1066-1069.)。In terms of the reliability of current flow, due to the low rate of diffusion of atoms through or across twin boundaries with low energy. When using electronic products, it is also difficult to move atoms inside the wire accompanied by high-density current. In this way, the problem of electromigration (Electromigration) that often occurs when the wire is passed through the current is solved. It has been reported in copper thin films that twins can inhibit the electromigration of materials (please refer to: K.C.Chen, W.W.Wu, C.N.Liao, L.J.Chen, and K.N.Tu, Observation of Atomic Diffusion at Twin-Modified Grain Boundaries in Copper, Science, vol.321, 2008, p.1066-1069.).
在半導體裝置中,本揭露的銀部件可以用作電極。相較於習知的銅柱(copper pillar)以及銲料(solder)接合結構,本揭露實施例具有孿晶結構的銀部件在低溫低壓接合製程中具有較佳的應用優勢。如前文所述,相較於其他金屬(例如銅、金、鎳等)銀具有較低的電阻率、疊差能以及熔點,其較容易形成奈米孿晶結構並且可以在低溫低壓的情況下進行接合製程。In semiconductor devices, the silver components of the present disclosure can be used as electrodes. Compared with the conventional copper pillar and solder (solder) bonding structures, the silver component with the twin structure in the disclosed embodiment has better application advantages in the low temperature and low pressure bonding process. As mentioned above, compared with other metals (such as copper, gold, nickel, etc.), silver has lower resistivity, stack energy and melting point, and it is easier to form nano-twin structure and can be formed at low temperature and low pressure. Carry out bonding process.
以下描述本揭露一些形成銀部件的具體實施例以及檢測結果。The following describes some specific examples of forming silver components and test results of the present disclosure.
實施例一Embodiment one
參照第2圖,將正面具有發光二極體之藍寶石基板晶粒背面濺鍍厚度為0.1微米的鈦黏著層,隨後在鈦黏著層上濺鍍厚度為8微米的銀奈米孿晶薄膜。將此具有銀奈米孿晶薄膜的藍寶石晶粒與表面覆蓋銅的氧化鋁陶瓷基板相互堆疊後,在真空度為10 -5Torr、壓力為20MPa以及溫度為200℃的情況下加熱30分鐘以完成固晶接合製程。隨後以推晶試驗量測其接合強度達32MPa,在波長為460奈米之反射率達46%。 Referring to Figure 2, sputter a titanium adhesive layer with a thickness of 0.1 micron on the back of the sapphire substrate grain with a light-emitting diode on the front, and then sputter a silver nano-twin film with a thickness of 8 microns on the titanium adhesive layer. After stacking the sapphire crystal grains with silver nanotwinned film and the alumina ceramic substrate covered with copper on the surface, heat for 30 minutes under the condition of vacuum degree of 10 -5 Torr, pressure of 20MPa and temperature of 200°C. Complete the die bonding process. Afterwards, the bonding strength was measured to be 32MPa by crystal push test, and the reflectivity was 46% at a wavelength of 460nm.
實施例二Embodiment two
參照第3圖,將正面具有發光二極體之藍寶石基板晶粒背面蒸鍍厚度為0.1微米的鈦黏著層,隨後在鈦黏著層上蒸鍍厚度為8微米的銀奈米孿晶薄膜。將此具有銀奈米孿晶薄膜的藍寶石晶粒與表面覆蓋銅的氧化鋁陶瓷基板相互堆疊後,在真空度為10 -5Torr、壓力為20MPa以及溫度為200℃的情況下加熱30分鐘以完成固晶接合製程。隨後以推晶試驗量測其接合強度達26MPa,在波長為460奈米之反射率達45%。 Referring to Fig. 3, a titanium adhesive layer with a thickness of 0.1 micron is evaporated on the back of the sapphire substrate grain with a light-emitting diode on the front, and then a silver nano-twin film with a thickness of 8 microns is evaporated on the titanium adhesive layer. After stacking the sapphire crystal grains with silver nanotwinned film and the alumina ceramic substrate covered with copper on the surface, heat for 30 minutes under the condition of vacuum degree of 10 -5 Torr, pressure of 20MPa and temperature of 200°C. Complete the die bonding process. Afterwards, the bonding strength was measured to be 26MPa by crystal pushing test, and the reflectivity at a wavelength of 460nm was 45%.
本揭露的實施例具有一些有利特徵。位於基板與銀奈米孿晶結構之間的黏著層,提供基板與銀奈米孿晶結構之間較佳的接合力,以避免產生剝落。黏著層同時具有晶格緩衝的效果,以減少基板晶格對成長銀奈米孿晶結構的影響。在接合結構的剖面圖中,銀奈米孿晶結構具有平行排列孿晶界,並佔總晶界40%以上。平行排列孿晶界具有90%以上的[111]結晶方位。銀奈米孿晶結構佔整體銀部件的至少80%。此外,相較於其他金屬(例如銅、金、鎳等),銀具有較低的電阻率、疊差能以及熔點,其較容易形成奈米孿晶結構並且可以在低溫低壓的情況下進行接合製程。所形成的接合界面不會因為高溫熱應力而導致破裂,同時避免晶片位移的問題,從而提高產品的可靠性。Embodiments of the present disclosure have some advantageous features. The adhesive layer located between the substrate and the silver nano twin structure provides better bonding force between the substrate and the silver nano twin structure to avoid peeling off. The adhesive layer also has the effect of lattice buffering, so as to reduce the influence of substrate lattice on the growth of silver nano twin structure. In the cross-sectional view of the junction structure, the silver nanotwin structure has twin boundaries arranged in parallel, and accounts for more than 40% of the total grain boundaries. Parallel twin boundaries have more than 90% [111] crystallographic orientations. The silver nanotwinned structure accounts for at least 80% of the overall silver part. In addition, compared with other metals (such as copper, gold, nickel, etc.), silver has lower resistivity, stacking energy and melting point, which is easier to form nano-twin structure and can be bonded at low temperature and low pressure Process. The formed joint interface will not be cracked due to high-temperature thermal stress, and at the same time, the problem of wafer displacement can be avoided, thereby improving the reliability of the product.
以上概述數個實施例之特徵,以使本發明所屬技術領域中具有通常知識者可以更加理解本發明實施例的觀點。本發明所屬技術領域中具有通常知識者應理解,可輕易地以本發明實施例為基礎,設計或修改其他製程和結構,以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應理解,此類等效的結構並無悖離本發明的精神與範圍,且可在不違背本發明之精神和範圍下,做各式各樣的改變、取代和替換。因此,本發明之保護範圍當視後附之申請專利範圍所界定為準。The features of several embodiments are summarized above, so that those skilled in the art of the present invention can better understand the viewpoints of the embodiments of the present invention. Those skilled in the art of the present invention should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and/or advantages as the embodiments described herein. Those who have ordinary knowledge in the technical field of the present invention should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and can be made in various ways without departing from the spirit and scope of the present invention. changes, substitutions and replacements. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.
10:基板 12:黏著層 14:銀奈米孿晶結構 16:銀奈米孿晶柱 20:發光元件 22:過渡晶粒層 30:基板 40:導電層 50:銀部件 100:接合結構 T1:厚度 T2:厚度 10: Substrate 12: Adhesive layer 14: Silver nano-twin structure 16:Silver nano-twin column 20: Light emitting element 22: Transition grain layer 30: Substrate 40: Conductive layer 50: silver parts 100: joint structure T1: Thickness T2: Thickness
以下將配合所附圖示詳述本揭露之各面向。應注意的是,依據在業界的標準做法,各種特徵並未按照比例繪製且僅用以說明例示。事實上,可能任意地放大或縮小單元的尺寸,以清楚地表現出本揭露的特徵。 第1A至1D圖係根據一些實施例,繪示接合結構在不同製造階段的示意剖面圖。 第2圖根據一些實施例,係銀奈米孿晶部件與藍寶石基板接合結構的聚焦離子束(FIB)圖,其接合結構係通過濺鍍製程所形成。 第3圖根據另一些實施例,係銀奈米孿晶部件與藍寶石基板接合結構的聚焦離子束(FIB)圖,其接合結構係通過蒸鍍製程所形成。 Various aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with the standard practice in the industry, the various features are not drawn to scale and are used for illustrative purposes only. In fact, the dimensions of the elements may be arbitrarily expanded or reduced to clearly represent the features of the present disclosure. Figures 1A-1D are schematic cross-sectional views illustrating bonding structures at different stages of fabrication, according to some embodiments. FIG. 2 is a focused ion beam (FIB) image of a joint structure of a silver nanotwinned component and a sapphire substrate, according to some embodiments, and the joint structure is formed by a sputtering process. FIG. 3 is a focused ion beam (FIB) image of a joint structure of a silver nanotwin component and a sapphire substrate according to other embodiments, and the joint structure is formed by evaporation process.
10:基板 10: Substrate
12:黏著層 12: Adhesive layer
14:銀奈米孿晶結構 14: Silver nano-twin structure
20:發光元件 20: Light emitting element
22:過渡晶粒層 22: Transition grain layer
30:基板 30: Substrate
40:導電層 40: Conductive layer
50:銀部件 50: silver parts
100:接合結構 100: joint structure
Claims (20)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW110117829A TWI810567B (en) | 2021-05-18 | 2021-05-18 | Bonding structures and methods for forming the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW110117829A TWI810567B (en) | 2021-05-18 | 2021-05-18 | Bonding structures and methods for forming the same |
Publications (2)
Publication Number | Publication Date |
---|---|
TW202247498A true TW202247498A (en) | 2022-12-01 |
TWI810567B TWI810567B (en) | 2023-08-01 |
Family
ID=85793367
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW110117829A TWI810567B (en) | 2021-05-18 | 2021-05-18 | Bonding structures and methods for forming the same |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI810567B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20230027664A1 (en) * | 2021-07-20 | 2023-01-26 | Ag Materials Technology Co., Ltd. | Bonding structures and methods for forming the same |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE112008002377T5 (en) * | 2007-08-31 | 2010-08-26 | Reactive Nanotechnologies Inc. | Method for low-temperature bonding of electronic components |
TWI703226B (en) * | 2020-01-21 | 2020-09-01 | 樂鑫材料科技股份有限公司 | Silver nano-twinned thin film structure and methods for forming the same |
-
2021
- 2021-05-18 TW TW110117829A patent/TWI810567B/en active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20230027664A1 (en) * | 2021-07-20 | 2023-01-26 | Ag Materials Technology Co., Ltd. | Bonding structures and methods for forming the same |
Also Published As
Publication number | Publication date |
---|---|
TWI810567B (en) | 2023-08-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI703226B (en) | Silver nano-twinned thin film structure and methods for forming the same | |
JP7542026B2 (en) | Junction structure and method for forming same | |
TWI401825B (en) | A bonding method for led chip and bonded led | |
JP4700681B2 (en) | Si circuit die, method of manufacturing Si circuit die, method of attaching Si circuit die to heat sink, circuit package and power module | |
TWI756106B (en) | Die bonding structures and methods for forming the same | |
US8021929B2 (en) | Apparatus and method configured to lower thermal stresses | |
TWI762342B (en) | Methods for forming bonding structures | |
US7745927B2 (en) | Heat sink formed of multiple metal layers on backside of integrated circuit die | |
TWI803857B (en) | Bonding structures and methods for forming the same | |
TWI810567B (en) | Bonding structures and methods for forming the same | |
TWI803984B (en) | Nano-twinned structure on metallic thin film surface and method for forming the same | |
US6534792B1 (en) | Microelectronic device structure with metallic interlayer between substrate and die | |
US20210225795A1 (en) | Power Semiconductor Device and Method for Fabricating a Power Semiconductor Device | |
TWI713175B (en) | Silver-indium transient liquid phase method of bonding semiconductor device and heat-spreading mount and semiconductor structure having silver-indium transient liquid phase bonding joint | |
US9349704B2 (en) | Jointed structure and method of manufacturing same | |
TWM582236U (en) | Power module package | |
TWM651995U (en) | Die bonding structure | |
US8188592B2 (en) | Apparatus and method configured to lower thermal stresses | |
JP2007109829A (en) | Solder joint forming method | |
US20150076516A1 (en) | Semiconductor device and semiconductor module | |
Ang et al. | Direct metal to metal bonding for microsystems interconnections and integration | |
TWI489596B (en) | Chip structure | |
Oh | Solid-state bonding by stress migration in Ag |