TW202245167A - Semiconductor package element - Google Patents

Abstract

A semiconductor package element includes a die, a passive layer, a conductive structure, and an encapsulation layer. The die includes a first surface, a second surface and a third surface. The second surface is opposite to the first surface, and the third surface is connected between the first surface and the second surface. The passive layer is disposed on the first surface and is formed with a hole. The conductive structure is electrically coupled to the die through the hole. The encapsulation layer covers the first surface and the third surface of the die, wherein the passive layer is embedded in the encapsulation layer, a portion of the conductive structure is embedded in the encapsulation layer, and the other portion of the conductive structure protrudes from an etched surface of the encapsulation layer. The etched surface is formed by plasma etching.

Description

Semiconductor Package Components

The present invention relates to a semiconductor packaging device, and more particularly to a semiconductor packaging device that removes the coating material above the conductive structure by plasma etching to expose the conductive structure.

With the miniaturization of semiconductor chips, high-end microelectronic packaging technology is continuing to develop from lead frames and wire bonding methods to bumps.

Please refer to FIG. 1 , which is a schematic cross-sectional view of a conventional semiconductor package device 10 with bumps 15 . The manufacturing method of the semiconductor package element 10 is as follows. Firstly, the metal pad 12, the protective layer 13 and the copper pillar 14 are formed on the first surface 11a of the die 11 in sequence, and then the third surface 11c of the die 11 is completely covered with a coating material. 1. The first surface 11a and the protective layer 13 and the copper pillars 14 on the first surface 11a. After the cladding material is solidified, the cladding material and the copper pillars 14 are ground to make the two equal heights and parallel through grinding processes such as chemical mechanical planarization. The copper pillars 14 are exposed, and finally the bumps 15 are formed on the copper pillars 14 , and the remaining cladding material is the cladding layer 16 .

However, during the grinding process, burrs and scratches will be generated on the surface of the copper pillars 14 , and stress will remain, which will affect the performance of the semiconductor package device 10 . Furthermore, the hardness of the copper pillar 14 is high, which will damage the service life of the grinding tool. In addition, the copper pillar 14 needs to reserve a grinding height, which requires a longer process time and higher material cost.

The object of the present invention is to provide a semiconductor packaging device to solve the above problems.

According to one embodiment of the present invention, a semiconductor packaging device is provided, which includes a die, a protection layer, a conductive structure and a cladding layer. The crystal grain includes a first surface, a second surface and a third surface, the second surface is opposite to the first surface, and the third surface is connected between the first surface and the second surface. The protective layer is disposed on the first surface and forms a hole. The conductive structure is electrically coupled to the grain through the hole. The cladding layer covers the first surface and the third surface of the crystal grain, wherein the protective layer is buried in the cladding layer, a part of the conductive structure is buried in the cladding layer, and the other part of the conductive structure protrudes from an etched part of the cladding layer. The etched surface is formed by plasma etching.

Compared with the prior art, the semiconductor packaging element of the present invention uses plasma etching to remove the coating material above the conductive structure, thereby avoiding the surface tearing, scratches and residual stress of the conductive structure due to grinding, and prolonging the grinding tool The service life is long, and the conductive structure does not need to reserve a grinding height, which can save process time and material cost.

The aforementioned and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of preferred embodiments with reference to the drawings. The directional terms mentioned in the following embodiments, such as: up, down, left, right, front, back, etc., are only directions referring to the attached drawings. Accordingly, the directional terms used are illustrative rather than limiting of the invention. In each of the following embodiments, the same or similar components will use the same or similar symbols.

In the present invention, two elements are substantially parallel means that there is an included angle between the two elements, and the included angle is 0°±10°, or the included angle is 180°±10°. The fact that the two elements are substantially perpendicular means that there is an included angle between the two elements, and the included angle is 90°±10°.

Please refer to FIG. 2 , which is a schematic cross-sectional view of a semiconductor package device 100 according to an embodiment of the present invention. The semiconductor package device 100 includes a die 110 , a passivation layer 130 , a conductive structure 140 and a cladding layer 160 .

The die 110 is a semiconductor die, such as a logic die, a memory die, and the like. The crystal grain 110 includes a first surface 111 , a second surface 112 and a third surface 113 , the second surface 112 is opposite to the first surface 111 , and the third surface 113 is connected between the first surface 111 and the second surface 112 . Metal pads 120 , such as aluminum pads, can be disposed on the first surface 111 as input/output pads (I/O pads) of the die 110 .

The protective layer 130 is disposed on the first surface 111 and has holes 131 formed therein. The protection layer 130 is made of epoxy resin or polyimide, and can be formed on the first surface 111 by spin coating, lamination, etc., and the holes 131 can be formed by exposure and development techniques.

The conductive structure 140 is electrically coupled to the die 110 through the hole 131 . In this embodiment, the conductive structure 140 is a metal layer and is directly disposed on the metal pad 120. In other embodiments, a re-distribution layer (re-distribution layer) may be provided between the conductive structure 140 and the metal pad 120 as required. ; RDL). The material of the metal layer is, for example, nickel, copper or a combination thereof, and can be formed by evaporation or sputtering.

The cladding layer 160 covers the first surface 111 and the third surface 113 of the die 110, wherein the protective layer 130 is buried in the cladding layer 160, a part of the conductive structure 140 is buried in the cladding layer 160, and the other part protrudes from the cladding layer 160. The etched surface 161 of the coating 160 is formed by plasma etching. The material of the cladding layer 160 can be a dielectric material, such as polypropylene or epoxy resin film plastic (Epoxy Molding Compound; EMC). The cladding layer 160 can provide the capability of the die 110 to withstand impact. The aforementioned "the etched surface 161 is formed by plasma etching" means that the cladding material forming the cladding layer 160 originally completely covers the first surface 111 of the crystal grain 110 and the protective layer 130 and the conductive structure 140 thereon. The coating material above the conductive structure 140 can be removed by plasma etching to expose the conductive structure 140, and the remaining coating material is the coating layer 160, and the surface of the coating layer 160 etched by the plasma is the etched surface 161 . Due to the directionality of plasma etching, its etching direction (refer to the etching direction E of the sub-figure of Fig. 5 (d)) is substantially perpendicular to the first surface 111, and the etched surface 161 may include the first etched portion 162, the first etched portion Two corroded parts 163 and a third corroded part 164, the third corroded part 164 is connected between the conductive structure 140 and the second corroded part 163, and the second corroded part 163 is connected to the third corroded part 164 and the third corroded part 164. Between an etched part 162, that is, the second etched part 163 is located between the conductive structure 140 and the first etched part 162, the first etched part 162 is substantially perpendicular to the etching direction, and the third etched part 164 is perpendicular to the etching direction. The directions are substantially parallel, and the cross-section of the second etched portion 163 is arc-shaped, that is, the plasma etching can produce a substantially vertical etching profile. By removing the cladding material above the conductive structure 140 by plasma etching, the disadvantages of conventional grinding methods can be avoided.

Please refer to FIG. 3 , which is a schematic cross-sectional view of a semiconductor package device 200 according to another embodiment of the present invention. The difference from FIG. 2 is that the conductive structure 140a includes a metal layer 141 (here, an UBM layer) and a bump 142. The metal layer 141 is disposed on the first surface 111, and the bump 142 is disposed on the metal layer 141. superior. The bump 142 defines a geometric center O, and the distance L1 between the geometric center O and the first surface 111 is greater than the distance L2 between the etched surface 161 and the first surface 111, where the bump 142 is exemplified as a solder ball, and the geometric center O is a solder ball center of the ball.

Please refer to FIG. 4 , which is a schematic cross-sectional view of a semiconductor package device 300 according to another embodiment of the present invention. The difference between Fig. 3 and Fig. 4 lies in the height of the eroded surface 161 (represented by the height of the first eroded portion 162 with a larger range). In FIG. 3 , the etched surface 161 is the alignment metal layer 141 , and in FIG. 4 , the etched surface 161 is the alignment bump 142 . Specifically, when manufacturing the semiconductor package element 200, the cladding layer 160 can be formed first and then the bumps 142 are formed. The bumps 142 are formed, and then the cladding layer 160 is formed. Therefore, the cladding layer 160 can cover part of the bumps 142 . For details, please refer to the description of FIGS. 5 to 10 . When the bump 142 is a solder ball, and the distance L1 between the geometric center O (ie, the center of the ball) and the first surface 111 is greater than or equal to the distance L2 between the eroded surface 161 and the first surface 111, the third eroded portion 164 and the solder ball The connection point P of the ball is substantially equal to the height of the center of the ball, which is due to the downward etching direction of the plasma etching, and the lateral length of the solder ball at the center of the ball is the largest, so the plasma cannot etch the cladding material below point P, and cause this structural feature.

Referring to FIGS. 5 and 6 , they are schematic diagrams of a manufacturing process of a semiconductor package device according to an embodiment of the present invention, which can be used to manufacture the semiconductor package device 200 in FIG. 3 .

In sub-figure (a) of FIG. 5, a plurality of independent and unpackaged first components 100a are fixed on the substrate 410, such as by glue 420. The first component 100a includes a die 110, a metal pad 120, and a protective layer. 130 and metal layer 141 (referring to Fig. 3), the substrate 410 can be a wafer or a panel, and the material of the panel is such as glass, ceramics or other supporting materials, and the shape of the substrate 410 can be any shape such as a circle or a strip . In sub-figure (b) of FIG. 5 , the first element 100 a is completely covered with the covering material 430 , such as by dispensing, printing, etc., and the covering material 430 is cured. In sub-figure (c) of FIG. 5 , part of the coating material 430 is initially removed, and can be ground with a grinding tool 440 so that the height H1 of the coating material 430 is slightly higher than the height H2 of the first component 100a. In sub-figure (d) of FIG. 5, a part of the cladding material 430 is removed by plasma etching, so that the height H3 of the cladding material 430 is lower than the height H2 of the first element 100a, so that the metal layer 141 is exposed, wherein the electric The etching direction E of the slurry 450 is downward and perpendicular to the first surface 111 or the substrate 410 . The gas used for plasma etching depends on the cladding material 430 , for example, oxygen, carbon tetrafluoride or a combination thereof.

In sub-figure (a) of FIG. 6 , the substrate 410 is removed, for example, the substrate 410 can be removed by grinding with a grinding tool 440 , and the colloid 420 can be removed by further grinding to the dotted line. In the sub-figure (b) of Figure 6, the bump 142 can be formed by using a ball drop process, or a tin layer can be formed by vapor deposition, printing, etc., and then reflowed to form the bump 142. desired shape. In sub-figure (c) of FIG. 6 , cutting is performed to obtain a plurality of independent semiconductor package components 200 , wherein the remaining cladding material 430 is the cladding layer 160 . In other embodiments, if the steps in the sub-figure (b) of FIG. 6 are omitted, the semiconductor package device 100 in FIG. 2 can be obtained.

Referring to FIGS. 7 and 8 , they are schematic diagrams of the manufacturing process of a semiconductor package device according to another embodiment of the present invention, which can also be used to manufacture the semiconductor package device 200 in FIG. 3 .

In sub-figure (a) of FIG. 7 , a plurality of independent and unpackaged first components 100 a are fixed on the substrate 410 , such as by a thermal release film 460 . In sub-figure (b) of FIG. 7 , the first element 100 a is completely covered by the covering material 430 . In sub-figure (c) of FIG. 7 , part of the covering material 430 is preliminarily removed, so that the height H4 of the covering material 430 is slightly higher than the height H5 of the first component 100a. In sub-figure (d) of FIG. 7 , plasma etching is used to remove part of the cladding material 430 , so that the height H6 of the cladding material 430 is lower than the height H5 of the first device 100 a, so that the metal layer 141 is exposed.

In sub-figure (a) of FIG. 8 , the substrate 410 is removed. For example, the viscosity of the pyrolytic adhesive film 460 can be reduced by heating, so that the pyrolytic adhesive film 460 can be easily peeled off together with the substrate 410 . In sub-figure (b) of FIG. 8 , bumps 142 are formed. In sub-figure (c) of FIG. 8 , dicing is performed to obtain a plurality of independent semiconductor package components 200 . In other embodiments, the steps in the sub-figure (b) of FIG. 8 can be omitted, and the semiconductor package device 100 of FIG. 2 can be obtained. For other details about Figures 7 and 8, please refer to the descriptions of Figures 5 and 6.

9 and 10 are schematic diagrams of the manufacturing process of the semiconductor package device according to another embodiment of the present invention, which can be used to manufacture the semiconductor package device 300 in FIG. 4 . The difference between Figures 9 and 10 and Figures 7 and 8 is that the bump 142 is first formed on the first element 100a. Hereinafter, the combination of the bump 142 and the first element 100a is referred to as the second element (not otherwise labeled) .

In sub-figure (a) of FIG. 9 , a plurality of independent and unpackaged second components are fixed on the substrate 410 . In sub-figure (b) of FIG. 9 , the second element is completely covered by the covering material 430 . In sub-figure (c) of FIG. 9 , part of the covering material 430 is preliminarily removed, so that the height H7 of the covering material 430 is slightly higher than the height H8 of the second element.

In sub-figure (a) of FIG. 10 , plasma etching is used to remove part of the cladding material 430 , so that the height H9 of the cladding material 430 is lower than the height H8 of the second device, so that the bump 142 is exposed. In sub-figure (b) of FIG. 10 , the substrate 410 is removed. In sub-figure (c) of FIG. 10 , dicing is performed to obtain a plurality of independent semiconductor package components 300 . In this embodiment, since the bumps 142 are formed first, and then the cladding layer 160 is formed, the cladding layer 160 can cover part of the bumps 142 . In addition, the exposed height of the bump 142 can be determined by controlling the parameters of the plasma etching. When the plasma etching depth is deeper, the height H9 of the cladding material 430 is reduced to the alignment metal layer 141, and the result shown in FIG. 3 can be obtained. A semiconductor package component 200 . For other details about Figures 9 and 10, please refer to the descriptions of Figures 5 to 8.

The present invention further provides a method 500 for manufacturing a semiconductor package device, including steps 510 to 580, wherein steps 530, 560, and 570 are optional.

Step 510 is to fix a plurality of independent and unpackaged components to the substrate.

Step 520 completely wraps the device with the wrapping material.

Step 530 removes a portion of the cladding material with a grinding tool.

Step 540 removes part of the cladding material by plasma etching, exposing the conductive structure of each device.

Step 550 is removing the substrate.

Step 560 is to carry out laser marking to mark the specifications, manufacturer and other information on the die.

Step 570 is to form bumps.

Step 580 is to perform dicing to obtain a plurality of independent semiconductor package components.

Compared with the prior art, the semiconductor package device of the present invention has the following advantages.

1. Semiconductor packaging components have a conductive structure, which does not require the use of traditional lead frames, substrates, and wire bonding, which is conducive to the development trend of miniaturization. 2. Use plasma etching to remove the coating material above the conductive structure, which can avoid surface tearing, scratches and residual stress of the conductive structure due to grinding, and can prolong the life of the grinding tool. 3. The conductive structure does not need to reserve a grinding height, which can save process time and material costs. 4. The present invention can package multiple chips at the same time and then cut them, which is suitable for wafer-level packaging and panel-level packaging. 5. In the present invention, the component is completely covered with the coating material first, and then the upper coating material is removed, which is beneficial to improve the structural strength of the package. The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

10, 100, 200, 300: semiconductor packaging components 11, 110: grain 11a, 111: first surface 11b, 112: second surface 11c, 113: third surface 12, 120: metal pad 13, 130: protective layer 14: copper pillar 15, 142: Bump 16, 160: cladding layer 100a: first element 161: Corroded surface 162: The first eroded part 163: The second eroded part 164: The third eroded part 131: hole 140, 140a: Conductive structures 141: metal layer 410: Substrate 420: colloid 430: cladding material 440: grinding tool 450:Plasma 460: Pyrolytic adhesive film 500: method 510~580: steps E: etching direction L1, L2: Distance O: geometric center P: connection point H1~H8: Height

FIG. 1 is a schematic cross-sectional view of a conventional semiconductor package with bumps. FIG. 2 is a schematic cross-sectional view of a semiconductor package device according to an embodiment of the present invention. FIG. 3 is a schematic cross-sectional view of a semiconductor package device according to another embodiment of the present invention. FIG. 4 is a schematic cross-sectional view of a semiconductor package device according to yet another embodiment of the present invention. FIG. 5 and FIG. 6 are schematic diagrams of the manufacturing process of the semiconductor package device according to an embodiment of the present invention. FIG. 7 and FIG. 8 are schematic diagrams of the manufacturing process of a semiconductor package device according to another embodiment of the present invention. FIG. 9 and FIG. 10 are schematic diagrams of the manufacturing process of the semiconductor package device according to another embodiment of the present invention.

100: Semiconductor packaging components

110: grain

111: first surface

112: second surface

113: The third surface

120: metal pad

130: protective layer

131: hole

140: Conductive structure

160: cladding layer

161: Corroded surface

162: The first eroded part

163: The second eroded part

164: The third eroded part

Claims (9)

A semiconductor packaging component, comprising: One die, containing: a first surface; a second surface opposite the first surface; and a third surface connected between the first surface and the second surface; a protective layer, disposed on the first surface and forming a hole; a conductive structure electrically coupled to the die through the hole; and A cladding layer covering the first surface and the third surface of the crystal grain, wherein the protection layer is embedded in the cladding material, a part of the conductive structure is embedded in the cladding layer, and another part of the conductive structure is embedded in the cladding material. A portion protrudes from an etched surface of the cladding layer formed by plasma etching. The semiconductor package element according to claim 1, wherein the etched surface includes a first etched portion and a second etched portion, and the second etched portion is located between the conductive structure and the first etched portion . The semiconductor package device as claimed in claim 2, wherein the plasma etching has an etching direction, and the first etched portion is substantially perpendicular to the etching direction. The semiconductor package element as claimed in claim 3, wherein the etched surface further includes a third etched portion connected between the conductive structure and the second etched portion, the third etched portion is substantially in the same direction as the etching direction up parallel. The semiconductor package device as claimed in claim 2, wherein the cross-section of the second etched portion is an arc. The semiconductor package device as claimed in claim 1, wherein the conductive structure is a metal layer. The semiconductor package element as claimed in item 1, wherein the conductive structure comprises: a metal layer disposed on the first surface; and A bump is arranged on the metal layer. The semiconductor package device as claimed in claim 7, wherein the bump defines a geometric center, and the distance between the geometric center and the first surface is greater than or equal to the distance between the etched surface and the first surface. The semiconductor package element as claimed in claim 8, wherein the bump is a solder ball, the geometric center is a center of the solder ball, and the etched surface includes a first etched part and a second etched part and a third corroded part, the third corroded part is connected between the conductive structure and the second corroded part, the second corroded part is connected to the third corroded part and the first corroded part Between, the connection point between the third eroded portion and the solder ball is substantially equal in height to the center of the ball.

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