TW202243194A - 半導體裝置及半導體模組 - Google Patents

半導體裝置及半導體模組 Download PDF

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TW202243194A
TW202243194A TW110148654A TW110148654A TW202243194A TW 202243194 A TW202243194 A TW 202243194A TW 110148654 A TW110148654 A TW 110148654A TW 110148654 A TW110148654 A TW 110148654A TW 202243194 A TW202243194 A TW 202243194A
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field effect
bump
semiconductor device
effect transistor
semiconductor
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TW110148654A
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TWI851952B (zh
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森沢文雅
上田和弘
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日商村田製作所股份有限公司
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Abstract

本發明提供可提高具有發熱元件之半導體裝置中之散熱性之半導體裝置及半導體模組。 半導體裝置101具備：P型之半導體基板301，其具有主面401及與主面401對向之主面402；N型之N井302，其設於半導體基板301之主面401側；單位場效電晶體303，其設於N井302；P型之散熱用保護環區域305，其於半導體基板301之俯視下，於N井之外側，設於半導體基板301之主面401側；及配線504、凸塊設置部5041、5043及凸塊5042、5044，其等設於散熱用保護環區域305上。

Description

半導體裝置及半導體模組
本發明係關於半導體裝置及半導體模組。
於行動電話等移動體通訊中，使用設有功率放大用之功率放大電路之半導體模組。於專利文獻1中，示出半導體模組，其具有覆蓋設有功率放大電路之半導體晶片之散熱構件以提高設有功率放大電路之半導體模組中之散熱性。 [先前技術文獻] [專利文獻]
[專利文獻1]日本特開2005-228811號公報
[發明所欲解決之問題]
於此種半導體模組中，除功率放大電路引起之發熱以外，對功率放大電路供給電源電壓之調節器電路中亦產生發熱。調節器電路例如使用MOSFET等場效電晶體進行電壓轉換。於該電壓轉換時，由場效電晶體產生之熱量影響調節器電路之動作，影響對功率放大電路供給電源電壓。其結果，存在功率放大電路中之功率放大狀態發生變化，半導體模組之動作變得不穩定之情況。
本發明係鑒於此種情況而成者，目的在於提供可提高具有發熱元件之半導體裝置中之散熱性之半導體裝置及半導體模組。 [解決問題之手段]
本發明之一態樣之半導體裝置，具備：第1導電型之半導體基板，其具有第1主面及與第1主面對向之第2主面；第2導電型之第1井，其設於半導體基板之第1主面側；場效電晶體，其設於第1井；第1導電型之第2井，其於半導體基板之俯視下，於第1井之外側，設於半導體基板之第1主面側；及金屬部，其設於第2井上。 [發明之效果]
根據本發明，可提供可提高具有發熱元件之半導體裝置中之散熱性之半導體裝置及半導體模組。
對第1實施形態進行說明。圖1示出第1實施形態之半導體模組10之方塊圖。半導體模組10具有半導體裝置101、半導體裝置102及半導體裝置103。又，半導體模組10具有端子1041、1042、1043、1044、1045、1046、1047、1048、1049、1050。
於半導體模組10中，半導體裝置102將通過端子1045輸入之輸入訊號Pin1放大，半導體裝置103將通過端子1046輸入之輸入訊號Pin2放大。半導體裝置101進行對半導體裝置102之偏壓電壓之供給及半導體裝置102、103之偏壓電路之控制。又，半導體裝置102及半導體裝置103作為功率放大電路發揮功能。半導體裝置101作為對作為功率放大電路之半導體裝置102、103進行控制之電路發揮功能。於半導體模組10中，例如於積層基板上構裝有半導體裝置101、102、103。
半導體裝置101具有LDO電路部1011、數位電路部1012、基準電路部1013、邏輯電路部1014、偏壓控制部1015及偏壓控制部1016。
LDO電路部1011根據自端子1041供給之輸入電壓VIN、及自端子1050供給於半導體裝置101之電源電壓Vcc1，對半導體裝置102供給電源電壓Vcc1_out。LDO電路部1011具有場效電晶體部10111及放大器部10112。LDO電路部1011之電路圖將於下文敍述。
數位電路部1012根據通過端子1042輸入之數位用電源電壓VIO、通過端子1043輸入之時脈訊號CLK及通過端子1044輸入之資料訊號DATA，對邏輯電路部1014、偏壓控制部1015、1016供給訊號。
基準電路部1013係對LDO電路部1011、數位電路部1012、邏輯電路部1014及偏壓控制部1015、1016供給基準電壓之電路。
邏輯電路部1014根據來自數位電路部1012之訊號，例如輸出表示資料之接收發送狀態之訊號及控制頻帶切換開關等之訊號等數位訊號LOUT。
偏壓控制部1015根據來自數位電路部1012之訊號，對半導體裝置102發送偏壓控制訊號BIAS1，控制半導體裝置102之動作。
偏壓控制部1016根據來自數位電路部1012之訊號，對半導體裝置103發送偏壓控制訊號BIAS2，控制半導體裝置103之動作。
半導體裝置102具有放大器10211、10212、10213、電感器10221、10222、10223、匹配元件10231、10232、10233及偏壓電路1024。各放大器及匹配元件串聯連接。自LDO電路部1011對各放大器供給電源電壓Vcc1_out。電感器10221、10222、10223作為扼流電感器連接於放大器10211、10212、10213之各者。若用於進行功率放大之控制訊號輸入至偏壓電路1024，則半導體裝置102放大輸入訊號Pin1，將輸出訊號Pout1輸出至端子1047。
半導體裝置103具有放大器10311、10312、10313、電感器10321、10322、10323、匹配元件10331、10332、10333及偏壓電路1034。半導體裝置103亦與半導體裝置102同樣地動作。半導體裝置103於通過端子1048供給電源電壓Vcc2之方面，與半導體裝置102不同。
圖2示出LDO電路部1011之電路圖。LDO電路部1011具有運算放大器201、場效電晶體202及電阻元件203、204。
對運算放大器201之反相輸入端子將輸入電壓VIN輸入。運算放大器201之非反相輸入端子通過電阻元件203接地連接，通過電阻元件204連接於場效電晶體202之源極。運算放大器201之輸出端子連接於場效電晶體202之閘極。
場效電晶體202對汲極供給電源電壓Vcc1。場效電晶體202根據自運算放大器201輸入之閘極電壓，自源極輸出電源電壓Vcc1_out。於本實施形態中，場效電晶體202藉由利用配線連接有多個場效電晶體而構成。於本實施形態中，將構成場效電晶體202之各個場效電晶體以單位場效電晶體之形式進行說明。
圖3示出設有單位場效電晶體303之半導體基板301之俯視圖。再者，圖3未示出下述配線層或絕緣層。單位場效電晶體303設於具有P型（第1導電型）導電型之半導體基板301。於半導體基板301設有具有N型（第2導電型）導電型之N井（第1井）302。單位場效電晶體303設於N井302。
單位場效電晶體303具有閘極電極3031、源極區域3032、汲極區域3033。以包圍單位場效電晶體303之方式設有背閘極區域304。背閘極區域304係為了適當進行單位場效電晶體303之動作而設置之具有N型導電型之區域。
具有P型導電型之散熱用保護環區域（第2井）305設於N井302之外側。更具體而言，散熱用保護環區域305以包圍背閘極區域304之方式設置。
圖4係設有單位場效電晶體303之半導體基板301之剖面圖。半導體基板301具有沿著xy平面之主面401（第1主面）及與主面401對向之主面402（第2主面）。N井302設於半導體基板301之主面401側。N井302係藉由在具有P型導電型之半導體基板301摻雜雜質而形成之半導體區域。於半導體基板301中，N井302係自主面401朝向z軸負方向凹陷之凹型區域。
源極區域3032及汲極區域3033係藉由在N井302摻雜雜質而形成於N井302內部之P型區域。於源極區域3032與汲極區域3033之間設有閘極電極3031。
背閘極區域304係藉由在N井302摻雜雜質而使導電型較N井302更N型之區域。
散熱用保護環區域305係藉由在半導體基板301摻雜雜質而設於半導體基板301之主面401側之P型區域。散熱用保護環區域305係於半導體基板301之主面401側形成為井狀之半導體區域。
P井306係藉由在半導體基板301摻雜雜質而設於半導體基板301之主面401側之P型區域。P井306係使導電型較半導體基板301之主面402側之區域（圖4中之P-sub）更P型之區域。P井306從主面401朝向主面402之深度與N井302之該深度相同。散熱用保護環區域305係藉由在P井306摻雜雜質而使導電型較P井306更P型之區域。藉由散熱用保護環區域305及P井306，抑制主面401附近之極性不穩定。
再者，半導體基板301、N井302、單位場效電晶體303、背閘極區域304、散熱用保護環區域305及P井306之極性可反轉。即，可於N型之半導體基板形成P型井，於該井設置場效電晶體。於此情形時，相當於散熱用保護環區域305之半導體基板之區域為使導電型較該半導體基板更N型之區域。
圖5係場效電晶體部10111之布局圖。場效電晶體部10111具有4個單位場效電晶體303a、303b、303c、303d。再者，場效電晶體部10111所具有之單位場效電晶體之個數並不限定於4個，可更多或減少。
單位場效電晶體303a至303d之各閘極電極3031a至3031d藉由梳狀之閘極配線501連接。
單位場效電晶體303a至303d之各源極區域3032a至3032d藉由梳狀之源極配線502連接。
單位場效電晶體303a至303d之各汲極區域3033a至3033d藉由梳狀之汲極配線503連接。
配線504設於單位場效電晶體303a至303d之各散熱用保護環區域305（未圖示）之z軸正方向側。配線504以分別包圍單位場效電晶體303a至303d之方式形成。
於源極配線502之z軸正方向側設有凸塊設置部5021及凸塊5022。凸塊設置部5021及凸塊5022為金屬構件。
於汲極配線503之z軸正方向側設有凸塊設置部5031及凸塊5032。凸塊設置部5031及凸塊5032為金屬構件。
於配線504之z軸正方向側設有凸塊設置部5041、5043及凸塊5042、5044。凸塊設置部5041、5043及凸塊5042、5044為金屬構件。
參照圖6，對包含單位場效電晶體303a、303b之場效電晶體部10111之剖面構造進行說明。
閘極配線501、源極配線502、汲極配線503及配線504設置於設於半導體基板301之z軸正方向側亦即上部之配線層601、602、603。
閘極配線501以位於閘極電極3031a、3031b之上部之方式設於配線層602。
源極配線502以位於源極區域3032a、3032b之上部之方式設於配線層601、602、603。
汲極配線503以位於汲極區域3033a、3033b之上部之方式設於配線層601、602、603。
配線504以位於散熱用保護環區域305之上部之方式設於配線層601、602。
各配線層601、602、603中之閘極配線501、源極配線502、汲極配線503及配線504藉由絕緣體相互絕緣。
於配線層603設有凸塊設置部5041及凸塊設置部5043。於凸塊設置部5041之上部設有凸塊5042。於凸塊設置部5043之上部設有凸塊5044。即，以具有配線504、凸塊設置部5041、5043及凸塊5042、5044之方式，於散熱用保護環區域305上設有金屬部（第1金屬部）。
圖7係具有半導體基板301之半導體裝置101通過凸塊5042、5044構裝於半導體模組10之情形時之剖面圖。於半導體裝置101中，半導體基板301藉由塑模樹脂M成形。半導體裝置101構裝於積層基板701。又，半導體裝置101具有LDO電路部（第1電路部）1011、及例如數位電路部1012等其他電路部（第2電路部）。設於半導體基板301之電路部706為示意性表示第2電路部之電路之圖。電路部706通過凸塊部707連接於積層基板701。於半導體裝置101，搭載有具有單位場效電晶體303之LDO電路部（第1電路部）1011、及除LDO電路部1011以外之數位電路部1012、基準電路部1013、邏輯電路部1014、偏壓控制部1015及偏壓控制部1016電路部。
積層基板701具有基板層7011、7012、7013。以沿著積層基板701之z軸方向延伸之方式設有通孔702、703。於距離半導體裝置101最遠之基板層7013設有電極704、705作為背面電極。通孔702與電極704連接，通孔703與電極705連接。
通孔702與凸塊5042連接，通孔703與凸塊5044連接。藉此，可自半導體裝置101向積層基板701側進行導熱。
參照圖7對半導體模組10中之散熱進行說明。若半導體模組10動作，藉由LDO電路部1011對半導體裝置102進行電源電壓之供給，則單位場效電晶體303a、303b分別發熱。
單位場效電晶體303a、303b產生之熱量向周圍構件傳導。此時，向N井302a、302b之z軸正方向側傳導之熱量朝向半導體基板301之z軸正方向側傳導。即，單位場效電晶體303a、303b產生之熱量之一部分傳導至半導體基板301之與積層基板701側為相反側之面之附近。以此方式傳導之熱量經過半導體基板301之P型區域向散熱用保護環區域305移動。
到達散熱用保護環區域305之熱量通過配線504、凸塊設置部5041、凸塊5042向積層基板701側移動。又，亦存在通過配線504、凸塊設置部5043、凸塊5044向積層基板701側移動之熱量之路徑。
到達凸塊5042之熱量傳導至通孔702。熱量通過通孔702到達電極704，向外部散熱。散熱亦通過凸塊5044、通孔703及電極705進行。藉此，可提高半導體基板301之散熱性。
參照圖8及圖9，亦對利用凸塊5022、5032之散熱進行說明。圖8係包含凸塊設置部5021、5031、凸塊5022、5032之剖面中之半導體基板301之剖面圖。
於配線層603設有凸塊設置部5021及凸塊設置部5031。於凸塊設置部5021之上部設有凸塊5022。於凸塊設置部5031之上部設有凸塊5032。即，以具有凸塊設置部5021及凸塊5022之方式，於單位場效電晶體303a上設有金屬部（第2金屬部）。
圖9係與圖7同樣地設有半導體裝置101之半導體模組10之剖面圖。
沿積層基板701之z軸方向設有通孔901、902。於距離半導體裝置101最遠之基板層7013設有電極903、904作為背面電極。通孔901與電極903連接，通孔902與電極904連接。通孔901與凸塊5022連接，通孔902與凸塊5032連接。
於此情形時，單位場效電晶體303a、303b產生之熱量之一部分通過源極配線502、凸塊設置部5021、凸塊5022、通孔901及電極903散熱。又，散熱亦通過汲極配線503、凸塊設置部5031、凸塊5032、通孔902及電極904進行。
半導體模組10除通過凸塊5042、5044進行散熱以外，亦藉由利用凸塊5022、5032進行散熱，可更加有效地對LDO電路部1011產生之熱量進行散熱。
對第2實施形態進行說明。於第2實施形態以後將省略關於與第1實施形態共通之情況之記述，僅對不同點進行說明。尤其是對於每一實施形態，將不再依次提及相同構成之相同作用效果。
圖10係第2實施形態之半導體裝置中之場效電晶體部10111A之布局圖。
場效電晶體部10111A於在源極配線502及汲極配線503之z軸正方向側設有配線1001及1002之方面與場效電晶體部10111不同。配線1001及配線1002於xy平面中之俯視下，設於各單位場效電晶體之內側。於配線1001設有凸塊10011。於配線1002設有凸塊10021。
圖11係場效電晶體部10111A之剖面圖。於場效電晶體部10111A中，於配線層603之上部設有絕緣層1101及配線層1102。配線1001、1002設於配線層1102。於配線1001之上部設有凸塊10011。於配線1002之上部設有凸塊10021。
圖12係構裝有具有場效電晶體部10111A之半導體裝置101A之半導體模組10A之剖面圖。於半導體模組10A中，與關於圖9之第1實施形態中之說明同樣地，亦可通過凸塊10011及凸塊10021進行散熱。
對第3實施形態進行說明。圖13係第3實施形態之半導體裝置中之場效電晶體部10111B之布局圖。
場效電晶體部10111B於在源極配線502及汲極配線503之z軸正方向側設有配線（第3金屬部）1301及1302之方面與場效電晶體部10111不同。於配線1301設有凸塊13011、13012。於配線1302設有凸塊13021、13022。凸塊13011及13021以位於配線504上之方式設置。
圖14係場效電晶體部10111B之剖面圖。於場效電晶體部10111B中，於配線層603之上部設有絕緣層1101及配線層1102。配線1301、1302設於配線層1102。於配線1301之上部設有凸塊13011、13012。於配線1302之上部設有凸塊13021、13022。
於場效電晶體部10111B中，以連接凸塊13011及散熱用保護環區域305之方式形成配線504。又，配線504以連接凸塊13021及散熱用保護環區域305之方式形成。散熱用保護環區域305通過配線504及配線1301連接於凸塊13012。散熱用保護環區域305通過配線504及配線1302連接於凸塊13022。
圖15係構裝有具有場效電晶體部10111B之半導體裝置101B之半導體模組10B之剖面圖。
於半導體模組10B中，與關於圖7之第1實施形態中之說明同樣地，通過配線504、配線1301、凸塊13011、通孔702及電極704進行散熱。散熱亦可通過配線504、配線1302、凸塊13021、通孔703及電極705進行。
於半導體模組10B中，除上述散熱以外，沿z軸方向自散熱用保護環區域305向配線504移動之熱量藉由沿xy平面於配線1301移動而向凸塊13012傳導。該熱量通過凸塊13012、通孔901及電極903散熱。藉此促進通過散熱用保護環區域305之散熱。通過配線1302之散熱亦同樣地得到促進。
又，於半導體模組10B中，由於亦存在與半導體模組10A相同之散熱路徑，因此可更加有效地進行散熱。
對第4實施形態進行說明。圖16係第4實施形態之半導體裝置中之場效電晶體部10111C之布局圖。
場效電晶體部10111C於在源極配線502及汲極配線503之z軸正方向側設有再配線（第4金屬部）1601之方面與場效電晶體部10111不同。再配線1601之材料例如可為導熱率較用於閘極配線501等之金屬材料高之金屬材料。例如可使閘極配線501等使用鋁，再配線1601使用銅。
於再配線1601之上部設有凸塊設置部16021、16031。於凸塊設置部16021之上部設有凸塊16022。於凸塊設置部16031之上部設有凸塊16032。再配線1601例如係形成為於xy平面上具有較凸塊設置部16021、16031及凸塊16022、16032大之面積之金屬部。
圖17係場效電晶體部10111C之剖面圖。於場效電晶體部10111C中，於絕緣層1101之上部設有再配線1601。於再配線1601之上部設有配線層1701。於配線層1701設有凸塊設置部16021、16031。於凸塊設置部16021之上部設有凸塊16022，於凸塊設置部16031之上部設有凸塊16032。
圖18係構裝有具有場效電晶體部10111C之半導體裝置101C之半導體模組10C之剖面圖。於半導體模組10C中，與關於圖9之第1實施形態中之說明同樣地，亦可通過凸塊16022及凸塊16032進行散熱。
又，於半導體模組10C中，單位場效電晶體303a、303b產生之熱量之一部分傳導至再配線1601。傳導至再配線1601之熱量通過凸塊16022及凸塊16032散熱。藉此，與圖12所示之情形相比，藉由從更廣範圍收集熱量而散熱，可進行有效之散熱。又，亦可通過再配線1601至積層基板701側這一除凸塊16022及凸塊16032以外之路徑進行散熱，可進行有效之散熱。
對第5實施形態進行說明。圖19係第5實施形態之半導體裝置中之場效電晶體部10111D之布局圖。
場效電晶體部10111D於在源極配線502及汲極配線503之z軸正方向側設有再配線1901之方面與場效電晶體部10111不同。再配線1901之材料可與再配線1601同樣地適當進行變更。
於再配線1901之上部設有凸塊設置部19021、19031。凸塊設置部19021、19031與再配線1901連接。於凸塊設置部19021之上部設有凸塊19022。於凸塊設置部19031之上部設有凸塊19032。
再配線1901例如係形成為於xy平面上具有較凸塊設置部19021、19031及凸塊19022、19032大之面積之金屬部。
於配線504之上部設有凸塊設置部19041、19051。於凸塊設置部19041之上部設有凸塊19042。於凸塊設置部19051之上部設有凸塊19052。
圖20係場效電晶體部10111D之剖面圖。於場效電晶體部10111D中，於絕緣層1101之上部設有配線層2001。於配線層2001之上部設有配線層2002。於配線層2001設有再配線1901。於配線層2002設有凸塊設置部19021、19031、19041、19051。於凸塊設置部19021之上部設有凸塊19022，於凸塊設置部19031之上部設有凸塊19032，於凸塊設置部19041之上部設有凸塊19042，於凸塊設置部19051之上部設有凸塊19052。
圖21係構裝有具有場效電晶體部10111D之半導體裝置101D之半導體模組10D之剖面圖。於半導體模組10D中，與關於圖18之第4實施形態中之說明同樣地，亦可通過凸塊19022及凸塊19032進行散熱。
又，於半導體模組10D中，與關於圖7之第1實施形態中之說明同樣地，進而可通過凸塊19042、19052進行散熱。藉此可進行有效之散熱。又，於以位於凸塊設置部19041及凸塊19042附近之方式配置再配線1901之情形時，可使於再配線1901傳導之熱量向凸塊設置部19041及凸塊19042移動而釋放。藉此亦可進行有效之散熱。
對第6實施形態進行說明。圖22係第6實施形態之半導體模組10E之示意性立體圖。
於半導體模組10E之半導體裝置中，以覆蓋包含場效電晶體之LDO電路部1011E及電路部706之方式設有散熱構件2201。散熱構件2201於積層基板701側具有開口部22011。通過開口部22011，LDO電路部1011E連接於積層基板701。散熱構件2201例如為金屬材料。
圖23係半導體模組10E之剖面圖。圖23示出具有散熱構件2201之半導體裝置101E構裝於積層基板701之情形時之剖面圖。
於半導體模組10E中，沿積層基板701之z軸方向設有通孔2302、2304。於基板層7013設有電極2303、2305作為背面電極。通孔2302與電極2303連接，通孔2304與電極2305連接。通孔2302、2304分別通過散熱構件2201之端部2301與散熱構件2201連接。
於半導體模組10E中，與關於圖7之第1實施形態中之說明同樣地，可通過凸塊5042、5044進行散熱。
又，傳導至單位場效電晶體303a、303b之上部而於半導體基板301蓄積之熱量可通過散熱構件2201向積層基板701側移動。於散熱構件2201移動之熱量藉由通過端部2301傳遞至通孔2302及電極2303而釋放至半導體模組10E之外部。散熱亦可自散熱構件2201通過通孔2304及電極2305進行。藉此可進行有效之散熱。再者，散熱構件只要以覆蓋單位場效電晶體303之方式設置即可，可不一定以覆蓋電路部706之方式設置。
以上，對本發明之例示性實施形態進行了說明。第1實施形態之半導體裝置101具備：P型之半導體基板301，其具有主面401及與主面401對向之主面402；N型之N井302，其設於半導體基板301之主面401側；單位場效電晶體303，其設於N井302；P型之散熱用保護環區域305，其於半導體基板301之俯視下，於N井之外側，設於半導體基板301之主面401側；及配線504、凸塊設置部5041、5043及凸塊5042、5044，其等設於散熱用保護環區域305上。
單位場效電晶體303所產生之熱量中，於半導體基板301傳導至N井302之主面402側之熱量通過P型之半導體基板301向主面401側之散熱用保護環區域305傳導。該熱量通過設於散熱用保護環區域305上之配線504、凸塊設置部5041、5043及凸塊5042、5044向半導體裝置101之外部釋放。如此，於半導體裝置101中，進行與靠近單位場效電晶體303之主面401側相反之主面402側之熱量之散熱。藉此，可提高半導體裝置中之散熱性。
又，半導體裝置101進一步具備設於單位場效電晶體303上之凸塊設置部5021、5031及凸塊5022、5032。藉此，半導體裝置101可進而通過凸塊5022、5032進行散熱。因此，可提高半導體裝置中之散熱性。
又，半導體裝置101B進一步具備於沿主面401之方向將配線504與凸塊13012連接之配線1301及將配線504與凸塊13022連接之配線1302。藉此，來自散熱用保護環區域305之熱量通過配線504由更多凸塊散熱。藉此，可提高半導體裝置中之散熱性。
又，半導體裝置101D進一步具備再配線1901，於凸塊19022和單位場效電晶體303之間與凸塊19022連接而設置，於半導體基板301之俯視下面積大於凸塊19022。藉此，再配線1901可自較凸塊19032更廣之範圍收集熱量。半導體裝置101D藉由通過凸塊19032將該熱量進行散熱，可進行有效之散熱。
又，半導體裝置101具備包含單位場效電晶體303之LDO電路部1011、及不包含單位場效電晶體303之電路部706。藉此，於半導體裝置101例如構裝於積層基板之情形時，散熱面積擴增電路部706之面積。藉此，提高半導體裝置中之散熱性。
又，半導體模組10具備半導體裝置101、及具有與凸塊5022、5032連接之通孔702、703之積層基板701。藉此，可通過通孔702、703進行散熱。因此，提高半導體模組10之散熱性。
又，半導體模組10E進一步具備於積層基板701具有開口部22011且以覆蓋LDO電路部（第1電路部）1011內之單位場效電晶體303及其他電路部（第2電路部）706之方式設置的散熱構件2201，積層基板701具有與散熱構件2201之積層基板701側之端部連接之通孔2302、2304。藉此，來自單位場效電晶體303之熱量之一部分於散熱構件2201移動。該熱量通過端部2301，然後通過通孔2302及電極2305散熱。藉此，單位場效電晶體303所產生之熱量釋放至半導體模組10E之外部。因此，提高半導體模組10之散熱性。
再者，以上說明之各實施形態係用於使本發明容易理解者，而非用於限定解釋本發明。本發明可不脫離其主旨而進行變更/改良，並且本發明中亦包含其等價物。即，本發明所屬技術領域中具有通常知識者對各實施形態適當施加設計變更而得者只要具備本發明之特徵，亦包含於本發明之範圍。例如，各實施形態所具備之各要素及其配置、材料、條件、形狀、尺寸等不應限定於例示者，而可適當進行變更。又，各實施形態為例示，不同實施形態中示出之構成當然可進行局部置換或組合，只要包含本發明之特徵，其等亦包含於本發明之範圍。
10、10A、10B、10C、10D、10E:半導體模組 101、101A、101B、101C、101D、101E:半導體裝置 1001、1002:配線 10011、10021:凸塊 1011、1011E:LDO電路部 10111、10111A、10111B、10111C、10111D:場效電晶體部 10112:放大器電路部 1012:數位電路部 1013:基準電路部 1014:邏輯電路部 1015、1016:偏壓控制部 102:半導體裝置 10211、10212、10213:放大器 10221、10222、10223:電感器 10231、10232、10233:匹配元件 1024、1034:偏壓電路 103:半導體裝置 10311、10312、10313:放大器 10321、10322、10323:電感器 10331、10332、10333:匹配元件 1041、1042、1043、1044、1045、1046、1047、1048、1049、1050:端子 1101:絕緣層 1102:配線層 1301、1302:配線 13011、13012、13021、13022:凸塊 1601:再配線 16021、16031:凸塊設置部 16022、16032:凸塊 1901:再配線 19021、19031、19041、19051:凸塊設置部 19022、19032、19042、19052:凸塊 2001、2002:配線層 201:運算放大器 202:場效電晶體 203、204:電阻元件 2201:散熱構件 22011:開口部 2301:端部 2302、2304:通孔 2303、2305:電極 301:半導體基板 302、302a、302b:N井 303:單位場效電晶體 303a、303b:單位場效電晶體 3031、3031a至3031d:閘極電極 3032、3032a至3032d:源極區域 3033、3033a至3033d:汲極區域 304:背閘極區域 305:散熱用保護環區域 306:P井 501:閘極配線 502:源極配線 5021、5031:凸塊設置部 5022、5032:凸塊 503:汲極配線 504:配線 5041、5043:凸塊設置部 5042、5044:凸塊 601、602、603:配線層 701:積層基板 7011、7012、7013:基板層 702、703:通孔 704、705:電極 706:電路部 707:凸塊部 901、903:通孔 903、904:電極 BIAS1、BIAS2:偏壓控制訊號 CLK:時脈訊號 DATA:資料訊號 LOUT:數位訊號 Pin1、Pin2:輸入訊號 Pout1:輸出訊號 Vcc1、Vcc2:電源電壓 Vcc1_out:電源電壓 VIN:輸入電壓 VIO:數位用電源電壓
[圖1]係第1實施形態之功率放大模組之方塊圖。 [圖2]係設於功率放大模組之調節器電路之電路圖。 [圖3]係調節器電路中之場效電晶體之俯視圖。 [圖4]係圖3之切割線IV-IV之剖面圖。 [圖5]係第1實施形態之半導體裝置之場效電晶體部之布局圖。 [圖6]係圖5之切割線VI-VI之剖面圖。 [圖7]係第1實施形態之功率放大模組之剖面圖。 [圖8]係圖5之切割線VIII-VIII之剖面圖。 [圖9]係第1實施形態之功率放大模組之另一剖面圖。 [圖10]係第2實施形態之半導體裝置之場效電晶體部之布局圖。 [圖11]係圖10之切割線XI-XI之剖面圖。 [圖12]係第2實施形態之功率放大模組之剖面圖。 [圖13]係第3實施形態之半導體裝置之場效電晶體部之布局圖。 [圖14]係圖13之切割線XIV-XIV之剖面圖。 [圖15]係第3實施形態之功率放大模組之剖面圖。 [圖16]係第4實施形態之半導體裝置之場效電晶體部之布局圖。 [圖17]係圖16之切割線XVII-XVII之剖面圖。 [圖18]係第4實施形態之功率放大模組之剖面圖。 [圖19]係第5實施形態之半導體裝置之場效電晶體部之布局圖。 [圖20]係圖19之切割線XX-XX之剖面圖。 [圖21]係第5實施形態之功率放大模組之剖面圖。 [圖22]係第6實施形態之功率放大模組之示意性立體圖。 [圖23]係第6實施形態之功率放大模組之剖面圖。
301:半導體基板
302a:N井
302b:N井
303a:單位場效電晶體
303b:單位場效電晶體
305:散熱用保護環區域
306:P井
501:閘極配線
502:源極配線
503:汲極配線
504:配線
601、602、603:配線層
10111:場效電晶體部
3031a:閘極電極
3031b:閘極電極
3032a:源極區域
3032b:源極區域
3033a:汲極區域
3033b:汲極區域
5041、5043:凸塊設置部
5042、5044:凸塊

Claims (7)

  1. 一種半導體裝置，具備： 第1導電型之半導體基板，其具有第1主面及與上述第1主面對向之第2主面； 第2導電型之第1井，其設於上述半導體基板之上述第1主面側； 場效電晶體，其設於上述第1井； 第1導電型之第2井，其於上述半導體基板之俯視下，於上述第1井之外側，設於上述半導體基板之上述第1主面側；及 金屬部，其設於上述第2井上。
  2. 如請求項1之半導體裝置，其中， 上述金屬部為第1金屬部， 上述半導體裝置進一步具備設於上述場效電晶體上之第2金屬部。
  3. 如請求項2之半導體裝置，其進一步具備： 第3金屬部，其於沿上述第1主面之方向，將上述第1金屬部與上述第2金屬部連接。
  4. 如請求項2之半導體裝置，其進一步具備： 第4金屬部，其於上述第2金屬部和上述場效電晶體之間與上述第2金屬部連接而設置，於上述半導體基板之俯視下，面積大於上述第2金屬部。
  5. 如請求項1至4中任一項之半導體裝置，其具備： 第1電路部，其包含上述場效電晶體；及 第2電路部，其不包含上述場效電晶體。
  6. 一種半導體模組，具備： 請求項1至5中任一項之半導體裝置；及 積層基板，其具有與上述金屬部連接之通孔。
  7. 如請求項6之半導體模組，其進一步具備： 散熱構件，其於上述積層基板側具有開口部，以覆蓋上述場效電晶體之方式設置； 上述積層基板具有與上述散熱構件之上述積層基板側之端部連接之通孔。
TW110148654A 2021-01-15 2021-12-24 半導體裝置及半導體模組 TWI851952B (zh)

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