TW202242668A - Data boundary detection circuit, and control chip and electronic device using the same including a temporary storage unit configured to store a plurality of input character byte data in a shifted manner, and a boundary address generating unit configured to generate an output boundary address - Google Patents

Abstract

A data boundary detection circuit includes: a temporary storage unit configured to store a plurality of input character byte data in a shifted manner and select two of the consecutive input character byte data according to an output boundary address to provide an output data; and a boundary address generating unit configured to generate the output boundary address according to the sum of an updateable boundary address and an updateable address offset value. The updateable boundary address is updated by a boundary address in which a boundary character of synchronization data appears in the plurality of input character byte data. The updatable address offset value is updated by a difference between a current value and a previous value of the boundary address.

Description

Data boundary detection circuit, control chip and electronic device using the same

The present invention relates to high-speed data reception, especially a boundary detection circuit for ensuring that high-speed data is received without misalignment.

In the case of higher and higher data transmission rate requirements, more and more electronic devices choose the C-PHY interface instead of the D-PHY interface as the high-speed communication interface, and the data width is also specified in the agreement. 7 characters (Symbol) Extended to 14 characters (Symbol), wherein, the D-PHY interface has multiple differential channels, one of which transmits a clock signal, and the remaining channels transmit data; relatively, the C-PHY interface has at least one three-wire channel to transmit data, The clock signal is obtained by performing a clock recovery operation on the data signal converted from the C-PHY interface signal at the receiving end.

However, in the process of C-PHY communication, since the clock signal is recovered from the data signal, when the data is wrong or lost during high-speed serial transmission, the recovered clock signal will also be wrong, resulting in misalignment of the data boundary And cause an unpacking error to occur in the subsequent DSI-2 protocol parsing logic unit. Therefore, in C-PHY transmission, it is necessary to dynamically track whether the data boundary is correct.

In order to solve the above problems, the general approach is to add synchronization information in the C-PHY protocol to determine whether the synchronization is lost during data transmission. If the synchronization of the data boundary is lost, it is necessary to restore the synchronization of the data boundary as soon as possible to ensure The correct capture of the next packet. That is, how to quickly determine the boundary synchronization loss and restore the data boundary as soon as possible to minimize data loss has become one of the key points in the C-PHY communication design.

However, in the parallel data transmission design using 14 symbols (Symbol), as shown in Figure 1, the synchronization information may exist in the upper 7 symbols (Symbol) or the lower 7 symbols (Symbol), resulting in three C-PHY channels The process of determining the synchronization between them becomes extremely complicated.

Therefore, there is an urgent need in the art for a novel data boundary detection circuit.

An object of the present invention is to provide a data boundary detection circuit, which can define a boundary address range and utilize a simple sequential logic circuit to detect a synchronization data boundary character before and after the boundary character within the boundary address range A boundary address calculation is performed at the last position, and the correct data capture boundary can be quickly restored to minimize data loss.

Another object of the present invention is to provide a control chip, which can quickly restore the correct data capture boundary through the above-mentioned data boundary detection circuit to minimize data loss.

Another object of the present invention is to provide an electronic device, which can quickly restore the correct data capture boundary through the above-mentioned control chip to minimize data loss.

In order to achieve the aforementioned purpose, a data boundary detection circuit is proposed, which has:

A temporary storage unit is used to store multiple input character byte data in a shifted manner, and it selects two consecutive input character byte data according to an output boundary address to provide an output data; and

A boundary address generating unit is used to generate the output boundary address according to the sum of an updateable boundary address and an updateable address offset value, wherein the updateable boundary address is generated by a synchronous A boundary character of the data is updated by a boundary address that appears in the multiple input character byte data, and the updateable address offset value is one of a current value and a previous value of the boundary address The difference is updated.

In one embodiment, the temporary storage unit has:

a shift register for storing the plurality of input character byte data; and

A control circuit is used for reading two consecutive pieces of input character byte data from the shift register according to the output boundary address to provide the output data.

In one embodiment, the boundary address generating unit has:

A boundary detection unit, used for detecting the position of the boundary character of the synchronization data in a boundary range according to the storage content of the shift register, and updating the boundary character only when the boundary character is detected The content of the updatable boundary address.

In one embodiment, the boundary address generating unit further has: A boundary address storage unit stores the updateable boundary address.

In one embodiment, the boundary address generating unit further has:

An address offset value storage unit stores the updateable address offset value.

In one embodiment, the data boundary detection circuit, wherein the boundary address generating unit further has:

a first multiplexer for selecting one of the current value and the previous value of the boundary address to generate the updateable boundary address;

a second multiplexer for selecting one of a current value and a previous value of the difference to generate the updateable address offset value; and

An adder is used for performing an addition operation on the updateable boundary address and the updateable address offset value to generate the output boundary address.

To achieve the above-mentioned purpose, the present invention further proposes a control chip, which has a signal conversion unit and a data boundary detection circuit, and the signal conversion unit is used to generate input character words according to the transmission signals of multiple C-PHY channels section data and transmit it to the data boundary detection circuit, and the data boundary detection circuit has:

A temporary storage unit is used to store multiple pieces of input character byte data in a shifted manner, and it selects two consecutive pieces of input character byte data according to an output boundary address to provide one piece of output data; as well as

A boundary address generating unit is used to generate the output boundary address according to the sum of an updateable boundary address and an updateable address offset value, wherein the updateable boundary address is generated by a synchronous A boundary character of the data is updated by a boundary address that appears in the multiple input character byte data, and the updateable address offset value is one of a current value and a previous value of the boundary address The difference is updated.

In one embodiment, the temporary storage unit has:

a shift register for storing the plurality of input character byte data; and

A control circuit is used for reading two consecutive pieces of input character byte data from the shift register according to the output boundary address to provide the output data.

In one embodiment, the boundary address generating unit has:

A boundary detection unit, used for detecting the position of the boundary character of the synchronization data in a boundary range according to the storage content of the shift register, and updating the boundary character only when the boundary character is detected The content of the updatable boundary address. In one embodiment, the data boundary detection circuit further has:

An output gate control unit has a plurality of input terminals to couple the plurality of state signals, an output end to provide the output pause signal, and an inverting gate to enable the The output suspend signal presents a low potential to enable the data output of the plurality of FIFO temporary storage units, and when any signal in the plurality of status signals is low, the output suspend signal presents a high potential to disable The data output of the plurality of first-in-first-out temporary storage units can be performed.

In one embodiment, the boundary address generating unit further has: A boundary address storage unit stores the updateable boundary address.

In one embodiment, the boundary address generating unit further has: An address offset value storage unit stores the updateable address offset value.

In one embodiment, the boundary address generating unit further has:

a first multiplexer for selecting one of the current value and the previous value of the boundary address to generate the updateable boundary address;

a second multiplexer for selecting one of a current value and a previous value of the difference to generate the updateable address offset value; and

An adder is used for performing an addition operation on the updateable boundary address and the updateable address offset value to generate the output boundary address.

In order to achieve the aforementioned object, the present invention further proposes an electronic device, which has a functional unit and the aforementioned control chip, and the functional unit includes an audio functional unit and/or a video functional unit.

In possible embodiments, the electronic device can be a display, a portable computer or a smart handheld device.

Please refer to FIG. 2 , which shows a circuit diagram including an embodiment of the data boundary detection circuit of the present invention. As shown in Figure 2, a data boundary detection circuit 100 includes a temporary storage unit 110, a boundary detection unit 120, a boundary address storage unit 130, an address comparison unit 140, an address offset value storage unit 150 , a first multiplexer 160 , a second multiplexer 170 and an adder 180 .

The temporary storage unit 110 has a shift register 110a and a control circuit 110b, wherein the shift register 110a has three storage units with a space of 14 characters for storing each pen 14 by moving 14 characters at a time. The input data SYMB _IN of the character, for example, assume that the 14 characters SYMB _IN of the first, second, third and fourth input are respectively S14 ₁ , S14 ₂ , S14 ₃ , S14 ₄ , then the storage content of the shift register 110a will be With (14 blank characters, 14 blank characters, 14 blank characters), (S14 ₁ , 14 blank characters, 14 blank characters), (S14 ₂ , S14 ₁ , 14 blank characters), (S14 ₃ , S14 ₂ , S14 ₁ ), (S14 ₄ , S14 ₃ , S14 ₂ ); the control circuit 110b is used to move from the 1st to the 42nd character space of the shift register 110a according to an output boundary address BAOUT 14 characters are read from the BAOUT+1 to BAOUT+14 character spaces to provide a 14-character output data SYMB _OUT , wherein BAOUT is an integer between 1 and 20.

The boundary detection unit 120 is used to detect the position of a boundary character of a 7-character synchronization data in 1 to 20 according to the storage content of the shift register 110a, and only when the boundary character is detected A first boundary address BA1 is generated by adding 1 to the position to determine a first boundary address BA1. For example, assuming that the 7-character synchronous data is (3, 4, 4, 4, 4, 4, 3), the boundary character is the leftmost character 3, and the boundary character is in the shift register 110a In the sixth character space counted from the left, the first boundary address BA1 = 6+1 = 7.

The boundary address storage unit 130 is used to store the first boundary address BA1 to provide a second boundary address BA2, wherein the second boundary address BA2 represents a previous value of the first boundary address BA1, that is, , when the boundary detection unit 120 generates the first boundary address BA1, the second boundary address BA2 output by the boundary address storage unit 130 is the previous value of the first boundary address BA1.

The address comparison unit 140 is used to generate a first selection signal SEL1, perform a difference operation on the first boundary address BA1 and the second boundary address BA2 to generate a first address difference DA1, and The first address difference DA1 and a second address difference DA2 perform a comparison operation to generate a second selection signal SEL2, wherein the first selection signal SEL1 initially assumes a first state, and then presents a A second state; the second selection signal SEL2 presents the first state initially, and then presents the first state when the first address difference DA1 and the second address difference DA2 are the same state, and present the second state when they are different.

The address offset value storage unit 150 is used to store the first address difference DA1 to provide a second address difference DA2, wherein the second address difference DA2 represents the difference between the first address difference DA1 A previous value, that is, when the address comparison unit 140 generates the first address difference DA1, the address difference DA2 output by the address offset value storage unit 150 is the value of the first address difference DA1 previous value.

The first multiplexer 160 is used to select the first boundary address BA1 or the second boundary address BA2 as a boundary address BA according to the control of the first selection signal SEL1, wherein when the first selection When the signal SEL1 presents the first state, the first multiplexer 160 selects the first boundary address BA1; when the first selection signal SEL1 presents the second state, the first multiplexer 160 selects the second boundary address BA1; Boundary address BA2.

The second multiplexer 170 is used to select the first address difference DA1 or the second address difference DA2 according to the control of the second selection signal SEL2 as an address difference DA, wherein, when the When the second selection signal SEL2 presents the first state, the second multiplexer 170 selects the second address difference DA2; when the second selection signal SEL2 presents the second state, the second multiplexer 170 The first address difference DA1 is selected.

The adder 180 is used to generate the output boundary address BAOUT according to the sum of the boundary address BA and the address difference DA.

According to the above technical solution, the present invention can effectively solve the problem of data boundary loss caused by symbol errors during C-PHY communication. That is to say, the present invention can reflect the position change of a boundary character in a quantitative manner by providing a quantized address space in a temporary storage unit; and by retaining the address information of the last boundary character, and By comparing the address information of the current boundary character with the address information of the last boundary character, the present invention can dynamically fine-tune the position of the boundary address of the output data, so as to quickly return to the state of correctly capturing the input data. It should be pointed out here that in the process of data transmission of multiple C-PHY channels, if data loss occurs, the entire parallel data will be offset, which will lead to subsequent DSI-2 unpacking failures. For this problem, we can not only rely on searching for synchronization information from the beginning, but also need to retain the last boundary information to effectively solve the misalignment problem caused by data loss.

According to the above description, the present invention further provides a control chip. Please refer to FIG. 3 , which shows a block diagram of an embodiment of the control chip of the present invention. As shown in FIG. 3, a control chip 200 has three signal conversion units 210 and a data boundary detection circuit 220, wherein a signal conversion unit 210 is used to transmit signals (CPHY0, CPHY1) according to three C-PHY channels. , CPHY2) Generate the 14-character SYMB _IN to send to the data boundary detection circuit 220, and the data boundary detection circuit 220 is realized by the data boundary detection circuit 100.

According to the above description, the present invention further provides an electronic device. Please refer to FIG. 4 , which shows a block diagram of an embodiment of the electronic device of the present invention. As shown in FIG. 4 , an electronic device 300 has a control chip 310 and a functional unit 320 , wherein the control chip 310 is realized by the control chip 200 , and the functional unit 320 may include an audio function unit or a video function unit. In addition, the electronic device 300 can be a display, a portable computer or a smart handheld device.

According to the above description, the present invention can provide the following advantages:

1. The data boundary detection circuit of the present invention can define a boundary address range, and utilize a simple sequential logic circuit to perform a boundary on the front and rear positions where the boundary character of a synchronization data appears in the boundary address range Address calculation, which can quickly restore the correct data capture boundary to minimize data loss.

2. The control chip of the present invention can quickly restore the correct data capture boundary through the above-mentioned data boundary detection circuit to minimize data loss.

3. The electronic device of the present invention can quickly restore the correct data capture boundary through the above-mentioned control chip to minimize data loss.

What is disclosed in the present invention is one of the preferred embodiments. For example, all partial changes or modifications derived from the technical idea of the present invention and easily deduced by those skilled in the art do not depart from the scope of the patent right of the present invention.

To sum up, regardless of the purpose, means and efficacy of this case, it shows that it is very different from the conventional technology, and its first invention is practical, and it does meet the patent requirements of the invention. I implore your review committee to understand it clearly and grant a patent as soon as possible. Society is for the Most Prayer.

100: Data boundary detection circuit 110: Temporary storage unit 110a: shift register 110b: control circuit 120: Boundary detection unit 130: boundary address storage unit 140: address comparison unit 150: Address offset value storage unit 160: The first multiplexer 170: Second multiplexer 180: Adder 200: control chip 210: Signal conversion unit 220: Data boundary detection circuit 300: electronic device 310: control chip 320: functional unit

In order to further disclose the specific technical content of the present invention, first please refer to the drawings, wherein: FIG. 1 is a schematic diagram showing that synchronization information may be stored in the upper 7 characters or the lower 7 characters in the conventional parallel data transmission design using 14 characters. FIG. 2 shows a circuit diagram of an embodiment of a data boundary detection circuit including the present invention. FIG. 3 shows a block diagram of an embodiment of the control chip of the present invention. FIG. 4 shows a block diagram of an embodiment of the electronic device of the present invention.

100: Data boundary detection circuit

110: Temporary storage unit

110a: shift register

110b: control circuit

120: Boundary detection unit

130: boundary address storage unit

140: address comparison unit

150: Address offset value storage unit

160: The first multiplexer

170: Second multiplexer

180: Adder

Claims (14)

A data boundary detection circuit, which has: A temporary storage unit is used to store multiple input character byte data in a shifted manner, and it selects two consecutive input character byte data according to an output boundary address to provide an output data; and A boundary address generating unit is used to generate the output boundary address according to the sum of an updateable boundary address and an updateable address offset value, wherein the updateable boundary address is generated by a synchronous A boundary character of the data is updated by a boundary address that appears in the multiple input character byte data, and the updateable address offset value is one of a current value and a previous value of the boundary address The difference is updated. The data boundary detection circuit described in item 1 of the scope of the patent application, wherein the temporary storage unit has: a shift register for storing the plurality of input character byte data; and A control circuit is used for reading two consecutive pieces of input character byte data from the shift register according to the output boundary address to provide the output data. The data boundary detection circuit as described in item 2 of the scope of the patent application, wherein the boundary address generating unit has: A boundary detection unit, used for detecting the position of the boundary character of the synchronization data in a boundary range according to the storage content of the shift register, and updating the boundary character only when the boundary character is detected The content of the updatable boundary address. The data boundary detection circuit as described in item 3 of the scope of the patent application, wherein the boundary address generation unit further has: A boundary address storage unit stores the updateable boundary address. The data boundary detection circuit described in item 4 of the scope of the patent application, wherein the boundary address generation unit further has: An address offset value storage unit stores the updateable address offset value. The data boundary detection circuit as described in item 5 of the scope of the patent application, wherein the boundary address generation unit further has: a first multiplexer for selecting one of the current value and the previous value of the boundary address to generate the updateable boundary address; a second multiplexer for selecting one of a current value and a previous value of the difference to generate the updateable address offset value; and An adder is used for performing an addition operation on the updateable boundary address and the updateable address offset value to generate the output boundary address. A control chip, which has a signal conversion unit and a data boundary detection circuit, the signal conversion unit is used to generate input character byte data according to the transmission signals of a plurality of C-PHY channels and transmit it to the data boundary detection circuit, and the data boundary detection circuit has: A temporary storage unit is used to store multiple pieces of input character byte data in a shifted manner, and it selects two consecutive pieces of input character byte data according to an output boundary address to provide one piece of output data; as well as A boundary address generating unit is used to generate the output boundary address according to the sum of an updateable boundary address and an updateable address offset value, wherein the updateable boundary address is generated by a synchronous A boundary character of the data is updated by a boundary address that appears in the multiple input character byte data, and the updateable address offset value is one of a current value and a previous value of the boundary address The difference is updated. The control chip as described in item 7 of the scope of the patent application, wherein the temporary storage unit has: a shift register for storing the plurality of input character byte data; and A control circuit is used for reading two consecutive pieces of input character byte data from the shift register according to the output boundary address to provide the output data. The control chip as described in item 8 of the scope of the patent application, wherein the boundary address generating unit has: A boundary detection unit, used for detecting the position of the boundary character of the synchronization data in a boundary range according to the storage content of the shift register, and updating the boundary character only when the boundary character is detected The content of the updatable boundary address. The control chip as described in item 9 of the scope of the patent application, wherein the boundary address generating unit further has: A boundary address storage unit stores the updateable boundary address. The control chip as described in item 10 of the scope of the patent application, wherein the boundary address generation unit further has: An address offset value storage unit stores the updateable address offset value. The control chip as described in item 11 of the scope of the patent application, wherein the boundary address generation unit further has: a first multiplexer for selecting one of the current value and the previous value of the boundary address to generate the updateable boundary address; a second multiplexer for selecting one of a current value and a previous value of the difference to generate the updateable address offset value; and An adder is used for performing an addition operation on the updateable boundary address and the updateable address offset value to generate the output boundary address. An electronic device has a functional unit and the control chip as described in claim 7 of the scope of the patent application, and the functional unit includes an audio functional unit and/or a video functional unit. The electronic device described in item 13 of the scope of the patent application is an electronic device selected from a group consisting of a display, a portable computer and a smart handheld device.

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