JP2006065418A - Serial-parallel conversion circuit, serial transmission device, and serial-parallel conversion method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform appropriate reception by detecting the superimposing of noise by means of a simple arrangement without greatly increasing power consumption. <P>SOLUTION: A serial-parallel conversion circuit includes a shift register 2 that produces a parallel signal P by converting a serial data signal SD from serial to parallel form by means of a clock signal CK<SB>1</SB>synchronized therewith, and a counter 3 that, when a count value obtained by counting pulses of the clock signals CK<SB>1</SB>has reached a predetermined value, transmits a data transfer direction signal T to cause the shift register 2 to output the parallel signal P. If there has been no pulse of the clock signal CK<SB>1</SB>while the pulse of a second clock signal CK<SB>2</SB>having a frequency lower than the clock signal CK<SB>1</SB>has been inputted twice or more, the count value of a counter is reset. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a serial / parallel conversion circuit that can prevent malfunction due to noise superimposed on a clock signal, a serial transmission device using the same, and a serial / parallel conversion method.

  In recent years, a serial transmission method is frequently used for data transmission between devices or between electronic components. Data transmission by the serial transmission method has an advantage that the number of signal lines required is smaller than that of the parallel transmission method because data is transmitted serially bit by bit using one transmission line.

  FIG. 4 is a circuit diagram showing a configuration example of a serial / parallel (S / P) conversion circuit 101 provided in a conventional serial transmission type receiver. 5A is a timing chart showing an example of normal reception (when noise is not superimposed) in the serial / parallel conversion circuit 101 shown in FIG. 4, and FIG. 5B shows a clock signal. It is a timing chart which shows an example when noise is superimposed on CK. 5A and 5B show a case where the data length of the serial data signal SD is m bits (m is an integer).

  As shown in FIG. 4, the serial / parallel conversion circuit 101 includes a shift register 102 and a counter 103.

  The serial data signal SD and the clock signal CK are input to the shift register 102, and the serial data signal SD is converted into a parallel signal P having a predetermined number of bits (serial / parallel conversion) by the clock signal CK.

  The clock signal CK input to the shift register 102 is also input to the counter 103. The counter 103 counts the number of bits (number of pulses) of the input clock signal CK. When a predetermined number of bits (here m bits) are counted, the data transfer instruction signal T is transmitted to the shift register 102 and the count value is reset (see FIG. 5A).

  When the shift register 102 receives the data transfer instruction signal T from the counter 103, the shift register 102 outputs a parallel signal P having a predetermined number of bits generated by serial / parallel conversion.

  Thus, the serial / parallel conversion circuit 101 generates and outputs a parallel signal P based on the received serial data signal SD and the clock signal.

  However, as shown in FIG. 5B, for example, when noise is superimposed on the clock signal CK, the counter 103 may erroneously count the noise. Such noise is mainly caused by crosstalk generated between a wiring for transmitting a clock signal and another wiring adjacent thereto, or an influence of static electricity.

  If the counter 103 incorrectly counts noise, as shown in FIG. 5B, the timing at which the data transfer instruction signal T should be transmitted is shifted from the original timing by the amount of noise that has been erroneously counted. End up.

  For this reason, data different from the original data to be transmitted as the serial data SD is transmitted to the circuit that receives the parallel signal P output from the serial / parallel conversion circuit 101.

  Further, when such a malfunction occurs, the conventional serial / parallel conversion circuit 101 does not have means for restoring the count value to the original count value. For this reason, unless it is initialized by a hard reset or the like in order to return to the original count value, even if no noise is superimposed on the clock signal CK received thereafter, data different from the original data is always transmitted. There was a problem. In other words, in synchronous serial communication, there is a serial-parallel converter at the receiving end, and a counter is provided in the serial-parallel converter. If this counter malfunctions due to clock noise, a command or data with a specific bit length will be used thereafter. Even if is transmitted, the counter remains in a deviated state and cannot be restored.

  Therefore, various techniques for solving such problems have been developed. For example, Patent Document 1 discloses a technique in which serial data, a transfer clock signal, and a data valid signal indicating that serial data are valid are input to a serial / parallel conversion circuit, and serial data is captured while referring to the data valid signal. Are listed. In this technique, when the data valid signal is valid, the serial data is output as a parallel signal when a predetermined number of bits are accumulated. On the other hand, when the data valid signal is invalid, it is captured so far. It is supposed to discard serial data.

  Japanese Patent Application Laid-Open No. 2004-228561 describes a technique for detecting the noise by measuring the initial pulse width of the serial clock to predict the transfer end time and comparing it with the actual serial communication time.

  Further, Patent Document 3 discloses a shift register that stores serial data, a counter that outputs a signal for clearing serial data stored in the shift register after counting a predetermined number of serial clocks, and the counter starts counting. There is described a serial transmission / reception circuit having a timer that starts a timer operation, and this timer clears the counter after a lapse of a predetermined time from the start of the operation.

  Patent Document 4 discloses a shift register for storing serial data, a counter for counting the number of serial clocks, and a circuit for notifying other hardware whether or not the count number of the counter has reached a predetermined number. A circuit for enabling / disabling serial communication operation and an initialization signal generating circuit for generating a signal for initializing a counter after a time slightly longer than the serial clock width, triggered by a signal input to the serial data transfer clock signal line Is described.

Further, Patent Document 5 discloses a shift register that serial-parallel converts serial data using a clock synchronized with the serial data, a counter that counts the clock to detect a 1-byte break in the serial data, and detects the presence or absence of a clock. A serial transmission device including a mono multivibrator that allows a counter to detect only effective clocks is described. In this technique, the mono multivibrator counts the second clock signal earlier than the first clock signal corresponding to the serial data for the period when the first clock signal is “L”, and resets the counter after a certain time. . As a result, even if noise is added to the first clock signal, it is determined whether or not it is a valid clock, and one byte of serial data can always be correctly recognized.
JP 11-15636 A (published January 22, 1999) JP 2000-347950 A (released on December 15, 2000) JP 2001-77800 A (published March 23, 2001) JP-A-5-252222 (published September 28, 1993) Japanese Patent Laid-Open No. 3-5864 (published on January 11, 1991)

  However, the above-described conventional techniques have a problem that the configuration is complicated, the number of wirings is increased, and the power consumption is increased.

  For example, in the technique of Patent Document 1, it is necessary to provide a circuit for generating a data valid signal in a transmission-side device, and it is necessary to add wiring for transmitting a data signal.

  In the technique of Patent Document 2, means for generating a clock faster than the serial clock for measuring the pulse width of the serial clock, means for predicting the transfer end time, and the predicted transfer end time as the actual serial communication time. And means for generating a shift clock internally from the measured pulse width.

  In the techniques of Patent Documents 3 and 4, it is necessary to provide a high-performance timer that measures the time from the start of operation of the counter (trigger input).

  In the technique of Patent Document 5, it is necessary to provide means for generating a second clock signal that is faster than the first clock signal corresponding to serial data. A serial signal transmitted in recent serial transmission is often a high-frequency signal of, for example, several tens to hundreds of MHz. Therefore, in the technique of Patent Document 5, it is necessary to provide means for generating a signal having a higher frequency than such a high frequency signal, and the apparatus cost increases. Further, there is a problem that the means for generating such a high frequency signal consumes a large amount of power.

  The present invention has been made in view of the above problems, and an object of the present invention is to detect noise superposition and perform appropriate reception with a simple configuration and without significantly increasing power consumption. An object of the present invention is to provide a serial / parallel conversion circuit that can be used, a serial transmission device including the same, and a serial / parallel conversion method.

  In order to solve the above-described problem, the serial-parallel conversion circuit of the present invention converts the serial data signal into a serial signal by using a first clock signal synchronized with the serial data, and generates a parallel signal. A serial-parallel conversion circuit comprising: counting means for counting pulses of a clock signal and transmitting an instruction to cause the conversion means to output the parallel signal when the count value reaches a predetermined number; The counting means resets the count value when the pulse of the first clock signal is not inputted while the pulse of the second clock signal having a frequency lower than that of the one clock signal is inputted a predetermined number of times. It is a feature.

  Here, the instruction to output the parallel signal to the conversion circuit may be transmitted from the counting means to the conversion means, or a receiving circuit for receiving the parallel signal output from the conversion means The parallel signal may be output from the conversion means by causing the reception circuit to interrupt the parallel signal output from the conversion means.

  According to the above configuration, when the pulse of the first clock signal is not input while the pulse of the second clock signal having a frequency lower than that of the first clock signal is input a predetermined number of times, the counting means counts the count value. To reset. Thereby, the count value of the counting means can be reset when the input of the first clock signal is not longer than a certain period.

  Further, in the above configuration, when the pulse of the first clock signal is not input while the pulse of the second clock signal is input a predetermined number of times compared to the conventional configuration, It is only necessary to add a circuit for resetting the value.

  In the above configuration, since the second clock signal having a frequency lower than that of the first clock signal is used, the power consumption is less than that in the case of using a signal having a frequency higher than that of the first clock signal. Further, as the second clock signal, a clock signal that constantly exists in a device provided with the serial-parallel conversion circuit of the present invention may be used. In this case, since it is not necessary to add a means for generating the second clock signal, a simpler configuration can be achieved.

  Therefore, according to the above configuration, noise can be detected and appropriate reception can be performed with a simple configuration and without significantly increasing power consumption.

  In the serial-parallel conversion circuit of the present invention, when the first clock signal and the second clock signal are input and the pulse of the second clock signal is input, the output signal is switched to the second state, When a pulse of the first clock signal is input, first switching means for switching the signal to be output to the first state, the signal output from the first switching means, the first clock signal, and the second clock And when the pulse of the second clock signal is input during the period in which the signal output from the first switching means is in the second state, the signal to be output is switched to the second state, Second counting means for switching a signal to be output to the first state when a pulse of the first clock signal is input, and the counting means receives the signal output from the second switching means. And, when the signal the received is in the second state may be configured to reset the count value.

  According to the above configuration, when the first switching unit receives a pulse of the second clock signal having a frequency lower than that of the first clock signal, the output signal output to the second switching unit is set to the second state. To do. The second switching means outputs a second output signal to be output to the counting means when the second clock signal is inputted during the period in which the output signal of the inputted first switching means is in the second state. The counting means resets the count value when the output signal from the second switching means changes from the first state to the second state.

  Thus, in the above configuration, the count value is reset when the pulse of the first clock signal is not input while the pulse of the second clock signal having a frequency lower than that of the first clock signal is input twice. . Therefore, the count value of the counting means is reset when the input of the first clock signal is not longer than a certain period, and it is assumed that the count value has shifted due to noise superimposed on the first clock signal. Also, the count value can be returned to the normal state.

  In addition, the configuration described above is simply by adding the first switching unit and the second switching unit to the conventional configuration and inputting a second clock signal having a frequency lower than that of the first clock signal to both switching units. Good.

  In the above configuration, since the second clock signal having a frequency lower than that of the first clock signal is used, the power consumption is less than that in the case of using a signal having a frequency higher than that of the first clock signal.

  Therefore, according to the above configuration, noise can be detected and appropriate reception can be performed with a simple configuration and without significantly increasing power consumption.

  The serial-parallel conversion circuit of the present invention includes a data input terminal, a clock terminal to which the second clock signal is input, a reset terminal to which the first clock signal is input, and an output terminal, and the data When the pulse of the second clock signal is input to the clock terminal while the input signal of the input terminal is in the second state, the output from the output terminal is switched to the second state, and the second terminal is connected to the reset terminal. A plurality of switching means for switching the output from the output terminal to the first state when a pulse of one clock signal is input is provided, and the data input terminal of the first-stage switching means has a second state signal. Is input to the data input terminal of the switching means in the second and subsequent stages, and the output terminal of the switching means in the previous stage is input to the output terminal of the switching means in the last stage. The counting means receives the signal output from the switching means at the final stage, and resets the count value when the received signal changes from the first state to the second state. It is good also as a structure.

  According to the above configuration, when the first switching unit receives a pulse of the second clock signal having a frequency lower than that of the first clock signal, the output signal output to the next switching unit is set to the second state. To do. When the second clock signal is input during the period when the output signal of the input first switching means is in the second state, the switching means after the second stage switches the output signal to the second state. . The final stage switching means receives the second output signal output to the counting means when the second clock signal is inputted during the period when the input output signal of the first switching means is in the second state. Switch to state. The counting means resets the count value when the output signal from the last-stage switching means changes from the first state to the second state.

  Thus, in the above configuration, the count value is reset when the pulse of the first clock signal is not input while the pulse of the second clock signal having a frequency lower than that of the first clock signal is input a predetermined number of times. To do. That is, the count value of the counting means is reset when the input of the first clock signal is not longer than a certain period, and it is assumed that the count value has shifted due to noise superimposed on the first clock signal. Also, the count value can be returned to the normal state.

  In addition, the above-described configuration is only required to add the plurality of stages of switching means to the conventional configuration and input a second clock signal having a frequency lower than that of the first clock signal to each switching means.

  In the above configuration, since the second clock signal having a frequency lower than that of the first clock signal is used, the power consumption is less than that in the case of using a signal having a frequency higher than that of the first clock signal.

  Therefore, according to the above configuration, noise can be detected and appropriate reception can be performed with a simple configuration and without significantly increasing power consumption.

  The frequency of the second clock signal may be less than or equal to ½ times the frequency of the first clock signal.

  According to said structure, it can prevent reliably resetting a count value accidentally in the middle of receiving the pulse of a 1st clock signal.

  In order to solve the above problems, the serial transmission device of the present invention includes any one of the serial-parallel conversion circuits described above. Therefore, according to the above configuration, noise can be detected and appropriate reception can be performed with a simple configuration and without significantly increasing power consumption.

  The serial-parallel conversion method of the present invention generates a parallel signal by serial-parallel conversion of a serial data signal using a first clock signal synchronized with the serial data, and a count value obtained by counting pulses of the first clock signal is a predetermined value. In the serial-parallel conversion method of outputting the parallel signal when the number reaches a predetermined number, the first clock is output while a pulse of the second clock signal having a frequency lower than that of the first clock signal is input a predetermined number of times. When the pulse of the signal is not input, the count value is reset.

  According to the above method, the count value is reset when the pulse of the first clock signal is not input while the pulse of the second clock signal having a frequency lower than that of the first clock signal is input a predetermined number of times. To do. Thereby, the count value of the counting means can be reset when the input of the first clock signal is not longer than a certain period. In addition, the above-described method can be applied to the configuration of the conventional serial-parallel conversion circuit when the pulse of the first clock signal is not input while the pulse of the second clock signal is input a predetermined number of times. This can be realized simply by adding a circuit for resetting the count value. In this case, since the second clock signal having a frequency lower than that of the first clock signal is used, power consumption can be reduced as compared with the case of using a signal having a frequency higher than that of the first clock signal. Therefore, according to the above method, it is possible to detect noise superposition and perform appropriate reception with a simple configuration and without significantly increasing power consumption.

  As described above, in the serial-parallel conversion circuit of the present invention, the pulse of the first clock signal is not input while the pulse of the second clock signal having a frequency lower than that of the first clock signal is input a predetermined number of times. In the case where the count value is detected, the count means resets the count value.

  The serial transmission device of the present invention includes any one of the serial-parallel conversion circuits described above.

  In the serial-parallel conversion method of the present invention, the pulse of the first clock signal is not input while the pulse of the second clock signal having a frequency lower than that of the first clock signal is input a predetermined number of times. The count value is reset.

  Therefore, according to the serial-parallel conversion, the serial transmission device, and the serial-parallel conversion method of the present invention, noise superposition is detected with a simple configuration and without significantly increasing power consumption. Reception can be performed.

  An embodiment of the present invention will be described. FIG. 1 is a circuit diagram showing a configuration of a serial / parallel conversion circuit (S / P conversion circuit) 1 according to the present embodiment. The serial-parallel conversion circuit 1 is provided in a serial transmission device that transmits commands and data using a serial transmission method.

  As shown in this figure, the serial-parallel conversion circuit 1 includes a shift register 2, a counter 3, a flip-flop 4, and a flip-flop 5.

Serial data SD and a clock signal (first clock signal, serial clock signal) CK ₁ are input to the shift register 2, and the serial data signal SD is converted into a parallel signal P having a predetermined number of bits by the clock signal CK ₁ ( (Serial / parallel conversion). Further, when receiving the data transfer instruction signal T from the counter 3, the shift register 2 outputs a parallel signal P having a predetermined number of bits generated by serial / parallel conversion.

The counter 3, the same clock signal CK ₁ and the clock signal CK ₁ is input to the shift register 2 are input. Counter 3 counts the number of bits is the input clock signal CK _1. When the predetermined number of bits is counted, a data transfer instruction signal T is transmitted to the shift register 2 and the count value is reset. The counter 3, even when the change in the output signal _{Q 2} of flip-flop 5 "L (Low)" (first state) to "H (High)" (second state), resets the count value .

A second clock signal (second clock signal) CK ₂ different from the clock signal CK ₁ input to the shift register 2 is input to the clock terminal CLK of the flip-flop 4. Note that the clock signal CK ₂ of the second is slower than the clock signal CK ₁ (low frequency or pulse width is long) is the signal. In the serial-parallel conversion circuit 1 according to the present embodiment, the frequency of the clock signal CK ₁ is about 20 MHz to about 150 MHz, and the frequency of the _second clock signal CK ₂ is several MHz. Here, the frequency of the second clock signal CK ₂ only needs to be lower than that of the clock signal CK ₁ and is not particularly limited, but is preferably ½ times or less than the clock signal CK ₁ . . By the second frequency of the clock signal CK ₂ than half the clock signal CK _1, during the reception of the pulse clock signal CK _1, reliably prevent would resets the count value by mistake it can.

Further, as the second clock signal CK ₂ , for example, a clock signal used for a purpose other than serial / parallel conversion in a serial transmission device provided with the serial / parallel conversion circuit 1, and a clock signal that exists constantly is used. May be. For example, a clock signal used in another control circuit (not shown) provided in the serial transmission device (reception device) together with the serial-parallel conversion circuit 1 may be used. In this case, since the clock signal used for other purposes is used in combination, the configuration of the serial transmission device can be further simplified without newly adding means for generating the _second clock signal CK2.

Further, the clock signal CK ₁ is input to the reset terminal CLR of the flip-flop 4, and the signal “H” is always input to the data input terminal D.

Then, the flip-flop 4, the output signal Q ₁ outputted from the output terminal Q when the second rise of the clock signal CK _2, switching from "L" to "H". The flip-flop 4, and resets the output signal Q ₁ at the time of the fall of the clock signal CK ₁ inputted to the reset terminal CLR, returned from "H" to "L".

The flip-flop 5 has the same configuration as the flip-flop 5. However, the data input terminal D is input the output signal Q ₁ outputted from the output terminal Q of the flip-flop 4, to the clock terminal CLK is input a second clock signal CK ₂ is a clock signal to the reset terminal CLR CK ₁ is input. The output terminal Q is connected to the counter 3, and the output signal Q ₂ from the output terminal Q is output to the counter 3.

Then, when the output signal Q ₁ of the input flip-flop 4 is “H”, the flip-flop 5 changes from the output terminal Q to the counter 3 when the _second clock signal CK ₂ input to the clock terminal CLK rises. switches the output signal Q ₂ to which output from "L" to "H". The flip-flop 5, resets the output signal Q ₂ at the falling edge of the clock signal CK ₁ inputted to the reset terminal CLR, returned from "H" to "L".

2, the serial-parallel conversion circuit 1, which is a timing chart showing an example of a case where the noise on the clock signal CK ₁ is superposed. Such noise is caused mainly the wiring for transmitting the impact and the clock signal CK ₁ of static electricity, such as by crosstalk caused between the another wiring adjacent thereto.

As shown in this figure, a serial data signal SD and a clock signal CK ₁ corresponding to the serial data signal SD are input to the serial / parallel conversion circuit 1, and the counter 3 counts one by one when the clock signal CK ₁ falls. Increase it. When the count value counts a predetermined number of bits (here, m bits), the counter 3 transmits the data transfer instruction signal T to the shift register 2 and resets the count value. FIG. 2 shows a case where the data length of the serial data signal SD is m bits (m is an integer).

  When receiving the data transfer instruction signal T from the counter 103, the shift register 102 outputs a parallel signal P having a predetermined number of bits generated by serial / parallel conversion.

Further, as described above, the second clock signal CK ₂ is input to the serial-parallel conversion circuit 1 in addition to the clock signal CK ₁ . Flip-flop 4, at the rising edge of the second clock signal CK _2, it switches the output signal Q ₁ to be output to the flip-flop 5 to "H". The flip-flop 4 returns the output signal Q ₁ to “L” when the clock signal CK ₁ falls during the period in which the output signal Q ₁ is “H”.

The flip-flop 5 sets the output signal Q ₂ output to the counter 3 to “H” when the second clock signal CK ₂ rises while the output signal Q ₁ of the flip-flop 4 is “H”. Switch. The flip-flop 5 sets the output signal Q ₂ to “L” when the clock signal CK ₁ falls.

Counter 3, when the output signal Q ₂ of the flip-flop 5 changes from "L" to "H", and resets the count value. Thus, for example, the serial-parallel conversion circuit 1, even when noise is superimposed on the clock signal CK _1, as shown in FIG. 2, the count value of the counter 3, the count value of the normal corresponding to the original clock signal CK ₁ Can be restored.

As described above, when the pulse of the second clock signal CK ₂ that is slower (lower in frequency) than the clock signal CK ₁ is input, the flip-flop 4 outputs the output signal Q ₁ output to the flip-flop 5 to “H”. " When the second clock signal CK ₂ is input while the output signal Q ₁ of the input flip-flop 4 is “H”, the flip-flop 5 outputs the output signal Q ₂ output to the counter 3. to "H", the counter 3 in the case of changes to "H" output signal Q ₂ from the flip-flop 5 changes from "L" and resets the count value. That is, the serial-parallel conversion circuit 1 counts when the pulse of the clock signal CK ₁ is not input while the pulse of the second clock signal CK _{2 having} a frequency lower than that of the clock signal CK ₁ is input twice. Reset the value.

As a result, the serial / parallel conversion circuit 1 resets the count value of the counter 3 when the input of the clock signal CK ₁ is not longer than a certain period, and counts by superimposing noise on the clock signal CK _1. Even if the value is shifted, the count value can be returned to the normal state.

The second clock signal CK ₂ is preferably frequency is less than 1/2 times the clock signal CK _1. By the second frequency of the clock signal CK ₂ or less half of the clock signal CK _1, the middle of receiving the normal pulse of the clock signal CK _1, thereby resetting the count value by mistake Can be prevented.

  In the present embodiment, the configuration including the two-stage flip-flops (flip-flops 4 and 5) has been described. However, the present invention is not limited to this, and a configuration including three or more stages of flip-flops may be used.

FIG. 3 is a circuit diagram showing a configuration example of the serial-parallel conversion circuit 1 including a three-stage flip-flop. In the configuration of FIG. 3, and further provided with a flip-flop 6 to the subsequent flip-flop 5 in the configuration of FIG. 1, the output signal Q ₂ from the output terminal Q of the flip-flop 5 receives the data input terminal D of the flip-flop 6 Has been entered. 3, members having the same configuration and function as those in FIG. 1 and performing the same operations are denoted by the same reference numerals as those in FIG.

Further, the second clock signal CK ₂ is input to the clock terminal CLK of the flip-flop 6, and the clock signal CK ₁ is input to the reset terminal CLR. The output from the output terminal Q of the flip-flop 6 is input to the counter 3.

When the pulse of the second clock signal CK ₂ is input while the output signal Q ₂ from the flip-flop 5 is “H”, the flip-flop 6 outputs the output signal Q ₃ from the output terminal Q to the counter 3. Set to “H”. The counter 3 resets the counter value when the output signal Q ₃ from the flip-flop 6 changes from “L” to “H”.

The clock signal CK ₁ is input to the reset terminal CLR of the flip-flop 6. When the pulse of the clock signal CK ₁ is input, the flip-flop 6 switches the output signal Q ₃ to “L”.

  Also in the serial / parallel conversion circuit 1 having such a configuration, substantially the same effect as the configuration of FIG. 1 can be obtained. Further, the number of flip-flops may be further increased without being limited to three. In this case, a flip-flop to be added may be connected between the flip-flop 5 and the flip-flop 6 in FIG.

Incidentally, the number of stages of flip-flops to be connected may be determined according to the clock signal CK ₁ and the second frequency of the clock signal CK _2. In other words, by determining the number of stages of flip-flops in response to the clock signal CK ₁ and the second frequency of the clock signal CK _2, the timing of resetting the count value of the counter 3 so as to optimize, the clock signal CK ₁ You may set the period which detects that there is no input.

In the description of FIG. 2, the serial data signal SD and the clock signal CK ₁ receives the serial-parallel conversion circuit, the description has been given of the case where m bit data length of the serial data signal SD and the clock signal CK ₁ is particularly It is not limited. For example, when the data to be transmitted is character data to be displayed on a display means provided in a mobile phone or the like, information of one pixel is 20 bits, and information of several pixels (n pixels (n is an integer)) is one data length. You may make it transmit by. In this case, data having a data length of m = 20 × n (bits) is transmitted. Further, when transmitting 22 bits of information for one pixel with one data length for several pixels, data having a data length of m = 22 × n (bits) is transmitted. For example, when transmitting information of 28 bits per pixel captured by a camera in a mobile phone with a camera with one data length for several pixels, data having a data length of m = 28 × n (bits) is transmitted. Become.

Further, the serial data signal SD and the clock signal CK ₁ received by the serial / parallel conversion circuit 1 may be differential signals or may not be differential signals.

  In the serial-parallel conversion circuit 1, the shift register 2 outputs the generated parallel signal P when receiving the data transfer instruction signal T from the counter 3. However, the present invention is not limited to this. For example, the counter 3 outputs a data transmission instruction signal (interrupt generation signal) T to a reception circuit (for example, a CPU (not shown)) that receives the parallel signal P from the shift register 2 to generate an interrupt. The receiving circuit may receive the parallel signal P output from the shift register 2 (the shift register 2 outputs the parallel signal P). In other words, the data transfer instruction signal T that causes the shift register 2 to output the parallel signal P may be transmitted from the counter 3 to the shift register 2, and is supplied to the receiving circuit that receives the parallel signal P from the shift register 2. It may be transmitted.

In the present embodiment, when the pulse of the second clock signal CK ₂ is input to the clock terminal of the flip-flop 5 while the output signal Q ₁ of the flip-flop 4 is “H”, the flip-flop 5 is set to "H" output signal Q ₂ is, when the output signal Q ₂ of the flip-flop 5 is "H", although the count value of the counter 3 is assumed to be reset, but not limited thereto. The operation in the case of “H” and the operation in the case of “L” in each part in the serial-parallel conversion circuit 1 may be reversed. For example, when the pulse of the second clock signal CK ₂ is input to the clock terminal of the flip-flop 5 while the output signal Q ₁ of the flip-flop 4 is “L” (second state), the flip-flop 5 of the output signal Q ₂ is set to "L" (second state), when the output signal Q ₂ of the flip-flop 5 is "L" (second state), even assuming that the count value of the counter 3 is reset Good.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. That is, embodiments obtained by combining technical means appropriately changed within the scope of the claims are also included in the technical scope of the present invention.

  The serial-parallel conversion circuit of the present invention can be applied to a serial transmission device that performs transmission using a serial transmission method. In addition, data transmission between electronic components is performed by a serial transmission method. Communication devices such as mobile phones, PHS (registered trademark), PDAs, display devices such as televisions, information processing devices such as personal computers and word processors, digital cameras, digital videos Recording devices such as cameras, recording devices such as magnetic tapes, magnetic disks, optical disks (magneto-optical disks), memory cards, mask ROMs, EPROMs, EEPROMs, flash ROMs, and other semiconductor memories, speakers and headphones It can be applied to various electronic devices such as acoustic devices. In particular, in a device having a small device size such as a portable information terminal, noise is generally likely to occur. However, according to the present invention, it is preferable because malfunction due to noise can be prevented with a simple configuration.

It is a circuit diagram which shows the structural example of the serial-parallel conversion circuit concerning one Embodiment of this invention. It is a timing chart of the serial-parallel conversion circuit concerning one Embodiment of this invention. It is a circuit diagram which shows the other structural example of the serial-parallel conversion circuit concerning one Embodiment of this invention. It is a circuit diagram which shows the structural example of the conventional serial-parallel conversion circuit. (A) is a timing chart at the time of normal reception in the conventional serial-parallel conversion circuit shown in FIG. 4, and (b) is a noise superimposed on the clock signal in the conventional serial-parallel conversion circuit shown in FIG. It is a timing chart in the case of doing.

Explanation of symbols

1 Serial-parallel conversion circuit 2 Shift register (conversion means)
3 Counter (counting means)
4 Flip-flop (first switching means, first stage switching means)
5 Flip-flop (second switching means, second stage switching means)
6 Flip-flop (last stage switching means)
SD Serial data signal CK ₁ clock signal (first clock signal)
CK ₂ second clock signal (second clock signal)
Q ₁ output signal of flip-flop 4 Q ₂ output signal of flip-flop 5 Q ₃ output signal of flip-flop 6 T data transfer instruction signal

Claims (6)

Conversion means for serial-parallel conversion of a serial data signal using a first clock signal synchronized with the serial data to generate a parallel signal, and counting the pulses of the first clock signal, and the count value reaches a predetermined number And a serial-parallel conversion circuit comprising counting means for transmitting an instruction to cause the conversion means to output the parallel signal,
If the pulse of the first clock signal is not input while the pulse of the second clock signal having a frequency lower than that of the first clock signal is input a predetermined number of times, the counting means resets the count value. A serial-parallel conversion circuit characterized by that. When the first clock signal and the second clock signal are input and the pulse of the second clock signal is input, the output signal is switched to the second state, and the pulse of the first clock signal is input A first switching means for switching the signal to be output to the first state,
During the period in which the signal output from the first switching means, the first clock signal, and the second clock signal are input and the signal output from the first switching means is in the second state, A second switching means for switching the output signal to the second state when a clock signal pulse is input, and for switching the output signal to the first state when the first clock signal pulse is input; Prepared,
The counting means receives a signal output from the second switching means, and resets the count value when the received signal changes from the first state to the second state. Serial-parallel conversion circuit described in 1. A data input terminal; a clock terminal to which the second clock signal is input; a reset terminal to which the first clock signal is input; and an output terminal; a period in which the input signal of the data input terminal is in a second state When the pulse of the second clock signal is input to the clock terminal, the output from the output terminal is switched to the second state, and the pulse of the first clock signal is input to the reset terminal. A plurality of switching means for switching the output from the output terminal to the first state;
The signal of the second state is input to the data input terminal of the first stage switching means,
A signal output from the output terminal of the previous stage switching means is input to the data input terminal of the switching means in the second stage and thereafter,
The counter is connected to the output terminal of the switching means at the final stage,
The counting means receives a signal output from the last-stage switching means, and resets the count value when the received signal changes from the first state to the second state. 2. The serial-parallel conversion circuit according to 1.   4. The serial-parallel conversion circuit according to claim 1, wherein the frequency of the second clock signal is equal to or less than ½ times the frequency of the first clock signal. 5.   The serial transmission apparatus provided with the serial parallel conversion circuit of any one of Claims 1-4. The parallel data is generated by serial-parallel conversion of the serial data signal with the first clock signal synchronized with the serial data. When the count value obtained by counting the pulses of the first clock signal reaches a predetermined number, the parallel data is generated. A serial-parallel conversion method for outputting a signal,
While the pulse of the second clock signal having a frequency lower than that of the first clock signal is input a predetermined number of times, the count value is reset when the pulse of the first clock signal is not input. To serial-parallel conversion method.

Images