TW202238402A - Connection interface conversion chip, connection interface conversion device and operation method - Google Patents

Connection interface conversion chip, connection interface conversion device and operation method Download PDF

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TW202238402A
TW202238402A TW111119619A TW111119619A TW202238402A TW 202238402 A TW202238402 A TW 202238402A TW 111119619 A TW111119619 A TW 111119619A TW 111119619 A TW111119619 A TW 111119619A TW 202238402 A TW202238402 A TW 202238402A
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pair
usb
equalizer
connector
circuit
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TWI806629B (en
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林正忠
林小琪
林宜興
陳建盛
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威鋒電子股份有限公司
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A connection interface conversion chip, a connection interface conversion device and an operation method are provided. The connection interface conversion chip includes a USB interface circuit, a DP interface circuit, a USB core circuit, and a switching circuit. The USB interface circuit is suitable for coupling to a USB connector. The DP interface circuit is coupled to a DP sink device through a DP connector. The USB core circuit is coupled to both the USB interface circuit and the DP interface circuit. The switching circuit is coupled to both the USB interface circuit and the DP interface circuit. The switching circuit supports only one specific conduction mode that only allows transmitting DP signals between the USB interface circuit and the DP interface circuit.

Description

連接介面轉換晶片、連接介面轉換裝置與操作方法Connection interface conversion chip, connection interface conversion device and operation method

本發明是有關於一種電子電路，且特別是有關於一種連接介面轉換晶片、連接介面轉換裝置與操作方法。The present invention relates to an electronic circuit, and in particular relates to a connection interface conversion chip, a connection interface conversion device and an operation method.

主機與裝置會使用相同傳輸介面來彼此進行資料傳輸。當主機所使用的傳輸介面不同於裝置所使用的傳輸介面時，主機與裝置之間需要配置連接介面轉換裝置，或是將連接介面轉換晶片配置在裝置中。舉例而言，假設主機的傳輸介面是通用序列匯流排（Universal Serial Bus，以下稱USB），而裝置所使用的傳輸介面是顯示埠（DisplayPort，以下稱DP）。連接介面轉換裝置（連接介面轉換晶片）可以提供介面轉換功能，以便將主機的USB Type-C連接器（又可稱為USB-C連接器）的資料傳輸給DP裝置的DP連接器，以及（或是）將DP裝置的DP連接器的資料傳輸給主機的USB-C連接器。The host and the device will use the same transmission interface to transmit data to each other. When the transmission interface used by the host is different from the transmission interface used by the device, a connection interface conversion device needs to be configured between the host and the device, or a connection interface conversion chip is configured in the device. For example, assume that the transmission interface of the host is Universal Serial Bus (hereinafter referred to as USB), and the transmission interface used by the device is DisplayPort (hereinafter referred to as DP). Connecting the interface conversion device (connecting the interface conversion chip) can provide the interface conversion function, so that the data of the USB Type-C connector (also known as the USB-C connector) of the host computer can be transmitted to the DP connector of the DP device, and ( Or) transmit the data of the DP connector of the DP device to the USB-C connector of the host.

連接介面轉換裝置的USB-C連接器連接至主機的USB-C連接器。USB-C連接器的第一面具有第一發送腳（transmitting pin，TX pin）對與第一接收腳（receiving pin，RX pin）對，而USB-C連接器的第二面具有第二發送腳對與第二接收腳對。在主機的USB-C連接器操作於USB 3.2規格的情況下，當USB-C插頭正面朝上插入USB-C連接器時，第一發送腳對與第一接收腳對可以被用來作為USB 3.2的通訊通道，而第二發送腳對與第二接收腳對則被閒置。反之，當USB-C插頭反面朝上插入USB-C連接器時，第一發送腳對與第一接收腳對被閒置，而第二發送腳對與第二接收腳對則可以被用來作為USB 3.2的通訊通道。Connect the USB-C connector of the interface conversion device to the USB-C connector of the host. The first side of the USB-C connector has a first pair of transmitting pins (TX pin) and a first pair of receiving pins (RX pin), while the second side of the USB-C connector has a second pair of transmitting pin pair and the second receiving pin pair. In the case that the USB-C connector of the host computer operates in the USB 3.2 specification, when the USB-C plug is inserted into the USB-C connector with the front facing up, the first pair of sending pins and the first pair of receiving pins can be used as USB 3.2 communication channels, while the second pair of sending pins and the second pair of receiving pins are idle. Conversely, when the USB-C plug is inserted into the USB-C connector with the reverse side up, the first pair of sending pins and the first pair of receiving pins are idle, while the second pair of sending pins and the second pair of receiving pins can be used as Communication channel for USB 3.2.

主機可操作於符合USB規格（例如USB 3.2規格）的顯示埠替代模式（DP ALT Mode，以下稱ALT模式）。當主機操作於ALT模式時，在主機的USB-C連接器中被閒置的發送腳對與接收腳對可以被用來傳輸符合DP規格的資料，以及在主機的USB-C連接器中的邊帶使用（Side Band Use，以下稱SBU）接腳可以被用來傳輸符合DP規格的輔助通道（AUX channel，以下稱AUX通道）訊號。The host computer can operate in a DisplayPort Alternative Mode (DP ALT Mode, hereinafter referred to as ALT Mode) conforming to USB specifications (such as USB 3.2 specifications). When the host is operating in ALT mode, the unused sending pin pair and receiving pin pair in the host's USB-C connector can be used to transmit data that conforms to the DP specification, and the edge in the host's USB-C connector The Side Band Use (hereinafter referred to as SBU) pin can be used to transmit the auxiliary channel (AUX channel, hereinafter referred to as AUX channel) signal conforming to the DP specification.

在主機的USB-C連接器操作於USB 4.0規格的情況下，USB-C連接器的第一面的第一發送腳對與第一接收腳對以及USB-C連接器的第二面的第二發送腳對與第二接收腳對都可以被用來作為USB 4.0的通訊通道。當主機的USB-C連接器傳輸符合USB 4.0規格的訊號時，主機的USB-C連接器的SBU接腳被用來傳輸符合USB規格的邊帶（Side Band）訊號。當主機的USB-C連接器操作於USB 4.0規格時，主機可以使用符合USB 4.0規格的顯示埠穿隧（DP Tunneling）協定而將符合DP規格的DP資料與AUX通道訊號編碼在USB 4.0訊號串流中。In the case where the USB-C connector of the host computer operates in the USB 4.0 specification, the first pair of sending pins and the first pair of receiving pins on the first side of the USB-C connector and the first pair of pins on the second side of the USB-C connector Both the two sending pin pairs and the second receiving pin pair can be used as communication channels of USB 4.0. When the host's USB-C connector transmits signals conforming to the USB 4.0 specification, the SBU pin of the host's USB-C connector is used to transmit sideband (Side Band) signals conforming to the USB specification. When the USB-C connector of the host is operating in the USB 4.0 specification, the host can use the DisplayPort Tunneling (DP Tunneling) protocol that complies with the USB 4.0 specification to encode the DP data and AUX channel signals that conform to the DP specification into the USB 4.0 signal string in flow.

連接介面轉換裝置的DP連接器連接至DP裝置的DP連接器。不論主機的USB-C連接器是操作於所述ALT模式或是操作於USB 4.0，連接介面轉換裝置（連接介面轉換晶片）皆須有能力處理主機的USB-C連接器的訊號，以便將來自於主機的DP資料傳輸給DP裝置。The DP connector connected to the interface conversion device is connected to the DP connector of the DP device. Regardless of whether the host’s USB-C connector is operating in the ALT mode or USB 4.0, the connection interface conversion device (connection interface conversion chip) must be able to process the signal from the host’s USB-C connector in order to transfer from The DP data from the host is transmitted to the DP device.

須注意的是，「先前技術」段落的內容是用來幫助了解本發明。在「先前技術」段落所揭露的部份內容（或全部內容）可能不是所屬技術領域中具有通常知識者所知道的習知技術。在「先前技術」段落所揭露的內容，不代表該內容在本發明申請前已被所屬技術領域中具有通常知識者所知悉。It should be noted that the content of the "Prior Art" paragraph is used to help understand the present invention. Some (or all) of the content disclosed in the "Prior Art" paragraph may not be known to those with ordinary skill in the art. The content disclosed in the "Prior Art" paragraph does not mean that the content has been known to those with ordinary knowledge in the technical field before the application of the present application.

本發明提供一種連接介面轉換晶片、連接介面轉換裝置與操作方法，其可以處理通用序列匯流排（Universal Serial Bus，以下稱USB）連接器的訊號，而不論USB連接器的訊號是符合USB規格（例如USB 3.2規格）的顯示埠（DisplayPort，以下稱DP）替代模式（ALT Mode，以下稱ALT模式）的訊號或是符合USB 4.0的顯示埠穿隧（DP Tunneling）協定的訊號。The present invention provides a connection interface conversion chip, a connection interface conversion device and an operation method, which can process the signal of a Universal Serial Bus (hereinafter referred to as USB) connector, regardless of whether the signal of the USB connector conforms to the USB specification ( For example, the display port (DisplayPort, hereinafter referred to as DP) alternative mode (ALT Mode, hereinafter referred to as ALT mode) signal of the USB 3.2 specification or the signal conforming to the display port tunneling (DP Tunneling) protocol of USB 4.0.

在本發明的一實施例中，上述的連接介面轉換晶片包括USB介面電路、DP介面電路、USB核心電路以及切換電路。USB介面電路適於耦接至USB連接器。DP介面電路經由DP連接器耦接至DP槽裝置。USB核心電路耦接至USB介面電路與DP介面電路。切換電路耦接至USB介面電路與DP介面電路。切換電路只支援一種特定導通模式，且這種特定導通模式僅允許在USB介面電路與DP介面電路之間傳輸DP訊號。In an embodiment of the present invention, the above connection interface conversion chip includes a USB interface circuit, a DP interface circuit, a USB core circuit and a switching circuit. The USB interface circuit is suitable for being coupled to the USB connector. The DP interface circuit is coupled to the DP slot device through the DP connector. The USB core circuit is coupled to the USB interface circuit and the DP interface circuit. The switching circuit is coupled to the USB interface circuit and the DP interface circuit. The switching circuit only supports one specific conduction mode, and this specific conduction mode only allows the DP signal to be transmitted between the USB interface circuit and the DP interface circuit.

在本發明的一實施例中，上述的連接介面轉換裝置包括USB連接器、DP連接器以及連接介面轉換晶片。連接介面轉換晶片包括USB介面電路、DP介面電路、USB核心電路以及切換電路。USB介面電路適於耦接至USB連接器。DP介面電路經由DP連接器耦接至DP槽裝置。USB核心電路耦接至USB介面電路與DP介面電路。切換電路耦接至USB介面電路與DP介面電路。切換電路只支援一種特定導通模式，且這種特定導通模式僅允許在USB介面電路與DP介面電路之間傳輸DP訊號。In an embodiment of the present invention, the above connection interface conversion device includes a USB connector, a DP connector and a connection interface conversion chip. The connection interface conversion chip includes a USB interface circuit, a DP interface circuit, a USB core circuit and a switching circuit. The USB interface circuit is suitable for being coupled to the USB connector. The DP interface circuit is coupled to the DP slot device through the DP connector. The USB core circuit is coupled to the USB interface circuit and the DP interface circuit. The switching circuit is coupled to the USB interface circuit and the DP interface circuit. The switching circuit only supports one specific conduction mode, and this specific conduction mode only allows the DP signal to be transmitted between the USB interface circuit and the DP interface circuit.

在本發明的一實施例中，上述的操作方法包括：在第一操作模式中，禁能該切換電路；以及在第二操作模式中，切換電路只支援一特定導通模式，且這種特定導通模式僅允許在USB介面電路與DP介面電路之間傳輸DP訊號。In an embodiment of the present invention, the above operation method includes: in the first operation mode, disabling the switching circuit; and in the second operation mode, the switching circuit only supports a specific conduction mode, and the specific conduction mode Mode only allows the transmission of DP signals between the USB interface circuit and the DP interface circuit.

基於上述，本發明諸實施例將切換電路配置在連接介面轉換晶片中。當USB連接器的訊號是符合USB規格的ALT模式的訊號時，切換電路可以經過USB介面電路接收USB連接器的DP資料，以及（或是）USB核心電路可以經過USB介面電路接收USB連接器的USB訊號。然後，切換電路可以將DP資料經過DP介面電路傳輸至DP連接器。當USB連接器的訊號是符合USB 4.0規格的顯示埠穿隧協定的USB訊號時，USB核心電路可以經過USB介面電路接收USB連接器的USB訊號並且對所述USB訊號進行解碼以獲得DP資料，然後USB核心電路可以將DP資料經過DP介面電路傳輸至DP連接器。亦即，切換電路不需要處理高頻寬的USB 4.0訊號，因此切換電路的成本可以盡可能的降低。連接介面轉換晶片（連接介面轉換裝置）可以處理USB連接器的訊號，而不論USB連接器的訊號是ALT模式的訊號或是符合USB 4.0的顯示埠穿隧協定的訊號。Based on the above, various embodiments of the present invention configure the switching circuit in the connection interface conversion chip. When the signal of the USB connector is an ALT mode signal conforming to the USB specification, the switching circuit can receive the DP data of the USB connector through the USB interface circuit, and (or) the USB core circuit can receive the USB connector through the USB interface circuit. USB signal. Then, the switching circuit can transmit the DP data to the DP connector through the DP interface circuit. When the signal of the USB connector is a USB signal conforming to the display port tunneling protocol of the USB 4.0 specification, the USB core circuit can receive the USB signal of the USB connector through the USB interface circuit and decode the USB signal to obtain DP data, Then the USB core circuit can transmit the DP data to the DP connector through the DP interface circuit. That is, the switching circuit does not need to process high-bandwidth USB 4.0 signals, so the cost of the switching circuit can be reduced as much as possible. The connection interface conversion chip (connection interface conversion device) can process the signal of the USB connector, regardless of whether the signal of the USB connector is an ALT mode signal or a display port tunneling protocol compliant signal of USB 4.0.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

在本案說明書全文（包括申請專利範圍）中所使用的「耦接（或連接）」一詞可指任何直接或間接的連接手段。舉例而言，若文中描述第一裝置耦接（或連接）於第二裝置，則應該被解釋成該第一裝置可以直接連接於該第二裝置，或者該第一裝置可以透過其他裝置或某種連接手段而間接地連接至該第二裝置。本案說明書全文（包括申請專利範圍）中提及的「第一」、「第二」等用語是用以命名元件（element）的名稱，或區別不同實施例或範圍，而並非用來限制元件數量的上限或下限，亦非用來限制元件的次序。另外，凡可能之處，在圖式及實施方式中使用相同標號的元件/構件/步驟代表相同或類似部分。不同實施例中使用相同標號或使用相同用語的元件/構件/步驟可以相互參照相關說明。The term "coupled (or connected)" used throughout the specification of this case (including the patent claims) may refer to any direct or indirect means of connection. For example, if it is described in the text that a first device is coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be connected to the second device through other devices or certain A connection means indirectly connected to the second device. The terms "first" and "second" mentioned in the entire description of this case (including the scope of the patent application) are used to name elements (elements), or to distinguish different embodiments or ranges, and are not used to limit the number of elements The upper or lower limit of , nor is it used to limit the order of the elements. In addition, wherever possible, elements/components/steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Elements/components/steps using the same symbols or using the same terms in different embodiments can refer to related descriptions.

圖1為依照本發明實施例所繪示，連接於主機20與裝置30之間的一種連接介面轉換裝置100的電路方塊（circuit block）示意圖。連接介面轉換裝置100具有顯示埠（DisplayPort，以下稱DP）連接器120。DP連接器120可以包括DP規格所規範的通道腳對DP0、通道腳對DP1、通道腳對DP2以及通道腳對DP3。DP連接器120可以經由電纜線連接（或是直接連接）至DP裝置30的DP連接器31。DP連接器31可以包括DP規格所規範的通道腳對DP0、通道腳對DP1、通道腳對DP2以及通道腳對DP3。連接介面轉換裝置100可以扮演源（source）裝置，而DP裝置30可以扮演槽（sink）裝置。依照應用需求，DP裝置30可以是顯示器或是其他DP裝置。FIG. 1 is a schematic diagram of a circuit block of a connection interface conversion device 100 connected between a host 20 and a device 30 according to an embodiment of the present invention. The connection interface converting device 100 has a DisplayPort (hereinafter referred to as DP) connector 120 . The DP connector 120 may include a pair of channel pins DP0 , a pair of channel pins DP1 , a pair of channel pins DP2 and a pair of channel pins DP3 regulated by the DP specification. The DP connector 120 may be connected (or directly connected) to the DP connector 31 of the DP device 30 via a cable. The DP connector 31 may include a pair of channel pins DP0 , a pair of channel pins DP1 , a pair of channel pins DP2 and a pair of channel pins DP3 regulated by the DP specification. The connection interface conversion device 100 can act as a source device, and the DP device 30 can act as a sink device. According to application requirements, the DP device 30 can be a display or other DP devices.

連接介面轉換裝置100還具有通用序列匯流排（Universal Serial Bus，以下稱USB）連接器110。USB連接器110可以是USB Type-C連接器（又可稱為USB-C連接器）。USB連接器110可以包括USB規格所規範的發送腳（transmitting pin，TX pin）對TX1、接收腳（receiving pin，RX pin）對RX1、發送腳對TX2、接收腳對RX2以及配置通道（Configuration Channel，以下稱CC）接腳CCa。所述CC接腳CCa可以包括USB規格所規範的CC1接腳與（或）CC2接腳。The connection interface conversion device 100 also has a universal serial bus (Universal Serial Bus, hereinafter referred to as USB) connector 110 . The USB connector 110 may be a USB Type-C connector (also called a USB-C connector). The USB connector 110 may include a transmitting pin (transmitting pin, TX pin) pair TX1, a receiving pin (receiving pin, RX pin) pair RX1, a transmitting pin pair TX2, a receiving pin pair RX2 and a configuration channel (Configuration Channel) regulated by the USB specification. , hereinafter referred to as CC) pin CCa. The CC pin CCa may include the CC1 pin and (or) the CC2 pin specified in the USB specification.

USB連接器110可以經由電纜線連接（或是直接連接）至主機20的USB連接器21。USB連接器21可以是USB-C連接器。USB連接器21可以包括USB規格所規範的發送腳對TX1、接收腳對RX1、發送腳對TX2、接收腳對RX2以及配置通道（Configuration Channel，以下稱CC）接腳CCb。所述CC接腳CCb可以包括USB規格所規範的CC1接腳與（或）CC2接腳。依照應用需求，主機20可以是個人電腦、筆記型電腦或是具有USB-C連接器的其他電子裝置。The USB connector 110 can be connected (or directly connected) to the USB connector 21 of the host 20 via a cable. The USB connector 21 may be a USB-C connector. The USB connector 21 may include a pair of transmitting pins TX1 , a pair of receiving pins RX1 , a pair of transmitting pins TX2 , a pair of receiving pins RX2 , and a configuration channel (Configuration Channel, hereinafter referred to as CC) pin CCb as specified in the USB specification. The CC pin CCb may include the CC1 pin and (or) the CC2 pin specified in the USB specification. According to application requirements, the host 20 can be a personal computer, a notebook computer or other electronic devices with a USB-C connector.

連接介面轉換裝置100還具有連接介面轉換晶片200與電力傳輸（Power Delivery，以下稱為PD）控制器130。USB連接器110的CC接腳CCa耦接於PD控制器130。當主機20的USB連接器21連接至USB連接器110時，PD控制器130可以經由CC接腳CCa偵測USB連接器110的連接組態。舉例來說，依據對CC接腳CCa的偵測結果，PD控制器130可以獲知主機20的USB插頭（未繪示）是正面朝上插入USB連接器110，還是反面朝上插入USB連接器110。The connection interface conversion device 100 also has a connection interface conversion chip 200 and a power delivery (Power Delivery, hereinafter referred to as PD) controller 130 . The CC pin CCa of the USB connector 110 is coupled to the PD controller 130 . When the USB connector 21 of the host 20 is connected to the USB connector 110 , the PD controller 130 can detect the connection configuration of the USB connector 110 through the CC pin CCa. For example, according to the detection result of the CC pin CCa, the PD controller 130 can know whether the USB plug (not shown) of the host 20 is plugged into the USB connector 110 with the front side up or the back side up into the USB connector 110 .

依據不同的應用情境，主機20可能是支持USB 4.0規格的電子裝置，或者主機20可能是支持USB規格（例如USB 3.2規格）的顯示埠替代模式（DP ALT Mode，以下稱ALT模式）的電子裝置。PD控制器130還可以經由CC接腳CCa向主機20交換配置資訊。因此，依據CC接腳CCa的配置資訊，PD控制器130可以獲知連接至USB連接器110的主機20是支持USB 4.0規格的電子裝置，還是運行ALT模式的電子裝置。PD（電力傳輸）控制與CC接腳的相關操作被規範於USB規格，故在此不予贅述。PD控制器130可以依照CC接腳CCa的配置資訊而提供連接組態訊號給連接介面轉換晶片200，而連接介面轉換晶片200依據PD控制器130所提供的連接組態訊號來動態決定操作於第一操作模式、第二操作模式以及（或是）其他模式。舉例來說，所述第一操作模式包括符合USB 4.0規格的顯示埠穿隧（DP Tunneling）協定，而所述第二操作模式包括符合USB規格的顯示埠替代模式（ALT模式）。According to different application scenarios, the host 20 may be an electronic device that supports the USB 4.0 specification, or the host 20 may be an electronic device that supports the display port alternative mode (DP ALT Mode, hereinafter referred to as ALT mode) of the USB specification (such as the USB 3.2 specification). . The PD controller 130 can also exchange configuration information with the host 20 via the CC pin CCa. Therefore, according to the configuration information of the CC pin CCa, the PD controller 130 can know whether the host 20 connected to the USB connector 110 is an electronic device supporting the USB 4.0 specification or an electronic device running in the ALT mode. The related operations of PD (power delivery) control and CC pin are regulated in the USB specification, so details will not be described here. The PD controller 130 can provide a connection configuration signal to the connection interface conversion chip 200 according to the configuration information of the CC pin CCa, and the connection interface conversion chip 200 dynamically determines to operate on the first connection according to the connection configuration signal provided by the PD controller 130. An operation mode, a second operation mode and (or) other modes. For example, the first operation mode includes a display port tunneling (DP Tunneling) protocol conforming to the USB 4.0 specification, and the second operation mode includes a display port alternative mode (ALT mode) conforming to the USB specification.

依據不同的應用情境，主機20可能是支持USB 4.0規格的電子裝置。亦即，主機20的USB連接器21所傳輸的訊號符合USB 4.0規格。在主機20的USB連接器21操作於USB 4.0規格的情況下，USB連接器21的發送腳對TX1、接收腳對RX1、發送腳對TX2與接收腳對RX2都可以被用來作為USB 4.0的通訊通道，因此USB連接器21的發送腳對TX1與發送腳對TX2可以傳送USB 4.0訊號串流至連接介面轉接裝置100的USB連接器110的接收腳對RX1與接收腳對RX2。當主機20的USB連接器21傳輸符合USB 4.0規格的訊號時，主機20可以使用符合USB 4.0規格的顯示埠穿隧協定而將符合DP規格的DP資料與AUX通道訊號編碼在所述USB 4.0訊號串流中。According to different application scenarios, the host 20 may be an electronic device supporting the USB 4.0 specification. That is, the signal transmitted by the USB connector 21 of the host 20 conforms to the USB 4.0 specification. In the case that the USB connector 21 of the host 20 operates in the USB 4.0 specification, the sending pin pair TX1, the receiving pin pair RX1, the sending pin pair TX2 and the receiving pin pair RX2 of the USB connector 21 can all be used as USB 4.0 Therefore, the pair of sending pins TX1 and TX2 of the USB connector 21 can transmit USB 4.0 signal streams to the pair of receiving pins RX1 and pair of receiving pins RX2 of the USB connector 110 of the connection interface adapter 100 . When the USB connector 21 of the host 20 transmits a signal conforming to the USB 4.0 specification, the host 20 can use the display port tunneling protocol conforming to the USB 4.0 specification to encode the DP data and the AUX channel signal conforming to the DP specification into the USB 4.0 signal streaming.

在主機20的USB連接器21操作於USB 4.0規格的情況下，連接介面轉換晶片200可以對應地操作於第一操作模式。在第一操作模式（USB 4.0模式）中，連接介面轉換晶片200可以對USB連接器110的接收腳對RX1與接收腳對RX2所接收的至少一個USB訊號對（差動訊號）進行解碼，以產生符合DP規格的DP資料。因此，連接介面轉換晶片200可以將DP資料經過DP連接器120的通道腳對DP0、通道腳對DP1、通道腳對DP2與通道腳對DP3其中至少一者輸出給DP裝置30。In the case that the USB connector 21 of the host 20 operates in the USB 4.0 specification, the connection interface conversion chip 200 can correspondingly operate in the first operation mode. In the first operation mode (USB 4.0 mode), the connection interface conversion chip 200 can decode at least one USB signal pair (differential signal) received by the receiving pin pair RX1 and the receiving pin pair RX2 of the USB connector 110, so as to Generate DP data that conforms to DP specifications. Therefore, the connection interface conversion chip 200 can output the DP data to the DP device 30 through at least one of the channel pin pair DP0 , the channel pin pair DP1 , the channel pin pair DP2 and the channel pin pair DP3 of the DP connector 120 .

依據不同的應用情境，主機20可能是支持USB規格（例如USB 3.2規格）的顯示埠替代模式（ALT模式）的電子裝置。在主機20的USB連接器21操作於USB 3.2規格的情況下，USB連接器21的一組傳輸通道可以被用來作為USB 3.2的通訊通道，而另一組傳輸通道則被閒置。舉例來說，當USB連接器21的發送腳對TX1與接收腳對RX1被用來作為USB 3.2的通訊通道時，USB連接器21的發送腳對TX2與接收腳對RX2則被閒置。當主機操作於ALT模式時，在主機20的USB連接器21中被閒置的發送腳對與接收腳對可以被用來傳輸符合DP規格的DP資料。According to different application scenarios, the host 20 may be an electronic device supporting a display port alternative mode (ALT mode) of a USB specification (eg USB 3.2 specification). When the USB connector 21 of the host 20 operates in the USB 3.2 specification, one set of transmission channels of the USB connector 21 can be used as USB 3.2 communication channels, while the other set of transmission channels is idle. For example, when the pair of transmitting pins TX1 and pair of receiving pins RX1 of the USB connector 21 is used as the communication channel of USB 3.2, the pair of transmitting pins TX2 and pair of receiving pins of the USB connector 21 are idle. When the host operates in the ALT mode, the idle sending pin pair and receiving pin pair in the USB connector 21 of the host 20 can be used to transmit DP data conforming to the DP specification.

在主機20的USB連接器21操作於ALT模式的情況下，連接介面轉換晶片200可以對應地操作於第二操作模式。在第二操作模式（ALT模式）中，當USB插頭（未繪示）正面朝上插入USB-C連接器時，連接介面轉換晶片200可以通過USB連接器110的發送腳對TX1與接收腳對RX1向主機20進行雙向USB通訊，而且主機20可以通過USB連接器110的發送腳對TX2與接收腳對RX2其中至少一者傳輸符合DP規格的DP資料給連接介面轉換晶片200。反之，當USB插頭（未繪示）反面朝上插入USB-C連接器時，連接介面轉換晶片200可以通過USB連接器110的發送腳對TX2與接收腳對RX2向主機20進行雙向USB通訊，而且主機20可以通過USB連接器110的發送腳對TX1與接收腳對RX1其中至少一者傳輸符合DP規格的DP資料給連接介面轉換晶片200。因此，連接介面轉換晶片200可以將DP資料經過DP連接器120的通道腳對DP0、通道腳對DP1、通道腳對DP2與通道腳對DP3其中至少一者輸出給DP裝置30。When the USB connector 21 of the host 20 operates in the ALT mode, the connection interface conversion chip 200 can correspondingly operate in the second operation mode. In the second operation mode (ALT mode), when the USB plug (not shown) is inserted into the USB-C connector with the front facing up, the connection interface conversion chip 200 can pass the sending pin pair TX1 and the receiving pin pair of the USB connector 110 RX1 performs two-way USB communication with the host 20, and the host 20 can transmit DP data conforming to the DP specification to the connection interface conversion chip 200 through at least one of the sending pin pair TX2 and the receiving pin pair RX2 of the USB connector 110 . Conversely, when the USB plug (not shown) is inserted into the USB-C connector with the reverse side up, the connection interface conversion chip 200 can perform two-way USB communication to the host computer 20 through the sending pin pair TX2 and the receiving pin pair RX2 of the USB connector 110, Moreover, the host 20 can transmit DP data conforming to the DP specification to the connection interface conversion chip 200 through at least one of the pair of sending pins TX1 and the pair of receiving pins RX1 of the USB connector 110 . Therefore, the connection interface conversion chip 200 can output the DP data to the DP device 30 through at least one of the channel pin pair DP0 , the channel pin pair DP1 , the channel pin pair DP2 and the channel pin pair DP3 of the DP connector 120 .

因此，連接介面轉換裝置100可適用於不同規格的主機20與DP裝置30之間的介面轉換。連接介面轉換裝置100（連接介面轉換晶片200）可以處理USB連接器110的訊號，而不論主機20傳輸給所述USB連接器110的訊號是第一操作模式的訊號（符合USB 4.0的顯示埠穿隧（DP Tunneling）協定的訊號）還是第二操作模式（ALT模式）的訊號。Therefore, the connection interface conversion device 100 is applicable to interface conversion between the host 20 and the DP device 30 of different specifications. The connection interface conversion device 100 (connection interface conversion chip 200) can process the signal of the USB connector 110, regardless of whether the signal transmitted from the host 20 to the USB connector 110 is the signal of the first operation mode (display port conforming to USB 4.0) Tunneling (DP Tunneling) protocol signal) or the signal of the second operation mode (ALT mode).

圖2為依照本發明一實施例說明圖1中所繪示的連接介面轉換晶片200的電路方塊示意圖。在圖2所示實施例中，連接介面轉換晶片200包括USB介面電路210、USB核心電路220、切換電路230以及DP介面電路240。USB介面電路210適於耦接至USB連接器110。舉例來說，USB介面電路210適於至少耦接至USB連接器110的發送腳對TX1、接收腳對RX1、發送腳對TX2與接收腳對RX2。DP介面電路240適於耦接至DP連接器120。舉例來說，DP介面電路240適於至少耦接至DP連接器120的通道腳對DP0、通道腳對DP1、通道腳對DP2與通道腳對DP3。USB核心電路220耦接至USB介面電路210與DP介面電路240。切換電路230耦接至USB介面電路210與DP介面電路240。圖2所示USB連接器110、DP連接器120、PD控制器130與連接介面轉換晶片200可以參照圖1的相關說明。FIG. 2 is a schematic circuit block diagram illustrating the connection interface conversion chip 200 shown in FIG. 1 according to an embodiment of the present invention. In the embodiment shown in FIG. 2 , the connection interface conversion chip 200 includes a USB interface circuit 210 , a USB core circuit 220 , a switching circuit 230 and a DP interface circuit 240 . The USB interface circuit 210 is adapted to be coupled to the USB connector 110 . For example, the USB interface circuit 210 is adapted to be coupled at least to the pair of transmit pins TX1 , pair of receive pins RX1 , pair of transmit pins TX2 and pair of receive pins RX2 of the USB connector 110 . The DP interface circuit 240 is adapted to be coupled to the DP connector 120 . For example, the DP interface circuit 240 is adapted to be coupled to at least the channel pin pair DP0 , the channel pin pair DP1 , the channel pin pair DP2 and the channel pin pair DP3 of the DP connector 120 . The USB core circuit 220 is coupled to the USB interface circuit 210 and the DP interface circuit 240 . The switching circuit 230 is coupled to the USB interface circuit 210 and the DP interface circuit 240 . The USB connector 110 , the DP connector 120 , the PD controller 130 and the connection interface conversion chip 200 shown in FIG. 2 can refer to the related description of FIG. 1 .

圖3為依照本發明一實施例所繪示的一種連接介面轉換晶片的操作方法的流程示意圖。請參照圖1、圖2與圖3。在步驟S310中，PD控制器130可以偵測USB連接器110的CC接腳CCa的訊號，以及經由CC接腳CCa向主機20交換配置資訊。因此，依據CC接腳CCa的配置資訊，PD控制器130以及（或是）連接介面轉換晶片200可以獲知連接至USB連接器110的主機20是支持USB 4.0規格的電子裝置，還是運行ALT模式的電子裝置。依照設計需求，USB核心電路220可以執行步驟S320的判斷操作，亦即USB核心電路220可以依據PD控制器130所提供連接組態訊號來判定USB連接器110的訊號是ALT模式的訊號還是顯示埠穿隧（DP Tunneling）協定的訊號。FIG. 3 is a schematic flowchart of an operation method for connecting an interface conversion chip according to an embodiment of the present invention. Please refer to Figure 1, Figure 2 and Figure 3. In step S310 , the PD controller 130 can detect the signal of the CC pin CCa of the USB connector 110 , and exchange configuration information with the host 20 through the CC pin CCa. Therefore, according to the configuration information of the CC pin CCa, the PD controller 130 and/or the connection interface conversion chip 200 can know whether the host computer 20 connected to the USB connector 110 is an electronic device supporting the USB 4.0 specification or running in ALT mode. electronic device. According to design requirements, the USB core circuit 220 can perform the judgment operation in step S320, that is, the USB core circuit 220 can judge whether the signal of the USB connector 110 is an ALT mode signal or a display port according to the connection configuration signal provided by the PD controller 130. The signal of the tunneling (DP Tunneling) protocol.

當USB連接器110的訊號被判定是ALT模式的訊號時（步驟S320的判斷結果是「ALT模式訊號」），連接介面轉換晶片200可以操作在第二操作模式。當USB連接器110的訊號是符合USB規格的ALT模式的訊號時，切換電路230可以經過USB介面電路210接收USB連接器110的DP資料，以及（或是）USB核心電路220可以經過USB介面電路210接收USB連接器110的USB訊號。然後，切換電路230可以將DP資料經過DP介面電路240傳輸至DP連接器120。因此在第二操作模式（ALT模式）中，USB連接器110所接收的DP資料會經過USB介面電路210、切換電路230與DP介面電路240而被傳輸至DP連接器120(步驟S330)。When the signal of the USB connector 110 is determined to be an ALT mode signal (the determination result of step S320 is “ALT mode signal”), the connection interface conversion chip 200 can operate in the second operation mode. When the signal of the USB connector 110 is an ALT mode signal conforming to the USB specification, the switching circuit 230 can receive the DP data of the USB connector 110 through the USB interface circuit 210, and (or) the USB core circuit 220 can pass through the USB interface circuit. 210 receives the USB signal from the USB connector 110 . Then, the switching circuit 230 can transmit the DP data to the DP connector 120 through the DP interface circuit 240 . Therefore, in the second operation mode (ALT mode), the DP data received by the USB connector 110 will be transmitted to the DP connector 120 through the USB interface circuit 210, the switching circuit 230 and the DP interface circuit 240 (step S330).

換句話說，在第二操作模式（ALT模式）中，USB核心電路220所輸出的USB資料會經過USB介面電路210而被傳輸至USB連接器110的發送腳對（例如發送腳對TX1），而USB連接器110的接收腳對（例如接收腳對RX1）從主機20所接收的USB資料會經過USB介面電路210而被傳輸至USB核心電路220。因此，USB核心電路220可以通過USB介面電路210與USB連接器110而對主機20進行雙向USB通訊。USB連接器110的另一個發送腳對（例如發送腳對TX2）與另一個接收腳對（例如接收腳對RX2）中的至少一者所接收的DP資料會經過USB介面電路210、切換電路230與DP介面電路240而被傳輸至DP連接器120的通道腳對DP0、通道腳對DP1、通道腳對DP2與通道腳對DP3中的至少一者。In other words, in the second operation mode (ALT mode), the USB data output by the USB core circuit 220 will be transmitted to the transmit pin pair (such as transmit pin pair TX1) of the USB connector 110 through the USB interface circuit 210, The USB data received by the receiving pin pair (for example, the receiving pin pair RX1 ) of the USB connector 110 from the host 20 will be transmitted to the USB core circuit 220 through the USB interface circuit 210 . Therefore, the USB core circuit 220 can perform two-way USB communication with the host 20 through the USB interface circuit 210 and the USB connector 110 . The DP data received by at least one of another pair of sending pins (such as sending pin pair TX2) and another pair of receiving pins (such as receiving pin pair RX2) of the USB connector 110 will pass through the USB interface circuit 210 and the switching circuit 230 The DP interface circuit 240 is transmitted to at least one of the channel pin pair DP0 , the channel pin pair DP1 , the channel pin pair DP2 and the channel pin pair DP3 of the DP connector 120 .

在一些應用情境中，USB核心電路220可能在ALT模式中不需要對主機20進行雙向USB通訊，亦即USB核心電路220可能不會使用USB連接器110的發送腳對TX1、接收腳對RX1、發送腳對TX2與接收腳對RX2。在這樣的情況下，USB連接器110的發送腳對TX1、接收腳對RX1、發送腳對TX2與接收腳對RX2可以全被用來傳輸DP資料。因此，在第二操作模式（ALT模式）中，USB連接器110的發送腳對TX1、接收腳對RX1、發送腳對TX2與接收腳對RX2所接收的DP資料可以經過USB介面電路210、切換電路230與DP介面電路240而被傳輸至DP連接器120的通道腳對DP0、通道腳對DP1、通道腳對DP2與通道腳對DP3。In some application scenarios, the USB core circuit 220 may not need to perform two-way USB communication with the host 20 in the ALT mode, that is, the USB core circuit 220 may not use the sending pin pair TX1, the receiving pin pair RX1, and the receiving pin pair of the USB connector 110. The sending pin is paired with TX2 and the receiving pin is paired with RX2. In this case, the pair of transmit pins TX1 , pair of receive pins RX1 , pair of transmit pins TX2 and pair of receive pins RX2 of the USB connector 110 can all be used to transmit DP data. Therefore, in the second operation mode (ALT mode), the DP data received by the sending pin pair TX1, receiving pin pair RX1, sending pin pair TX2, and receiving pin pair RX2 of the USB connector 110 can pass through the USB interface circuit 210, switch The circuit 230 and the DP interface circuit 240 are transmitted to the channel pin pair DP0 , the channel pin pair DP1 , the channel pin pair DP2 and the channel pin pair DP3 of the DP connector 120 .

當USB連接器110的訊號被判定是USB 4.0的顯示埠穿隧（DP Tunneling）協定的訊號時（步驟S320的判斷結果是「DP Tunneling訊號」），連接介面轉換晶片200可以操作在第一操作模式。當USB連接器110的訊號是符合USB 4.0規格的顯示埠穿隧協定的USB訊號時，USB核心電路220可以經過USB介面電路210接收USB連接器110的USB訊號對，並且對所述USB訊號對進行解碼以獲得DP資料。然後，USB核心電路220可以將DP資料經過DP介面電路240傳輸至DP連接器120(步驟S340)。換句話說，在第一操作模式中，USB連接器110的接收腳對RX1與接收腳對RX2所接收的USB訊號對會經過USB介面電路210，由USB核心電路220解碼出DP資料，再由DP介面電路240傳輸至DP連接器120的通道腳對DP0、通道腳對DP1、通道腳對DP2與通道腳對DP3中的至少一者。When the signal of the USB connector 110 is determined to be a signal of the USB 4.0 Display Port Tunneling (DP Tunneling) protocol (the determination result of step S320 is "DP Tunneling signal"), the connection interface conversion chip 200 can operate in the first operation model. When the signal of the USB connector 110 is a USB signal conforming to the DisplayPort Tunneling Protocol of the USB 4.0 specification, the USB core circuit 220 can receive the USB signal pair of the USB connector 110 through the USB interface circuit 210, and respond to the USB signal pair. Decode to get DP data. Then, the USB core circuit 220 can transmit the DP data to the DP connector 120 through the DP interface circuit 240 (step S340 ). In other words, in the first operation mode, the USB signal pair received by the receiving pin pair RX1 and the receiving pin pair RX2 of the USB connector 110 will pass through the USB interface circuit 210, and the DP data will be decoded by the USB core circuit 220, and then the DP data will be decoded by the USB core circuit 220. The DP interface circuit 240 transmits to at least one of the channel pin pair DP0 , the channel pin pair DP1 , the channel pin pair DP2 and the channel pin pair DP3 of the DP connector 120 .

因此在第一操作模式（USB 4.0模式）中，USB連接器110所接收的USB訊號對會經過USB介面電路210，由USB核心電路220解碼出DP資料，再由DP介面電路240傳輸至DP連接器120。此時（第一操作模式），切換電路230可以依照設計需求而被禁能（disable），以節省功耗。切換電路230不需要處理高頻寬的USB 4.0訊號，因此切換電路230的成本可以盡可能的降低。Therefore, in the first operation mode (USB 4.0 mode), the USB signal pair received by the USB connector 110 will pass through the USB interface circuit 210, and the DP data will be decoded by the USB core circuit 220, and then transmitted to the DP connection by the DP interface circuit 240. device 120. At this time (the first operation mode), the switching circuit 230 can be disabled according to the design requirements, so as to save power consumption. The switching circuit 230 does not need to process high-bandwidth USB 4.0 signals, so the cost of the switching circuit 230 can be reduced as much as possible.

圖4為依照本發明一實施例說明圖2中所繪示的USB介面電路210的電路方塊示意圖。在圖4所示實施例中，USB介面電路210包括介面電路211、介面電路212、介面電路213、介面電路214、驅動器215、接收器216、接收器217、驅動器218、緩衝器B1、緩衝器B2、緩衝器B3以及緩衝器B4。依照設計需求，介面電路211可以包括並列輸入串列輸出（parallel-in-serial-out，以下稱PISO）介面電路以及（或是）其他電路。USB核心電路220所輸出的USB資料可以被傳輸至介面電路211的輸入端。驅動器215的差動輸入對耦接至介面電路211的差動輸出對，以接收差動訊號（USB資料）。驅動器215的差動輸出對適於耦接至USB連接器110的發送腳對TX1。FIG. 4 is a schematic circuit block diagram illustrating the USB interface circuit 210 shown in FIG. 2 according to an embodiment of the present invention. In the embodiment shown in FIG. 4, the USB interface circuit 210 includes an interface circuit 211, an interface circuit 212, an interface circuit 213, an interface circuit 214, a driver 215, a receiver 216, a receiver 217, a driver 218, a buffer B1, a buffer B2, buffer B3, and buffer B4. According to design requirements, the interface circuit 211 may include a parallel-in-serial-out (hereinafter referred to as PISO) interface circuit and (or) other circuits. The USB data output by the USB core circuit 220 can be transmitted to the input terminal of the interface circuit 211 . The differential input pairs of the driver 215 are coupled to the differential output pairs of the interface circuit 211 to receive differential signals (USB data). The differential output pair of the driver 215 is adapted to be coupled to the transmit pin pair TX1 of the USB connector 110 .

接收器216的差動輸入對適於耦接至USB連接器110的接收腳對RX1。接收器216的差動輸出對耦接至介面電路212的差動輸入對。介面電路212的輸出端耦接至USB核心電路220的輸入端。依照設計需求，介面電路212可以包括時脈與資料回復（clock and data recovery，以下稱CDR）電路、串列輸入並列輸出（serial-in-parallel-out，以下稱SIPO）介面電路以及（或是）其他電路。介面電路212可以依照當下的訊號品質而調校接收器216的等化（Equalization，以下稱EQ）參數。介面電路212還可以將所述EQ參數提供給USB核心電路220。The differential input pair of the receiver 216 is adapted to be coupled to the receiving pin pair RX1 of the USB connector 110 . The differential output pairs of the receiver 216 are coupled to the differential input pairs of the interface circuit 212 . The output terminal of the interface circuit 212 is coupled to the input terminal of the USB core circuit 220 . According to design requirements, the interface circuit 212 may include a clock and data recovery (CDR) circuit, a serial-in-parallel-out (SIPO) interface circuit and (or ) other circuits. The interface circuit 212 can adjust the equalization (Equalization, hereinafter referred to as EQ) parameters of the receiver 216 according to the current signal quality. The interface circuit 212 can also provide the EQ parameters to the USB core circuit 220 .

接收器217的差動輸入對適於耦接至USB連接器110的接收腳對RX2。接收器217的差動輸出對耦接至介面電路213的差動輸入對。介面電路213的輸出端耦接至USB核心電路220的輸入端。依照設計需求，介面電路213可以包括CDR電路、SIPO介面電路以及（或是）其他電路。介面電路213可以依照當下的訊號品質而調校接收器217的EQ參數。介面電路213還可以將所述EQ參數提供給USB核心電路220。The differential input pair of the receiver 217 is adapted to be coupled to the receiving pin pair RX2 of the USB connector 110 . The differential output pairs of the receiver 217 are coupled to the differential input pairs of the interface circuit 213 . The output terminal of the interface circuit 213 is coupled to the input terminal of the USB core circuit 220 . According to design requirements, the interface circuit 213 may include a CDR circuit, a SIPO interface circuit and (or) other circuits. The interface circuit 213 can adjust the EQ parameters of the receiver 217 according to the current signal quality. The interface circuit 213 can also provide the EQ parameters to the USB core circuit 220 .

依照設計需求，介面電路214可以包括PISO介面電路以及（或是）其他電路。USB核心電路220所輸出的USB資料可以被傳輸至介面電路214的輸入端。驅動器218的差動輸入對耦接至介面電路214的差動輸出對，以接收差動訊號（USB資料）。驅動器218的差動輸出對適於耦接至USB連接器110的發送腳對TX2。According to design requirements, the interface circuit 214 may include a PISO interface circuit and (or) other circuits. The USB data output by the USB core circuit 220 can be transmitted to the input terminal of the interface circuit 214 . The differential input pairs of the driver 218 are coupled to the differential output pairs of the interface circuit 214 to receive differential signals (USB data). The differential output pair of the driver 218 is adapted to be coupled to the transmit pin pair TX2 of the USB connector 110 .

緩衝器B1的差動輸入對適於耦接至USB連接器110的該第一發送腳對TX1。緩衝器B1的差動輸出對耦接至切換電路230。緩衝器B2的差動輸入對適於耦接至USB連接器110的該第一接收腳對RX1。緩衝器B2的差動輸出對耦接至切換電路230。緩衝器B3的差動輸入對適於耦接至USB連接器110的接收腳對RX2。緩衝器B3的差動輸出對耦接至切換電路230。緩衝器B4的差動輸入對適於耦接至USB連接器110的發送腳對TX2。緩衝器B4的差動輸出對耦接至切換電路230。The differential input pair of the buffer B1 is adapted to be coupled to the first transmit pin pair TX1 of the USB connector 110 . The differential output pair of the buffer B1 is coupled to the switching circuit 230 . The differential input pair of the buffer B2 is adapted to be coupled to the first receiving pin pair RX1 of the USB connector 110 . The differential output pair of the buffer B2 is coupled to the switching circuit 230 . The differential input pair of the buffer B3 is adapted to be coupled to the receiving pin pair RX2 of the USB connector 110 . The differential output pair of the buffer B3 is coupled to the switching circuit 230 . The differential input pair of the buffer B4 is adapted to be coupled to the transmit pin pair TX2 of the USB connector 110 . The differential output pair of the buffer B4 is coupled to the switching circuit 230 .

在第一操作模式（USB 4.0模式）中，USB核心電路220可以禁能（disable）緩衝器B1、緩衝器B2、緩衝器B3以及緩衝器B4。在第二操作模式（ALT模式）中，USB核心電路220可以致能（enable）緩衝器B1、緩衝器B2、緩衝器B3以及緩衝器B4中的至少一者。舉例來說，假設USB核心電路220使用USB連接器110的發送腳對TX1與接收腳對RX1對主機20進行雙向USB通訊，因此USB核心電路220在第二操作模式（ALT模式）中可以禁能緩衝器B1與緩衝器B2以及致能緩衝器B3以及緩衝器B4。假設USB核心電路220使用USB連接器110的發送腳對TX2與接收腳對RX2對主機20進行雙向USB通訊，因此USB核心電路220在第二操作模式（ALT模式）中可以禁能緩衝器B3與緩衝器B4以及致能緩衝器B1以及緩衝器B2。In the first operation mode (USB 4.0 mode), the USB core circuit 220 can disable the buffer B1 , the buffer B2 , the buffer B3 and the buffer B4 . In the second operation mode (ALT mode), the USB core circuit 220 can enable at least one of the buffer B1 , the buffer B2 , the buffer B3 and the buffer B4 . For example, assume that the USB core circuit 220 uses the sending pin pair TX1 and the receiving pin pair RX1 of the USB connector 110 to perform two-way USB communication with the host 20, so the USB core circuit 220 can be disabled in the second operation mode (ALT mode). Buffer B1 and buffer B2 and enable buffer B3 and buffer B4. Assuming that the USB core circuit 220 uses the sending pin pair TX2 and the receiving pin pair RX2 of the USB connector 110 to perform two-way USB communication with the host 20, the USB core circuit 220 can disable the buffer B3 and the buffer B3 in the second operation mode (ALT mode). Buffer B4 and enable buffer B1 and buffer B2.

在一些應用情境中，USB核心電路220可能在ALT模式中不需要對主機20進行雙向USB通訊，亦即USB核心電路220可能不會使用USB連接器110的發送腳對TX1、接收腳對RX1、發送腳對TX2與接收腳對RX2。在這樣的情況下，USB核心電路220在第二操作模式（ALT模式）中可以致能緩衝器B1、緩衝器B2、緩衝器B3以及緩衝器B4。在其他模式中（既不是USB 4.0模式也不是ALT模式），USB核心電路220可以禁能緩衝器B1、緩衝器B2、緩衝器B3以及緩衝器B4。In some application scenarios, the USB core circuit 220 may not need to perform two-way USB communication with the host 20 in the ALT mode, that is, the USB core circuit 220 may not use the sending pin pair TX1, the receiving pin pair RX1, and the receiving pin pair of the USB connector 110. The sending pin is paired with TX2 and the receiving pin is paired with RX2. In this case, the USB core circuit 220 can enable the buffer B1 , the buffer B2 , the buffer B3 and the buffer B4 in the second operation mode (ALT mode). In other modes (neither USB 4.0 mode nor ALT mode), the USB core circuit 220 can disable buffer B1 , buffer B2 , buffer B3 and buffer B4 .

圖5為依照本發明一實施例說明圖2中所繪示的切換電路230與DP介面電路240的電路方塊示意圖。在圖5所示實施例中，切換電路230包括等化器231、等化器232、等化器233、等化器234、等化器235、等化器236、等化器237與等化器238。依據USB介面電路210所決定的等化（EQ）參數，USB核心電路220可以對應控制/調整等化器231～238的EQ參數。FIG. 5 is a schematic circuit block diagram illustrating the switching circuit 230 and the DP interface circuit 240 shown in FIG. 2 according to an embodiment of the present invention. In the embodiment shown in FIG. 5, the switching circuit 230 includes an equalizer 231, an equalizer 232, an equalizer 233, an equalizer 234, an equalizer 235, an equalizer 236, an equalizer 237 and an equalizer device 238. According to the equalization (EQ) parameters determined by the USB interface circuit 210 , the USB core circuit 220 can correspondingly control/adjust the EQ parameters of the equalizers 231 - 238 .

等化器231的差動輸入對耦接至緩衝器B4的差動輸出對。等化器232的差動輸入對耦接至緩衝器B1的差動輸出對。等化器233的差動輸入對耦接至緩衝器B3的差動輸出對。等化器234的差動輸入對耦接至緩衝器B2的差動輸出對。等化器235的差動輸入對耦接至緩衝器B2的差動輸出對。等化器236的差動輸入對耦接至緩衝器B3的差動輸出對。等化器237的差動輸入對耦接至緩衝器B1的差動輸出對。等化器238的差動輸入對耦接至緩衝器B4的差動輸出對。The differential input pair of the equalizer 231 is coupled to the differential output pair of the buffer B4. The differential input pair of the equalizer 232 is coupled to the differential output pair of the buffer B1. The differential input pair of the equalizer 233 is coupled to the differential output pair of the buffer B3. The differential input pair of the equalizer 234 is coupled to the differential output pair of the buffer B2. The differential input pair of the equalizer 235 is coupled to the differential output pair of the buffer B2. The differential input pair of equalizer 236 is coupled to the differential output pair of buffer B3. The differential input pair of the equalizer 237 is coupled to the differential output pair of the buffer B1. The differential input pair of equalizer 238 is coupled to the differential output pair of buffer B4.

在圖5所示實施例中，DP介面電路240包括預驅動器（pre-driver）241_1、預驅動器241_2、預驅動器241_3、預驅動器241_4、預驅動器241_5、預驅動器241_6、預驅動器241_7、預驅動器241_8、驅動器242_1、驅動器242_2、驅動器242_3以及驅動器242_4。預驅動器241_1的差動輸入對耦接至等化器231的差動輸出對。預驅動器241_2的差動輸入對耦接至等化器232的差動輸出對。預驅動器241_3的差動輸入對耦接至等化器233的差動輸出對。預驅動器241_4的差動輸入對耦接至等化器234的差動輸出對。預驅動器241_5的差動輸入對耦接至等化器235的差動輸出對。預驅動器241_6的差動輸入對耦接至等化器236的差動輸出對。預驅動器241_7的差動輸入對耦接至等化器237的差動輸出對。預驅動器241_8的差動輸入對耦接至等化器238的差動輸出對。In the embodiment shown in FIG. 5, the DP interface circuit 240 includes a pre-driver (pre-driver) 241_1, a pre-driver 241_2, a pre-driver 241_3, a pre-driver 241_4, a pre-driver 241_5, a pre-driver 241_6, a pre-driver 241_7, and a pre-driver 241_8 , driver 242_1, driver 242_2, driver 242_3, and driver 242_4. The differential input pair of the pre-driver 241_1 is coupled to the differential output pair of the equalizer 231 . The differential input pair of the pre-driver 241_2 is coupled to the differential output pair of the equalizer 232 . The differential input pair of the pre-driver 241_3 is coupled to the differential output pair of the equalizer 233 . The differential input pair of the pre-driver 241_4 is coupled to the differential output pair of the equalizer 234 . The differential input pair of the pre-driver 241_5 is coupled to the differential output pair of the equalizer 235 . The differential input pair of the pre-driver 241_6 is coupled to the differential output pair of the equalizer 236 . The differential input pair of the pre-driver 241_7 is coupled to the differential output pair of the equalizer 237 . The differential input pair of the pre-driver 241_8 is coupled to the differential output pair of the equalizer 238 .

驅動器242_1的差動輸入對耦接至預驅動器241_1的差動輸出對以及預驅動器241_2的差動輸出對。驅動器242_1的差動輸出對適於耦接至DP連接器120的通道腳對DP0。驅動器242_2的差動輸入對耦接至預驅動器241_3的差動輸出對以及預驅動器241_4的差動輸出對。驅動器242_2的差動輸出對適於耦接至DP連接器120的通道腳對DP1。驅動器242_3的差動輸入對耦接至預驅動器241_5的差動輸出對以及預驅動器241_6的差動輸出對。驅動器242_3的差動輸出對適於耦接至DP連接器120的通道腳對DP2。驅動器242_4的差動輸入對耦接至預驅動器241_7的差動輸出對以及預驅動器241_8的差動輸出對。驅動器242_4的差動輸出對適於耦接至DP連接器120的通道腳對DP3。The differential input pair of the driver 242_1 is coupled to the differential output pair of the pre-driver 241_1 and the differential output pair of the pre-driver 241_2 . The differential output pair of the driver 242_1 is suitable for coupling to the channel pin pair DP0 of the DP connector 120 . The differential input pair of the driver 242_2 is coupled to the differential output pair of the pre-driver 241_3 and the differential output pair of the pre-driver 241_4 . The differential output pair of the driver 242_2 is suitable for coupling to the channel pin pair DP1 of the DP connector 120 . The differential input pair of the driver 242_3 is coupled to the differential output pair of the pre-driver 241_5 and the differential output pair of the pre-driver 241_6 . The differential output pair of the driver 242_3 is suitable for coupling to the channel pin pair DP2 of the DP connector 120 . The differential input pair of the driver 242_4 is coupled to the differential output pair of the pre-driver 241_7 and the differential output pair of the pre-driver 241_8 . The differential output pair of the driver 242_4 is suitable for coupling to the channel pin pair DP3 of the DP connector 120 .

在第一操作模式（USB 4.0模式）中，USB核心電路220可以禁能緩衝器B1～B4、等化器231～238以及預驅動器241_1～241_8。在第二操作模式（ALT模式）中，當USB-C插頭（未繪示）正面朝上插入USB連接器110時，USB核心電路220可以禁能等化器232、預驅動器241_2、等化器234、預驅動器241_4、等化器236、預驅動器241_6、等化器238與預驅動器241_8。當USB-C插頭（未繪示）反面朝上插入USB連接器110時，USB核心電路220可以禁能等化器231、預驅動器241_1、等化器233、預驅動器241_3、等化器235、預驅動器241_5、等化器237與預驅動器241_7。In the first operation mode (USB 4.0 mode), the USB core circuit 220 can disable the buffers B1 - B4 , the equalizers 231 - 238 and the pre-drivers 241_1 - 241_8 . In the second operation mode (ALT mode), when the USB-C plug (not shown) is plugged into the USB connector 110 facing upward, the USB core circuit 220 can disable the equalizer 232, the pre-driver 241_2, the equalizer 234 , the pre-driver 241_4 , the equalizer 236 , the pre-driver 241_6 , the equalizer 238 and the pre-driver 241_8 . When the USB-C plug (not shown) is inserted into the USB connector 110 with the reverse side up, the USB core circuit 220 can disable the equalizer 231, the pre-driver 241_1, the equalizer 233, the pre-driver 241_3, the equalizer 235, The pre-driver 241_5 , the equalizer 237 and the pre-driver 241_7 .

在等化器232、等化器234、等化器236與等化器238被禁能的情況下，USB核心電路220可以在第二操作模式（ALT模式）中致能等化器231、等化器233、等化器235與等化器237中的至少一者。舉例來說，假設USB核心電路220使用USB連接器110的發送腳對TX1與接收腳對RX1對主機20進行雙向USB通訊，因此USB核心電路220在第二操作模式（ALT模式）中可以禁能緩衝器B1、緩衝器B2、等化器235、等化器237、預驅動器241_5與預驅動器241_7以及致能緩衝器B3、緩衝器B4、等化器231、等化器233、預驅動器241_1與預驅動器241_3。假設USB核心電路220使用USB連接器110的發送腳對TX2與接收腳對RX2對主機20進行雙向USB通訊，因此USB核心電路220在第二操作模式（ALT模式）中可以禁能緩衝器B3、緩衝器B4、等化器231、等化器233、預驅動器241_1與預驅動器241_3以及致能緩衝器B1、緩衝器B2、等化器235、等化器237、預驅動器241_5與預驅動器241_7。In the case that the equalizer 232, the equalizer 234, the equalizer 236, and the equalizer 238 are disabled, the USB core circuit 220 can enable the equalizer 231, etc. in the second operation mode (ALT mode). At least one of the equalizer 233 , the equalizer 235 and the equalizer 237 . For example, assume that the USB core circuit 220 uses the sending pin pair TX1 and the receiving pin pair RX1 of the USB connector 110 to perform two-way USB communication with the host 20, so the USB core circuit 220 can be disabled in the second operation mode (ALT mode). Buffer B1, buffer B2, equalizer 235, equalizer 237, pre-driver 241_5 and pre-driver 241_7 and enable buffer B3, buffer B4, equalizer 231, equalizer 233, pre-driver 241_1 and Pre-driver 241_3. Assume that the USB core circuit 220 uses the sending pin pair TX2 and the receiving pin pair RX2 of the USB connector 110 to perform two-way USB communication with the host 20, so the USB core circuit 220 can disable the buffer B3, The buffer B4, the equalizer 231, the equalizer 233, the pre-driver 241_1 and the pre-driver 241_3 and the enable buffer B1, the buffer B2, the equalizer 235, the equalizer 237, the pre-driver 241_5 and the pre-driver 241_7.

在等化器231、等化器233、等化器235與等化器237被禁能的情況下，USB核心電路220可以在第二操作模式（ALT模式）中致能等化器232、等化器234、等化器236與等化器238中的至少一者。舉例來說，假設USB核心電路220使用USB連接器110的發送腳對TX1與接收腳對RX1對主機20進行雙向USB通訊，因此USB核心電路220在第二操作模式（ALT模式）中可以禁能緩衝器B1、緩衝器B2、等化器232、等化器234、預驅動器241_2與預驅動器241_4以及致能緩衝器B3、緩衝器B4、等化器236、等化器238、預驅動器241_6與預驅動器241_8。假設USB核心電路220使用USB連接器110的發送腳對TX2與接收腳對RX2對主機20進行雙向USB通訊，因此USB核心電路220在第二操作模式（ALT模式）中可以禁能緩衝器B3、緩衝器B4、預驅動器241_1、預驅動器241_3、等化器236、等化器238、預驅動器241_6與預驅動器241_8以及致能緩衝器B1、緩衝器B2、等化器232、等化器234、預驅動器241_2與預驅動器241_4。In the case that the equalizer 231, the equalizer 233, the equalizer 235, and the equalizer 237 are disabled, the USB core circuit 220 can enable the equalizer 232, etc. in the second operation mode (ALT mode). At least one of the equalizer 234 , the equalizer 236 and the equalizer 238 . For example, assume that the USB core circuit 220 uses the sending pin pair TX1 and the receiving pin pair RX1 of the USB connector 110 to perform two-way USB communication with the host 20, so the USB core circuit 220 can be disabled in the second operation mode (ALT mode). Buffer B1, buffer B2, equalizer 232, equalizer 234, pre-driver 241_2 and pre-driver 241_4 and enable buffer B3, buffer B4, equalizer 236, equalizer 238, pre-driver 241_6 and Pre-driver 241_8. Assume that the USB core circuit 220 uses the sending pin pair TX2 and the receiving pin pair RX2 of the USB connector 110 to perform two-way USB communication with the host 20, so the USB core circuit 220 can disable the buffer B3, Buffer B4, pre-driver 241_1, pre-driver 241_3, equalizer 236, equalizer 238, pre-driver 241_6 and pre-driver 241_8 and enable buffer B1, buffer B2, equalizer 232, equalizer 234, Pre-driver 241_2 and pre-driver 241_4.

在一些應用情境中，USB核心電路220可能在ALT模式中不需要對主機20進行雙向USB通訊，亦即USB核心電路220可能不會使用USB連接器110的發送腳對TX1、接收腳對RX1、發送腳對TX2與接收腳對RX2。在USB核心電路220不使用發送腳對TX1、接收腳對RX1、發送腳對TX2與接收腳對RX2的情況下，以及在等化器232、等化器234、等化器236與等化器238被禁能的情況下，USB核心電路220在第二操作模式（ALT模式）中可以致能緩衝器B1、緩衝器B2、緩衝器B3、緩衝器B4、等化器231、等化器233、等化器235、等化器237、預驅動器241_1、預驅動器241_3、預驅動器241_5以及預驅動器241_7。在USB核心電路220不使用發送腳對TX1、接收腳對RX1、發送腳對TX2與接收腳對RX2的情況下，以及在等化器231、等化器233、等化器235與等化器237被禁能的情況下，USB核心電路220在第二操作模式（ALT模式）中可以致能緩衝器B1、緩衝器B2、緩衝器B3、緩衝器B4、等化器232、等化器234、等化器236、等化器238、預驅動器241_2、預驅動器241_4、預驅動器241_6以及預驅動器241_8。In some application scenarios, the USB core circuit 220 may not need to perform two-way USB communication with the host 20 in the ALT mode, that is, the USB core circuit 220 may not use the sending pin pair TX1, the receiving pin pair RX1, and the receiving pin pair of the USB connector 110. The sending pin is paired with TX2 and the receiving pin is paired with RX2. When the USB core circuit 220 does not use the sending pin pair TX1, the receiving pin pair RX1, the sending pin pair TX2 and the receiving pin pair RX2, and the equalizer 232, the equalizer 234, the equalizer 236 and the equalizer When 238 is disabled, the USB core circuit 220 can enable buffer B1, buffer B2, buffer B3, buffer B4, equalizer 231, and equalizer 233 in the second operation mode (ALT mode). , equalizer 235, equalizer 237, pre-driver 241_1, pre-driver 241_3, pre-driver 241_5, and pre-driver 241_7. When the USB core circuit 220 does not use the sending pin pair TX1, the receiving pin pair RX1, the sending pin pair TX2 and the receiving pin pair RX2, and the equalizer 231, the equalizer 233, the equalizer 235 and the equalizer When 237 is disabled, the USB core circuit 220 can enable buffer B1, buffer B2, buffer B3, buffer B4, equalizer 232, and equalizer 234 in the second operation mode (ALT mode). , equalizer 236, equalizer 238, pre-driver 241_2, pre-driver 241_4, pre-driver 241_6, and pre-driver 241_8.

在其他模式中（既不是USB 4.0模式也不是ALT模式），USB核心電路220可以禁能緩衝器B1、緩衝器B2、緩衝器B3、緩衝器B4、等化器231～238以及預驅動器241_1～241_8。In other modes (neither USB 4.0 mode nor ALT mode), USB core circuit 220 can disable buffer B1, buffer B2, buffer B3, buffer B4, equalizers 231-238 and pre-drivers 241_1- 241_8.

依照不同的設計需求，上述USB介面電路210、USB核心電路220、切換電路230以及（或是）DP介面電路240的方塊的實現方式可以是硬體（hardware）、韌體（firmware）、軟體（software，即程式）或是前述三者中的多者的組合形式。According to different design requirements, the above-mentioned USB interface circuit 210, USB core circuit 220, switching circuit 230 and (or) DP interface circuit 240 may be realized in hardware, firmware, software ( software, that is, a program) or a combination of more of the above three.

以硬體形式而言，上述USB介面電路210、USB核心電路220、切換電路230以及（或是）DP介面電路240的方塊可以實現於積體電路（integrated circuit）上的邏輯電路。上述USB介面電路210、USB核心電路220、切換電路230以及（或是）DP介面電路240的相關功能可以利用硬體描述語言（hardware description languages，例如Verilog HDL或VHDL）或其他合適的編程語言來實現為硬體。舉例來說，上述USB介面電路210、USB核心電路220、切換電路230以及（或是）DP介面電路240的相關功能可以被實現於一或多個控制器、微控制器、微處理器、特殊應用積體電路（Application-specific integrated circuit, ASIC）、數位訊號處理器（digital signal processor, DSP）、場可程式邏輯閘陣列（Field Programmable Gate Array, FPGA）及/或其他處理單元中的各種邏輯區塊、模組和電路。In terms of hardware, the aforementioned blocks of the USB interface circuit 210 , the USB core circuit 220 , the switching circuit 230 and (or) the DP interface circuit 240 may be implemented as logic circuits on an integrated circuit. The relevant functions of the above-mentioned USB interface circuit 210, USB core circuit 220, switching circuit 230, and (or) DP interface circuit 240 can be implemented using hardware description languages (hardware description languages, such as Verilog HDL or VHDL) or other suitable programming languages. Implemented as hardware. For example, the relevant functions of the above-mentioned USB interface circuit 210, USB core circuit 220, switching circuit 230, and (or) DP interface circuit 240 may be implemented in one or more controllers, microcontrollers, microprocessors, special Various logic in application-specific integrated circuit (ASIC), digital signal processor (DSP), field programmable gate array (Field Programmable Gate Array, FPGA) and/or other processing units Blocks, modules and circuits.

以軟體形式及/或韌體形式而言，上述USB介面電路210、USB核心電路220、切換電路230以及（或是）DP介面電路240的相關功能可以被實現為編程碼（programming codes）。例如，利用一般的編程語言（programming languages，例如C、C++或組合語言）或其他合適的編程語言來實現上述USB介面電路210、USB核心電路220、切換電路230以及（或是）DP介面電路240。所述編程碼可以被記錄/存放在記錄媒體中，所述記錄媒體中例如包括唯讀記憶體（Read Only Memory，ROM）、存儲裝置及/或隨機存取記憶體（Random Access Memory，RAM）。電腦、中央處理器（Central Processing Unit，CPU）、控制器、微控制器或微處理器可以從所述記錄媒體中讀取並執行所述編程碼，從而達成相關功能。作為所述記錄媒體，可使用「非臨時的電腦可讀取媒體（non-transitory computer readable medium）」，例如可使用帶（tape）、碟（disk）、卡（card）、半導體記憶體、可程式設計的邏輯電路等。而且，所述程式也可經由任意傳輸媒體（通信網路或廣播電波等）而提供給所述電腦（或CPU）。所述通信網路例如是互聯網（Internet）、有線通信（wired communication）、無線通信（wireless communication）或其它通信介質。In terms of software and/or firmware, the related functions of the USB interface circuit 210 , the USB core circuit 220 , the switching circuit 230 and/or the DP interface circuit 240 may be implemented as programming codes. For example, the USB interface circuit 210, the USB core circuit 220, the switch circuit 230, and (or) the DP interface circuit 240 may be implemented using general programming languages (such as C, C++ or assembly language) or other suitable programming languages. . The programming code can be recorded/stored in a recording medium, which includes, for example, a read-only memory (Read Only Memory, ROM), a storage device, and/or a random access memory (Random Access Memory, RAM) . A computer, a central processing unit (Central Processing Unit, CPU), a controller, a microcontroller or a microprocessor can read and execute the programming code from the recording medium, so as to achieve related functions. As the recording medium, "non-transitory computer readable medium" can be used, for example, a tape, a disk, a card, a semiconductor memory, etc. can be used. Programmed logic circuits, etc. Furthermore, the program may be provided to the computer (or CPU) via any transmission medium (communication network, broadcast wave, etc.). The communication network is, for example, the Internet (Internet), wired communication (wired communication), wireless communication (wireless communication) or other communication media.

綜上所述，上述諸實施例將切換電路230配置在連接介面轉換晶片200中。當USB連接器110的訊號是符合USB規格的ALT模式的訊號時，切換電路230可以經過USB介面電路210接收USB連接器110的DP資料，以及（或是）USB核心電路220可以經過USB介面電路110接收USB連接器110的USB訊號。然後，切換電路230可以將DP資料經過DP介面電路240傳輸至DP連接器120。當USB連接器110的訊號是符合USB 4.0規格的顯示埠穿隧（DP Tunneling）協定的USB訊號時，USB核心電路220可以經過USB介面電路210接收USB連接器110的至少一USB訊號對並且對所述USB訊號對進行解碼以獲得DP資料。然後，USB核心電路220可以將DP資料經過DP介面電路240傳輸至DP連接器120。亦即，切換電路230不需要處理高頻寬的USB 4.0訊號，因此切換電路230的成本可以盡可能的降低。連接介面轉換晶片200（連接介面轉換裝置100）可以處理USB連接器110的訊號，而不論USB連接器110的訊號是ALT模式的訊號或是符合USB 4.0的顯示埠穿隧協定的訊號。To sum up, in the above-mentioned embodiments, the switch circuit 230 is configured in the connection interface conversion chip 200 . When the signal of the USB connector 110 is an ALT mode signal conforming to the USB specification, the switching circuit 230 can receive the DP data of the USB connector 110 through the USB interface circuit 210, and (or) the USB core circuit 220 can pass through the USB interface circuit. 110 receives the USB signal from the USB connector 110 . Then, the switching circuit 230 can transmit the DP data to the DP connector 120 through the DP interface circuit 240 . When the signal of the USB connector 110 is a USB signal conforming to the DP Tunneling protocol of the USB 4.0 specification, the USB core circuit 220 can receive at least one pair of USB signals of the USB connector 110 through the USB interface circuit 210 and send the The USB signal pair is decoded to obtain DP data. Then, the USB core circuit 220 can transmit the DP data to the DP connector 120 through the DP interface circuit 240 . That is, the switching circuit 230 does not need to process high-bandwidth USB 4.0 signals, so the cost of the switching circuit 230 can be reduced as much as possible. The connection interface conversion chip 200 (connection interface conversion device 100 ) can process the signal of the USB connector 110 , regardless of whether the signal of the USB connector 110 is an ALT mode signal or a display port tunneling protocol compliant signal of USB 4.0.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

20:主機 21、110:通用序列匯流排（USB）連接器 30:顯示埠（DP）裝置 31、120:DP連接器 100:連接介面轉換裝置 130:電力傳輸（PD）控制器 200:連接介面轉換晶片 210:USB介面電路 211～214:介面電路 215、218:驅動器 216、217:接收器 220:USB核心電路 230:切換電路 231～238:等化器 240:DP介面電路 241_1～241_8:預驅動器 242_1～242_4:驅動器 B1～B4:緩衝器 CCa、CCb:配置通道（CC）接腳 DP0、DP1、DP2、DP3:通道腳對 RX1、RX2:接收腳對 S310～S340:步驟 TX1、TX2:發送腳對 20: Host 21, 110: Universal serial bus (USB) connector 30: Display port (DP) device 31, 120: DP connector 100: Connect the interface conversion device 130: Power Delivery (PD) Controller 200: connection interface conversion chip 210: USB interface circuit 211～214: interface circuit 215, 218: drive 216, 217: Receiver 220:USB core circuit 230: switching circuit 231～238: Equalizer 240: DP interface circuit 241_1～241_8: pre-driver 242_1～242_4: Driver B1～B4: Buffer CCa, CCb: Configuration Channel (CC) pins DP0, DP1, DP2, DP3: channel pin pair RX1, RX2: receiving pin pair S310～S340: Steps TX1, TX2: send pin pair

圖1為依照本發明實施例所繪示，連接於主機與裝置之間的一種介面轉換裝置的電路方塊（circuit block）示意圖。 圖2為依照本發明一實施例說明圖1中所繪示的連接介面轉換晶片的電路方塊示意圖。 圖3為依照本發明一實施例所繪示的一種連接介面轉換晶片的操作方法的流程示意圖。 圖4為依照本發明一實施例說明圖2中所繪示的USB介面電路的電路方塊示意圖。 圖5為依照本發明一實施例說明圖2中所繪示的切換電路與DP介面電路的電路方塊示意圖。 FIG. 1 is a schematic diagram of a circuit block of an interface conversion device connected between a host and a device according to an embodiment of the present invention. FIG. 2 is a schematic circuit block diagram illustrating the connection interface conversion chip shown in FIG. 1 according to an embodiment of the present invention. FIG. 3 is a schematic flowchart of an operation method for connecting an interface conversion chip according to an embodiment of the present invention. FIG. 4 is a schematic circuit block diagram illustrating the USB interface circuit shown in FIG. 2 according to an embodiment of the present invention. FIG. 5 is a schematic circuit block diagram illustrating the switching circuit and the DP interface circuit shown in FIG. 2 according to an embodiment of the present invention.

100:連接介面轉換裝置 100: Connect the interface conversion device

110:通用序列匯流排(USB)連接器 110: Universal serial bus (USB) connector

120:顯示埠(DP)連接器 120: Display Port (DP) connector

130:電力傳輸(PD)控制器 130: Power Delivery (PD) Controller

200:連接介面轉換晶片 200: connection interface conversion chip

210:USB介面電路 210: USB interface circuit

220:USB核心電路 220:USB core circuit

230:切換電路 230: switching circuit

240:DP介面電路 240: DP interface circuit

CCa:配置通道(CC)接腳 CCa: Configuration Channel (CC) pin

DP0、DP1、DP2、DP3:通道腳對 DP0, DP1, DP2, DP3: channel pin pair

RX1、RX2:接收腳對 RX1, RX2: receiving pin pair

TX1、TX2:發送腳對 TX1, TX2: send pin pair

Claims (28)

一種連接介面轉換晶片，包括： 一通用序列匯流排介面電路，適於耦接至一通用序列匯流排連接器； 一顯示埠介面電路，經由一顯示埠連接器耦接至一顯示埠槽裝置； 一通用序列匯流排核心電路，耦接至該通用序列匯流排介面電路與該顯示埠介面電路；以及 一切換電路，耦接至該通用序列匯流排介面電路與該顯示埠介面電路，其中該切換電路只支援一特定導通模式，該特定導通模式僅允許在該通用序列匯流排介面電路與該顯示埠介面電路之間傳輸顯示埠訊號。 A connection interface conversion chip, comprising: a universal serial bus interface circuit adapted to be coupled to a universal serial bus connector; a display port interface circuit coupled to a display port slot device via a display port connector; a USB core circuit coupled to the USB interface circuit and the DisplayPort interface circuit; and A switch circuit, coupled to the UCB interface circuit and the display port interface circuit, wherein the switch circuit only supports a specific conduction mode, and the specific conduction mode is only allowed between the UCB interface circuit and the display port Display port signals are transmitted between interface circuits. 如請求項1所述的連接介面轉換晶片，其中該通用序列匯流排連接器包括一USB-C連接器。The connection interface conversion chip as claimed in claim 1, wherein the UBS connector includes a USB-C connector. 如請求項1所述的連接介面轉換晶片，其中 在一第一操作模式中，該通用序列匯流排連接器所接收的至少一通用序列匯流排訊號對會經由該通用序列匯流排介面電路而被傳輸至該通用序列匯流排核心電路，並由該通用序列匯流排核心電路解碼出一第一顯示埠資料，該第一顯示埠資料是從該通用序列匯流排核心電路傳輸至該顯示埠介面電路而不傳輸至該切換電路，再由該顯示埠介面電路將該第一顯示埠資料傳輸至該顯示埠連接器；以及 在一第二操作模式中，該通用序列匯流排連接器所接收的至少一第二顯示埠資料會經過該通用序列匯流排介面電路、該切換電路與該顯示埠介面電路而被傳輸至該顯示埠連接器。 The connection interface conversion chip as described in claim 1, wherein In a first operation mode, at least one USB signal pair received by the USB connector is transmitted to the USB core circuit through the USB interface circuit, and is transmitted by the USB core circuit. The UBS core circuit decodes a first display port data, and the first display port data is transmitted from the UBS core circuit to the display port interface circuit but not to the switching circuit, and then transmitted from the display port the interface circuit transmits the first DisplayPort data to the DisplayPort connector; and In a second operation mode, at least one second DisplayPort data received by the USB connector is transmitted to the display via the USB interface circuit, the switching circuit and the DisplayPort interface circuit port connector. 如請求項3所述的連接介面轉換晶片，其中該第一操作模式包括符合USB 4.0規格的一顯示埠穿隧協定，而該第二操作模式包括符合USB規格的一顯示埠替代模式。The connection interface conversion chip as described in claim 3, wherein the first operation mode includes a display port tunneling protocol conforming to the USB 4.0 specification, and the second operation mode includes a display port replacement mode complying with the USB specification. 如請求項3所述的連接介面轉換晶片，其中該切換電路在該第一操作模式被禁能。The connection interface conversion chip as claimed in claim 3, wherein the switching circuit is disabled in the first operation mode. 如請求項1所述的連接介面轉換晶片，其中該通用序列匯流排介面電路適於至少耦接至該通用序列匯流排連接器的一第一發送腳對、一第一接收腳對、一第二發送腳對與一第二接收腳對，以及該顯示埠介面電路適於至少耦接至該顯示埠連接器的一第一通道腳對、一第二通道腳對、一第三通道腳對與一第四通道腳對。The connection interface conversion chip as described in claim 1, wherein the UBS interface circuit is adapted to at least be coupled to a first pair of sending pins, a first pair of receiving pins, and a first pair of pins of the UBS connector. Two pairs of sending pins and a second pair of receiving pins, and the display port interface circuit is suitable for at least being coupled to a first pair of channel pins, a second pair of channel pins, and a third pair of channel pins of the display port connector Pair with a fourth channel pin. 如請求項6所述的連接介面轉換晶片，其中在該第一操作模式中，該通用序列匯流排連接器的該第一接收腳對與該第二接收腳對所接收的該通用序列匯流排訊號對會經過該通用序列匯流排介面電路，由該通用序列匯流排核心電路解碼出該第一顯示埠資料，再由該顯示埠介面電路傳輸至該顯示埠連接器的該第一通道腳對、該第二通道腳對、該第三通道腳對與該第四通道腳對中的至少一者。The connection interface conversion chip as claimed in claim 6, wherein in the first operation mode, the universal serial bus received by the first receiving pin pair and the second receiving pin pair of the universal serial bus connector The signal pair will pass through the universal serial bus interface circuit, and the universal serial bus core circuit will decode the first display port data, and then transmit the display port interface circuit to the first channel pin pair of the display port connector , at least one of the second channel pin pair, the third channel pin pair, and the fourth channel pin pair. 如請求項6所述的連接介面轉換晶片，其中在該第二操作模式中，該通用序列匯流排連接器的該第一發送腳對、該第一接收腳對、該第二發送腳對與該第二接收腳對所接收的該至少一第二顯示埠資料會經過該通用序列匯流排介面電路、該切換電路與該顯示埠介面電路而被傳輸至該顯示埠連接器的該第一通道腳對、該第二通道腳對、該第三通道腳對與該第四通道腳對。The connection interface conversion chip as described in claim 6, wherein in the second operation mode, the first pair of sending pins, the first pair of receiving pins, the second pair of sending pins and the The at least one second display port data received by the second receiving pin pair will be transmitted to the first channel of the display port connector through the universal serial bus interface circuit, the switching circuit and the display port interface circuit The pin pair, the second channel pin pair, the third channel pin pair, and the fourth channel pin pair. 如請求項6所述的連接介面轉換晶片，其中在該第二操作模式中，該通用序列匯流排核心電路所輸出的一第一通用序列匯流排資料會經過該通用序列匯流排介面電路而被傳輸至該通用序列匯流排連接器的該第一發送腳對，該通用序列匯流排連接器的該第一接收腳對所接收的一第二通用序列匯流排資料會經過該通用序列匯流排介面電路而被傳輸至該通用序列匯流排核心電路，該通用序列匯流排連接器的該第二發送腳對與該第二接收腳對中的至少一者所接收的該至少一第二顯示埠資料會經過該通用序列匯流排介面電路、該切換電路與該顯示埠介面電路而被傳輸至該顯示埠連接器的該第一通道腳對、該第二通道腳對、該第三通道腳對與該第四通道腳對中的至少一者。The connection interface conversion chip as described in claim 6, wherein in the second operation mode, a first universal serial bus data output by the universal serial bus core circuit will be passed through the universal serial bus interface circuit transmitted to the first sending pin pair of the UBS connector, a second UBS data received by the first receiving pin pair of the UBS connector will pass through the UBS interface The at least one second display port data received by at least one of the second sending pin pair and the second receiving pin pair of the universal serial bus connector is transmitted to the UBS core circuit. will be transmitted to the first channel pin pair, the second channel pin pair, the third channel pin pair and the display port connector through the universal serial bus interface circuit, the switching circuit and the display port interface circuit At least one of the fourth channel pin pair. 如請求項6所述的連接介面轉換晶片，其中該通用序列匯流排介面電路包括： 一第一驅動器，具有一差動輸出對適於耦接至該通用序列匯流排連接器的該第一發送腳對； 一第一接收器，具有一差動輸入對適於耦接至該通用序列匯流排連接器的該第一接收腳對； 一第二驅動器，具有一差動輸出對適於耦接至該通用序列匯流排連接器的該第二發送腳對； 一第二接收器，具有一差動輸入對適於耦接至該通用序列匯流排連接器的該第二接收腳對； 一第一緩衝器，具有一差動輸入對適於耦接至該通用序列匯流排連接器的該第一發送腳對； 一第二緩衝器，具有一差動輸入對適於耦接至該通用序列匯流排連接器的該第一接收腳對； 一第三緩衝器，具有一差動輸入對適於耦接至該通用序列匯流排連接器的該第二接收腳對；以及 一第四緩衝器，具有一差動輸入對適於耦接至該通用序列匯流排連接器的該第二發送腳對。 The connection interface conversion chip as described in claim 6, wherein the universal serial bus interface circuit includes: a first driver having a differential output pair adapted to be coupled to the first transmit pin pair of the universal serial bus connector; a first receiver having a differential input pair adapted to be coupled to the first receiver pin pair of the universal serial bus connector; a second driver having a differential output pair adapted to be coupled to the second transmit pin pair of the Universal Serial Bus connector; a second receiver having a differential input pair adapted to be coupled to the second receiving pin pair of the universal serial bus connector; a first buffer having a differential input pair adapted to be coupled to the first transmit pin pair of the universal serial bus connector; a second buffer having a differential input pair adapted to be coupled to the first receive pin pair of the universal serial bus connector; a third buffer having a differential input pair adapted to be coupled to the second receiving pin pair of the universal serial bus connector; and A fourth buffer has a differential input pair adapted to be coupled to the second transmit pin pair of the USB connector. 如請求項10所述的連接介面轉換晶片，其中該第一緩衝器、該第二緩衝器、該第三緩衝器與該第四緩衝器在該第一操作模式被禁能。The connection interface conversion chip as claimed in claim 10, wherein the first buffer, the second buffer, the third buffer and the fourth buffer are disabled in the first operation mode. 如請求項10所述的連接介面轉換晶片，其中該第一緩衝器、該第二緩衝器、該第三緩衝器與該第四緩衝器中的至少一者在該第二操作模式被致能。The connection interface conversion chip as claimed in claim 10, wherein at least one of the first buffer, the second buffer, the third buffer and the fourth buffer is enabled in the second operation mode . 如請求項10所述的連接介面轉換晶片，其中該切換電路包括： 一第一等化器，具有一差動輸入對耦接至該第四緩衝器的一差動輸出對； 一第二等化器，具有一差動輸入對耦接至該第一緩衝器的一差動輸出對； 一第三等化器，具有一差動輸入對耦接至該第三緩衝器的一差動輸出對； 一第四等化器，具有一差動輸入對耦接至該第二緩衝器的一差動輸出對； 一第五等化器，具有一差動輸入對耦接至該第二緩衝器的該差動輸出對； 一第六等化器，具有一差動輸入對耦接至該第三緩衝器的該差動輸出對； 一第七等化器，具有一差動輸入對耦接至該第一緩衝器的該差動輸出對；以及 一第八等化器，具有一差動輸入對耦接至該第四緩衝器的該差動輸出對。 The connection interface conversion chip as described in claim 10, wherein the switching circuit includes: a first equalizer having a differential input pair coupled to a differential output pair of the fourth buffer; a second equalizer having a differential input pair coupled to a differential output pair of the first buffer; a third equalizer having a differential input pair coupled to a differential output pair of the third buffer; a fourth equalizer having a differential input pair coupled to a differential output pair of the second buffer; a fifth equalizer having a differential input pair coupled to the differential output pair of the second buffer; a sixth equalizer having a differential input pair coupled to the differential output pair of the third buffer; a seventh equalizer having a differential input pair coupled to the differential output pair of the first buffer; and An eighth equalizer has a differential input pair coupled to the differential output pair of the fourth buffer. 如請求項13所述的連接介面轉換晶片，其中該第一等化器、該第二等化器、該第三等化器、該第四等化器、該第五等化器、該第六等化器、該第七等化器與該第八等化器在該第一操作模式被禁能。The connection interface conversion chip as described in claim 13, wherein the first equalizer, the second equalizer, the third equalizer, the fourth equalizer, the fifth equalizer, the first equalizer, The sixth equalizer, the seventh equalizer and the eighth equalizer are disabled in the first operation mode. 如請求項13所述的連接介面轉換晶片，其中在該第二操作模式中，該第一等化器、該第三等化器、該第五等化器與該第七等化器被禁能，或是該第二等化器、該第四等化器、該第六等化器與該第八等化器被禁能。The connection interface conversion chip as claimed in claim 13, wherein in the second operation mode, the first equalizer, the third equalizer, the fifth equalizer, and the seventh equalizer are disabled enabled, or the second equalizer, the fourth equalizer, the sixth equalizer, and the eighth equalizer are disabled. 如請求項13所述的連接介面轉換晶片，其中 在該第二操作模式中以及在該第一等化器、該第三等化器、該第五等化器與該第七等化器被禁能的情況下，該第二等化器、該第四等化器、該第六等化器與該第八等化器被致能；以及 在該第二操作模式中以及在該第二等化器、該第四等化器、該第六等化器與該第八等化器被禁能的情況下，該第一等化器、該第三等化器、該第五等化器與該第七等化器被致能。 The connection interface conversion chip as described in claim 13, wherein In the second mode of operation and with the first equalizer, the third equalizer, the fifth equalizer and the seventh equalizer disabled, the second equalizer, the fourth equalizer, the sixth equalizer and the eighth equalizer are enabled; and In the second mode of operation and with the second equalizer, the fourth equalizer, the sixth equalizer and the eighth equalizer disabled, the first equalizer, The third equalizer, the fifth equalizer and the seventh equalizer are enabled. 如請求項13所述的連接介面轉換晶片，其中 在該第二操作模式中以及在該第一等化器、該第三等化器、該第五等化器與該第七等化器被禁能的情況下，該第二等化器與該第四等化器被禁能，以及該第六等化器與該第八等化器被致能；以及 在該第二操作模式中以及在該第二等化器、該第四等化器、該第六等化器與該第八等化器被禁能的情況下，該第一等化器與該第三等化器被致能，以及該第五等化器與該第七等化器被禁能。 The connection interface conversion chip as described in claim 13, wherein In the second mode of operation and with the first equalizer, the third equalizer, the fifth equalizer and the seventh equalizer disabled, the second equalizer and the fourth equalizer is disabled, and the sixth equalizer and the eighth equalizer are enabled; and In the second mode of operation and with the second equalizer, the fourth equalizer, the sixth equalizer and the eighth equalizer disabled, the first equalizer and The third equalizer is enabled, and the fifth and seventh equalizers are disabled. 如請求項13所述的連接介面轉換晶片，其中該顯示埠介面電路包括： 一第一預驅動器，具有一差動輸入對耦接至該第一等化器的一差動輸出對； 一第二預驅動器，具有一差動輸入對耦接至該第二等化器的一差動輸出對； 一第三預驅動器，具有一差動輸入對耦接至該第三等化器的一差動輸出對； 一第四預驅動器，具有一差動輸入對耦接至該第四等化器的一差動輸出對； 一第五預驅動器，具有一差動輸入對耦接至該第五等化器的該差動輸出對； 一第六預驅動器，具有一差動輸入對耦接至該第六等化器的該差動輸出對； 一第七預驅動器，具有一差動輸入對耦接至該第七等化器的該差動輸出對； 一第八預驅動器，具有一差動輸入對耦接至該第八等化器的該差動輸出對； 一第三驅動器，具有一差動輸入對耦接至該第一預驅動器的一差動輸出對以及該第二預驅動器的一差動輸出對，其中該第三驅動器的一差動輸出對適於耦接至該顯示埠連接器的該第一通道腳對； 一第四驅動器，具有一差動輸入對耦接至該第三預驅動器的一差動輸出對以及該第四預驅動器的一差動輸出對，其中該第四驅動器的一差動輸出對適於耦接至該顯示埠連接器的該第二通道腳對； 一第五驅動器，具有一差動輸入對耦接至該第五預驅動器的一差動輸出對以及該第六預驅動器的一差動輸出對，其中該第五驅動器的一差動輸出對適於耦接至該顯示埠連接器的該第三通道腳對；以及 一第六驅動器，具有一差動輸入對耦接至該第七預驅動器的一差動輸出對以及該第八預驅動器的一差動輸出對，其中該第六驅動器的一差動輸出對適於耦接至該顯示埠連接器的該第四通道腳對。 The connection interface conversion chip as described in claim 13, wherein the display port interface circuit includes: a first pre-driver having a differential input pair coupled to a differential output pair of the first equalizer; a second pre-driver having a differential input pair coupled to a differential output pair of the second equalizer; a third pre-driver having a differential input pair coupled to a differential output pair of the third equalizer; a fourth pre-driver having a differential input pair coupled to a differential output pair of the fourth equalizer; a fifth pre-driver having a differential input pair coupled to the differential output pair of the fifth equalizer; a sixth pre-driver having a differential input pair coupled to the differential output pair of the sixth equalizer; a seventh pre-driver having a differential input pair coupled to the differential output pair of the seventh equalizer; an eighth pre-driver having a differential input pair coupled to the differential output pair of the eighth equalizer; A third driver having a differential input pair coupled to a differential output pair of the first pre-driver and a differential output pair of the second pre-driver, wherein a differential output pair of the third driver is adapted to the first pair of channel pins coupled to the DisplayPort connector; A fourth driver having a differential input pair coupled to a differential output pair of the third pre-driver and a differential output pair of the fourth pre-driver, wherein a differential output pair of the fourth driver is suitable for the second channel pin pair coupled to the DisplayPort connector; A fifth driver having a differential input pair coupled to a differential output pair of the fifth pre-driver and a differential output pair of the sixth pre-driver, wherein a differential output pair of the fifth driver is adapted to on the third channel pin pair coupled to the DisplayPort connector; and A sixth driver having a differential input pair coupled to a differential output pair of the seventh pre-driver and a differential output pair of the eighth pre-driver, wherein a differential output pair of the sixth driver is suitable for The fourth channel pin pair coupled to the DisplayPort connector. 一種連接介面轉換裝置，包括： 一通用序列匯流排連接器； 一顯示埠連接器；以及 一連接介面轉換晶片，包括： 一通用序列匯流排介面電路，適於耦接至該通用序列匯流排連接器； 一顯示埠介面電路，經由該顯示埠連接器耦接至一顯示埠槽裝置； 一通用序列匯流排核心電路，耦接至該通用序列匯流排介面電路與該顯示埠介面電路；以及 一切換電路，耦接至該通用序列匯流排介面電路與該顯示埠介面電路，其中該切換電路只支援一特定導通模式，該特定導通模式僅允許在該通用序列匯流排介面電路與該顯示埠介面電路之間傳輸顯示埠訊號。 A connection interface conversion device, comprising: a universal serial bus connector; a display port connector; and A connection interface conversion chip, including: a universal serial bus interface circuit adapted to be coupled to the universal serial bus connector; a display port interface circuit coupled to a display port slot device through the display port connector; a USB core circuit coupled to the USB interface circuit and the DisplayPort interface circuit; and A switch circuit, coupled to the UCB interface circuit and the display port interface circuit, wherein the switch circuit only supports a specific conduction mode, and the specific conduction mode is only allowed between the UCB interface circuit and the display port Display port signals are transmitted between interface circuits. 如請求項19所述的連接介面轉換裝置，其中 在一第一操作模式中，該通用序列匯流排連接器所接收的至少一通用序列匯流排訊號對會經由該通用序列匯流排介面電路而被傳輸至該通用序列匯流排核心電路，並由該通用序列匯流排核心電路解碼出一第一顯示埠資料，該第一顯示埠資料是從該通用序列匯流排核心電路傳輸至該顯示埠介面電路而不傳輸至該切換電路，再由該顯示埠介面電路將該第一顯示埠資料傳輸至該顯示埠連接器；以及 在一第二操作模式中，該通用序列匯流排連接器所接收的至少一第二顯示埠資料會經過該通用序列匯流排介面電路、該切換電路與該顯示埠介面電路而被傳輸至該顯示埠連接器。 The connection interface conversion device as described in claim 19, wherein In a first operation mode, at least one USB signal pair received by the USB connector is transmitted to the USB core circuit through the USB interface circuit, and is transmitted by the USB core circuit. The UBS core circuit decodes a first display port data, and the first display port data is transmitted from the UBS core circuit to the display port interface circuit but not to the switching circuit, and then transmitted from the display port the interface circuit transmits the first DisplayPort data to the DisplayPort connector; and In a second operation mode, at least one second DisplayPort data received by the USB connector is transmitted to the display via the USB interface circuit, the switching circuit and the DisplayPort interface circuit port connector. 一種連接介面轉換晶片的操作方法，該連接介面轉換晶片包括一通用序列匯流排介面電路、一顯示埠介面電路、一通用序列匯流排核心電路與一切換電路，該通用序列匯流排介面電路適於耦接至一通用序列匯流排連接器，該顯示埠介面電路經由一顯示埠連接器耦接至一顯示埠槽裝置，以及所述操作方法包括： 在一第一操作模式中，禁能該切換電路；以及 在一第二操作模式中，該切換電路只支援一特定導通模式，該特定導通模式僅允許在該通用序列匯流排介面電路與該顯示埠介面電路之間傳輸顯示埠訊號。 An operation method for a connection interface conversion chip, the connection interface conversion chip includes a universal serial bus interface circuit, a display port interface circuit, a universal serial bus core circuit and a switching circuit, the universal serial bus interface circuit is suitable for Coupled to a Universal Serial Bus connector, the DisplayPort interface circuit is coupled to a DisplayPort device via a DisplayPort connector, and the method of operation includes: In a first mode of operation, disabling the switching circuit; and In a second operation mode, the switching circuit only supports a specific conduction mode, and the specific conduction mode only allows display port signals to be transmitted between the USB interface circuit and the display port interface circuit. 如請求項21所述的操作方法，其中 在該第一操作模式中，將該通用序列匯流排連接器所接收的至少一通用序列匯流排訊號對經由該通用序列匯流排介面電路而被傳輸至該通用序列匯流排核心電路，並由該通用序列匯流排核心電路解碼出一第一顯示埠資料，該第一顯示埠資料是從該通用序列匯流排核心電路傳輸至該顯示埠介面電路而不傳輸至該切換電路，再由該顯示埠介面電路將該第一顯示埠資料傳輸至該顯示埠連接器；以及 在該第二操作模式中，將該通用序列匯流排連接器所接收的至少一第二顯示埠資料經過該通用序列匯流排介面電路、該切換電路與該顯示埠介面電路傳輸至該顯示埠連接器。 The operation method as described in claim 21, wherein In the first operation mode, at least one USB signal pair received by the USB connector is transmitted to the USB core circuit through the USB interface circuit, and is transmitted by the USB core circuit. The UBS core circuit decodes a first display port data, and the first display port data is transmitted from the UBS core circuit to the display port interface circuit but not to the switching circuit, and then transmitted from the display port the interface circuit transmits the first DisplayPort data to the DisplayPort connector; and In the second operation mode, the at least one second display port data received by the universal serial bus connector is transmitted to the display port connection through the universal serial bus interface circuit, the switching circuit and the display port interface circuit device. 如請求項21所述的操作方法，其中該通用序列匯流排連接器包括一USB-C連接器。The operation method as claimed in claim 21, wherein the UBS connector includes a USB-C connector. 如請求項21所述的操作方法，其中該第一操作模式包括符合USB 4.0規格的一顯示埠穿隧協定，而該第二操作模式包括符合USB規格的一顯示埠替代模式。The operation method according to claim 21, wherein the first operation mode includes a display port tunneling protocol conforming to the USB 4.0 specification, and the second operation mode includes a display port replacement mode complying with the USB specification. 如請求項21所述的操作方法，其中該通用序列匯流排介面電路適於至少耦接至該通用序列匯流排連接器的一第一發送腳對、一第一接收腳對、一第二發送腳對與一第二接收腳對，以及該顯示埠介面電路適於至少耦接至該顯示埠連接器的一第一通道腳對、一第二通道腳對、一第三通道腳對與一第四通道腳對。The operation method as described in claim 21, wherein the UBS interface circuit is adapted to at least be coupled to a first sending pin pair, a first receiving pin pair, and a second sending pin pair of the UBS connector. The pin pair and a second receiving pin pair, and the DisplayPort interface circuit is suitable for being coupled to at least a first channel pin pair, a second channel pin pair, a third channel pin pair and a Fourth channel pin pair. 如請求項25所述的操作方法，更包括： 在該第一操作模式中，將該通用序列匯流排連接器的該第一接收腳對與該第二接收腳對所接收的該通用序列匯流排訊號對經過該通用序列匯流排介面電路，由該通用序列匯流排核心電路解碼出該第一顯示埠資料，再由該顯示埠介面電路傳輸至該顯示埠連接器的該第一通道腳對、該第二通道腳對、該第三通道腳對與該第四通道腳對中的至少一者。 The operation method as described in claim item 25, further comprising: In the first operation mode, the universal serial bus signal pair received by the first receiving pin pair and the second receiving pin pair of the universal serial bus connector passes through the universal serial bus interface circuit, thereby The UBS core circuit decodes the first display port data, and then transmits the display port interface circuit to the first channel pin pair, the second channel pin pair, and the third channel pin pair of the display port connector. pair with at least one of the pin pairs of the fourth channel. 如請求項25所述的操作方法，更包括： 在該第二操作模式中，將該通用序列匯流排連接器的該第一發送腳對、該第一接收腳對、該第二發送腳對與該第二接收腳對所接收的該至少一第二顯示埠資料經過該通用序列匯流排介面電路、該切換電路與該顯示埠介面電路傳輸至該顯示埠連接器的該第一通道腳對、該第二通道腳對、該第三通道腳對與該第四通道腳對。 The operation method as described in claim item 25, further comprising: In the second operation mode, at least one of the first transmit pin pair, the first receive pin pair, the second transmit pin pair, and the second receive pin pair of the UBS connector receives the at least one The second display port data is transmitted to the first channel pin pair, the second channel pin pair, and the third channel pin pair of the display port connector through the universal serial bus interface circuit, the switching circuit and the display port interface circuit pair with the fourth channel pin. 如請求項25所述的操作方法，更包括： 在該第二操作模式中，將該通用序列匯流排核心電路所輸出的一第一通用序列匯流排資料經過該通用序列匯流排介面電路傳輸至該通用序列匯流排連接器的該第一發送腳對； 在該第二操作模式中，將該通用序列匯流排連接器的該第一接收腳對所接收的一第二通用序列匯流排資料經過該通用序列匯流排介面電路傳輸至該通用序列匯流排核心電路；以及 在該第二操作模式中，將該通用序列匯流排連接器的該第二發送腳對與該第二接收腳對中的至少一者所接收的該至少一第二顯示埠資料經過該通用序列匯流排介面電路、該切換電路與該顯示埠介面電路傳輸至該顯示埠連接器的該第一通道腳對、該第二通道腳對、該第三通道腳對與該第四通道腳對中的至少一者。 The operation method as described in claim item 25, further comprising: In the second operation mode, a first universal serial bus data output by the universal serial bus core circuit is transmitted to the first sending pin of the universal serial bus connector through the universal serial bus interface circuit right; In the second operation mode, a second USB data received by the first receiving pin pair of the USB connector is transmitted to the USB core through the USB interface circuit circuits; and In the second operation mode, the at least one second DisplayPort data received by at least one of the second pair of sending pins and the pair of second receiving pins of the UBS connector passes through the UBS The first channel pin pair, the second channel pin pair, the third channel pin pair, and the fourth channel pin pair that are transmitted from the bus interface circuit, the switching circuit, and the display port interface circuit to the display port connector at least one of .
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