TW202234812A - Inverter control device, inverter circuit, motor module, and inverter control method - Google Patents

Abstract

Provided is an inverter control device which controls a three-phase inverter having a two-phase modulation scheme, wherein: the three-phase inverter comprises a first input terminal, a second input terminal, a capacitor, and three serial bodies; the inverter control device comprises a signal generation unit that generates three PWM signals to be input to the three serial bodies, respectively; the PWM signals include at least a negative-phase PWM segment to which a negative-phase PWM signal is applied; the phase of the negative-phase PWM signal is inverse of a positive-phase PWM signal; in the negative-phase PWM segment, the positive-phase PWM signal is applied to two phases among the three phases and the negative-phase PWM signal is applied to one phase among the three phases; and, in the negative-phase PWM segment, the signal generation unit selects, as a negative-phase PWM phase, the phase in which current zero-crossing will next occur when looking in the temporal axis direction.

Description

Inverter control device, inverter circuit, motor module, and inverter control method

The present invention relates to an inverter control device, an inverter circuit, a motor module and an inverter control method.

An inverter control device that controls a three-phase inverter is known (for example, Patent Document 1). In the inverter control device described in Patent Document 1, which of the two triangular waves is to be compared with each phase and which phase is fixed to the maximum value or the minimum value are determined based on the phase of the output voltage and the phase of the output current of the inverter. value to switch.

prior art literature Patent Document 1: International Publication No. 2017/34028

The technical problem to be solved by the invention However, in the inverter control device described in Patent Document 1, when the current phase is delayed with respect to the voltage phase, the memory is in twelve operating states for one rotation in electrical angle. Furthermore, when the delay of the current phase is large and the power factor is low, a different operating state is further applied. Therefore, the control of switching the operation state becomes complicated, and the control program becomes complicated. The present invention has been made in view of the above-mentioned technical problems, and an object of the present invention is to provide an inverter control device, an inverter circuit, a motor module, and an inverter control method that can simplify a control program.

Technical solutions adopted to solve technical problems An exemplary inverter control device of the present invention controls a three-phase inverter of a two-phase modulation method. The three-phase inverter includes a first input terminal, a second input terminal, a capacitor and three series bodies. A first voltage is applied to the first input terminal. A second voltage is applied to the second input terminal. The second voltage is lower than the first voltage. The capacitor is connected between the first input terminal and the second input terminal. In three of the series bodies, two semiconductor switching elements are connected in series. The inverter control device includes a signal generating unit. The signal generation unit generates three PWM signals to be input to the three series bodies, respectively. The PWM signal includes at least an inverted PWM interval to which the inverted PWM signal is applied. The inverted PWM signal is of the opposite phase with respect to the non-inverted PWM signal. The inverse-phase PWM interval is a period in which the normal-phase PWM signal is applied to two of the three phases and the inverse-phase PWM signal is applied to one of the three phases. The signal generation unit selects the phase in which the current zero-crossing point occurs next as viewed in the time axis direction in the inverse-phase PWM section as the inverse-phase PWM phase. An exemplary inverter circuit of the present invention includes the above-described inverter control device, a first input terminal, a second input terminal, a capacitor, and three series bodies. A first voltage is applied to the first input terminal. A second voltage is applied to the second input terminal. The second voltage is lower than the first voltage. The capacitor is connected between the first input terminal and the second input terminal. In three of the series bodies, two semiconductor switching elements are connected in series. An exemplary motor module of the present invention includes the above-described inverter control device, a three-phase inverter, and a three-phase motor. The three-phase inverter is controlled by the inverter control device. The three-phase inverter is in a two-phase modulation mode. The output of the inverter is input to the three-phase motor. An exemplary inverter control method of the present invention is a method of controlling a three-phase inverter of a two-phase modulation method. The three-phase inverter includes a first input terminal, a second input terminal, a capacitor and three series bodies. A first voltage is applied to the first input terminal. A second voltage is applied to the second input terminal. The second voltage is lower than the first voltage. The capacitor is connected between the first input terminal and the second input terminal. In three of the series bodies, two semiconductor switching elements are connected in series. Three PWM signals are input to the three series bodies, respectively. The PWM signal includes at least an inverted PWM interval to which the inverted PWM signal is applied. The inverted PWM signal is of the opposite phase with respect to the non-inverted PWM signal. The inverse-phase PWM interval is a period in which the normal-phase PWM signal is applied to two of the three phases and the inverse-phase PWM signal is applied to one of the three phases. The inverter control method includes a selection process in which, in the inverse PWM section, a phase that generates a current zero-crossing point next as viewed in the time axis direction is selected as an inverse PWM phase.

Invention effect According to the exemplary invention, the control program can be simplified.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the same symbols are attached to the same or equivalent parts in the drawings, and the description thereof will not be repeated.

The motor module 200 according to the embodiment of the present invention will be described with reference to FIGS. 1 and 2 . FIG. 1 is a block diagram of a motor module 200 according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing the inverter unit 110 .

As shown in FIG. 1 , the motor module 200 includes a motor driving circuit 100 and a three-phase motor M. The three-phase motor M is driven by the motor drive circuit 100 . The three-phase motor M is, for example, a brushless DC motor. The three-phase motor M has a U-phase, a V-phase, and a W-phase. In addition, the motor drive circuit 100 corresponds to an example of an "inverter circuit".

The motor drive circuit 100 controls the driving of the three-phase motor M in a two-phase modulation method. The motor drive circuit 100 includes an inverter unit 110 and an inverter control device 12 . In addition, the inverter unit 110 corresponds to an example of a "three-phase inverter".

The inverter unit 110 is controlled by the inverter control device 12 . The inverter unit 110 uses a two-phase modulation method and is three-phase. The inverter section 110 includes three output terminals 102 . The three output terminals 102 include an output terminal 102u, an output terminal 102v, and an output terminal 102w. The three output terminals 102 output three-phase output voltages and three-phase output currents to the three-phase motor M. Specifically, the output terminal 102u outputs the U-phase output voltage Vu and the U-phase output current Iu to the three-phase motor M. The output terminal 102v outputs the V-phase output voltage Vv and the V-phase output current Iv to the three-phase motor M. The output terminal 102w outputs the W-phase output voltage Vw and the W-phase output current Iw to the three-phase motor M. The output of the inverter unit 110 is input to the three-phase motor M.

As shown in FIG. 2 , the inverter unit 110 includes a first input terminal P, a second input terminal N, a capacitor C, and three series bodies 112 . The inverter section 110 also includes a DC voltage source B. In addition, the DC voltage source B may be located outside the inverter unit 110 .

The first voltage V1 is applied to the first input terminal P. As shown in FIG. The first input terminal P is connected to the DC voltage source B.

The second voltage V2 is applied to the second input terminal N. The second input terminal N is connected to the DC voltage source B. The second voltage V2 is lower than the first voltage V1.

The capacitor C is connected between the first input terminal P and the second input terminal N.

In the three series bodies 112, two semiconductor switching elements are connected in series. The semiconductor switching element is, for example, an IGBT (Insulated Gate Bipolar Transistor). In addition, the semiconductor switching element may be other transistors such as field effect transistors. The three serial bodies 112 include a serial body 112u, a serial body 112v, and a serial body 112w. The three series bodies 112 are connected in parallel with each other. One end of each of the three series bodies 112 is connected to the first input terminal P. As shown in FIG. The other end of each of the three series bodies 112 is connected to the second input terminal N. As shown in FIG. The first input terminal P side (upper side in the drawing) is the cathode, and the second input terminal N side (the lower side in the drawing) is the anode, and the rectifier elements D are connected in parallel with the semiconductor switching elements, respectively. When a field effect transistor is used as a semiconductor switching element, a parasitic diode can also be used as the above-mentioned rectifying element.

The three series bodies 112 each have a first semiconductor switching element and a second semiconductor switching element. Specifically, the series body 112u includes a first semiconductor switching element Up and a second semiconductor switching element Un. The series body 112v has a first semiconductor switching element Vp and a second semiconductor switching element Vn. The series body 112w has a first semiconductor switching element Wp and a second semiconductor switching element Wn.

The first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are connected to the first input terminal P. In other words, the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are semiconductor switching elements on the high voltage side.

The second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are connected to the second input terminal N. In other words, the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are semiconductor switching elements on the low voltage side.

The first semiconductor switching element and the second semiconductor switching element are connected at the connection point 114 . In detail, the first semiconductor switching element Up and the second semiconductor switching element Un are connected at the connection point 114u. The first semiconductor switching element Vp and the second semiconductor switching element Vn are connected at the connection point 114v. The first semiconductor switching element Wp and the second semiconductor switching element Wn are connected at the connection point 114w.

The respective connection points 114 of the three series bodies 112 are connected to the three output terminals 102 . Specifically, the connection point 114u of the series body 112u is connected to the output terminal 102u. The connection point 114v of the series body 112v is connected to the output terminal 102v. The connection point 114w of the series body 112w is connected to the output terminal 102w.

A PWM signal is input to the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp. The PWM signal is output by the signal generating unit 120 . Hereinafter, in this specification, the PWM signal input to the first semiconductor switching element Up may be referred to as "UpPWM signal". Moreover, the PWM signal input to the 1st semiconductor switching element Vp may be described as "VpPWM signal". The PWM signal input to the first semiconductor switching element Wp may be referred to as "WpPWM signal". The first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are switched on and off at a predetermined PWM cycle. For example, the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are turned on when the UpPWM signal, the VpPWM signal, and the WpPWM signal are at HIGH levels, respectively. On the other hand, the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are turned off when the UpPWM signal, the VpPWM signal, and the WpPWM signal are at a low (LOW) level, respectively.

A PWM signal is input to the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn. The PWM signal is output by the signal generating unit 120 . Hereinafter, in this specification, the PWM signal input to the second semiconductor switching element Un may be referred to as "UnPWM signal". In addition, the PWM signal input to the second semiconductor switching element Vn may be referred to as "VnPWM signal". The PWM signal input to the second semiconductor switching element Wn may be referred to as "WnPWM signal". The second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are switched on and off at a predetermined PWM cycle. For example, the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are turned on when the UpPWM signal, the VpPWM signal, and the WpPWM signal are at a high level, respectively. On the other hand, the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are turned off when the UpPWM signal, the VpPWM signal, and the WpPWM signal are at the low level, respectively.

As shown in FIG. 1 , the inverter control device 12 includes a signal generation unit 120 . The signal generation unit 120 includes a carrier generation unit 122 , a voltage command value generation unit 124 , and a comparison unit 126 . The signal generation unit 120 is a hardware circuit composed of a processor such as a CPU (Central Processing Unit), an ASIC (Application Specific Integrated Circuit), and the like. Furthermore, the processor of the signal generation unit 120 functions as the carrier generation unit 122 , the voltage command value generation unit 124 , and the comparison unit 126 by executing the computer program stored in the storage device.

The signal generation unit 120 controls the inverter unit 110 . Specifically, the signal generation unit 120 controls the inverter unit 110 by generating a PWM signal and outputting the PWM signal. More specifically, the signal generation unit 120 generates three PWM signals respectively input to the three series bodies 112 .

The carrier generation unit 122 generates a carrier signal. The carrier signal is, for example, a triangular wave. In addition, the carrier signal may be a sawtooth wave.

The voltage command value generating unit 124 generates a voltage command value. The voltage command value corresponds to the voltage value output from the motor drive circuit 100 . That is, the voltage command value generating unit 124 generates voltage values corresponding to the output voltage Vu, the output voltage Vv, and the output voltage Vw as the voltage command value.

The comparison unit 126 generates a PWM signal by comparing the carrier signal and the voltage command value.

The operation of the signal generation unit 120 will be described with reference to FIG. 3 . FIG. 3 is a graph showing output voltage and output current.

The upper graph of FIG. 3 shows the output voltage Vu, the output voltage Vv, and the output voltage Vw. In the upper graph of FIG. 3 , the output voltage Vu is shown by a solid line, the output voltage Vv is shown by a broken line, and the output voltage Vw is shown by a dashed-dotted line. The vertical axis of FIG. 3 represents the voltage value normalized by the input voltages V1-V2, and the output voltage of each phase takes a value in the range of 0 to 1. In addition, this value also represents the duty value, which is the ratio of the ON time of the first semiconductor switching element of each phase to the PWM period. The horizontal axis of FIG. 3 represents the electrical rotation angle of the motor, and the unit is degrees.

The lower graph of FIG. 3 shows the output current Iu, the output current Iv, and the output current Iw. In the lower graph of FIG. 3 , the output current Iu is shown by a solid line, the output current Iv is shown by a broken line, and the output current Iw is shown by a dashed-dotted line. The horizontal axis of FIG. 3 represents the electrical rotation angle of the motor, and the unit is degrees.

As shown in FIG. 3 , the output voltage waveform has a period during which one of the three phases is turned off and fixed. Off-fix means that the first semiconductor switching element is continuously turned off and the second semiconductor switching element is continuously turned on during a plurality of PWM periods. In detail, the output voltage Vu becomes off-fixed at an electrical angle of 210 degrees to an electrical angle of 330 degrees. The output voltage Vv becomes off-fixed at 0 degrees to 90 degrees in electrical angle and 210 degrees to 330 degrees in electrical angle. The output voltage Vw is turned off and fixed at an electrical angle of 210 degrees to an electrical angle of 330 degrees. In this specification, as shown in FIG. 3 , a modulation method in which the output voltage waveform has a period during which one of the three phases is turned off is sometimes described as a modulation method of a fixed off mode (Min type: minimum size).

As shown in FIG. 3 , the signal generation unit 120 divides the electrical angle cycle into a plurality of divided sections. The signal generation unit 120 divides one electric angle cycle into a plurality of divided sections for each current zero-crossing point. Specifically, the signal generation unit 120 divides the electrical angle cycle into a first divided section T1, a second divided section T2, a third divided section T3, a fourth divided section T4, a fifth divided section T5, and a sixth divided section T6. In this specification, the first divided section T1 , the second divided section T2 , the third divided section T3 , the fourth divided section T4 , the fifth divided section T5 , and the sixth divided section T6 are collectively referred to as divided sections T in some cases. In addition, the present invention is not limited to the case where the signal generation unit 120 divides the divided interval T completely at the current zero-crossing point. For example, the signal generation unit 120 may divide the divided section T in the vicinity of the current zero-crossing point. The detection of the current zero-crossing point can be directly observed by a technology such as a current sensor, or it can be obtained by a prediction based on an operation.

The second divided interval T2 follows the first divided interval T1. The third divided interval T3 follows the second divided interval T2. The fourth divided interval T4 follows the third divided interval T3. The fifth divided interval T5 follows the fourth divided interval T4. The sixth divided interval T6 follows the fifth divided interval T5. Here, the first divided interval T1 is an electrical angle of 20 degrees to an electrical angle of 80 degrees. The second divided interval T2 is an electrical angle of 80 degrees to an electrical angle of 140 degrees. The third divided interval T3 is an electrical angle of 140 degrees to an electrical angle of 200 degrees. The fourth divided interval T4 is an electrical angle of 200 degrees to an electrical angle of 260 degrees. The fifth divided interval T5 is an electrical angle of 260 degrees to an electrical angle of 320 degrees. The sixth divided interval T6 is an electrical angle of 320 degrees to an electrical angle of 360 degrees.

The first divided section T1 is a section in which only the output current Iv of the V-phase is negative. The second divided section T2 is a section in which only the output current Iu of the U-phase is positive. The third divided section T3 is a section in which only the output current Iw of the W-phase is negative. The fourth divided section T4 is a section in which only the output current Iv of the V-phase is positive. The fifth divided section T5 is a section in which only the output current Iu of the U-phase is negative. The sixth divided section T6 is a section in which only the output current Iw of the W-phase is positive.

The PWM signal includes at least an inverted PWM interval to which the inverted PWM signal is applied. The inverted PWM signal is of the opposite phase relative to the non-inverted PWM signal. The opposite phase means that, for example, when the U-phase and the V-phase are switched, the state where only the first semiconductor switching element Up is turned on and the state where only the first semiconductor switching element Vp is turned on exist in one PWM cycle. phase offset. More preferably, the opposite phase is expressed in that there is no state in which the first semiconductor switching element Up and the first semiconductor switching element Vp are both turned on and both the first semiconductor switching element Up and the first semiconductor switching element Vp are turned off during one PWM period state in such a way that the phase is shifted. For example, the opposite phase represents a 180 degree phase shift. In addition, it may be slightly deviated from 180 degrees. The reverse-phase PWM section is a section in which the normal-phase PWM signal is applied to two of the three phases and the reverse-phase PWM signal is applied to one of the three phases.

The signal generation unit 120 determines each of the plurality of divided sections T as any one of a normal-phase PWM section and a reverse-phase PWM section in which the normal-phase PWM signal is applied to all three phases. Here, in the first divided period T1, the third divided period T3, and the fifth divided period T5, the signal generation unit 120 applies the inverted PWM period. In the second divided period T2, the fourth divided period T4, and the sixth divided period T6, the signal generation unit 120 applies the positive-phase PWM period to all the phases.

The signal generation unit 120 selects the phase in which the current zero-cross point occurs next as viewed in the time axis direction as the inverse-phase PWM phase in the inverse-phase PWM section. In detail, in the first divided section T1 which is the inversion PWM section, the W phase that generates the current zero-crossing point next when viewed in the time axis direction is selected as the inversion PWM phase. In the third divided interval T3, which is an inversion PWM section, the U-phase that generates the current zero-crossing point next when viewed in the time axis direction is selected as the inversion PWM phase. In the fifth divided interval T5, which is an inversion PWM section, the V phase that generates the current zero-cross point next when viewed in the time axis direction is selected as the inversion PWM phase.

Then, the signal generation unit 120 switches the phase to which the reversed-phase PWM signal is applied in the reversed-phase PWM section to the normal-phase PWM signal at the current zero-cross point. The phase in which the current zero-cross point occurs is the phase with the smallest absolute value of the current observed in the time axis direction. In addition, the present invention is not limited to the fact that the signal generation unit 120 switches the phase to which the inverted PWM signal is applied in the inverted PWM section to the non-inverted PWM signal completely at the current zero-cross point. For example, the signal generation unit 120 may switch the phase to which the reversed-phase PWM signal is applied in the reversed-phase PWM section to the normal-phase PWM signal in the vicinity of the current zero-cross point. The detection of the current zero-crossing point can be directly observed by a technology such as a current sensor, or it can be obtained by a prediction based on an operation.

4 to 7C , the selection of the normal-phase PWM period and the reverse-phase PWM period by the signal generation unit 120 will be described. FIG. 4 is a graph showing output voltage and output current. 5A to 7C are diagrams for explaining the charge and discharge currents of the capacitor C. FIG.

As shown in FIG. 4 , the phases of the three-phase output currents (output current Iu, output current Iv, and output current Iw) are delayed by 20 from the phases of the three-phase output voltages (output voltage Vu, output voltage Vv, and output voltage Vw). Spend.

First, the case where the normal-phase PWMs are input to the first semiconductor switching element in the section (A) will be described. FIGS. 5A to 5C are diagrams showing a section of an electrical angle of 140 to 200 degrees in the section of (A).

As shown in FIG. 5C , a positive-phase PWM signal is input to the first semiconductor switching element Up. A positive-phase PWM signal is input to the first semiconductor switching element Vp. A low-level signal is input to the first semiconductor switching element Wp.

In the section (1) in FIG. 5C , as shown in FIG. 5A , the Up gate signal and the Vp gate signal are at the high level. Also, the Wp gate signal is at a low level. Therefore, the first semiconductor switching element Up and the first semiconductor switching element Vp are turned on, and the first semiconductor switching element Wp is turned off. On the other hand, the second semiconductor switching element Un and the second semiconductor switching element Vn are turned off, and the second semiconductor switching element Wn is turned on. Therefore, the discharge current from the capacitor C increases.

In the section (2) in FIG. 5C , as shown in FIG. 5B , the Up gate signal, the Vp gate signal, and the Wp gate signal are at the low level. Therefore, the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are turned off. On the other hand, the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are turned on. Therefore, the charging current to the capacitor C increases.

In this way, when the positive-phase PWMs are input to the first semiconductor switching element in the section (A), the discharge current from the capacitor C increases.

Next, the case where the inversion PWM is applied in the section (A) will be described. 6A to 6C are diagrams showing a section of an electrical angle of 140 to 200 degrees in the section of (A).

As shown in FIG. 6C , the inverted PWM signal is input to the first semiconductor switching element Up. A positive-phase PWM signal is input to the first semiconductor switching element Vp. A low-level signal is input to the first semiconductor switching element Wp.

In the section of (1) in FIG. 6C , as shown in FIG. 6A , the Vp gate signal is at a high level. Also, the Up gate signal and the Wp gate signal are at a low level. Therefore, the first semiconductor switching element Vp is turned on, and the first semiconductor switching element Up and the first semiconductor switching element Wp are turned off. On the other hand, the second semiconductor switching element Vn is turned off, and the second semiconductor switching element Un and the second semiconductor switching element Wn are turned on. Therefore, compared with the case of FIG. 5A , the inverter current is dispersed, and the charging and discharging current of the capacitor C can be suppressed.

In the section of (2) in FIG. 6C , as shown in FIG. 6B , the Up gate signal is at a high level. In addition, the Vp gate signal and the Wp gate signal are at a low level. Therefore, the first semiconductor switching element Up is turned on, and the first semiconductor switching element Vp and the first semiconductor switching element Wp are turned off. On the other hand, the second semiconductor switching element Un is turned off, and the second semiconductor switching element Vn and the second semiconductor switching element Wn are turned on. Therefore, compared with the case of FIG. 5B , the inverter current is dispersed, and the charging and discharging current of the capacitor C can be suppressed.

In this way, when the inversion PWM is applied in the section (A), the inverter current is dispersed, and the charging and discharging current of the capacitor C can be suppressed.

Next, the case where the inversion PWM is applied in the section (B) will be described. FIGS. 7A to 7C are diagrams showing a section of an electrical angle of 80 to 140 degrees in the section of (B).

As shown in FIG. 7C , the PWM signal of the positive phase is input to the first semiconductor switching element Up. The inverted PWM signal is input to the first semiconductor switching element Vp. A low-level signal is input to the first semiconductor switching element Wp.

In the section of (1) in FIG. 7C , as shown in FIG. 7A , the Up gate signal is at a high level. In addition, the Vp gate signal and the Wp gate signal are at a low level. Therefore, the first semiconductor switching element Up is turned on, and the first semiconductor switching element Vp and the first semiconductor switching element Wp are turned off. On the other hand, the second semiconductor switching element Un is turned off, and the second semiconductor switching element Vn and the second semiconductor switching element Wn are turned on.

In the section of (2) in FIG. 7C , as shown in FIG. 7B , the Vp gate signal is at a high level. Also, the Up gate signal and the Wp gate signal are at a low level. Therefore, the first semiconductor switching element Vp is turned on, and the first semiconductor switching element Up and the first semiconductor switching element Wp are turned off. On the other hand, the second semiconductor switching element Vn is turned off, and the second semiconductor switching element Un and the second semiconductor switching element Wn are turned on. In this case, the reverse flow of the current to the capacitor C occurs, and the charge and discharge current of the capacitor C increases. Therefore, in the section (B), it is preferable to apply a PWM waveform between normal phases as shown in FIG. 5C .

7A to 7C and FIG. 8 , the selection of the normal-phase PWM period and the reverse-phase PWM period by the signal generation unit 120 will be described. FIG. 8 is a graph showing output voltage and output current.

As shown in FIG. 8 , the phases of the three-phase output currents (output current Iu, output current Iv, and output current Iw) are delayed by 40 from the phases of the three-phase output voltages (output voltage Vu, output voltage Vv, and output voltage Vw). Spend.

When the phase delay of the three-phase output current exceeds 30 degrees, the interval (A) decreases according to the degree of the exceeding, and the interval (C) occurs. Section (C) corresponds to the period after the stationary phase switching is turned off until the current zero-crossing point occurs.

In the section of (C) with an electrical angle of 90 degrees to 100 degrees, as described with reference to FIGS. 7A to 7C , the current reverses to the capacitor C, and the charge and discharge current of the capacitor C increases. Therefore, in the section (C), it is preferable to apply a PWM waveform between normal phases as shown in FIG. 5C .

Referring to FIG. 9 , the inversion application section will be further described. FIG. 9 is a graph showing output voltage and output current. FIG. 9 is a diagram showing a case where the rotation direction of the motor M is CW rotation (clockwise rotation). That is, the rotation direction is the direction in which the electrical angle goes from 0 degrees to 360 degrees.

As shown in FIG. 9 , the phases of the three-phase output currents (output current Iu, output current Iv, and output current Iw) are delayed by 40 from the phases of the three-phase output voltages (output voltage Vu, output voltage Vv, and output voltage Vw). Spend.

In the first divided interval T1, the third divided interval T3, and the fifth divided interval T5, the inverted PWM interval is applied. As described above with reference to FIG. 3 , in the inversion PWM section, the phase that generates the current zero-cross point next as viewed in the time axis direction is selected as the inversion PWM phase. For example, in the first divided interval T1, the positive-phase PWM signal is applied to the V-phase and the U-phase of the three phases, and the reverse-phase PWM signal is applied to the W-phase of the three phases. Therefore, as shown in FIG. 9 , even when the phases of the three-phase output currents are delayed by more than 30 degrees from the three-phase output voltages, and a section (C) in which it is preferable not to apply the inverted PWM signal occurs, in (C) In the interval of (C), the W-phase to which the inverted PWM signal was applied is continuously disconnected, and in the interval of (C), the normal-phase PWM signal is automatically applied to the U-phase and V-phase that perform switching operations. Therefore, there is no need to classify cases where the current phase delay exceeds 30 degrees and when it does not. Therefore, the control program can be simplified.

In the third divided interval T3, the positive-phase PWM signal is applied to the V-phase and the W-phase of the three phases, and the reverse-phase PWM signal is applied to the U-phase of the three phases. Therefore, as in the first divided section T1 , in the section (C), the positive-phase PWM signal is automatically applied to the V-phase and the W-phase that perform switching operations.

In the fifth divided interval T5, the positive-phase PWM signal is applied to the U-phase and the W-phase of the three phases, and the reverse-phase PWM signal is applied to the V-phase of the three phases. Therefore, as in the first divided section T1 , in the section (C), the positive-phase PWM signal is automatically applied to the U-phase and the W-phase that perform switching operations.

Referring to FIG. 10 , the inversion application section will be further described. FIG. 10 is a graph showing output voltage and output current. FIG. 10 is a diagram showing a case where the rotation direction of the motor M is CCW rotation (counterclockwise rotation). That is, the rotation direction is the direction in which the electrical angle goes from 360 degrees to 0 degrees.

As shown in FIG. 10 , the phases of the three-phase output currents (output current Iu, output current Iv, and output current Iw) are delayed by 40 from the phases of the three-phase output voltages (output voltage Vu, output voltage Vv, and output voltage Vw). Spend.

In the first divided interval T1, the third divided interval T3, and the fifth divided interval T5, the inverted PWM interval is applied. As described above with reference to FIG. 3 , in the inversion PWM section, the phase that generates the current zero-cross point next as viewed in the time axis direction is selected as the inversion PWM phase. For example, in the first divided interval T1, the positive-phase PWM signal is applied to the V-phase and the W-phase of the three phases, and the reverse-phase PWM signal is applied to the U-phase of the three phases. Therefore, as shown in FIG. 10 , even when the phases of the three-phase output currents are delayed by more than 30 degrees from the three-phase output voltages, and a section (C) in which it is preferable not to apply the inverted PWM signal occurs, in (C) In the interval of (C), the U-phase to which the inverted PWM signal was applied is continuously disconnected, and in the interval of (C), the normal-phase PWM signal is automatically applied to the V-phase and W-phase that are switching. Therefore, there is no need to classify cases where the current phase delay exceeds 30 degrees and when it does not. Therefore, the control program can be simplified.

In the third divided interval T3, the positive-phase PWM signal is applied to the U-phase and the W-phase of the three phases, and the reverse-phase PWM signal is applied to the V-phase of the three phases. Therefore, as in the first divided section T1 , in the section (C), the positive-phase PWM signal is automatically applied to the U-phase and the W-phase that perform switching operations.

In the fifth divided interval T5, the positive-phase PWM signal is applied to the U-phase and the V-phase of the three phases, and the reverse-phase PWM signal is applied to the W-phase of the three phases. Therefore, as in the first divided section T1 , in the section (C), the positive-phase PWM signal is automatically applied to the U-phase and the V-phase that perform switching operations.

As described with reference to FIGS. 9 and 10 , the inverter control device 12 can change the order of the phases of the three-phase output waveforms. Therefore, the degree of freedom of control can be improved. When the motor is driven, the rotation direction of the motor can be switched.

Then, the signal generation unit 120 switches the phase to which the reversed-phase PWM signal is applied in the reversed-phase PWM section to the normal-phase PWM signal at the current zero-cross point. Therefore, the control program can be simplified.

Then, the signal generation unit 120 determines each of the plurality of divided sections T as any one of a normal-phase PWM section and a reverse-phase PWM section in which the normal-phase PWM signal is applied to all three phases. Therefore, the control program can be simplified.

Then, the signal generation unit 120 divides one electric angle cycle into divided sections T for each current zero-crossing point. Therefore, the control program can be simplified.

Then, the signal generation unit 120 divides the electrical angle cycle into a first divided section T1, a second divided section T2, a third divided section T3, a fourth divided section T4, a fifth divided section T5, and a sixth divided section T6. Therefore, the control program can be simplified.

Furthermore, in the first divided period T1 , the third divided period T3 , and the fifth divided period T5 , the signal generation unit 120 applies the inverted PWM period. In the second divided period T2, the fourth divided period T4, and the sixth divided period T6, the signal generation unit 120 applies the positive-phase PWM period to all the phases. Therefore, the off-fixed mode (Min type) can be controlled.

Next, another example of the operation of the signal generation unit 120 will be described with reference to FIG. 11 . FIG. 11 is a graph showing output voltage and output current.

The upper graph of FIG. 11 shows the output voltage Vu, the output voltage Vv, and the output voltage Vw. In the upper diagram of FIG. 11 , the output voltage Vu is shown by a solid line, the output voltage Vv is shown by a broken line, and the output voltage Vw is shown by a dashed-dotted line. The vertical axis of FIG. 11 represents the voltage value normalized by the input voltages V1-V2, and the output voltage of each phase takes a value in the range of 0 to 1. In addition, this value also represents the duty value, which is the ratio of the ON time of the first semiconductor switching element of each phase to the PWM period. The horizontal axis of FIG. 11 represents the electrical rotation angle of the motor, and the unit is degrees.

The lower graph of FIG. 11 shows the output current Iu, the output current Iv, and the output current Iw. In the lower graph of FIG. 11 , the output current Iu is shown by a solid line, the output current Iv is shown by a broken line, and the output current Iw is shown by a dashed-dotted line. The horizontal axis of FIG. 11 represents the electrical rotation angle of the motor, and the unit is degrees.

As shown in FIG. 11 , the output voltage waveform has a period during which one of the three phases is turned on and fixed. On-fix means that the first semiconductor switching element is continuously turned on and the second semiconductor switching element is continuously turned off during a plurality of PWM periods. Specifically, the output voltage Vu becomes on-fixed at an electrical angle of 30 degrees to an electrical angle of 150 degrees. The output voltage Vv becomes on-fixed at an electrical angle of 150 degrees to an electrical angle of 270 degrees. The output voltage Vw becomes on-fixed at 0 degrees to 30 degrees in electrical angle and 270 degrees to 360 degrees in electrical angle. In this specification, as shown in FIG. 11 , the modulation method in which the output voltage waveform has a period during which one of the three phases is turned on is sometimes described as the modulation method of the on-fixed mode (Max type: maximum type).

In the present embodiment, in the second divided period T2, the fourth divided period T4, and the sixth divided period T6, the signal generation unit 120 applies the inverted PWM period. In the first divided interval T1, the third divided interval T3, and the fifth divided interval T5, the normal-phase PWM interval is applied. Therefore, the ON fixed mode (Max type) can be controlled.

In the present embodiment, the signal generation unit 120 also selects the phase in which the current zero-cross point occurs next as viewed in the time axis direction as the inverse PWM phase in the inverse PWM section. In detail, in the second divided section T2 which is the inversion PWM section, the V phase which generates the current zero-crossing point next as viewed in the time axis direction is selected as the inversion PWM phase. In the fourth divided interval T4, which is an inverted PWM interval, the W phase that generates the current zero-crossing point next when viewed in the time axis direction is selected as the inverted PWM phase. In the sixth divided interval T6, which is an inversion PWM section, the U-phase that generates the current zero-cross point next when viewed in the time axis direction is selected as the inversion PWM phase.

In the on-fixed mode (Max type), there is also no need to classify the cases when the current phase delay exceeds 30 degrees and when it does not. Therefore, the control program can be simplified.

Next, another example of the operation of the signal generation unit 120 will be described with reference to FIG. 12 . FIG. 12 is a graph showing output voltage and output current.

The upper graph of FIG. 12 shows the output voltage Vu, the output voltage Vv, and the output voltage Vw. In the upper graph of FIG. 12 , the output voltage Vu is shown by a solid line, the output voltage Vv is shown by a broken line, and the output voltage Vw is shown by a dashed-dotted line. The vertical axis of FIG. 12 represents the voltage value normalized by the input voltages V1-V2, and the output voltage of each phase takes a value in the range of 0 to 1. In addition, this value also represents the duty value, which is the ratio of the ON time of the first semiconductor switching element of each phase to the PWM period. The horizontal axis of FIG. 12 represents the electrical rotation angle of the motor, and the unit is degrees.

The lower graph of FIG. 12 shows the output current Iu, the output current Iv, and the output current Iw. In the lower graph of FIG. 12 , the output current Iu is shown by a solid line, the output current Iv is shown by a broken line, and the output current Iw is shown by a dashed-dotted line. The horizontal axis of FIG. 12 represents the electrical rotation angle of the motor, and the unit is degrees.

As shown in FIG. 12 , the output voltage waveform has a period during which one of the three phases is fixed on and a period during which one of the three phases is fixed off. In detail, the output voltage Vu becomes on-fixed at an electrical angle of 80 degrees to an electrical angle of 140 degrees. The output voltage Vu is turned off and fixed at an electrical angle of 260 degrees to an electrical angle of 320 degrees. The output voltage Vv becomes on-fixed at an electrical angle of 200 degrees to an electrical angle of 260 degrees. The output voltage Vv becomes an off-fix at an electrical angle of 20 degrees to an electrical angle of 80 degrees. The output voltage Vw becomes on-fixed at 0 degrees to 20 degrees in electrical angle and 320 degrees to 360 degrees in electrical angle. The output voltage Vw is turned off and fixed at an electrical angle of 140 degrees to an electrical angle of 200 degrees. As shown in FIG. 12 , the modulation method in which the output voltage waveform has a period during which one of the three phases is fixed on and a period during which one phase of the three phases is fixed off is sometimes described as an on-off fixed mode. (Max-Min type: minimum-maximum type) modulation method. The modulation method of the on-off fixed mode (Max-Min type) is a modulation mode in which the on fixed mode (Max type) and the off fixed mode (Min type) are switched every 60 degree interval.

The charging and discharging current of the capacitor C will be described with reference to FIGS. 12 to 14C . 13A to 14C are diagrams for explaining charge and discharge currents of the capacitor C. FIG.

As shown in FIG. 12 , the phases of the three-phase output currents (output current Iu, output current Iv, and output current Iw) are delayed by 20 from the phases of the three-phase output voltages (output voltage Vu, output voltage Vv, and output voltage Vw). Spend.

First, the case where inversion PWM is applied in the section (A) will be described. 13A to 13C are diagrams showing a section of an electrical angle of 140 to 200 degrees in the section of (A).

As shown in FIG. 13C, the PWM signal of the normal phase is input to the first semiconductor switching element Vp. The inverted PWM signal is input to the first semiconductor switching element Up. A low-level signal is input to the first semiconductor switching element Wp.

In the section of (1) in FIG. 13C , as shown in FIG. 13A , the Vp gate signal is at a high level. Also, the Up gate signal and the Wp gate signal are at a low level. Therefore, the first semiconductor switching element Vp is turned on, and the first semiconductor switching element Up and the first semiconductor switching element Wp are turned off. On the other hand, the second semiconductor switching element Vn is turned off, and the second semiconductor switching element Un and the second semiconductor switching element Wn are turned on. Therefore, compared with the case of FIG. 5A , the inverter current is dispersed, and the charging and discharging current of the capacitor C can be suppressed.

In the case of the modulation method of the ON-OFF fixed mode (Max-Min type), not only inversion PWM is applied in the section (A), but also inversion PWM is applied in the section (B).

Next, the case where the inversion PWM is applied in the section (B) will be described. FIGS. 14A to 14C are diagrams showing the sections of the electrical angle of 0 to 20 degrees and the sections of 320 to 360 degrees in the section (B).

As shown in FIG. 14C, the PWM signal of the positive phase is input to the first semiconductor switching element Vp. The inverted PWM signal is input to the first semiconductor switching element Up. A low-level signal is input to the first semiconductor switching element Wp.

In the section (1) in FIG. 14C , as shown in FIG. 14A , the Vp gate signal and the Wp gate signal are at the high level. Also, the Up gate signal is at a low level. Therefore, the first semiconductor switching element Vp and the first semiconductor switching element Wp are turned on, and the first semiconductor switching element Up is turned off. On the other hand, the second semiconductor switching element Vn and the second semiconductor switching element Wn are turned off, and the second semiconductor switching element Un is turned on. In this case, a backflow current to the capacitor C does not occur. Therefore, the charge and discharge current of the capacitor C can be suppressed.

In the section (2) in FIG. 14C , as shown in FIG. 14B , the Up gate signal and the Wp gate signal are at the high level. Also, the Vp gate signal is low. Therefore, the first semiconductor switching element Up and the first semiconductor switching element Wp are turned on, and the first semiconductor switching element Vp is turned off. On the other hand, the second semiconductor switching element Un and the second semiconductor switching element Wn are turned off, and the second semiconductor switching element Vn is turned on. In this case, the reverse flow of the current to the capacitor C occurs, and the charge and discharge current of the capacitor C increases. In this case, a backflow current to the capacitor C does not occur. Therefore, the charge and discharge current of the capacitor C can be suppressed.

Referring to FIG. 15 , the inversion application section will be described. FIG. 15 is a graph showing output voltage and output current. FIG. 15 is a diagram showing a case where the rotation direction of the motor M is CW rotation (clockwise rotation). That is, the rotation direction is the direction in which the electrical angle goes from 0 degrees to 360 degrees.

As shown in FIG. 15 , the phases of the three-phase output currents (output current Iu, output current Iv, and output current Iw) are delayed by 40 from the phases of the three-phase output voltages (output voltage Vu, output voltage Vv, and output voltage Vw). Spend.

In the first divided period T1, the second divided period T2, the third divided period T3, the fourth divided period T4, the fifth divided period T5, and the sixth divided period T6, the signal generation unit 120 applies the inverted PWM period. Therefore, the ON-OFF fixed mode (Min-Max type) can be controlled.

In the inverting PWM section, the phase that produces the current zero-crossing point in the time axis direction is selected as the inverting PWM phase. For example, in the first divided interval T1, the positive-phase PWM signal is applied to the V-phase and the U-phase of the three phases, and the reverse-phase PWM signal is applied to the W-phase of the three phases. In the second divided interval T2, the positive-phase PWM signal is applied to the U-phase and the W-phase of the three phases, and the reverse-phase PWM signal is applied to the V-phase of the three phases. In the third divided interval T3, the positive-phase PWM signal is applied to the V-phase and the W-phase of the three phases, and the reverse-phase PWM signal is applied to the U-phase of the three phases. In the fourth divided interval T4, the positive-phase PWM signal is applied to the V-phase and the U-phase of the three phases, and the reverse-phase PWM signal is applied to the W-phase of the three phases. In the fifth divided interval T5, the positive-phase PWM signal is applied to the U-phase and the W-phase of the three phases, and the reverse-phase PWM signal is applied to the V-phase of the three phases. In the sixth divided interval T6, the positive-phase PWM signal is applied to the V-phase and the W-phase of the three phases, and the reverse-phase PWM signal is applied to the U-phase of the three phases.

The inverter control device 12 includes an ON fixed mode (Max type) and an OFF fixed mode (Min type). The signal generation unit 120 switches between the ON fixed mode (Max type) and the OFF fixed mode (Min type) every time the current zero crosses. Therefore, the control program can be simplified. In the present embodiment, the waveform of the ON fixed pattern (Max type) is applied to the divided section T in which only one phase is a positive current. Specifically, in the present embodiment, the waveform of the ON fixed pattern (Max type) is applied to the second divided section T2 , the fourth divided section T4 , and the sixth divided section T6 . On the other hand, the waveform of the off-fixed pattern (Min type) is applied to the divided section T in which only one phase is negative current. Specifically, in the present embodiment, the waveform of the off-fixed pattern (Min type) is applied to the first divided section T1 , the third divided section T3 , and the fifth divided section T5 .

In the present embodiment, even when the phases of the three-phase output currents are delayed by more than 30 degrees from the three-phase output voltages and the interval (C) occurs, the backflow current to the capacitor C can be suppressed. Therefore, there is no need to classify cases where the current phase delay exceeds 30 degrees and when it does not. Therefore, the control program can be simplified.

Referring to FIG. 16 , the inversion application section will be further described. FIG. 16 is a graph showing output voltage and output current. FIG. 16 is a diagram showing a case where the rotation direction of the motor M is CCW rotation (counterclockwise rotation). That is, the rotation direction is the direction in which the electrical angle goes from 360 degrees to 0 degrees.

As shown in FIG. 16 , the phases of the three-phase output currents (output current Iu, output current Iv, and output current Iw) are delayed by 40 from the phases of the three-phase output voltages (output voltage Vu, output voltage Vv, and output voltage Vw). Spend.

In the first divided period T1, the second divided period T2, the third divided period T3, the fourth divided period T4, the fifth divided period T5, and the sixth divided period T6, the signal generation unit 120 applies the inverted PWM period.

In the inverting PWM section, the phase that produces the current zero-crossing point in the time axis direction is selected as the inverting PWM phase. For example, in the first divided interval T1, the positive-phase PWM signal is applied to the V-phase and the W-phase of the three phases, and the reverse-phase PWM signal is applied to the U-phase of the three phases. In the second divided interval T2, the positive-phase PWM signal is applied to the U-phase and the V-phase of the three phases, and the reverse-phase PWM signal is applied to the W-phase of the three phases. In the third divided interval T3, the positive-phase PWM signal is applied to the U-phase and the W-phase of the three phases, and the reverse-phase PWM signal is applied to the V-phase of the three phases. In the fourth divided interval T4, the positive-phase PWM signal is applied to the V-phase and the W-phase of the three phases, and the reverse-phase PWM signal is applied to the U-phase of the three phases. In the fifth divided interval T5, the positive-phase PWM signal is applied to the U-phase and the V-phase of the three phases, and the reverse-phase PWM signal is applied to the W-phase of the three phases. In the sixth divided interval T6, the positive-phase PWM signal is applied to the U-phase and the W-phase of the three phases, and the reverse-phase PWM signal is applied to the V-phase of the three phases.

The inverter control device 12 includes an ON fixed mode (Max type) and an OFF fixed mode (Min type). The signal generation unit 120 switches between the ON fixed mode (Max type) and the OFF fixed mode (Min type) every time the current zero crosses. In the present embodiment, the waveform of the ON fixed pattern (Max type) is applied to the divided section T in which only one phase is a positive current. Specifically, in the present embodiment, the waveform of the ON fixed pattern (Max type) is applied to the second divided section T2 , the fourth divided section T4 , and the sixth divided section T6 . On the other hand, the waveform of the off-fixed pattern (Min type) is applied to the divided section T in which only one phase is negative current. Specifically, in the present embodiment, the waveform of the off-fixed pattern (Min type) is applied to the first divided section T1 , the third divided section T3 , and the fifth divided section T5 .

In the present embodiment, even when the phases of the three-phase output currents are delayed by more than 30 degrees from the three-phase output voltages and the interval (C) occurs, the backflow current to the capacitor C can be suppressed. Therefore, there is no need to classify cases where the current phase delay exceeds 30 degrees and when it does not. Therefore, the control program can be simplified.

Referring to FIG. 17 , the inversion application section will be further described. FIG. 17 is a diagram showing a section to which the inverted PWM is applied and the phase to which the inverted PWM signal is applied in each divided section.

As shown in FIG. 17 , in the CW rotation in the off-fixed mode (Min type), an inverted PWM signal is applied to the W phase in the first divided interval T1 . In the third division period T3, an inverted PWM signal is applied to the U-phase. In the fifth division period T5, an inverted PWM signal is applied to the V phase.

In the CCW rotation in the off-fixed mode (Min type), an inverted PWM signal is applied to the U-phase in the first divided interval T1. In the third division period T3, an inverted PWM signal is applied to the V phase. In the fifth division period T5, an inverted PWM signal is applied to the W phase.

In the CW rotation in the ON fixed mode (Max type), an inverted PWM signal is applied to the V phase in the second divided section T2. In the fourth division period T4, an inverted PWM signal is applied to the W phase. In the sixth division period T6, an inverted PWM signal is applied to the U-phase.

In the CCW rotation in the ON fixed mode (Max type), an inverted PWM signal is applied to the W phase in the second divided interval T2. In the fourth division period T4, an inverted PWM signal is applied to the U-phase. In the sixth division period T6, an inverted PWM signal is applied to the V phase.

In the CW rotation of the ON-OFF fixed mode (Min-Max type), an inverted PWM signal is applied to the W phase in the first divided interval T1. In the second division period T2, an inverted PWM signal is applied to the V phase. In the third division period T3, an inverted PWM signal is applied to the U-phase. In the fourth division period T4, an inverted PWM signal is applied to the W phase. In the fifth division period T5, an inverted PWM signal is applied to the V phase. In the sixth division period T6, an inverted PWM signal is applied to the U-phase.

In the CCW rotation of the ON-OFF fixed mode (Min-Max type), an inverted PWM signal is applied to the U-phase in the first divided interval T1. In the second division period T2, an inverted PWM signal is applied to the W phase. In the third division period T3, an inverted PWM signal is applied to the V phase. In the fourth division period T4, an inverted PWM signal is applied to the U-phase. In the fifth division period T5, an inverted PWM signal is applied to the W phase. In the sixth division period T6, an inverted PWM signal is applied to the V phase.

As shown in FIG. 17 , the signal generation unit 120 applies the inverted PWM signal to different phases according to the rotation direction for the same divided period T to which the inverted PWM signal is applied. Therefore, control can be performed according to the rotation direction.

An inverter control method will be described with reference to FIG. 18 . FIG. 18 is a flowchart illustrating an inverter control method. Inverter control is performed by executing the processing of steps S102 to S118 shown in FIG. 18 . The inverter control method is a method of controlling a three-phase inverter of a two-phase modulation method.

Step S102 : The signal generation unit 120 exports the transient angle. In detail, the current rotor position (electrical angle) is exported. The process proceeds to step S104.

Step S104: The signal generation unit 120 outputs the instantaneous values of the outputs of each phase. In detail, the sine wave output voltage of each phase is calculated based on the transient angle. The process proceeds to step S106.

Step S106 : The signal generation unit 120 determines in which divided section T the transient angle is included. The process proceeds to step S108.

Step S106 : The signal generation unit 120 calculates the modulation offset amount in a variable format (Max type or Min type) corresponding to the divided interval T. That is, the duty (Duty) is exported.

Step S108 : the signal generation unit 120 selects the inversion PWM application mode according to the divided interval T and the rotation direction. Specifically, the signal generation unit 120 selects whether or not to apply the inverted PWM and which phase to apply. More specifically, the signal generation unit 120 selects the phase in which the current zero-crossing point occurs next as viewed in the time axis direction as the inverse-phase PWM phase in the inverse-phase PWM section. In addition, step S108 corresponds to an example of a "selection process". The process proceeds to step S112.

Step S112: The signal generation unit 120 judges whether or not the phase to which the inversion is applied exists. When the signal generation unit 120 determines that the phase to which the inversion is applied does not exist (step S102 : NO), the process proceeds to step S116 . When the signal generation unit 120 determines that the phase to which the inversion is applied exists (step S102 : YES), the process proceeds to step S114 .

Step S114: The signal generation unit 120 changes the Duty of the inverted PWM phase to 1-Duty. The process proceeds to step S116.

Step S116: The signal generation unit 120 sets the Duty value in the register. The process proceeds to step S118.

Step S118: The signal generation unit 120 sets the normal-phase PWM and the reverse-phase PWM. Processing ends.

As described above with reference to FIG. 18 , the inverter control method includes the selection step of selecting, as the inverse PWM phase, the phase in which the current zero-cross point occurs next when viewed in the time axis direction in the above-mentioned inverse PWM section. When the phase selected as the inverting PWM phase is fixed on or off, as in the section in (C) of FIG. 9 , FIG. 10 , FIG. 15 , and FIG. 16 , in the state where the inverting PWM phase is set, the setting is set to The Duty value to the register can be set to 1 to 0. Therefore, there is no need to classify cases where the current phase delay exceeds 30 degrees and when it does not. Therefore, the control program can be simplified.

The embodiments of the present invention have been described above with reference to the accompanying drawings ( FIGS. 1 to 18 ). However, the present invention is not limited to the above-described embodiments, and can be implemented in various forms without departing from the gist of the present invention. For ease of understanding, the drawings schematically show the main bodies of each structural element, and for the convenience of drawing, the thickness, length, number, etc. of each structural element shown in the drawings are different from actual ones. In addition, the material, shape, dimension, etc. of each constituent element shown in the above-mentioned embodiment are examples and are not particularly limited, and various changes can be made within a range that does not substantially deviate from the effects of the present invention.

industrial availability The present invention can be ideally used in an inverter control device, an inverter circuit, a motor module and an inverter control method.

12: Inverter control device 100: Motor drive circuit (inverter circuit) 102, 102u, 102v, 102w: output terminal 110: Inverter section (three-phase inverter) 112, 112u, 112v, 112w: tandem 114, 114u, 114v, 114w: Connection point 120: Signal generation section 122: Carrier generation part 124: Voltage command value generator 126: Comparison Department 200: Motor Module B: DC voltage source C: capacitor D: Rectifier element Iu, Iv, Iw: output current Vu, Vv, Vw: output voltage M: motor N: The second input terminal P: The first input terminal T: split interval T1: The first division interval T2: The second division interval T3: The third division interval T4: the fourth division interval T5: Fifth division interval T6: The sixth segment Un: Second semiconductor switching element Up: first semiconductor switching element V1: first voltage V2: The second voltage Vn: second semiconductor switching element Vp: first semiconductor switching element Wn: second semiconductor switching element Wp: first semiconductor switching element U, V, W: three-phase CW: Clockwise CCW: counterclockwise

FIG. 1 is a block diagram of a motor module according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing an inverter section FIG. 3 is a graph showing output voltage and output current. FIG. 4 is a graph showing output voltage and output current. FIG. 5A is a diagram for explaining charge and discharge currents of capacitors. FIG. 5B is a diagram for explaining charge and discharge currents of the capacitor. FIG. 5C is a diagram for explaining charge and discharge currents of the capacitor. FIG. 6A is a diagram for explaining charge and discharge currents of capacitors. FIG. 6B is a diagram for explaining charge and discharge currents of the capacitor. FIG. 6C is a diagram for explaining charge and discharge currents of the capacitor. FIG. 7A is a diagram for explaining charge and discharge currents of capacitors. FIG. 7B is a diagram for explaining charge and discharge currents of the capacitor. FIG. 7C is a diagram for explaining charge and discharge currents of the capacitor. FIG. 8 is a graph showing output voltage and output current. FIG. 9 is a graph showing output voltage and output current. FIG. 10 is a graph showing output voltage and output current. FIG. 11 is a graph showing output voltage and output current. FIG. 12 is a graph showing output voltage and output current. FIG. 13A is a diagram for explaining charge and discharge currents of capacitors. FIG. 13B is a diagram for explaining charge and discharge currents of capacitors. FIG. 13C is a diagram for explaining charge and discharge currents of the capacitor. FIG. 14A is a diagram for explaining charge and discharge currents of capacitors. FIG. 14B is a diagram for explaining charge and discharge currents of the capacitor. FIG. 14C is a diagram for explaining charge and discharge currents of the capacitor. FIG. 15 is a graph showing output voltage and output current. FIG. 16 is a graph showing output voltage and output current. FIG. 17 is a diagram showing a section to which the inverted PWM is applied and the phase to which the inverted PWM signal is applied in each divided section. FIG. 18 is a flowchart illustrating an inverter control method.

U, V, W: three-phase

CW: Clockwise

CCW: counterclockwise

Claims (14)

An inverter control device controls a three-phase inverter in a two-phase modulation mode, The three-phase inverter includes: a first input terminal to which a first voltage is applied; a second input terminal, a second voltage lower than the first voltage is applied to the second input terminal; a capacitor connected between the first input terminal and the second input terminal; and three series bodies in which two semiconductor switching elements are connected in series, The inverter control device includes a signal generation unit that generates three PWM signals respectively input to the three series bodies, The PWM signal includes at least an inverted PWM interval to which the inverted PWM signal is applied, The inverting PWM signal is in the opposite phase with respect to the non-inverting PWM signal, The inversion PWM interval is an interval in which the normal phase PWM signal is applied to two of the three phases and the inversion PWM signal is applied to one of the three phases, The signal generation unit selects the phase in which the current zero-crossing point occurs next as viewed in the time axis direction in the inverse-phase PWM section as the inverse-phase PWM phase. The inverter control device according to claim 1, wherein, The order of the phases of the output waveforms of the three phases can be changed. The inverter control device according to claim 1 or 2, wherein, The signal generation unit switches the phase to which the reversed-phase PWM signal is applied in the reversed-phase PWM section to the normal-phase PWM signal at a current zero-cross point. The inverter control device according to claim 1, wherein, The signal generation unit divides the electrical angle cycle into a plurality of divided sections, The signal generation unit determines each of the plurality of divided sections as any one of the normal-phase PWM section in which the normal-phase PWM signal is applied to all three phases and the reverse-phase PWM section. The inverter control device according to claim 4, wherein, The signal generation unit divides the electrical angle cycle into the divided sections for each of the current zero-cross points. The inverter control device according to claim 4 or 5, wherein, The signal generating unit divides the electrical angle cycle into: the first segment; a second split interval following the first split interval; a third division interval following the second division interval; a fourth division interval following the third division interval; a fifth partitioned interval following the fourth partitioned interval; and A sixth divided interval following the fifth divided interval. The inverter control device according to claim 6, wherein, In the first divided section, the third divided section and the fifth divided section, the signal generation unit applies the inversion PWM section, In the second divided period, the fourth divided period, and the sixth divided period, the signal generation unit applies the normal-phase PWM period to all the phases. The inverter control device according to claim 6, wherein, In the second divided section, the fourth divided section and the sixth divided section, the signal generation unit applies the inversion PWM section, In the first divided section, the third divided section and the fifth divided section, the normal-phase PWM section is applied. The inverter control device according to claim 6, wherein, The signal generation unit applies the inverted PWM period in the first divided section, the second divided section, the third divided section, the fourth divided section, the fifth divided section, and the sixth divided section. The inverter control device according to claim 9, wherein, Including on-fixed mode and off-fixed mode, The signal generation unit switches the on-fixed mode and the off-fixed mode for each of the current zero-cross points. The inverter control device according to claim 1, wherein, The signal generation unit applies the inverted PWM signal to different phases according to the rotation direction for the same divided section to which the inverted PWM signal is applied. An inverter circuit includes: The inverter control device of claim 1; a first input terminal to which a first voltage is applied; a second input terminal, a second voltage lower than the first voltage is applied to the second input terminal; a capacitor connected between the first input terminal and the second input terminal; and Three series bodies, in the three series bodies, two semiconductor switching elements are connected in series. A motor module, comprising: The inverter control device of claim 1; a three-phase inverter, the three-phase inverter is controlled by the inverter control device, and is a two-phase modulation method; and A three-phase motor to which the output of the inverter is input. An inverter control method, which controls a three-phase inverter in a two-phase modulation mode, The three-phase inverter includes: a first input terminal to which a first voltage is applied; a second input terminal, a second voltage lower than the first voltage is applied to the second input terminal; a capacitor connected between the first input terminal and the second input terminal; and three series bodies in which two semiconductor switching elements are connected in series, Three PWM signals are respectively input to the three said series bodies, The PWM signal includes at least an inverted PWM interval to which the inverted PWM signal is applied, The inverting PWM signal is in the opposite phase with respect to the non-inverting PWM signal, The inversion PWM interval is an interval in which the normal phase PWM signal is applied to two of the three phases and the inversion PWM signal is applied to one of the three phases, The inverter control method includes: In the selection step, in the inversion PWM section, a phase that generates a current zero-crossing point next as viewed in the time axis direction is selected as an inversion PWM phase.

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