TW202234700A - Semiconductor device including a superlattice with different non-semiconductor material monolayers and associated methods - Google Patents

Abstract

A semiconductor device may include a semiconductor substrate, and a superlattice on the semiconductor substrate and including a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A first at least one non-semiconductor monolayer may be constrained within the crystal lattice of a first pair of adjacent base semiconductor portions and comprise a first non-semiconductor material, and a second at least one non-semiconductor monolayer may be constrained within the crystal lattice of a second pair of adjacent base semiconductor portions and comprise a second non-semiconductor material different than the first non-semiconductor material.

Description

Semiconductor devices comprising superlattices having monolayers of different non-semiconductor materials and related methods

The present invention generally relates to semiconductor devices, and in particular, the present invention relates to semiconductor devices employing enhancement-mode semiconductor materials and related methods.

There have been many proposals for related structures and techniques to improve the performance of semiconductor devices, such as by enhancing the mobility of charge carriers. For example, U.S. Patent Application No. 2003/0057416 to Currie et al. discloses strained material layers of silicon, silicon-germanium, and relaxed silicon that also include impurity-free regions that would otherwise degrade performance zones). The biaxial strain in the upper silicon layer caused by these layers of strained material alters the carrier mobility, enabling higher speed and/or lower power devices. US Patent Application Publication No. 2003/0034529 to Fitzgerald et al. discloses a CMOS inverter also based on similar strained silicon technology.

US Patent No. 6,472,685 B2 to Takagi discloses a semiconductor device comprising a layer of silicon and carbon sandwiched between layers of silicon to subject the conduction and valence bands of the second silicon layer to tensile strain. In this way, electrons with smaller effective mass and induced by the electric field applied to the gate will be confined in the second silicon layer. Therefore, the N-channel MOSFET can be considered to have higher migration rate.

U.S. Patent No. 4,937,204 to Ishibashi et al. discloses a superlattice comprising a plurality of layers less than eight monolayers and containing fractional or binary semiconductors layer or a binary compound semiconductor layer, the multiple layers are alternately grown by epitaxial growth. The main current directions are perpendicular to the layers of the superlattice.

US Patent No. 5,357,119 to Wang et al. discloses a silicon-germanium short period superlattice that achieves higher mobility by reducing alloy scattering in the superlattice. Based on a similar principle, US Patent No. 5,683,934 to Candelaria discloses a MOSFET with better mobility comprising a channel layer comprising silicon alloyed with a second material that enables the The percentage of the channel layer under tensile stress is instead present in the silicon lattice.

US Patent No. 5,216,262 to Tsu discloses a quantum well structure comprising two barrier regions and a thin epitaxially grown semiconductor layer sandwiched therebetween. Each barrier region is composed of SiO2/Si monolayers with a thickness ranging approximately from two to six alternating. The barrier region is sandwiched by a much thicker silicon section.

In Applied Physics and Materials Science & Processing pp. 391 – 402, published online September 6, 2000, Tsu in an article entitled "Phenomena in Silicon Nanostructured Devices" (Phenomena in silicon nanostructure devices) discloses the semiconductor-atomic superlattice (SAS) of silicon and oxygen. The silicon/oxygen superlattice structure was revealed to be useful for silicon quantum and light-emitting devices. In particular, it is disclosed how to fabricate and test a green electroluminescence diode structure. The direction of current flow in the diode structure is vertical, ie, perpendicular to the layers of the SAS. The SAS disclosed herein may comprise semiconductor layers separated by adsorbed species, such as oxygen atoms, and CO molecules. Silicon grown outside the adsorbed oxygen monolayer is described as an epitaxial layer with a relatively low defect density. One of the SAS structures contains a 1.1 nm thick silicon portion, which is about eight atomic layers of silicon, while the other structure has a silicon portion that is twice as thick. In Physics Review Letters, Vol. 89, No. 7 (August 12, 2002), Luo et al. published an article entitled "Chemical Design of Direct Interstitial Luminescent Silicon". Direct-Gap Light-Emitting Silicon) discusses Tsu's light-emitting SAS structure further.

US Patent No. 7,105,895 to Wang et al. discloses thin silicon and oxygen, carbon, nitrogen, phosphorus, antimony, arsenic, or hydrogen barrier building blocks that reduce the current flow vertically through the lattice by more than Four orders of magnitude. Its insulating/barrier layer allows low defect epitaxial silicon to be deposited next to the insulating layer.

Published UK Patent Application No. 2,347,520 to Mears et al. discloses that aperiodic photonic band-gap (APBG) structures can be used in electronic bandgap engineering. In detail, the application discloses that material parameters, such as the location of band minima, effective mass, etc., can be adjusted to obtain new aperiodic materials with desired band structure properties. Other parameters, such as electrical conductivity, thermal conductivity, and dielectric permittivity or magnetic permeability, are disclosed and possibly engineered into the material.

In addition, US Pat. No. 6,376,337 to Wang et al. discloses a method for making an insulating or barrier layer for semiconductor devices comprising depositing a layer of silicon and at least one other element on a silicon substrate such that the deposited layer Substantially defect-free, so that substantially defect-free epitaxial silicon can be deposited on the deposition layer. Alternatively, a monolayer of one or more elements, preferably including oxygen, is absorbed on the silicon substrate. A plurality of insulating layers sandwiched between epitaxial silicon to form a barrier complex.

Despite the existence of the aforementioned methods, it is desirable to further enhance the use of advanced semiconductor materials and processing techniques in order to achieve improvements in the performance of semiconductor devices.

A semiconductor device may include a semiconductor substrate, and a superlattice on the semiconductor substrate, the superlattice comprising a plurality of stacked layer groups. Each layer group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor constrained within a lattice of adjacent base semiconductor portions single layer. The first at least one non-semiconductor monolayer constrained within the lattice of the first pair of adjacent base semiconductor portions may comprise a first non-semiconductor material and constrained to the crystals of the second pair of adjacent base semiconductor portions The second at least one non-semiconductor monolayer within the cell may comprise a second non-semiconductor material different from the first non-semiconductor material.

For example, the first non-semiconductor material can include oxygen and nitrogen, and the second non-semiconductor material can include at least one of carbon and oxygen. In an exemplary embodiment, a third at least one non-semiconductor monolayer bound within the lattice of a third pair of adjacent base semiconductor portions may comprise a different material than the first non-semiconductor material and the second non-semiconductor material. The third non-semiconductor material of the semiconductor material.

In an exemplary embodiment, the first non-semiconductor material can include nitrogen, and the first at least one non-semiconductor monolayer can be over the second at least one non-semiconductor monolayer in the superlattice. According to another example, a portion of the base semiconductor between the first at least one non-semiconductor monolayer and the second at least one non-semiconductor monolayer may include a carbon dopant. The base semiconductor monolayer may comprise, for example, silicon. The semiconductor device may further include separated source and drain regions defining a channel inside the superlattice, and a gate overlying the channel.

A method for fabricating a semiconductor device may include forming a superlattice on a semiconductor substrate, the superlattice comprising a plurality of stacked layer groups. Each layer group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor constrained within a lattice of adjacent base semiconductor portions single layer. The first at least one non-semiconductor monolayer constrained within the lattice of a first pair of adjacent base semiconductor portions may comprise a first non-semiconductor material, and constrained between a second pair of adjacent base semiconductor portions. The second at least one non-semiconductor monolayer within the crystal lattice may comprise a second non-semiconductor material different from the first non-semiconductor material.

For example, the first non-semiconductor material can include oxygen and nitrogen, and the second non-semiconductor material can include at least one of carbon and oxygen. In an exemplary embodiment, a third at least one non-semiconductor monolayer bound within the lattice of a third pair of adjacent base semiconductor portions may comprise a different material than the first non-semiconductor material and the second non-semiconductor material. The third non-semiconductor material of the semiconductor material.

In an exemplary embodiment, the first non-semiconductor material can include nitrogen, and the first at least one non-semiconductor monolayer can be over the second at least one non-semiconductor monolayer in the superlattice. According to another example, a portion of the base semiconductor between the first at least one non-semiconductor monolayer and the second at least one non-semiconductor monolayer may include a carbon dopant. The base semiconductor monolayer may comprise, for example, silicon. In an exemplary embodiment, the method may further include forming a channel of spaced source and drain regions within the superlattice, and a gate overlying the channel.

Exemplary embodiments are described in detail with reference to the accompanying drawings in the specification, in which exemplary embodiments are shown. Embodiments, however, may be embodied in many different forms and should not be construed as limited to the specific examples provided in this specification. Rather, these embodiments are provided only to make the disclosure of the present invention complete and detailed. Throughout the specification and drawings, the same drawing symbols refer to the same elements, and prime (') and double prime ('') are used to designate similar elements in different embodiments.

In general, the present invention relates to the use of enhanced superlattice material within the source and drain regions to reduce the Schottky barrier height, thereby reducing the contact resistance of the source and drain. In this specification and the accompanying drawings, the enhanced semiconductor superlattice is also referred to as the "MST" layer or "MST technology".

及

：

為電子之定義，且：

為電洞之定義，其中f為費米-狄拉克分佈(Fermi-Dirac distribution)，EF為費米能量(Fermi energy)，T為溫度，E(k,n)為電子在對應於波向量k及第n個能帶狀態中的能量，下標i及j係指直交座標x，y及z，積分係在布里羅因區(Brillouin zone，B.Z.)內進行，而加總則是在電子及電洞的能帶分別高於及低於費米能量之能帶中進行。 In particular, MST technology involves advanced semiconductor materials, such as superlattices 25, which will be described further below. It is the applicant's theory (but the applicant does not wish to be bound by this theory) that the superlattice structure described in this specification can reduce the effective mass of the charge carriers and thereby lead to higher charge carrier transport Rate. Various definitions of effective mass are described in the literature to which this invention pertains. To measure the improvement in effective mass, the applicant used the "conductivity reciprocal effective mass tensor" for electrons and holes, respectively.

and

:

is the definition of electron, and:

is the definition of a hole, where f is the Fermi-Dirac distribution, EF is the Fermi energy, T is the temperature, and E(k,n) is the electron in the corresponding wave vector k and the energy in the nth band state, the subscripts i and j refer to the orthogonal coordinates x, y and z, the integration is performed in the Brillouin zone (BZ), and the summation is performed in the electron and The energy bands of the holes are higher and lower than the Fermi energy, respectively.

The applicant defines the conductivity inverse effective mass tensor as the larger value of the corresponding component of the conductivity inverse effective mass tensor of a material, the greater the tensorial component of the conductivity. The applicant again proposes a theory (but does not wish to be bound by this theory) that the superlattice described in this specification can set the value of the conductivity inverse effective mass tensor to enhance the conductivity of the material, such as charge carrier transport The typical preferred direction. The inverse of the appropriate number of tensor terms is referred to herein as the conductivity effective mass. In other words, in order to describe the characteristics of the semiconductor material structure, as described above, the effective mass of conductivity of electrons/holes in the predetermined transport direction of carriers can be calculated, which can be used to identify the better material.

Applicants have identified improved materials or structures that can be used in semiconductor devices. More specifically, the materials or structures identified by the applicant have band structures with values of the appropriate conductive effective mass for electrons and/or holes that are substantially smaller than those corresponding to silicon. In addition to being characterized by better mobility, these structures are formed or used in such a way that they provide piezoelectric, pyroelectric and/or ferroelectric properties that are beneficial for a variety of different device type applications, as discussed further below.

Referring to Figures 1 and 2, the material or structure is in the form of a superlattice 25, the structure of which is controlled at the atomic or molecular level and can be formed using known techniques for atomic or molecular layer deposition. The superlattice 25 includes a plurality of stacked layer groups 45a-45n, as shown in the schematic cross-sectional view of FIG. 1 .

As shown, each layer group 45a-45n of the superlattice 25 includes a plurality of stacked base semiconductor monolayers 46 that define respective base semiconductor portions 46a-46n and a band modification layer 50 thereon . For clarity of presentation, the band modification layer 50 is represented by noise dots in FIG. 1 .

As shown, the band modification layer 50 comprises a non-semiconductor monolayer that is constrained within a lattice of adjacent substrate semiconductor portions. The term "constrained within a lattice of adjacent base semiconductor portions" means that at least some of the semiconductor atoms from the opposing base semiconductor portions 46a-46n pass through the non-semiconductor between the opposing base semiconductor portions Monolayer 50, chemically bonded together, as shown in FIG. In general, such a configuration may be made possible by controlling the amount of non-semiconductor material deposited over the semiconductor portions 46a-46n by atomic layer deposition techniques such that not all of the available semiconductor bond sites (ie, Incomplete or less than 100% coverage) is occupied by bonds to non-semiconductor atoms, as discussed further below. Thus, as more monolayer 46 of semiconductor material is deposited on or over a non-semiconductor monolayer 50, newly deposited semiconductor atoms can fill the remaining unoccupied semiconductor atomic bonding sites below the non-semiconductor monolayer.

In other embodiments, it is possible to use more than one such non-semiconductor monolayer. It should be noted that when this specification refers to a non-semiconductor monolayer or a semiconductor monolayer, it means that the material used in the monolayer would be a non-semiconductor or a semiconductor if it were formed on the body. That is, the properties exhibited by a single monolayer of a material (eg, silicon) are not necessarily the same as those exhibited when formed in a bulk or relatively thick layer, as will be understood by those skilled in the art to which this invention pertains.

The applicant's theory is that (but the applicant does not wish to be bound by this theory), the band modification layer 50 and the adjacent base semiconductor portions 46a-46n can make the superlattice 25 in the direction parallel to the layers, have Appropriately conductive effective mass for lower charge carriers than originally. Thinking in another way, this parallel direction is orthogonal to the stacking direction. The band modification layer 50 can also enable the superlattice 25 to have a general energy band structure, while advantageously functioning as an insulator between multiple layers or regions vertically above and below the superlattice.

Furthermore, the superlattice structure can also be advantageously used as a barrier for dopant and/or material diffusion between the layers above and below the superlattice 25 vertically. Thus, these properties may advantageously allow the superlattice 25 to provide an interface for high-k dielectrics that not only reduces diffusion of high-k material into the channel region, but also advantageously reduces unwanted scattering effects and improves the device The mobility should be understood by those skilled in the art to which the present invention pertains.

The theory of the present invention also holds that semiconductor devices including superlattice 25 may enjoy higher charge carrier mobility due to lower conductive effective mass than originally. In certain embodiments, because of the band engineering enabled by the present invention, the superlattice 25 may further have a substantially direct band gap that is particularly advantageous for, for example, optoelectronic devices.

Superlattice 25 may also include a capping layer 52 over an upper layer group 45n. The capping layer 52 may include a plurality of base semiconductor monolayers 46 . The capping layer 52 may comprise between 2 and 100 monolayers of the base semiconductor, and preferably between 10 and 50 monolayers.

Each of the base semiconductor portions 46a-46n may include a base semiconductor selected from the group consisting of group IV semiconductors, group III-V semiconductors, and group II-VI semiconductors. Of course, group IV semiconductors also include group IV-IV semiconductors, which should be understood by those skilled in the art to which the present invention pertains. In more detail, the base semiconductor may include, for example, at least one of silicon and germanium.

Each band modification layer 50 may include a non-semiconductor selected from the group consisting of, for example, oxygen, nitrogen, fluorine, carbon, and carbon-oxygen. The non-semiconductor also preferably has the property of remaining thermally stable during deposition of the next layer, thereby facilitating fabrication. In other embodiments, the non-semiconductor may be another inorganic or organic element or compound compatible with a given semiconductor process, as will be understood by those skilled in the art to which this invention pertains. In more detail, the base semiconductor may include, for example, at least one of silicon and germanium.

It should be noted that the term "monolayer" herein refers to comprising a single atomic layer, as well as comprising a single molecular layer. It should also be noted that the band-modifying layer 50 provided via a single monolayer should also include monolayers in which all possible positions in the layer are not fully occupied (ie, incomplete or less than 100% coverage). For example, referring to the atomic diagram of FIG. 2, which presents a 4/1 repeating structure with silicon as the base semiconductor material and oxygen as the band-modifying material. Only half of the possible positions for oxygen atoms are occupied.

In other embodiments and/or the use of different materials, it is not necessarily a one-half occupancy situation, as will be understood by those skilled in the art to which the present invention pertains. In fact, those skilled in the art of atomic deposition will understand that even in this schematic it can be seen that the individual oxygen atoms in a given monolayer are not exactly aligned along a flat plane. For example, a preferred occupancy is one where one-eighth to one-half of the possible sites for oxygen are filled, although other occupancies can be used in certain embodiments.

Since silicon and oxygen are now widely used in general semiconductor processes, manufacturers will be able to apply the materials described in this specification immediately. Atomic deposition or monolayer deposition is also a widely used technique. Therefore, the semiconductor device incorporating the superlattice 25 according to the present invention can be immediately adopted and implemented, as will be understood by those skilled in the art to which the present invention pertains.

Applicants theorize (but the applicant does not wish to be bound by this theory) that for a superlattice, such as the silicon/oxygen superlattice, the number of silicon monolayers should ideally be seven or less , so that the energy bands of the superlattice are common or relatively uniform everywhere to achieve the desired advantages. The silicon/oxygen 4/1 repeating structure shown in Figures 1 and 2 has been modeled to represent the preferred mobility of electrons and holes in the X-direction. For example, the calculated conductivity effective mass for electrons (isotropic with respect to the host silicon) is 0.26, and the calculated conductivity effective mass for a 4/1 silicon/oxygen superlattice in the X direction is 0.12 , the ratio of the two is 0.46. Similarly, in the calculation of holes, the value of the host silicon is 0.36, the value of the 4/1 silicon/oxygen superlattice is 0.16, and the ratio of the two is 0.44.

While this directionally preferential feature may benefit some semiconductor devices, other semiconductor devices may also benefit from a more uniform increase in mobility in any direction parallel to the layer group. An increase in the mobility of both electrons and holes at the same time, or an increase in the mobility of only one of the charge carriers, may also have benefits, as will be understood by those skilled in the art to which the present invention pertains.

The lower conductive effective mass of the 4/1 silicon/oxygen implementation of superlattice 25 may be less than two-thirds the conductive effective mass of the non-superlattice 25, and this is the case for electrons and holes All are. Of course, the superlattice 25 may further include at least one type of conductive dopant therein, as will be understood by those skilled in the art to which the present invention pertains.

Another embodiment of a superlattice 25' having different properties in accordance with the present invention will now be described with reference to FIG. In this embodiment, the repetition pattern is 3/1/5/1. In more detail, the lowermost base semiconductor portion 46a' has three monolayers, and the second lower base semiconductor portion 46b' has five monolayers. This pattern repeats throughout the superlattice 25'. Each band modification layer 50' may comprise a single monolayer. For such a superlattice 25' comprising silicon/oxygen, the increase in charge carrier mobility is independent of the orientation of the planes of the layers. Other elements in FIG. 3 that are not mentioned here are similar to those discussed above with reference to FIG. 1 , so the discussion will not be repeated.

In certain device implementations, each base semiconductor portion of its superlattice may be the same number of monolayers thick. In other embodiments, at least some of the base semiconductor portions of its superlattice may be the thickness of a different number of monolayers. In other embodiments, each base semiconductor portion of its superlattice may be a different number of monolayers thick.

4A-4C present band structures calculated using Density Functional Theory (DFT). It is well known in the art to which the present invention pertains that DFT generally underestimates the absolute value of the band gap. Therefore, all bands above the gap can be shifted with appropriate "scissors correction". However, the shape of the energy band is considered to be far more reliable. The energy of the vertical axis should be interpreted from this perspective.

FIG. 4A presents the band structures calculated from Gacode points (G) for both the host silicon (represented by the solid line) and the 4/1 silicon/oxygen superlattice 25 of FIG. 1 (represented by the dashed line). The directions in the figure refer to the unit cell of the 4/1 silicon/oxygen structure rather than the general unit cell of silicon, although the direction (001) in the figure does correspond to the general unit cell of silicon. direction (001), and thus shows the expected location of the silicon conduction band minimum. The direction (100) and the direction (010) in the figure correspond to the direction (110) and the direction (-110) of a general silicon unit cell. As will be understood by those skilled in the art to which the present invention pertains, the silicon energy bands in the figures are folded so as to be represented in the appropriate reciprocal lattice directions of the 4/1 silicon/oxygen structure.

It can be seen from the figure that, compared with the host silicon, the conduction band minimum of the 4/1 silicon/oxygen structure is located at point G, while the valence band minimum of the 4/1 silicon/oxygen structure appears at the edge of the Breroyne region in the direction (001). , which we call the Z point. We can also note that the curvature of the conduction band minimum of the 4/1 silicon/oxygen structure is larger compared to the curvature of the conduction band minimum of silicon, which is caused by the perturbation introduced by the additional oxygen layer. Because of band splitting.

Figure 4B presents the band structures calculated from the Z point for both the host silicon (solid line) and the 4/1 silicon/oxygen superlattice 25 (dashed line). This graph depicts the increasing curvature of the bid band in direction (100).

Figure 4C presents a graph of the band structures calculated from the Gacode and Z points for both the host silicon (solid line) and the 5/1/3/1 silicon/oxygen superlattice 25' (dashed line) of Figure 3 . Due to the symmetry of the 5/1/3/1 silicon/oxygen structure, the calculated band structures in the (100) and (010) directions are comparable. Thus, in a plane parallel to the layers, ie perpendicular to the stacking direction (001), the conductive effective mass and mobility can be expected to be isotropic. Note that in this 5/1/3/1 silicon/oxygen embodiment, both the conduction band minimum and the valence band maximum are at or near the Z point.

Although an increase in curvature is an indicator of a decrease in effective mass, proper comparison and discrimination can be made through the calculation of the conductivity inverse effective mass tensor. This leads the applicant of this case to further infer that the 5/1/3/1 superlattice 25' should be a direct band gap in essence. As will be understood by those skilled in the art to which the present invention pertains, the appropriate matrix element of optical transitions is another indicator for distinguishing between direct and indirect bandgap behavior.

5-9, other exemplary superlattice structures incorporating different types of non-semiconductor materials in different non-semiconductor monolayers 50 are illustrated. As a background note, Weeks et al. in US Patent Application Serial No. 16/176,005, which is assigned to the present applicant, the entire contents of which are hereby incorporated into this specification, teach a method for treating the aforementioned MST material as a A method for use as a nitrogen gettering layer. For example, by diffusing nitrogen into the MST film monolayer after epitaxial deposition, the final dose of nitrogen can be increased to greatly facilitate dopant blocking and mobility enhancement.

While this method is advantageous in many applications, it is characterized by the fact that the nitrogen implanted into the MST getter layer penetrates all non-semiconductor monolayers 50, so that in the case of a silicon/oxygen superlattice, each The non-semiconductor monolayer will contain both oxygen and nitrogen. In some instances, in addition to absorbing nitrogen within the superlattice 25, it may be desirable to confine nitrogen to certain portions or regions of the superlattice. This can be accomplished, for example, by introducing another non-semiconductor material, such as carbon, into the one or more non-semiconductor monolayers 50, or into the base silicon portions 46a-46n below the regions where nitrogen is to be confined.

In detail, in the example shown in FIG. 5 , a semiconductor (eg, silicon) substrate 121 (which may or may not be patterned) may be formed with a superlattice 125 comprising oxygen monolayers in a stacking sequence. Layer 150a, carbon-doped base silicon portion 146a, oxygen monolayer 150b, carbon-free base silicon portion 146b, oxygen monolayer 150c, and carbon-doped base silicon portion 146c. The carbon in the base silicon portion 146c can advantageously assist in blocking or blocking the diffusion of nitrogen 153 down into the monolayers 150a-150c.

In detail, during nitrogen annealing, nitrogen 153 is blocked by carbon in the base silicon portion 146c from entering the underlying oxygen monolayers 150a-150c. This allows most or all of the nitrogen to be trapped in the upper MST spacer and the intercalated MST oxygen layer. The total amount of nitrogen absorbed will be equal to the total amount of nitrogen that would be uniformly distributed over the entire stack of superlattice 125 without the carbon barrier.

Thus, the next three non-semiconductor monolayers 150d-150f in the stack (with base silicon portions 146d and 146e therebetween) contain oxygen and nitrogen. A silicon capping layer 152 may be formed on the upper non-semiconductor layer 150f and terminate in the nitride (SiN) layer 154 . The illustrated embodiment includes six non-semiconductor monolayers 150a-150f (three of which are above the last carbon implanted base silicon portion 146c), where the carbon also helps to stabilize or prevent oxygen loss, but in other Different numbers of base semiconductor portions and non-semiconductor monolayers may also be used in embodiments.

For greater nitrogen enhancement, more oxygen monolayers may be added under the carbon in some embodiments. This will allow the total amount of nitrogen 153' extracted from the surface to accumulate in the topmost oxygen monolayer above the carbon. Depending on the degree to which nitrogen 153' is deposited in the upper carbon-free base silicon portion, this method can be used to form silicon oxynitride layers or for larger quantum mechanical manipulations. Those skilled in the art of the present invention should understandable.

Reference is also made to superlattice 125' shown in Figure 6, which depicts a similar configuration in which all three lower base silicon portions 146a'-146c' comprise carbon. The upper base silicon portions 146d' to 146e' are free of carbon, while the oxygen monolayers 150d' to 150f' will receive all of the absorbed nitrogen 153' dose. Surface nitrogen 153', although attracted by all the oxygen in the entire superlattice 125' stack, cannot enter the lower oxygen monolayers 150a' to 150c' because it is blocked by carbon in the underlying silicon portions 146a' to 146c'. In another exemplary embodiment, if desired, only the base silicon portion 146c' may include carbon (ie, the base silicon portions 146a' to 146b' do not contain carbon).

Still another exemplary embodiment is described with reference to FIG. 7, wherein superlattice 225 includes substrate 221, non-semiconductor (eg, oxygen) monolayers 250a-250f, base semiconductor (eg, silicon) portions 246a-246e, semiconductor (eg, silicon) portions 246a-246e ) capping layer 252, and a nitride (eg, SiN) layer 254, similar to the previous embodiments. However, in the configuration shown in FIG. 7, the base silicon portions 246a-246e are free of carbon dopant. Instead, a carbon source gas is injected during the insertion step of the oxygen monolayer 250c so that the monolayer contains both carbon and oxygen atoms.

It should be noted that in different embodiments, carbon may be added together, after oxygen, or before oxygen. Thus, in this example, the carbon used to block the diffusion of nitrogen 253 to the lower oxygen monolayers 250a, 250b is present in monolayer 250c along with oxygen, rather than in any of the base silicon portions 246a-246e. As shown, in this example only the middle oxygen monolayer 250c contains carbon, but in different embodiments other oxygen monolayers may also contain carbon to further bind nitrogen 253 to the upper two oxygen monolayers 250e, 250f and base silicon portions 246d, 246e. In other words, all or nearly all of the dose of nitrogen 253 that would otherwise be distributed in the six oxygen monolayers 250a to 250f will be bound in the upper two oxygen monolayers 250e, 250f. The superlattice 225' shown in FIG. 8 is an example, and the bottom three oxygen monolayers 250a' to 250c' have carbon atoms inserted therein.

In yet another exemplary embodiment of the superlattice 325 depicted in FIG. 9, carbon may be inserted into the base silicon portion and the oxygen monolayer. In the illustrated embodiment, superlattice 325 includes substrate 321, non-semiconductor (eg, oxygen) monolayers 350a-350f, base semiconductor (eg, silicon) portions 346a-346e, semiconductor (eg, silicon) capping layer 352, and Nitride (eg, SiN) layer 354, similar to the previous embodiment. However, all of the lower oxygen monolayers 350a-350d and base silicon portions 346a-346c contain carbon to further trap nitrogen 353 in the upper oxygen monolayers 350e, 350f and base silicon layers 346d, 346e.

Referring now to the flowchart 400 of FIG. 10 and to FIG. 11, an exemplary method for fabricating a semiconductor device 420 including a superlattice 425 as previously described is described. Beginning at block 401, an MST superlattice process (block 402) may be performed to form a base MST structure on a semiconductor substrate 421 that is implanted or deposited on one or more base semiconductors (eg, silicon) Parts and/or non-semiconductor (eg, oxygen) monolayers have barrier materials (eg, carbon) in them. If carbon is implanted during oxygen monolayer insertion, the dose may be about 1E15 atoms/cm ² (or less) per implant, specifically about 2.5E14 atoms/cm ² per implant, for example.

If carbon is added during the formation of the base semiconductor portion, its concentration may be between 0.01 and 10 atomic percent, in particular between 0.1 and 2 atomic percent of carbon in each base silicon portion, for example, and Word. The carbon source gas may be added together with the silicon precursor gas during the chemical vapor deposition of the underlying silicon layer. Examples of gaseous carbon sources may include, for example, propylene (propylene _C3H6 ), cyclopropane ( _{C3H6 )} , and _methylsilane ( _{SiH3CH3 )} . Another approach is to implant carbon only in the lower base silicon portion, leaving the upper base silicon portion free of carbon.

As previously described, after the superlattice structure of MST process 402 is formed, additional processing steps may be performed during device process 403 to fabricate semiconductor device 420, in this example a planar MOSFET. However, those skilled in the art to which this invention pertains will appreciate that the materials and techniques discussed in this specification can be used in many different types of semiconductor devices, such as discrete devices and/or integrated circuits. As shown, MOSFET 420 includes a substrate 421, source/drain regions 422, 423, source/drain extensions 426, 427, and a superlattice 425 therebetween Access area provided. The source/drain silicide layers 430, 431 and the source/drain contacts 432, 433 are overlying the source/drain regions, which should be understood by those skilled in the art to which the present invention pertains. The regions shown by dashed lines 434, 435 are selectively residual portions that were initially formed with the superlattice 425 and later heavily doped. In other embodiments, the residual superlattice regions 434 and 435 may not exist, as will be understood by those skilled in the art to which the present invention pertains. As shown, a gate 435 includes a gate insulating layer 437 adjacent to the channel provided by the superlattice 425, and a gate electrode layer 436 overlying the gate insulating layer. As shown, MOSFET 420 also provides sidewall spacers 440, 441.

The foregoing techniques may allow the use of oxygen monolayers and/or carbon in the underlying silicon portion during nitrogen annealing to isolate some of the underlying semiconductor layers and non-semiconductor monolayers closest to the substrate from nitrogen, which attracts oxygen from the surface come. On the other hand, tempering a hydrogen-terminated MST superlattice without carbon in a nitrogen environment would result in a uniform distribution of nitrogen throughout the MST stack.

In other words, the method of the present invention utilizes carbon to block/sequester part or all of the nitrogen dose into the upper unblocked intercalated oxygen monolayer. This can advantageously increase the total nitrogen content in the upper unblocked superlattice layer. For example, a seven-layer MST superlattice stack with 1.58E15 atoms/cm ² of carbon has been shown to generate sufficient driving force to attract 0.5E15 atoms/cm ² of nitrogen during nitrogen tempering at 900 ^° C. By adding carbon to some of the lower oxygen monolayers and/or portions of the base silicon, Applicants theorize (but Applicants do not wish to be bound by this theory) that the nitrogen absorbed during the nitrogen tempering process will be affected by All oxygen is attracted in all seven monolayers/substrate silicon portions, but these nitrogens are trapped in the carbon-free upper MST layer due to carbon blocking atoms in the lower MST layer. In the seven-layer example, if the lower four oxygen monolayers and/or the base silicon portion have been doped with carbon, then nitrogen will be bound in the upper three oxygen monolayers and/or the base silicon portion, Instead, the layers receive the total dose that would otherwise be distributed throughout the seven layers.

Relative to mobility enhancement (eg, in the channel of a MOSFET transistor), the localized enhancement may be greater because of the higher nitrogen content near the surface. In silicon-on-insulator (SOI) applications, the goal may be to have a sufficient number of carbon-containing layers beneath several carbon-free layers in the MST superlattice so that the carbon-free layers can be changed due to increased nitrogen content must be insulated.

Various modifications and other embodiments will come to mind to those skilled in the art to which this invention pertains having the benefit of the teachings disclosed in this specification and the accompanying drawings. Therefore, it should be understood that the present invention is not limited to the specific embodiments described in this specification, and related modifications and embodiments all fall within the scope defined by the following claims.

21,21': Substrate 25,25': superlattice 45a~45n, 45a'~45n': layer group 46,46': base semiconductor monolayer 46a~46n, 46a'~46n': base semiconductor part 50, 50': can be modified with layers 52,52': top cover 121, 121', 221, 221', 321: Substrate 125, 125', 225, 225', 325, 425: superlattice 146a,146a',146b,146b',146c,146c',146d,146d',146e,146e',246a,246a',246b,246b',246c,246c',246d,246d',246e,246e,346a ,346b,346c,346d,346e: Base silicon part 150a,150a',150b,150b',150c,150c',150d,150d',150e,150e',150f,150f',250a,250a',250b,250b',250c,250c',250d,250d', 250e, 250e', 250f, 250f', 350a, 350b, 350c, 350d, 350e, 350f: Oxygen Monolayer 152, 152', 252, 252', 352: Cap layer 153, 153', 253, 253', 353: nitrogen 154, 154', 254, 254', 354: Nitride layer 420: Semiconductor Components 421: Semiconductor substrates 422: source region 423: drain region 426: source extension 427: drain extension 430: source silicide layer 431: drain silicide layer 432: source contact 433: Drain contact 434, 435: Residual superlattice regions 435: Gate 436: Gate electrode layer 437: gate insulating layer 440, 441: Sidewall Spacers

1 is an enlarged schematic cross-sectional view of a superlattice for a semiconductor device according to an example embodiment.

FIG. 2 is a perspective schematic atomic diagram of a portion of the superlattice shown in FIG. 1 .

3 is an enlarged schematic cross-sectional view of a superlattice according to another example embodiment.

FIG. 4A is a graph of the band structures calculated from the Gacode point (G) for both the prior art host silicon and the 4/1 silicon/oxygen superlattice shown in FIGS. 1-2.

4B is a graph of the band structures calculated from the Z point for both the conventional host silicon and the 4/1 silicon/oxygen superlattice shown in FIGS. 1-2.

FIG. 4C is a graph of the band structures calculated from the G point and the Z point for both the conventional host silicon and the 5/1/3/1 silicon/oxygen superlattice shown in FIG. 3 .

5-9 illustrate schematic cross-sectional views of superlattices having layers of distinct non-semiconductor materials in various exemplary embodiments.

10 is a flowchart illustrating a method of fabricating a semiconductor device including any of the superlattices depicted in FIGS. 5-9 according to an exemplary embodiment.

FIG. 11 shows a schematic cross-sectional view of an exemplary semiconductor device that may be fabricated according to the method of FIG. 10 .

420: Semiconductor Components

421: Semiconductor substrates

422: source region

423: drain region

426: source extension

427: drain extension

430: source silicide layer

431: drain silicide layer

432: source contact

433: Drain contact

434, 435: Residual superlattice regions

435: Gate

436: Gate electrode layer

437: gate insulating layer

440, 441: Sidewall Spacers

Claims (16)

A semiconductor element comprising: A superlattice on a semiconductor substrate, the superlattice comprising a plurality of stacked layer groups, each layer group comprising a plurality of stacked base semiconductor monolayers, defining a base semiconductor portion, and constrained in at least one non-semiconductor monolayer within a lattice of adjacent semiconductor portions of the substrate; The first at least one non-semiconductor monolayer wherein constrained within the lattice of a first pair of adjacent base semiconductor portions comprises a first non-semiconductor material, and wherein constrained between a second pair of adjacent base semiconductor portions The second at least one non-semiconductor monolayer within the crystal lattice comprises a second non-semiconductor material different from the first non-semiconductor material; and At least one of the base semiconductor portions includes carbon dopants distributed throughout the at least one base semiconductor portion. The semiconductor device of claim 1, wherein the first non-semiconductor material includes oxygen and nitrogen. The semiconductor device of claim 1, wherein the second non-semiconductor material includes at least one of carbon and oxygen. The semiconductor device of claim 1, wherein a third at least one non-semiconductor monolayer bound within the lattice of a third pair of adjacent base semiconductor portions comprises a material different from the first non-semiconductor and the second non-semiconductor The third non-semiconductor material of the material. The semiconductor device of claim 1, wherein the first non-semiconductor material comprises nitrogen, and wherein the first at least one non-semiconductor monolayer is located over the second at least one non-semiconductor monolayer in the superlattice. The semiconductor device of claim 1, wherein the at least one base silicon portion comprising carbon dopants distributed throughout the at least one base semiconductor portion is interposed between the first at least one non-semiconductor monolayer and the second at least one between a non-semiconductor monolayer. The semiconductor device of claim 1, wherein the base semiconductor monolayers comprise silicon. The semiconductor device of claim 1, further comprising separated source and drain regions formed inside the superlattice to define a channel, and a gate overlying the channel. A method for fabricating a semiconductor device, the method comprising: A superlattice is formed on a semiconductor substrate, the superlattice includes a plurality of stacked layer groups, each layer group includes a plurality of stacked base semiconductor monolayers, which define a base semiconductor portion, and are constrained at least one non-semiconductor monolayer within a lattice of adjacent substrate semiconductor portions; The first at least one non-semiconductor monolayer wherein constrained within the lattice of a first pair of adjacent base semiconductor portions comprises a first non-semiconductor material, and wherein constrained between a second pair of adjacent base semiconductor portions The second at least one non-semiconductor monolayer within the crystal lattice comprises a second non-semiconductor material different from the first non-semiconductor material; and At least one of the base semiconductor portions includes carbon dopants distributed throughout the at least one base semiconductor portion. The method of claim 9, wherein the first non-semiconductor material comprises oxygen and nitrogen. The method of claim 9, wherein the second non-semiconductor material includes at least one of carbon and oxygen. 9. The method of claim 9, wherein a third at least one non-semiconductor monolayer bound within the lattice of a third pair of adjacent semiconductor portions of the base comprises a material different from the first non-semiconductor material and the second non-semiconductor material The third non-semiconductor material. 9. The method of claim 9, wherein the first non-semiconductor material comprises nitrogen, and wherein the first at least one non-semiconductor monolayer is located over the second at least one non-semiconductor monolayer in the superlattice. The method of claim 9, wherein the at least one base silicon portion comprising carbon dopants distributed throughout the at least one base semiconductor portion is between the first at least one non-semiconductor monolayer and the second at least one between non-semiconductor monolayers. The method of claim 9, wherein the base semiconductor monolayers comprise silicon. The method of claim 9, further comprising forming separate source and drain regions defining a channel within the superlattice, and a gate overlying the channel.

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