TWI751609B - Varactor with hyper-abrupt junction region including a superlattice and associated methods - Google Patents

Abstract

A semiconductor device may include a substrate and a hyper-abrupt junction region carried by the substrate. The hyper-abrupt junction region may include a first semiconductor layer having a first conductivity type, a superlattice layer on the first semiconductor layer, and a second semiconductor layer on the superlattice layer and having a second conductivity type different than the first conductivity type. The superlattice may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a first contact coupled to the hyper-abrupt junction region, and a second contact coupled to the substrate to define a varactor.

Description

Variable capacitors with steep junction regions containing superlattices and related methods

The present invention generally relates to semiconductor devices, and in particular, the present invention relates to semiconductor devices having bumps and steep junction regions and related methods.

There have been many proposals for related structures and techniques to improve the performance of semiconductor devices, such as by enhancing the mobility of charge carriers. For example, U.S. Patent Application No. 2003/0057416 to Currie et al. discloses strained material layers of silicon, silicon-germanium, and relaxed silicon that also include impurity-free regions that would otherwise degrade performance zones). The biaxial strain in the upper silicon layer caused by these layers of strained material changes the mobility of carriers, enabling higher speed and/or lower power devices. US Patent Application Publication No. 2003/0034529 to Fitzgerald et al. discloses a CMOS inverter also based on similar strained silicon technology.

US Patent No. 6,472,685 B2 to Takagi discloses a semiconductor device comprising a layer of silicon and carbon sandwiched between layers of silicon to subject the conduction and valence bands of the second silicon layer to tensile strain. In this way, electrons with smaller effective mass and induced by the electric field applied to the gate will be confined in the second silicon layer. Therefore, the N-channel MOSFET can be considered to have higher migration rate.

U.S. Patent No. 4,937,204 to Ishibashi et al. discloses a superlattice comprising a plurality of layers less than eight monolayers and containing fractional or binary semiconductors layer or a binary compound semiconductor layer, the multiple layers are alternately grown by epitaxial growth. The main current directions are perpendicular to the layers of the superlattice.

US Patent No. 5,357,119 to Wang et al. discloses a silicon-germanium short period superlattice that achieves higher mobility by reducing alloy scattering in the superlattice. Based on a similar principle, US Patent No. 5,683,934 to Candelaria discloses a MOSFET with better mobility comprising a channel layer comprising silicon alloyed with a second material that enables the The percentage of the channel layer under tensile stress is instead present in the silicon lattice.

US Patent No. 5,216,262 to Tsu discloses a quantum well structure comprising two barrier regions and a thin epitaxially grown semiconductor layer sandwiched therebetween. Each barrier region is composed of alternating monolayers of SiO2/Si with a thickness ranging approximately from two to six. The barrier region is sandwiched by a much thicker silicon section.

In Applied Physics and Materials Science & Processing, pp. 391-402, published online September 6, 2000, Tsu in an article entitled "Phenomena in Silicon Nanostructured Devices" (Phenomena in silicon nanostructure devices) discloses silicon and oxygen semiconductor-atomic superlattice (semiconductor-atomic superlattice, SAS). The silicon/oxygen superlattice structure was revealed to be useful for silicon quantum and light-emitting devices. In particular, it is disclosed how to fabricate and test a green electroluminescence diode structure. The direction of current flow in the diode structure is vertical, ie, perpendicular to the layers of the SAS. The SAS disclosed herein may comprise semiconductor layers separated by adsorbed species, such as oxygen atoms, and CO molecules. Silicon grown outside the adsorbed oxygen monolayer is described as an epitaxial layer with a relatively low defect density. one of them One SAS structure contains a 1.1 nm thick silicon portion, which is about eight atomic layers of silicon, and the other structure has a silicon portion that is twice as thick. In Physics Review Letters, Vol.89, No.7 (August 12, 2002), Luo et al. published an article entitled "Chemical Design of Direct Interstitial Luminescent Silicon" Direct-Gap Light-Emitting Silicon) discusses Tsu's light-emitting SAS structure further.

US Patent No. 7,105,895 to Wang et al. discloses thin silicon and oxygen, carbon, nitrogen, phosphorus, antimony, arsenic, or hydrogen barrier building blocks that reduce the current flow vertically through the lattice by more than Four orders of magnitude. Its insulating/barrier layer allows low defect epitaxial silicon to be deposited next to the insulating layer.

Published UK Patent Application No. 2,347,520 to Mears et al. discloses that aperiodic photonic band-gap (APBG) structures can be used in electronic bandgap engineering. In detail, the application discloses that material parameters, such as the location of band minima, effective mass, etc., can be adjusted to obtain new aperiodic materials with desired band structure properties. Other parameters, such as electrical conductivity, thermal conductivity, and dielectric permittivity or magnetic permeability, are disclosed and possibly engineered into the material.

In addition, US Pat. No. 6,376,337 to Wang et al. discloses a method for making an insulating or barrier layer for semiconductor devices comprising depositing a layer of silicon and at least one other element on a silicon substrate such that the deposited layer Substantially defect-free, so that substantially defect-free epitaxial silicon can be deposited on the deposition layer. Alternatively, a monolayer of one or more elements, preferably including oxygen, is absorbed on the silicon substrate. A plurality of insulating layers sandwiched between epitaxial silicon to form a barrier complex.

Despite the existence of the aforementioned methods, it is desirable to further enhance the use of advanced semiconductor materials and processing techniques in order to achieve improvements in the performance of semiconductor devices.

A semiconductor device may include a substrate and a hyper-abrupt junction region on the substrate. The abrupt junction region may include a first semiconductor layer having a first conductivity type, a superlattice layer on the first semiconductor layer, and a second semiconductor layer on the superlattice layer, which have different in the second conductivity type of the first conductivity type. The superlattice layer may comprise a plurality of stacked layer groups, each layer group comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and constrained to one of adjacent base semiconductor portions At least one non-semiconductor monolayer within the lattice. The semiconductor device may further include a first contact coupled to the bump junction region and a second contact coupled to the substrate to define a varactor.

In more detail, the abrupt junction region further includes an intrinsic semiconductor layer above or below the superlattice layer. The first, second and intrinsic semiconductor layers and the superlattice layer may be parallel to underlying portions of the substrate. The semiconductor device may further include an intermediate semiconductor layer between the substrate and the junction region; and the second contact may include an implant laterally spaced from the junction and from the middle A surface of the semiconductor layer extends to the substrate. Furthermore, by way of example, the semiconductor element may further comprise a collector implant in the intermediate semiconductor layer below the bump junction. Also by way of example, the base semiconductor monolayers may include silicon, germanium, etc., and the at least one non-semiconductor monolayer may include at least one of oxygen, nitrogen, fluorine, carbon, and carbon-oxygen.

A method for fabricating a semiconductor device may include forming a steep junction region over a substrate. The abrupt junction region may include a first semiconductor layer having a first conductivity type, in the first half A superlattice layer on the conductor layer, and a second semiconductor layer on the superlattice layer, which have a second conductivity type different from the first conductivity type. The superlattice layer may comprise a plurality of stacked layer groups, each layer group comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and constrained to one of adjacent base semiconductor portions At least one non-semiconductor monolayer within the lattice. The method may further include forming a first contact coupled to the bump junction region, and forming a second contact coupled to the substrate to define a variable capacitor.

In more detail, the abrupt junction region further includes an intrinsic semiconductor layer above or below the superlattice layer. The first, second and intrinsic semiconductor layers and the superlattice layer may be parallel to the underlying portion of the substrate. The method can further include forming an intermediate semiconductor layer between the substrate and the bump junction region, and forming the second contact can include implanting a dopant laterally spaced from the bump junction and extending from a surface of the intermediate semiconductor layer to the substrate. Additionally, the method may further include forming a collector implant in the intermediate semiconductor layer below the bump junction, for example. Also by way of example, the base semiconductor monolayers may include silicon, germanium, etc., and the at least one non-semiconductor monolayer may include at least one of oxygen, nitrogen, fluorine, carbon, and carbon-oxygen.

21, 21': Substrate

25, 25': Superlattice

45a~45n, 45a'~45n': layer group

46, 46': base semiconductor monolayer

46a~46n, 46a'~46n': base semiconductor part

50, 50': can be modified layer

52, 52': top cover layer

100: JFET

101, 201, 201', 301, 301', 301": Substrate

102: Back gate

104: source region

105: Drain region

106, 107, 110: Contacts

108, 208: steep junction area

109: Back gate penetration area

111, 117, 311, 311', 311": Quarantine

112, 212, 212', 312, 312', 312": the first semiconductor layer

113, 213, 213', 313: the second semiconductor layer

115, 215, 215': gate electrode layer

116: gate contact

125a, 225a, 325a: first superlattice layer

125b, 225b, 325b: the second superlattice layer

200, 200': IGFET

202, 202': semiconductor layer

214, 214': gate dielectric layer

225', 325', 325": superlattice layers

228, 228': Dielectric layer

230, 230': drain extension area

233, 233': body area

234, 234': source region

235, 235': the first dielectric layer

236, 236': the second dielectric layer

237, 237': source contact layer

238, 238': drain contact layer

239', 339', 339": intrinsic semiconductor layer

240, 240': Conductive channel

300, 300’, 300”: Variable Capacitors

302, 302', 302": Cathode layer

303, 303', 303": collector layer

308, 308’, 308”: steep junction

340, 340’, 340”: Anode area

341, 341', 341", 343, 343', 343": metal layer

342, 342', 342": Penetrating Implants

1 is an enlarged schematic cross-sectional view of a superlattice for a semiconductor device according to an example embodiment.

FIG. 2 is a perspective schematic atomic diagram of a portion of the superlattice shown in FIG. 1 .

3 is an enlarged schematic cross-sectional view of a superlattice according to another example embodiment.

FIG. 4A is a graph of the band structures calculated from the Gacode point (G) for both the conventional host silicon and the 4/1 silicon/oxygen superlattice shown in FIGS. 1-2 .

4B is a graph of the band structures calculated from the Z point for both the conventional host silicon and the 4/1 silicon/oxygen superlattice shown in FIGS. 1-2.

FIG. 4C is a graph of the energy band structures calculated from the G point and the Z point for both the conventional host silicon and the 5/1/3/1 silicon/oxygen superlattice shown in FIG. 3 .

5 shows a schematic cross-sectional view of a JFET having a steep junction with multiple superlattices, according to an exemplary embodiment.

6 shows a schematic cross-sectional view of an IGFET with abrupt junctions including multiple superlattices, according to an exemplary embodiment.

7 shows a schematic cross-sectional view of another IGFET having a steep junction including a single superlattice, according to an exemplary embodiment.

8 illustrates a schematic cross-sectional view of a variable capacitor with abrupt junctions including multiple superlattices, according to an exemplary embodiment.

9A and 9B illustrate schematic cross-sectional views of other variable capacitors having steep junctions including a single superlattice, according to exemplary embodiments.

FIG. 10 shows a flowchart of a method associated with fabricating the device shown in FIGS. 5-7.

FIG. 11 shows a flowchart of a method associated with fabricating the elements shown in FIGS. 8-9.

Exemplary embodiments are described in detail with reference to the accompanying drawings in the specification, in which exemplary embodiments are shown. Embodiments, however, may be embodied in many different forms and should not be construed as limited to the specific examples provided in this specification. Rather, these examples are provided only to enable the disclosure of the present invention The content of the invention is more complete and detailed. Throughout the specification and drawings, the same drawing symbols refer to the same elements, and prime (') and double prime (") are used to designate similar elements in different embodiments.

In general, this specification relates to devices having a reinforced semiconductor superlattice inside. In this specification and the accompanying drawings, the enhanced semiconductor superlattice is also referred to as a "MST" layer or "MST technology".

及

：

為電子之定義，且：

為電洞之定義，其中f為費米-狄拉克分佈(Fermi-Dirac distribution)，EF為費米能量(Fermi energy)，T為溫度，E(k,n)為電子在對應於波向量k及第n個能帶狀態中的能量，下標i及j係指直交座標x，y及z，積分係在布里羅因區(Brillouin zone， B.Z.)內進行，而加總則是在電子及電洞的能帶分別高於及低於費米能量之能帶中進行。 In particular, MST technology involves advanced semiconductor materials, such as superlattices 25, which will be described further below. It is the applicant's theory (but the applicant does not wish to be bound by this theory) that the superlattice structure described in this specification can reduce the effective mass of the charge carriers and thereby lead to higher charge carrier transport Rate. Various definitions of effective mass are described in the literature to which this invention pertains. To measure the improvement in effective mass, the applicant used the "conductivity reciprocal effective mass tensor" for electrons and holes, respectively.

and

:

is the definition of electron, and:

is the definition of a hole, where f is the Fermi-Dirac distribution, EF is the Fermi energy, T is the temperature, and E(k,n) is the electron in the corresponding wave vector k and the energy in the nth band state, the subscripts i and j refer to the orthogonal coordinates x, y and z, the integration is performed in the Brillouin zone (BZ), and the summation is performed in the electron and The energy bands of the holes are higher and lower than the Fermi energy, respectively.

The applicant defines the conductivity inverse effective mass tensor as the larger value of the corresponding component of the conductivity inverse effective mass tensor of a material, the greater the tensorial component of the conductivity. The applicant again proposes a theory (but does not wish to be bound by this theory) that the superlattice described in this specification can set the value of the conductivity inverse effective mass tensor to enhance the conductivity of the material, such as charge carrier transport The typical preferred direction. The inverse of the appropriate number of tensor terms is referred to herein as the conductivity effective mass. In other words, to describe the characteristics of the semiconductor material structure, as mentioned above, the effective mass of the conductivity of electrons/holes in the predetermined carrier transport direction can be calculated, which can be used to identify a better material.

Applicants have identified improved materials or structures that can be used in semiconductor devices. More specifically, the materials or structures identified by the applicant have band structures that have values of the appropriate conductive effective mass for electrons and/or holes that are substantially smaller than those corresponding to silicon. In addition to being characterized by better mobility, these structures are formed or used in such a way that they provide piezoelectric, pyroelectric and/or ferroelectric properties that are beneficial for a variety of different device type applications, as discussed further below.

Referring to Figures 1 and 2, the material or structure is in the form of a superlattice 25, the structure of which is controlled at the atomic or molecular level and can be formed using known techniques for atomic or molecular layer deposition. The superlattice 25 includes a plurality of stacked layer groups 45a-45n, as shown in the schematic cross-sectional view of FIG. 1 .

As shown, each layer group 45a-45n of the superlattice 25 includes a plurality of stacked base semiconductor monolayers 46 that define respective base semiconductor portions 46a-46n and a band modification layer 50 thereon . For clarity of presentation, the band modification layer 50 is represented by noise dots in FIG. 1 .

As shown, the band modification layer 50 comprises a non-semiconductor monolayer that is constrained within a lattice of adjacent substrate semiconductor portions. The term "constrained within a lattice of adjacent base semiconductor portions" means that at least some of the semiconductor atoms from the opposing base semiconductor portions 46a-46n pass through the non-semiconductor between the opposing base semiconductor portions Monolayer 50, chemically bonded together, as shown in FIG. In general, such a configuration may be made possible by controlling the amount of non-semiconductor material deposited over the semiconductor portions 46a-46n by atomic layer deposition techniques so that not all of the available semiconductor bond sites (ie, Incomplete or less than 100% coverage) is occupied by bonds to non-semiconductor atoms, as discussed further below. Thus, as more monolayer 46 of semiconductor material is deposited on or over a non-semiconductor monolayer 50, newly deposited semiconductor atoms can fill the remaining unoccupied semiconductor atomic bonding sites below the non-semiconductor monolayer.

In other embodiments, it is possible to use more than one such non-semiconductor monolayer. It should be noted that when this specification refers to a non-semiconductor monolayer or a semiconductor monolayer, it means that the material used in the monolayer would be a non-semiconductor or a semiconductor if it were formed on the body. That is, the properties exhibited by a single monolayer of a material (eg, silicon) are not necessarily the same as those exhibited when formed in a bulk or relatively thick layer, as will be understood by those skilled in the art to which this invention pertains.

The applicant's theory is that (but the applicant does not wish to be bound by this theory), the energy band modification layer 50 and the adjacent base semiconductor portions 46a-46n can make the superlattice 25 in the direction of the parallel layer, have Appropriately conductive effective mass for lower charge carriers than originally. Thinking in another way, this parallel direction is orthogonal to the stacking direction. The band modification layer 50 can also enable the superlattice 25 to have a general energy band structure, while advantageously functioning as an insulator between multiple layers or regions vertically above and below the superlattice.

Furthermore, the superlattice structure can also be advantageously used as a barrier for dopant and/or material diffusion between layers vertically above and below the superlattice 25 . Therefore, these properties may advantageously allow the superlattice 25 to be High-K dielectrics provide an interface that not only reduces the diffusion of high-K materials into the channel region, but also advantageously reduces unwanted scattering effects and improves device mobility, as will be understood by those skilled in the art to which the present invention pertains .

The theory of the present invention also holds that semiconductor devices including superlattice 25 may enjoy higher charge carrier mobility due to lower conductive effective mass than originally. In certain embodiments, because of the band engineering enabled by the present invention, the superlattice 25 may further have a substantially direct band gap that is particularly advantageous for, for example, optoelectronic devices.

Superlattice 25 may also include a capping layer 52 over an upper layer group 45n. The capping layer 52 may include a plurality of base semiconductor monolayers 46 . The capping layer 52 may comprise between 2 and 100 monolayers of the base semiconductor, and preferably between 10 and 50 monolayers.

Each of the base semiconductor portions 46a-46n may include a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors. Of course, group IV semiconductors also include group IV-IV semiconductors, which should be understood by those skilled in the art to which the present invention pertains. In more detail, the base semiconductor may include, for example, at least one of silicon and germanium.

Each band modification layer 50 may include a non-semiconductor selected from the group consisting of, for example, oxygen, nitrogen, fluorine, carbon, and carbon-oxygen. The non-semiconductor also preferably has the property of remaining thermally stable during deposition of the next layer, thereby facilitating fabrication. In other embodiments, the non-semiconductor may be another inorganic or organic element or compound compatible with a given semiconductor process, as will be understood by those skilled in the art to which this invention pertains. In more detail, the base semiconductor may include, for example, at least one of silicon and germanium.

It should be noted that the term "monolayer" herein refers to comprising a single atomic layer, as well as comprising a single molecular layer. It should also be noted that the band-modifying layer provided via a single monolayer 50, and should also include monolayers in which all possible positions in the layer are not fully occupied (ie, incomplete or less than 100% coverage). For example, referring to the atomic diagram of FIG. 2, which presents a 4/1 repeating structure with silicon as the base semiconductor material and oxygen as the band-modifying material. Only half of the possible positions for oxygen atoms are occupied.

In other implementations and/or the use of different materials, it is not necessarily a one-half occupancy situation, as will be understood by those skilled in the art to which the present invention pertains. In fact, those skilled in the art of atomic deposition will understand that even in this schematic it can be seen that the individual oxygen atoms in a given monolayer are not exactly aligned along a flat plane. For example, a preferred occupancy is one where one-eighth to one-half of the possible sites for oxygen are filled, although other occupancies can be used in certain embodiments.

Since silicon and oxygen are now widely used in general semiconductor processes, manufacturers will be able to apply the materials described in this specification immediately. Atomic deposition or monolayer deposition is also a widely used technique. Therefore, the semiconductor device incorporating the superlattice 25 according to the present invention can be immediately adopted and implemented, as will be understood by those skilled in the art to which the present invention pertains.

Applicants theorize, but applicants do not wish to be bound by this theory, that for a superlattice, such as the silicon/oxygen superlattice, the number of silicon monolayers should ideally be seven or less , so that the energy bands of the superlattice are common or relatively uniform everywhere to achieve the desired advantages. The silicon/oxygen 4/1 repeating structure shown in Figures 1 and 2 has been modeled to represent the preferred mobility of electrons and holes in the X-direction. For example, the calculated conductivity effective mass for electrons (isotropic with respect to the host silicon) is 0.26, and the calculated conductivity effective mass for a 4/1 silicon/oxygen superlattice in the X direction is 0.12 , the ratio of the two is 0.46. Similarly, in the calculation results of holes, the value of the host silicon is 0.36, the value of the 4/1 silicon/oxygen superlattice is 0.16, and the ratio of the two is 0.44.

While this directionally preferential feature may be beneficial for some semiconductor devices, other semiconductor devices may also benefit from mobility in any direction parallel to the layer group a more uniform increase. An increase in the mobility of both electrons and holes at the same time, or an increase in the mobility of only one of the charge carriers, may also have benefits, as will be understood by those skilled in the art to which the present invention pertains.

The lower conductive effective mass of the 4/1 silicon/oxygen implementation of superlattice 25 may be less than two-thirds the conductive effective mass of the non-superlattice 25, and this is the case for electrons and holes All are. Of course, the superlattice 25 may further include at least one type of conductive dopant therein, as will be understood by those skilled in the art to which the present invention pertains.

Another embodiment of a superlattice 25' having different properties in accordance with the present invention will now be described with reference to FIG. In this embodiment, the repetition pattern is 3/1/5/1. In more detail, the lowermost base semiconductor portion 46a' has three monolayers, and the second lower base semiconductor portion 46b' has five monolayers. This pattern repeats throughout the superlattice 25'. Each band modification layer 50' may comprise a single monolayer. For such a superlattice 25' comprising silicon/oxygen, the increase in charge carrier mobility is independent of the orientation of the planes of the layers. Other elements in FIG. 3 that are not mentioned here are similar to those discussed above with reference to FIG. 1 , so the discussion will not be repeated.

In certain device implementations, each base semiconductor portion of its superlattice may be the same number of monolayers thick. In other embodiments, at least some of the base semiconductor portions of its superlattice may be the thickness of a different number of monolayers. In other embodiments, each base semiconductor portion of its superlattice may be a different number of monolayers thick.

4A-4C present band structures calculated using Density Functional Theory (DFT). It is well known in the art to which the present invention pertains that DFT generally underestimates the absolute value of the band gap. Therefore, all bands above the gap can be shifted with appropriate "scissors correction". However, the shape of the energy band is considered to be far more reliable. The energy of the vertical axis should be interpreted from this perspective.

FIG. 4A presents the band structures calculated from Gacode points (G) for both the host silicon (represented by the solid line) and the 4/1 silicon/oxygen superlattice 25 of FIG. 1 (represented by the dashed line). The directions in the figure refer to the unit cell of the 4/1 silicon/oxygen structure rather than the general unit cell of silicon, although the direction (001) in the figure does correspond to the general unit cell of silicon. direction (001), and thus shows the expected location of the silicon conduction band minimum. The direction (100) and the direction (010) in the figure correspond to the direction (110) and the direction (-110) of a general silicon unit cell. As will be understood by those skilled in the art to which the present invention pertains, the silicon energy bands shown in the figures are folded so as to be represented in the appropriate reciprocal lattice directions of the 4/1 silicon/oxygen structure.

It can be seen from the figure that, compared with the host silicon, the conduction band minimum of the 4/1 silicon/oxygen structure is located at point G, while the valence band minimum of the 4/1 silicon/oxygen structure appears at the edge of the Brillouin zone in the direction (001). , which we call the Z point. We can also note that the curvature of the conduction band minimum of the 4/1 silicon/oxygen structure is larger compared to the curvature of the conduction band minimum of silicon, which is caused by the perturbation introduced by the additional oxygen layer. Because of band splitting.

Figure 4B presents the band structures calculated from the Z point for both the host silicon (solid line) and the 4/1 silicon/oxygen superlattice 25 (dashed line). This graph depicts the increasing curvature of the bid band in direction (100).

Figure 4C presents a graph of the band structures calculated from the Gacode and Z points for both the host silicon (solid line) and the 5/1/3/1 silicon/oxygen superlattice 25' (dashed line) of Figure 3 . Due to the symmetry of the 5/1/3/1 silicon/oxygen structure, the calculated band structures in direction (100) and direction (010) are comparable. Thus, in a plane parallel to the layers, ie perpendicular to the stacking direction (001), the conductive effective mass and mobility can be expected to be isotropic. Note that in this 5/1/3/1 silicon/oxygen embodiment, both the conduction band minimum and the valence band maximum are at or near the Z point.

Although an increase in curvature is an indicator of a decrease in effective mass, proper comparison and discrimination can be made through the calculation of the conductivity inverse effective mass tensor. This leads the applicant in this case to further infer that the The 5/1/3/1 superlattice 25' should essentially be a direct band gap. As will be understood by those skilled in the art to which the present invention pertains, the appropriate matrix element of optical transitions is another indicator for distinguishing between direct and indirect bandgap behavior.

Referring now to FIG. 5, the superlattice structure described above can be advantageously used to provide abrupt junctions in a variety of semiconductor devices. In conventional bump or super-junction devices, thin layers (eg, 50 nm to 300 nm) of P-type and N-type are grown adjacent to each other to form super-junction channels. The problem with this configuration, however, is that adjacent P-type and N-type thin layers readily compensate each other through diffusion and limit the amount and mobility of charges that can be effectively combined with the layers without degradation.

In an exemplary embodiment of the present specification, one or more diffusion blocking superlattice layers, such as the aforementioned MST superlattice layers, may be advantageously combined with a steep junction stack. The superlattice layer can advantageously block inter-diffusion, thereby increasing the available charge with higher mobility due to reduced ionized impurity scattering. According to a first example, as shown, a JFET 100 includes a semiconductor substrate 101 with a back gate 102 disposed therein. Separated source and drain regions 104, 105 with corresponding contacts 106, 107 are formed on the back gate 102, and a steep junction region 108 is also formed on the back gate 102, located between the source and the back gate 102. between the drain regions. In addition, a back gate reach through region 109 with contact 110 is coupled to the back gate 102, and an isolation region 111 (eg oxide) separates the back gate reach through region from the source and drain regions 104 and 105 are separated. It should be noted that in some embodiments, the back gate penetration region 109 extends from the backside of the substrate 101 rather than the top/front side of the substrate 101 as shown; in this case, The contacts 110 will be on the backside of the substrate.

In more detail, as shown, the bump junction region 108 includes a first semiconductor layer 112 having a first conductivity type (N or P), a first superlattice layer 125a, which is in the first semiconductor layer 112. On a semiconductor layer, a second semiconductor layer 113 is on the first superlattice layer and has a second conductivity type different from the first conductivity type Two conductivity types (P or N), and a second superlattice layer 125b on the second semiconductor layer. In addition, as shown, a gate electrode is above the second superlattice layer 125b and includes a gate electrode 115, which generally has the same conductivity type as the back gate electrode 102 and the first semiconductor layer 112 (ie, the first conductivity type) , while the semiconductor layer 113 and the source/drain regions 104 and 105 have the same conductivity type (here, the second conductivity type). The second semiconductor layer 113 of the steep junction region 108 defines the steep channel of the JFET 100 . The superlattice layers 125a, 125b can effectively block interdiffusion, thereby increasing the available charge with higher mobility within the channel due to reduced free impurity scattering.

Referring additionally to the flowchart 120 of FIG. 10, beginning at block 121, the semiconductor layers 112, 113 and the superlattices 125a, 125b may be alternately formed to blanket the substrate 101 or selectively cover the substrate as desired. position to form the abrupt junction region 108 (at block 122). In the illustrated embodiment, the superlattices 125a, 125b extend into the source and drain regions 104, 105 and into the back gate penetration region 109, however, if desired, in some embodiments, the The superlattice is confined in the channel region. Next, at block 123, gate electrode layer 115 may be formed over superlattice 125b, followed by gate contact 116. At block 125, the source and drain regions 104, 105 may be formed by doping with dopants of the appropriate conductivity type (p-type for p-channel, and so on), and the back gate penetration region 109 may be formed in a similar manner. An isolation region 117 is then formed to separate the source and drain contacts 106, 107 from the gate contacts. As shown, the method of FIG. 10 ends at block 126 .

Referring now to FIG. 6 , the foregoing techniques can also be used to fabricate other FET structures, such as IGFET 200 . As shown, IGFET 200 includes a substrate 201 and a semiconductor layer 202 on the substrate. The bump junction region 208 is disposed inside the semiconductor layer 202 and partially extends into the substrate 201 . As shown, the bump junction region 208 includes a first semiconductor layer 212 having a first conductivity type (N or P), a first superlattice layer 225a on the first semiconductor layer, a second semiconductor layer 213 on the first superlattice layer and having a second conductivity type (P or N) different from the first conductivity type, and a second superlattice layer 225b, It is on the second semiconductor layer. In addition, the steep junction region 208 is U-shaped, which can form a filled trench structure by sequentially depositing the aforementioned layers in a trench extending through the semiconductor layer 202 to the substrate 201 .

Above the steep junction region 208 are the drain extension region 230 and the dielectric layer 228 . In addition, gate electrode layer 215 is above dielectric layer 228 and is surrounded by gate dielectric layer 214 . The body region 233 surrounds the gate dielectric layer and defines a conductive channel 240 adjacent to the gate dielectric layer 214 . Above the body region 233 is a source region 234, and above the source and gate are first and second dielectric layers 235, 236. Additionally, a source contact layer 237 (eg, semiconductor) can be formed over the top of the device 200 (ie, covering the gate structure and semiconductor layer 202 ), and a drain contact layer 238 (eg, a metal layer) can be formed on the substrate 201 on the back.

Referring now to FIG. 7, according to another exemplary embodiment of an IGFET 200', the steep junction region 208' is shown to include a single superlattice layer 225'. In more detail, in this example, the steep junction region 208' includes a first semiconductor layer 212' having a first conductivity type (N or P), a superlattice layer 225', a The second semiconductor layer 213' has a second conductivity type 213' (P or N) opposite to the first conductivity type, and optionally includes an intrinsic semiconductor layer 239'. The remaining elements of IGFET 200' may be similar to those previously discussed with reference to FIG.

8 and the flow chart 130 of FIG. 11, the variable capacitor 300 including the abrupt junction layer 308 and the related fabrication method will be described. As shown, the variable capacitor 300 includes a substrate 301 having a cathode layer 302 and a collector layer 303 on the cathode layer. Beginning at block 131, a junction region 308 may be grown on the collector layer 303 of the substrate 301 (block 132). In more detail, as shown, the bump junction region 308 includes a first semiconductor layer 312 having a first conductivity type (P or N), a first superlattice layer 325a, which is in the first semiconductor layer 312. On a semiconductor layer, a second semiconductor layer 313 is on the first superlattice layer and has different A second conductivity type (N or P) on (ie opposite to) the first conductivity type, and a second superlattice layer 325b on the second semiconductor layer.

Next, at block 133 , an anode region 340 and an associated metal layer 341 (ie, a first contact) are formed on the bump junction region 308 . A reach through implant 342 and associated metal layer 343 (ie, second contact) are then formed (block 134) to contact the cathode layer 302 of the substrate 301 (it should be noted that in some implementations For example, it can be formed as a backside contact if desired). Penetrating implant 342 is laterally spaced from junction 308 and extends from a surface of collector layer 303 to cathode layer 302 . In more detail, the penetrating implant 342 may have a conductivity type opposite to that of the cathode layer 302 and the collector layer 303, and the collector layer and the first semiconductor layer 312 may have the same conductivity type. Additionally, an isolation region 311 (eg, a dielectric) may be formed around the junction region 308 and the penetrating implant 342 . The method of FIG. 11 ends at block 135 .

Another similar variable capacitor 330' is illustrated with reference to FIG. 9A, wherein the bump junction 308' includes a single superlattice layer 325'. In more detail, as shown, the abrupt junction 308' includes a first semiconductor layer 312', a superlattice layer 325', an intrinsic semiconductor layer 339', and a second semiconductor layer 340' (which also acts as an anode) area use). Figure 9B shows yet another similar variable capacitor 330", all of which are the same as variable capacitor 330', except that intrinsic semiconductor layer 339" is below the superlattice layer 325" instead of above. Variable capacitor 330 ', 330" of the remaining elements may be similar to those discussed above with reference to FIG. 8 .

Further details on JFET, IGFET, and variable capacitor structures can be found in US Patent No. 7,825,441 to Eshun et al.; US Patent Publication No. 2007/0278565 to Tu et al.; and US Patent No. 2007/0278565 to Coolbaugh et al., respectively. Case No. 7,183,628, the entire contents of which are hereby incorporated as a part of this specification.

Various modifications and other embodiments will come to mind to those skilled in the art to which this invention pertains having the benefit of the teachings disclosed in this specification and the accompanying drawings. Therefore, it should be understood that the present invention is not limited to this The specific implementations described in the specification, as well as related modifications and implementations, fall within the scope defined by the following claims.

300': Variable Capacitor

301’: Substrate

302': Cathode layer

303’: collector layer

308’: steep junction

311’: Quarantine

312': first semiconductor layer

325': superlattice layer

339': intrinsic semiconductor layer

340': Anode area

341', 343': metal layer

342': Penetrating Implant

Claims (22)

A semiconductor element, comprising: a substrate; a steep junction area supported by the substrate and comprising: a first semiconductor layer, which has a first conductivity type, a superlattice layer, which is in the first semiconductor layer On a semiconductor layer, the superlattice layer includes a plurality of stacked layer groups, each layer group includes a plurality of stacked base semiconductor monolayers, which define a portion of the base semiconductor and are constrained to adjacent base semiconductors at least one non-semiconductor monolayer within a portion of a lattice, and a second semiconductor layer on the superlattice layer and having a second conductivity type different from the first conductivity type; and coupled to A first contact of the abrupt junction region and a second contact coupled to the substrate define a variable capacitor. The semiconductor device of claim 1, wherein the steep junction region further comprises an intrinsic semiconductor layer above the superlattice layer. The semiconductor device of claim 1, wherein the abrupt junction region further comprises an intrinsic semiconductor layer below the superlattice layer. The semiconductor device of claim 1, wherein the first and second semiconductor layers and the superlattice layer are parallel to the lower portion of the substrate. The semiconductor device of claim 1, further comprising an intermediate semiconductor layer between the substrate and the bump junction region; and wherein the second contact includes an implant laterally spaced from the bump junction open and extend from a surface of the intermediate semiconductor layer to the substrate. The semiconductor device of claim 5, further comprising a collector implant in the intermediate semiconductor layer below the bump junction. The semiconductor device of claim 1, wherein the first and second semiconductor layers each have a thickness ranging from 50 nm to 300 nm. The semiconductor device of claim 1, wherein the base semiconductor monolayers comprise silicon monolayers. The semiconductor device of claim 1, wherein the at least one non-semiconductor monolayer contains oxygen. The semiconductor device of claim 1, wherein the base semiconductor monolayers comprise germanium. The semiconductor device of claim 1, wherein the at least one non-semiconductor monolayer comprises at least one of oxygen, nitrogen, fluorine, carbon, and carbon-oxygen. A method for fabricating a semiconductor device, comprising: forming a steep junction area over a substrate to include a first semiconductor layer having a first conductivity type, a superlattice layer, On the first semiconductor layer, the superlattice layer includes a plurality of stacked layer groups, each layer group includes a plurality of stacked base semiconductor monolayers, which define a base semiconductor portion and are constrained to adjacent substrates at least one non-semiconductor monolayer within a lattice of the semiconductor portion, and a second semiconductor layer on the superlattice layer and having a second conductivity type different from the first conductivity type; and forming a A first contact coupled to the abrupt junction region and a second contact coupled to the substrate define a variable capacitor. The method of claim 12, wherein the abrupt junction region further comprises an intrinsic semiconductor layer over the superlattice layer. The method of claim 12, wherein the abrupt junction region further comprises an intrinsic semiconductor layer below the superlattice layer. The method of claim 12, wherein the first and second semiconductor layers and the superlattice layer are parallel to the underlying portion of the substrate. The method of claim 12, further comprising forming an intermediate semiconductor layer between the substrate and the bump junction region; and wherein forming the second contact includes implanting a dopant so that it interacts with the bump Junctions are laterally spaced and extend from a surface of the intermediate semiconductor layer to the substrate. The method of claim 16, further comprising forming a collector implant in the intermediate semiconductor layer below the bump junction. The method of claim 12, wherein the first and second semiconductor layers each have a thickness in the range of 50 nanometers to 300 nanometers. The method of claim 12, wherein the base semiconductor monolayers comprise silicon monolayers. The method of claim 12, wherein the at least one non-semiconductor monolayer comprises oxygen. The method of claim 12, wherein the base semiconductor monolayers comprise germanium. The method of claim 12, wherein the at least one non-semiconductor monolayer comprises at least one of oxygen, nitrogen, fluorine, carbon, and carbon-oxygen.

Images