TW202233021A - Semiconductor deposition system and operation method thereof - Google Patents

Abstract

A semiconductor deposition system includes a chamber, a target, an electrostatic chuck, a first radiofrequency alternating current device, and a second radiofrequency alternating current device. The target is disposed above the chamber. The electrostatic chuck is disposed in the chamber and below the target and includes a first chuck portion and a second chuck portion laterally surrounding the first chuck portion. The first radiofrequency alternating current device is located outside of the chamber and connected to the first chuck portion of the electrostatic chuck. The second radiofrequency alternating current device is located outside of the chamber and connected to the second chuck portion of the electrostatic chuck.

Description

Semiconductor deposition system and method of operation

A semiconductor deposition system, and more particularly, relates to a semiconductor deposition system including an electrostatic chuck and a method of operation thereof.

In the past decades, the semiconductor integrated circuit industry has experienced rapid development. Technological advances in semiconductor materials and design have produced smaller and more complex circuits. These material and design advancements have been made possible as the technologies associated with processing and manufacturing have also undergone technological advancements. During semiconductor development, the number of interconnected devices per unit area has increased as the smallest feature size that can be reliably fabricated has decreased.

In the manufacture of electronic components on substrates, such as semiconductors and displays, many vacuum processes, such as chemical vapor deposition, physical vapor deposition, etching, implantation, oxidation, nitridation, or other processes, are used to form electronic components. The substrates are typically tethered to an electrostatic chuck in a substrate processing chamber and processed one by one.

In some embodiments, a semiconductor deposition system includes a process chamber, a target, an electrostatic chuck, a first RF source generator, and a second RF source generator. The target is located above the process chamber. The electrostatic chuck is located in the process chamber, below the target, and includes a first chuck portion and a second chuck portion horizontally surrounding the first chuck portion. The first RF source generator is located outside the process chamber and is connected to the first chuck portion of the electrostatic chuck. The second RF source generator is located outside the process chamber and connected to the second chuck portion of the electrostatic chuck.

In some embodiments, a semiconductor deposition system includes a process chamber, a target, an electrostatic chuck, and a first RF source generator. The target is located above the process chamber. The electrostatic chuck is located in the process cavity and includes a circular chuck part, a first annular chuck part and a second annular chuck part. The first annular chuck portion of the electrostatic chuck horizontally surrounds the circular chuck portion of the electrostatic chuck, and the second annular chuck portion of the electrostatic chuck horizontally surrounds the first annular chuck portion of the electrostatic chuck . The first RF source generator is located outside the process chamber and is connected to the second annular chuck portion of the electrostatic chuck.

In some embodiments, a method of operating a semiconductor deposition system includes: placing a wafer on an electrostatic chuck in a process chamber; supplying a DC voltage to a target carrying structure above the process chamber; generating a plasma in the process chamber providing a first RF bias to a first chuck portion of the electrostatic chuck; and providing a second RF bias to a second chuck portion of the electrostatic chuck, wherein the second chuck portion horizontally surrounds the first clamp the disk portion, and the second radio frequency bias is different from the first radio frequency bias.

The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of elements and configurations are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include an embodiment between the first feature and the second feature An embodiment in which additional features are formed between the first and second features so that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or text in various instances. This repetition is for the purpose of simplicity and clarity, and in itself does not indicate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms (eg, "below", "below", "below", "above", "above", etc. related terms) are used here to simply describe the elements shown in the figures or The relationship of a feature to another element or feature. In use or operation, these spatially relative terms encompass different turns of the device in addition to the turns shown in the figures. Furthermore, these devices can be rotated (90 degrees or other angles) and the spatially relative descriptors used herein can be interpreted accordingly.

Please refer to Figure 1A, Figure 1B, and Figure 1C. 1A illustrates a cross-sectional view of a deposition system 100 having an electrostatic chuck 110 in accordance with some embodiments. FIG. 1B shows a top view of the electrostatic chuck 110 according to some embodiments. FIG. 1C shows a top view of wafer 108 in accordance with some embodiments. In some embodiments, the deposition system 100 performs physical vapor deposition (PVD). Physical vapor deposition is a technique used to form layers of materials, including sputtering, on semiconductor wafers. In sputter deposition, the plasma 101 is used to excite ions, typically an inert gas (eg, argon ions (Ar ⁺ )), to promote vigorous impingement on the target. Atoms of the target material are released by the excited ion impact and then condense on the exposed surface of the semiconductor wafer to form a thin layer or film of the target material. Some other PVD chambers can also be used in the etching process using excited ions, noble gases or metal ions to generate impacts on the layers of the semiconductor wafer to be etched.

In FIG. 1A , deposition system 100 has sidewalls 103 and blocking baffles 102 (restricting baffle structures) in sidewalls 103 to form chamber 104 . The wafer 108 is supported by an electrostatic chuck or e-chuck 110 and brought into position within the chamber 104 . Clamps (not shown) may be located at the edges of the wafer 108 to help hold the wafer 108 in place. The electrostatic chuck 110 may be made of a dielectric material, such as a ceramic material. The electrostatic chuck 110 also includes a chuck electrode 160 . The chuck electrode 160 may comprise a conductive metal or metal alloy mesh, and is embedded in a structure made of a dielectric material in the electrostatic chuck 110 . The chuck electrode 160 may be composed of various conductors, such as non-magnetic materials such as aluminum, copper, iron, molybdenum, titanium, tungsten, or alloys of the foregoing metals. The electrostatic chuck 110 may have a temperature control and maintenance system integrated therein to control the temperature of the wafer 108 . For example, electrostatic chuck 110 may be used to cool wafer 108 while chamber 104 is heated to generate plasma 101 therein. Adjusting the temperature of the wafer 108 can improve the characteristics of the deposited material layer and increase the deposition rate by promoting condensation.

In some embodiments, a target carrier structure 112 supports the target 114 above the chamber 104 relative to the wafer 108 and electrostatic chuck 110 . During operation of deposition system 100 , target carrier structure 112 holds target 114 . Target 114 is for the layer of material to be formed on wafer 108 . The target 114 may be a conductive material (eg, copper), an insulating material, or may be a precursor material that reacts with a gas to form a molecule that makes the layer of deposited material. For example, a metal oxide or metal nitride can be deposited using metal target 114 that does not contain oxygen or nitrogen.

Several power supplies (power sources) are provided in the deposition system 100 in order to generate and control the plasma 101 in the chamber 104 and to control sputtering and etching or re-sputtering as required. A direct current (DC) power supply (DC power source) 120 is connected to the target carrier structure 112 to provide its direct current. A radio frequency alternating current (RF) power supply (radio frequency power source) 122 is connected to the electrostatic chuck 110 . The DC power source 120 and the RF power source 122 are used to enable the deposition system 100 to perform the deposition process and the sputter etching process at the same time. In some embodiments, the DC power source 120 of the deposition system 100 is used to perform the deposition process, and the RF power source 122 of the deposition system 100 is used to perform the sputter etching process. Plasma density in deposition system 100 relates to the number of plasma particles per unit volume of plasma 101 , which is primarily controlled by DC power source 120 . The RF power source 122 of the deposition system 100 may be used to enhance the intensity of the plasma bombardment of the material of the target 114 on the wafer 108 .

Specifically, the electrostatic chuck 110 can function as a capacitive coupling structure, while the conductive plasma above the electrostatic chuck 110 provides a complementary electrode. A higher plasma density provides a higher number of plasma particles for sputter etching. The RF bias power of the RF power source 122 of the deposition system 100 can create an electric field substantially normal to the surface of the wafer 108 that can accelerate plasma ions to the surface of the wafer 108 and/or away from the surface of the wafer 108. surface, whereby ions sputter etch wafer 108 by physically bombarding the surface of wafer 108 .

In a simultaneous deposition/sputtering process, increasing the RF bias power of the RF power source 122 can increase the sputter etch rate on horizontal surfaces, thereby reducing the net deposition rate. In some embodiments, the sputter etch in the deposition system 100 can inhibit overhangs that may form in the trenches when depositing the trenches, thereby increasing the process tolerance of the subsequent deposition process when filling the trenches (process window).

Therefore, the cooperation of the RF power source 122 and the DC power source 120 of the deposition system 100 can achieve a predetermined deposition to sputter (D/S) ratio on the wafer 108 . In some embodiments, the deposition to sputtering ratio can be as follows: D/S=Ds/[Ds−D(S+B)]; where D/S is the deposition to sputtering ratio, Ds is the deposition rate under the application of the DC power source 102 120 , and D(S+B) is the case where both the DC power source 120 and the RF power source 122 are applied lower deposition rate.

During the deposition process in the deposition system 100, the RF power source 122 and the DC power source 120 can be varied in many ways to achieve a predetermined deposition to sputter ratio. For example, the deposition to sputter ratio on wafer 108 may be increased by increasing the deposition rate with a substantially constant sputter etch rate, or by substantially constant deposition rate and decreasing the sputter etch rate. In contrast, in some embodiments, deposition and sputtering on wafer 108 may be reduced by substantially constant sputter etch rate and reduced deposition rate, or by substantially constant deposition rate and increased sputter etch rate shot ratio. In some embodiments, the sputter etch rate can be reduced by reducing the RF bias energy of the RF power source 122 , and thus the deposition rate can be increased, thereby increasing the deposition to sputter ratio on the lower wafer 108 . In contrast, in some embodiments, by increasing the RF bias energy of the RF power source 122 , the sputter etch rate is increased, thereby reducing the deposition to sputter ratio on the wafer 108 .

In some embodiments, during the deposition process in deposition system 100, the frequency range of RF power source 122 may be between about 10 MHz and about 16 MHz, and its RF bias power may be about 5000 W, but the present The disclosure is not limited to this.

In some embodiments, the plasma density distribution in the deposition system 100 is not uniform. For example, the central region of the chamber 104 has a higher plasma density, while the peripheral regions in the chamber 104 have a lower plasma density. Thus, during the deposition process in deposition system 100, different plasma densities in chamber 104 may result in different deposition-to-sputter ratios in different regions on wafer 108.

For example, as shown in FIG. 1C, the wafer 108 can be divided into a first region 108a, a second region 108b and a third region 108c. The first area 108a is a circular area. The second region 108b is an annular region surrounding the first region 108a. The third area 108c is an annular area surrounding the second area 108b. However, the distinction of different regions on the wafer 108 is not limited to the foregoing but is merely an example. In some embodiments, the first region 108a , the second region 108b , and the third region 108c of the wafer 108 may have different deposition to sputter ratios when the plasma density distribution in the deposition system 100 is not uniform. . For example, the deposition to sputter ratio of the third region 108c may be smaller than that of the first region 108a and the deposition to sputter ratio of the second region 108b and/or the second region 108b may be smaller than that of the first region 108a.

In this embodiment, the RF power source 122 includes a plurality of RF source generators. The multiple RF power generators of the RF power source 122 (eg, the first RF power generator 122a, the second RF power generator 122b, the third RF power generator 122c shown in FIG. Different regions on the wafer 108 (eg, the first region 108a, the second region 108b, the third region 108c shown in FIG. 1C) can achieve substantially the same deposition in the case of non-uniform plasma density distribution in In some embodiments, the multiple RF source generators of the RF power source 122 may enable different areas on the wafer 108 to reach different areas on the wafer 108 in the event of a non-uniform plasma density distribution in the deposition system 100 Design different deposition to sputter ratios.

As shown in FIG. 1A, the RF power source 122 includes a first RF power generator 122a, a second RF power generator 122b, a third RF power generator 122c, a first impedance matching circuit 124a, a second impedance matching circuit 124b, and The third impedance matching circuit 124c. As shown in FIGS. 1A and 1B , an electrostatic chuck or e-chuck 110 includes a first chuck portion 110a, a second chuck portion 110b, and a third chuck portion 110c. The first chuck portion 110a is a circular portion. The second chuck portion 110b is an annular portion surrounding the first chuck portion 110a. The third chuck portion 110c is an annular portion surrounding the second chuck portion 110b. However, in some embodiments, the distinction between different parts on the electrostatic chuck 110 is not limited to the foregoing but is only an example. As shown in FIG. 1A, the chuck electrode 160 of the electrostatic chuck 110 includes a first chuck electrode portion 160a, a second chuck electrode portion 160b, and a third chuck electrode portion 160c. The first chuck electrode portion 160a is located in the first chuck portion 110a. The second chuck electrode portion 160b is located in the second chuck portion 110b. The third chuck electrode portion 160c is located in the third chuck portion 110c. The first chuck electrode portion 160a, the second chuck electrode portion 160b, and the third chuck electrode portion 160c are electrically insulated from each other.

In FIG. 1A , the first RF source generator 122a may be coupled to the first chuck electrode portion 160a in the first chuck portion 110a of the electrostatic chuck 110 via the first impedance matching circuit 124a. The second RF source generator 122b may be coupled to the second chuck electrode portion 160b in the second chuck portion 110b of the electrostatic chuck 110 via the second impedance matching circuit 124b. The third RF source generator 122c may be coupled to the third chuck electrode portion 160c in the third chuck portion 110c of the electrostatic chuck 110 via the third impedance matching circuit 124c.

In some embodiments, at least two of the first RF source generator 122a, the second RF source generator 122b, and the third RF source generator 122c of the RF power source 122 can generate different RF bias powers. Therefore, the first RF source generator 122 a , the second RF source generator 122 b , and the third RF source generator 122 c that generate different RF bias powers are located in the first region 108 a , the second region 108 b , the third RF source generator 122 c of the wafer 108 . Different electric fields are generated on the surfaces of the three regions 108c. The aforementioned electric field can cause the plasma ions to accelerate to different speeds on the surface of the wafer 108 and/or at different speeds away from the surface of the wafer 108 , whereby the plasma ions bombard different areas on the wafer 108 to sputter etch the wafer 108 . The intensity of the different regions will also be different. When the plasma density distribution in the deposition system 100 is not uniform, different electric fields are generated in the first region 108 a , the second region 108 b and the third region 108 c on the surface of the wafer 108 . The first region 108a, the second region 108b, and the third region 108c achieve substantially the same deposition to sputtering ratio.

For example, the bias power of the third RF source generator 122a may be greater than the bias power of the first RF source generator 122a and/or the bias power of the second RF source generator 122b. The bias power of the second RF source generator 122b may be greater than the bias power of the first RF source generator 122a. Therefore, the electric field of the third region 108c on the surface of the wafer 108 may be greater than the electric field of the first region 108a and/or the electric field of the second region 108b. The electric field of the second region 108b on the surface of the wafer 108 may be greater than the electric field of the first region 108a. The aforementioned electric field may cause plasma ions located in the peripheral regions of the chamber 104 to accelerate to and/or away from the surface of the wafer 108 faster than plasma ions located in the central region of the chamber 104 to the surface of the wafer 108 and/or velocity away from the surface of wafer 108 . Thus, the plasma ions located in the outer region of the chamber 104 bombard the wafer 108 with the intensity of the sputter etched wafer 108 than the plasma ions located in the central region of the chamber 104 to bombard the wafer 108 and sputter etch the wafer 108 Strength of. In the case where the central area of the chamber 104 has a higher plasma density than the peripheral area, the first area 108a, the second area 108b, and the third area 108c on the wafer 108 as shown in FIG. 1C can be substantially the same deposition to sputtering ratio.

In some embodiments, when the RF bias power of the first RF source generator 122a, the second RF source generator 122b, and the third RF source generator 122c is increased or decreased, the first RF source generator 122a, the third A change of about 10% in the RF bias power levels of the second RF source generator 122b and the third RF source generator 122c can cause the first area 108a , the second area 108b , and the third area 108c on the wafer 108 The sputter etch rate was changed by about 10%. In some embodiments, about a 10% variation in the RF bias power levels of the first RF source generator 122a, the second RF source generator 122b, and the third RF source generator 122c can cause the first RF source generator 122a on the wafer 108 to The sputter etch rate of the first region 108a, the second region 108b, and the third region 108c varies by less than about 5%.

In some embodiments, the first RF source generator 122a, the second RF source generator 122b, and the third RF source generator 122c, which generate different RF bias powers, are located in the first region 108a on the surface of the wafer 108 , on the second region 108b and the third region 108c, different electric fields can be generated, thereby achieving different deposition and sputtering designs in the first region 108a, the second region 108b, and the third region 108c on the surface of the wafer 108 shot ratio. In some embodiments, the bias power of the third RF source generator 122a may be smaller than the bias power of the first RF source generator 122a and/or the bias power of the second RF source generator 122b. In some embodiments, the bias power of the second RF source generator 122b may be smaller than the bias power of the first RF source generator 122a.

In some embodiments, different parts of the electrostatic chuck 110 may have different widths. As shown in FIG. 1A , the width of the first chuck portion 110a of the electrostatic chuck 110 is larger than the width of the second chuck portion 110b and the width of the third chuck portion 110c. The width of the second chuck portion 110b of the electrostatic chuck 110 is greater than the width of the third chuck portion 110c, but the width of the chuck portion in the present disclosure is not limited to this. In some embodiments, the different portions may have substantially the same width.

In some embodiments, in addition to the DC power supply 120 , a radio frequency AC power supply 122 is also provided to the target carrier structure 112 .

During the deposition process in deposition system 100 in some embodiments, a low level of pressure is maintained in chamber 104 . For example, the pressure may be from about 10 mTorr to about 150 mTorr. Gas and pressure system 142 is part of deposition system 100 . Gas and pressure system 142 includes valves, conduits, and pressure and fluid sensors that control the pressure within chamber 104 to introduce reactive gases and remove waste gases. The aforementioned gas and pressure system 142 is connected to the control system 140 .

In some embodiments, the power provided by the DC power supply 120 and/or the RF AC power supply 122 is controlled by a control system 140 that includes one or more processors connected to memory. The memory may include programming methods that are pre-programmed for use in device manufacturing. The memory may contain instructions that describe and implement this method. The processor is connected to a power supply and a plurality of sensors within the deposition system 100, which may include temperature sensors, pressure sensors, position sensors, field sensors, and the like.

In Figure 1A, the deposition system 100 further includes some magnets. The magnets may include transverse magnets 130 and 132 located outside the blocking baffle 102 in the deposition system 100 and may be coil magnets. A radio frequency alternating current (RF) power supply (radio frequency power source) 126 is connected to the transverse magnets 130 and 132 . In addition, a magnetron 134 is provided over the target carrying structure 112 , this magnetron 134 provides the chamber 104 magnetic field to facilitate control and use of the plasma 101 .

Please refer to Figure 2. FIG. 2 illustrates a cross-sectional view of a deposition system 200 according to some embodiments. As shown in FIG. 2, the deposition system 200 is substantially the same as the deposition system 100 shown in FIGS. 1A-1C. The difference between the deposition system 200 shown in FIG. 2 and the deposition system 100 shown in FIGS. 1A to 1C is that the electrostatic chuck 210 of the deposition system 200 has a first chuck portion 210 a , a second chuck portion 210 b and The relative relationship between the widths of the third chuck portion 210c is different from the relative relationship between the widths of the first chuck portion 110a, the second chuck portion 110b and the third chuck portion 110c in the electrostatic chuck 110 of the deposition system 100 . In FIG. 2, the width of the first chuck portion 210a, the width of the second chuck portion 210b, and the width of the third chuck portion 210c in the electrostatic chuck 210 of the deposition system 200 are substantially the same.

Please refer to Figure 3. 3 illustrates a cross-sectional view of a deposition system 300 according to some embodiments. As shown in FIG. 3, the deposition system 300 is substantially the same as the deposition system 100 shown in FIGS. 1A-1C. The difference between the deposition system 300 shown in FIG. 3 and the deposition system 100 shown in FIGS. 1A to 1C is that the electrostatic chuck 310 of the deposition system 300 has a first chuck portion 310 a , a second chuck portion 310 b and The relative relationship between the widths of the third chuck portion 310c is different from the relative relationship between the widths of the first chuck portion 110a, the second chuck portion 110b and the third chuck portion 110c in the electrostatic chuck 110 of the deposition system 100 . In FIG. 2, the width of the third chuck portion 310c in the electrostatic chuck 310 of the deposition system 300 is larger than the width of the first chuck portion 310a and/or the width of the second chuck portion 310b. The width of the second chuck portion 310b is greater than the width of the first chuck portion 210a.

Please refer to Figure 4 in conjunction with Figures 1A to 1C. FIG. 4 illustrates a flowchart of a method M of operation of the deposition system 100 according to some embodiments. Although the method M of operation of the disclosed deposition system 100 is illustrated and described herein as a series of steps or events, it should be understood that the depicted order of such steps or events is not to be construed in a limiting sense. For example, some steps may occur in different orders and/or concurrently with other steps or events than in the order shown and/or described herein. Additionally, not all illustrated operations may be required to implement one or more aspects or implementations described herein. Further, one or more of the steps described herein may be implemented in one or more separate steps and/or stages. Specifically, the operation method M of the deposition system 100 includes steps S1001 to S1005.

In step 1001 , the wafer 108 is placed on the electrostatic chuck 110 in the process chamber 104 . The electrostatic chuck 110 includes a first chuck portion 110a, a second chuck portion 110b and a third chuck portion 110c. The first chuck portion 110a is a circular portion. The second chuck portion 110b is an annular portion surrounding the first chuck portion 110a. The third chuck portion 110c is an annular portion surrounding the second chuck portion 110b.

In step 1002 , plasma 101 is generated in process chamber 104 . In some embodiments, the plasma 101 is unevenly distributed in the process chamber 104 . For example, the central region of the chamber 104 has a higher plasma density, while the peripheral regions in the chamber 104 have a lower plasma density. In some embodiments, the plasma 101 is uniformly distributed in the process chamber 104 . For example, the plasma density in the central region of the chamber 104 is substantially the same as the plasma density in the peripheral regions of the chamber 104 .

In step 1003 , a DC voltage is provided through the DC power source 120 to the target carrier structure 112 located above the process chamber 104 to perform a deposition process in the process chamber 104 .

In step 1004, a first RF bias is provided to the first chuck portion 110a of the electrostatic chuck 110 through the first RF source generator 122a, and a second RF bias is provided to the electrostatic chuck through the second RF source generator 122b The first chuck portion 110b of the electrostatic chuck 110 is provided with a third RF bias voltage to the first chuck portion 110c of the electrostatic chuck 110 through the third RF source generator 122c. The bias values of at least two of the first radio frequency bias voltage, the second radio frequency bias voltage and the third radio frequency bias voltage are different. In some embodiments, the first RF bias, the second RF bias, and the third RF bias have different bias values from each other.

Specifically, the DC power source 120, the first RF source generator 122a, the second RF source generator 122b, and the third RF source generator 122c are used to enable the deposition system 100 to simultaneously perform the deposition process and the sputter etching process. In some embodiments, the DC power source 120 of the deposition system 100 is used to perform the deposition process, and the RF power source 122 of the deposition system 100 is used to perform the sputter etching process. The first RF source generator 122 a , the second RF source generator 122 b , and the third RF source generator 122 c that generate different RF bias powers correspond to the first area 108 a , the second area 108 b and the first area 108 b on the wafer 108 . Different electric fields are generated on the surfaces of the three regions 108c. The different electric fields can cause the plasma ions in the semiconductor deposition system 100 to be accelerated to the first region 108a, the second region 108b and the third region 108c of the wafer 108 at different speeds and/or away from the first region 108a, The speed of the second region 108b and the third region 108c is different, whereby the intensity of the first region 108a, the second region 108b and the third region 108c on the wafer 108 by plasma ion sputter etching will also be different accordingly. Therefore, when the plasma density distribution in the deposition system 100 is not uniform, the first region 108a , the second region 108b and the third region 108c on the surface of the wafer 108 generate different electric fields, which may The first region 108a and the second region 108b on 108 achieve substantially the same deposition to sputtering ratio.

From the aforementioned embodiments, it can be seen that the present disclosure provides advantages in the fabrication of integrated circuit structures. It should be understood, however, that other embodiments may provide additional advantages, and not all advantages are necessarily disclosed herein. One advantage is that the radio frequency power source of the semiconductor deposition system includes multiple radio frequency source generators. Multiple RF source generators are connected to different areas on the electrostatic chuck. The RF power generators of different RF power sources can generate different RF bias powers. Therefore, multiple RF source generators producing different RF bias powers will generate different electric fields on the surface of different regions on the wafer. The aforementioned electric fields can cause the plasma ions in the semiconductor deposition system to accelerate to the surface of the wafer and/or away from the surface of the wafer at different speeds, whereby the intensity of the plasma ions sputter etch different regions on the wafer. will be different. In the case of non-uniform plasma density distribution in the deposition system, different electric fields are generated in different regions on the surface of the wafer, and substantially the same deposition to sputtering ratio can be achieved in different regions on the wafer.

In some embodiments, a semiconductor deposition system includes a process chamber, a target, an electrostatic chuck, a first RF source generator, and a second RF source generator. The target is located above the process chamber. The electrostatic chuck is located in the process chamber below the target, and includes a first chuck portion and a second chuck portion surrounding the first chuck portion. The first RF source generator is located outside the process chamber and is connected to the first chuck portion of the electrostatic chuck. The second RF source generator is located outside the process chamber and connected to the second chuck portion of the electrostatic chuck.

In some embodiments, a semiconductor deposition system includes a process chamber, a target, an electrostatic chuck, and a first RF source generator. The electrostatic chuck is located in the process cavity and includes a circular chuck part, a first annular chuck part and a second annular chuck part. The first annular chuck portion of the electrostatic chuck surrounds the circular chuck portion of the electrostatic chuck, and the second annular chuck portion of the electrostatic chuck surrounds the first annular chuck portion of the electrostatic chuck. The first RF source generator is located outside the process chamber and is connected to the second annular chuck portion of the electrostatic chuck.

In some embodiments, a method of operating a semiconductor system includes: placing a wafer on an electrostatic chuck in a process chamber; generating a plasma in the process chamber; providing a DC voltage to a target carrier above the process chamber structure; providing a first RF bias to a first chuck portion of the electrostatic chuck; and providing a second RF bias to a second chuck portion of the electrostatic chuck, wherein the second chuck portion horizontally surrounds the first chuck position, and the second radio frequency bias is different from the first radio frequency bias.

The foregoing has outlined features of several embodiments in order that those of ordinary skill in the art may better understand various aspects of the present disclosure. Those of ordinary skill in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same benefits of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and alterations without departing from the spirit and scope of the present disclosure.

100: Sedimentation system 101: Plasma 102: Blocking the baffle 103: Sidewalls 104: Chamber 108: Wafer 108a: The first area 108b: The second area 108c: The third area 110: Electrostatic chuck 110a: The first chuck part 110b: The second chuck part 110c: The third chuck part 112: Target bearing structure 114: target material 120: DC power source 122: RF power source 122a: The first radio frequency source generator 122b: Second RF source generator 122c: The third RF source generator 124a: The first impedance matching circuit 124b: The second impedance matching circuit 124c: The third impedance matching circuit 126: RF AC power supply 130: Transverse magnet 132: Transverse magnet 134: Magnetron 140: Control system 142: Gas and Pressure Systems 160: Chuck Electrode 160a: The first chuck electrode part 160a: The second chuck electrode part 160b: The third chuck electrode part 160c: Gas and Pressure Systems 200: Sedimentation system 210a: The first chuck part 210b: The second chuck part 210c: The third chuck part 300: Sedimentation system 310a: The first chuck part 310b: The second chuck part 310c: The third chuck part M: method S1001: Steps S1002: Steps S1003: Steps S1004: Steps

Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is understood that in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1A shows a cross-sectional view of a deposition system with an electrostatic chuck in accordance with some embodiments. FIG. 1B shows a top view of an electrostatic chuck according to some embodiments. FIG. 1C shows a top view of a wafer according to some embodiments. Figure 2 illustrates a cross-sectional view of a deposition system according to some embodiments. Figure 3 illustrates a cross-sectional view of a deposition system according to some embodiments. FIG. 4 illustrates a flow diagram of a method of operation of a deposition system according to some embodiments.

Domestic storage information (please note in the order of storage institution, date and number) none Foreign deposit information (please note in the order of deposit country, institution, date and number) none

100: Deposition System

101: Plasma

102: Blocking the bezel

103: Sidewall

104: Chamber

108: Wafer

110: Electrostatic chuck

110a: The first chuck part

110b: Second chuck part

110c: The third chuck part

112: Target carrying structure

114: Target

120: DC power source

122: RF Power Source

122a: first radio frequency source generator

122b: Second RF source generator

122c: Third RF Source Generator

124a: first impedance matching circuit

124b: second impedance matching circuit

124c: Third Impedance Matching Circuit

126: RF AC Power Supply

130, 132: Transverse magnet

134: Magnetron

140: Control System

142: Gas and Pressure Systems

160: Chuck electrode

160a: the first chuck electrode part

160a: Second chuck electrode part

160b: The third chuck electrode part

160c: Gas and Pressure Systems

Claims (10)

A semiconductor deposition system, comprising: a process cavity; a target, located above the process cavity; an electrostatic chuck, located in the process chamber and below the target, and comprising a first chuck part and a second chuck part horizontally surrounding the first chuck part; a first radio frequency generator located outside the process chamber and connected to the first chuck portion of the electrostatic chuck; and A second RF source generator is located outside the process chamber and connected to the second chuck portion of the electrostatic chuck. The semiconductor deposition system as claimed in claim 1, further comprising: A third RF source generator is located outside the process chamber, wherein the electrostatic chuck further includes a third chuck portion, the third chuck portion horizontally surrounds the second chuck portion, and the third RF source A generator is connected to the third chuck portion of the electrostatic chuck. The semiconductor deposition system of claim 1, wherein the electrostatic chuck further comprises: a first chuck electrode portion located in the first chuck portion; and a second chuck electrode portion located in the second chuck portion, wherein the first RF source generator is connected to the first chuck electrode portion of the first chuck portion of the electrostatic chuck, the second The RF source generator is connected to the second chuck electrode portion of the second chuck portion of the electrostatic chuck, and the first chuck electrode portion is electrically insulated from the second chuck electrode portion. The semiconductor deposition system as claimed in claim 1, further comprising: a first impedance matching circuit located outside the process chamber; and a second impedance matching circuit located outside the process chamber, wherein the first RF source generator is connected to the first chuck portion of the electrostatic chuck through the first impedance matching circuit, and the second RF source generator is connected to the second chuck portion of the electrostatic chuck through the second impedance matching circuit. The semiconductor deposition system of claim 1, wherein the width of the first chuck portion of the electrostatic chuck is greater than the width of the second chuck portion of the electrostatic chuck. A semiconductor deposition system, comprising: a process cavity; a target, located above the process cavity; An electrostatic chuck is located in the process chamber and includes a circular chuck part, a first annular chuck part and a second annular chuck part, wherein the first annular clamp of the electrostatic chuck The disc portion horizontally surrounds the circular chuck portion of the electrostatic chuck, and the second annular chuck portion of the electrostatic chuck horizontally surrounds the first annular chuck portion of the electrostatic chuck; and A first RF source generator is located outside the process chamber and connected to the second annular chuck portion of the electrostatic chuck. The semiconductor deposition system of claim 6, wherein the width of the first annular chuck portion of the electrostatic chuck is different from the width of the second annular chuck portion of the electrostatic chuck. The semiconductor deposition system as described in claim 6, further comprising: a second RF source generator located outside the process chamber and connected to the second annular chuck portion of the electrostatic chuck; and A third radio frequency source generator is located outside the process chamber and connected to the circular chuck portion of the electrostatic chuck. A method of operating a semiconductor deposition system, comprising: placing a wafer on an electrostatic chuck in a process chamber; generating a plasma in the process chamber; providing a DC voltage to a target carrying structure above the process chamber; providing a first RF bias to a first chuck portion of the electrostatic chuck; and A second RF bias is provided to a second chuck portion of the electrostatic chuck, wherein the second chuck portion horizontally surrounds the first chuck portion, and the second RF bias is different from the first RF bias bias. The operating method of a semiconductor deposition system as claimed in claim 9, wherein the second RF bias voltage is greater than the first RF bias voltage.

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