TW202226339A - Treatments to enhance material structures - Google Patents

Abstract

A method of forming a high-κ dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-κ dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-κ dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-κ dielectric cap layer, and removing the sacrificial silicon cap layer.

Description

Treatment of Reinforced Material Structures

Various embodiments described herein relate generally to semiconductor device fabrication, and more particularly, to systems and methods for forming layers of high quality high-κ dielectric materials and metal gate structures in semiconductor structures.

As metal-oxide-semiconductor field-effect transistors (MOSFETs) have been reduced in size for high device performance and low power dissipation, the thickness of the traditional silicon dioxide ( _SiO2 ) gate dielectric has been reduced to its physical limit. Therefore, in order to achieve further scaling, it has become inevitable to replace the silicon dioxide gate dielectric with a high-κ dielectric material. Among various high-κ dielectric materials, hafnium oxide (HfO _{2 )} has been applied since the 45nm MOSFET technology node, due to its high dielectric constant and superior thermal stability on silicon substrates sex. However, simply reducing the thickness of the high-κ dielectric material layer is problematic for further reductions in the equivalent oxide thickness (EOT) of the 32nm MOSFET technology node and beyond because the current The leakage current of the high-κ dielectric material layer is increased.

In addition, conventional polycrystalline silicon (polysilicon) gates have been constructed of metal layers (eg, titanium (Ti), tantalum (Ta), tungsten (W)) and metal-containing conductive compound layers (eg, titanium nitride (TiN) ), tantalum nitride (TaN)) to reduce the undesired voltage drop associated with the polysilicon depletion effect, and to improve the drive current performance and operating speed of the MOSFET. However, such metal gates are typically formed by a furnace-based process using metal-containing precursors (eg, titanium chloride, TiCl ₄ ) and nitrogen-containing precursors (eg, ammonia, NH ₃ ). Such a process may include high concentrations of oxygen and thus may not be ideal for future scalability.

Accordingly, there is a need for systems and methods that can be used to form thin (eg, EOT less than 1 nm) layers of high-κ dielectric materials and metal gates without high concentrations of oxygen with controlled to ensure the desired structural and electrical properties of the chemical structure.

Various embodiments of the present disclosure provide a method of forming a high-κ dielectric cap layer on a semiconductor structure formed on a substrate. The method includes the steps of: depositing the high-κ dielectric cap layer on the semiconductor structure; depositing a sacrificial silicon cap layer on the high-κ dielectric cap layer; performing a post cap anneal processes to harden and densify the deposited high-κ dielectric capping layer; and remove the sacrificial silicon capping layer.

Various embodiments of the present disclosure also provide a method of forming a high-κ dielectric capping layer on a semiconductor structure formed on a substrate. The method includes the steps of: depositing the high-κ dielectric capping layer on the semiconductor structure; depositing a sacrificial silicon capping layer on the high-κ dielectric capping layer; performing a back-cap annealing process to harden and densify the depositing a high-κ dielectric capping layer; and removing the sacrificial silicon capping layer.

Various embodiments of the present disclosure further provide a processing system. The processing system includes a first processing chamber, a second processing chamber, a third processing chamber, a fourth processing chamber, and a system controller. The system controller is configured to deposit, in the first processing chamber, a high-κ dielectric capping layer on the high-κ gate dielectric layer; depositing a sacrificial silicon capping layer on the high-κ dielectric capping layer; in the third processing chamber, performing a back cap anneal process to harden and densify the deposited high-κ dielectric capping layer; and in the fourth processing chamber In the processing chamber, the sacrificial silicon capping layer is removed. Transfer the substrate between the first processing chamber, the second processing chamber, the third processing chamber, and the fourth processing chamber without disrupting the vacuum environment in the processing system .

As gate structures shrink to smaller dimensions, new material structures are constantly being sought to provide improvements. The use of high-κ dielectric materials increases the dielectric constant of the gate structure compared to conventional gate structures utilizing materials such as silicon oxide. However, similar to silicon oxide, the leakage current increases as the thickness of the gate structure decreases. For example, gate leakage increases as the effective oxide thickness decreases. Therefore, the inverse relationship between gate leakage and effective oxide thickness may create limitations on the performance of the devices and transistors produced.

High-κ dielectric materials can provide greater electrostatic control of the channel than silicon oxide of similar physical thickness. As the industry continues to seek lower effective oxide thicknesses without increasing gate leakage, due to morphological The effort to maximize the κ value”) is about to reach its limit. Conventional techniques have struggled to overcome the inherent properties of high-κ materials (which may set an upper limit on the value of κ), and subsequent modification of components to try to incorporate new membranes.

Additionally, typical furnace-based processes for forming metal gates in place of polysilicon from metal layers and metal-containing conductive compounds may include high concentrations of oxygen during the process, and thus may not be ideal for future scalability.

Various embodiments described herein provide systems and methods for forming thin (eg, EOT less than 1 nm) layers of high-κ dielectric materials and forming metal gates. By producing high-κ dielectric materials exhibiting specific morphologies or grain structures, higher dielectric constants and consequent improved device performance can be achieved. In order to control the in-film morphology in the exemplary element, treatments can be performed to provide an activated substrate surface capable of causing a specific film morphology, as well as to stabilize the film after formation , which can result in a higher dielectric constant. Forming the metal gate without a high concentration of oxygen content enables further reduction of the equivalent oxide thickness (EOT).

1 is a schematic top view of an example of a multi-chamber processing system 100 in accordance with some examples of the present disclosure. The processing system 100 generally includes: a factory interface 102; load lock chambers 104, 106; transfer chambers 108, 110 with corresponding transfer robots 112, 114; holding chambers 116, 118; and processing chambers 120, 122 , 124, 126, 128, 130. As detailed herein, wafers in the processing system 100 may be processed in various chambers and transferred between the various chambers without exposing the wafers to the surrounding environment outside the processing system 100 ( For example, atmospheric environments such as may exist in a fab). For example, the wafers may be processed in and transferred between the various chambers in a low pressure (eg, less than or equal to about 300 Torr) or vacuum environment without damaging the wafers in the processing system 100 A low pressure or vacuum environment between the various processes being performed. Thus, processing system 100 may provide an integrated solution for some processing of wafers.

Examples of processing systems that may be suitably modified in accordance with the teachings provided herein include the ^Endura® , Producer®, or ^{Centura® integrated} processing systems, or other suitable processing systems, commercially available from Applied Materials, Inc., located in Santa Clara, California, USA. It is contemplated that other processing systems, including those from other manufacturers, may be adapted to benefit from the various aspects described herein.

In the illustrated example of FIG. 1, the factory interface 102 includes a docking station 140 and a factory interface robot 142 to illustrate transferring wafers. The docking station 140 is configured to receive one or more front opening standard pods (FOUPs) 144 . In some examples, each fab robot 142 generally includes a blade 148 disposed on one end of the corresponding fab robot 142 configured to transfer wafers from the fab 102 to the load lock chambers 104 , 106 .

The load lock chambers 104 , 106 have respective ports 150 , 152 coupled to the factory interface 102 and respective ports 154 , 156 coupled to the transfer chamber 108 . The transfer chamber 108 also has respective ports 158 , 160 coupled to the holding chambers 116 , 118 and respective ports 162 , 164 coupled to the processing chambers 120 , 122 . Similarly, transfer chamber 110 has respective ports 166 , 168 coupled to holding chambers 116 , 118 and respective ports 170 , 172 , 174 , 176 coupled to processing chambers 124 , 126 , 128 , 130 . Ports 154 , 156 , 158 , 160 , 162 , 164 , 166 , 168 , 170 , 172 , 174 , 176 may be, for example, slit valve openings with slit valves for transferring wafers by means of transfer robots 112 , 114 Pass therethrough and serve to provide seals between the respective chambers to prevent the passage of gas between the chambers. Typically, any ports are open for transferring wafers therethrough. Otherwise, the port is closed.

Load lock chambers 104, 106, transfer chambers 108, 110, hold chambers 116, 118, and process chambers 120, 122, 124, 126, 128, 130 may be fluidly coupled to a gas and pressure control system (not shown in detail). Shows). The gas and pressure control system may include one or more gas pumps (eg, turbo pumps, cryo-pumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to the various chambers. In operation, factory interface robot 142 transfers wafers from FOUP 144 to load lock chamber 104 or 106 via port 150 or 152 . The gas and pressure control system then pumps down the load lock chamber 104 or 106 . The gas and pressure control system further maintains the transfer chambers 108, 110 and holding chambers 116, 118 in an internal low pressure or vacuum environment (which may include an inert gas). Thus, pumping down the load lock chamber 104 or 106 facilitates transferring wafers between the atmospheric environment, eg, the factory interface 102 , and the low pressure or vacuum environment of the transfer chamber 108 .

With the wafers in the load lock chambers 104 or 106 that have been pumped out, the transfer robot 112 transfers the wafers from the load lock chambers 104 or 106 into the transfer chamber 108 via ports 154 or 156 . The transfer robot 112 can then transfer the wafer to and/or between any of the processing chambers 120, 122 and the holding chambers 116, 118 by corresponding Ports 162, 164 transfer wafers to processing chambers 120, 122 for processing, and via respective ports 158, 160 to holding chambers 116, 118 for holding for further transfer. Similarly, transfer robot 114 can access wafers in holding chambers 116 or 118 via ports 166 or 168 and can transfer wafers to processing chambers 124, 126, 128, 130 and holding chambers 116, 116, Transfer wafers to and/or between any of the chambers 118 to the processing chambers 124, 126 for processing via respective ports 170, 172, 174, 176 , 128, 130, the wafers are transferred by respective ports 166, 168 to the holding chambers 116, 118 for holding for further transfer. The transfer and holding of wafers within and between the various chambers can be performed in a low pressure or vacuum environment provided by gas and pressure control systems.

The processing chambers 120, 122, 124, 126, 128, 130 may be any suitable chambers for processing wafers. In some examples, process chamber 122 may be capable of performing cleaning processes, process chamber 120 may be capable of performing etch processes, and process chambers 124, 126, 128, 130 may be capable of performing corresponding epitaxial growth processes. Processing chamber 122 may be a SiCoNi™ pre-clean chamber available from Applied Materials, Inc. of Santa Clara, California, USA. Processing chamber 120 may be a Selectra™ etch chamber available from Applied Materials, Inc. of Santa Clara, California, USA.

System controller 190 is coupled to processing system 100 for controlling processing system 100 or components of processing system 100 . For example, the system controller 190 may use direct control of the chambers 104, 106, 108, 116, 118, 110, 120, 122, 124, 126, 128, 130 of the processing system 100 to control the operation of the processing system 100, or The operation of the processing system 100 is controlled by controlling the controllers associated with the chambers 104 , 106 , 108 , 116 , 118 , 110 , 120 , 122 , 124 , 126 , 128 , 130 . In operation, the system controller 190 can enable data collection and feedback from the corresponding chambers to coordinate the operation of the processing system 100 .

System controller 190 generally includes a central processing unit (CPU) 192 , memory 194 and support circuits 196 . CPU 192 may be one of any form of general purpose processor capable of being used in an industrial setting. The memory 194 or non-transitory computer readable medium can be accessed by the CPU 192 and may be such as random access memory (RAM), read only memory (ROM), floppy disk, hard disk or any other form of local or one or more memories such as remote digital storage devices. Support circuits 196 are coupled to CPU 192 and may include cache memory, clock circuits, input/output subsystems, power supplies, and the like. The various methods disclosed herein may generally be implemented under the control of CPU 192 by CPU 192 executing code of computer instructions stored in memory 194 (or memory in a particular process chamber) as, for example, software routines. When the computer instruction code is executed by the CPU 192, the CPU 192 controls the chambers to perform processes according to various methods.

Other processing systems may take other configurations. For example, more or fewer processing chambers may be coupled to the transfer device. In the illustrated example, the transfer apparatus includes transfer chambers 108 , 110 and holding chambers 116 , 118 . In other examples, more or fewer transfer chambers (eg, one transfer chamber) and/or more or fewer holding chambers (eg, no holding chambers) may serve as transfer devices in a processing system to fulfill.

2 is a process flow diagram of a method 200 of forming a semiconductor structure 300 in accordance with one or more embodiments of the present disclosure. 3A and 3B are cross-sectional views of a portion of a semiconductor structure 300 corresponding to various states of the method 200 . It should be understood that FIGS. 3A and 3B only show partial schematic views of semiconductor structure 300, and semiconductor structure 300 may include any number of transistor portions and additional materials having various aspects as shown. It should also be noted that although the method steps shown in FIG. 2 are described sequentially, including one or more that have been omitted and/or added, and/or have been rearranged in another desired order Other processing sequences of method steps or steps are also within the scope of the various embodiments of the present disclosure provided herein.

The method 200 begins with a pre-clean process in block 210 to pre-clean the surface of the substrate 302 . The pre-cleaning process may include etching the surface of the substrate 302 by a dry etching process or a wet etching process using an etching solution such as NH ₄ OH (ammonium hydroxide), H ₂ O ₂ Standard Clean 1 (SC1) etching solution of (hydrogen peroxide) and H ₂ O (water), the dry etching process is, for example, a SiConi™ remote plasma-assisted dry etching process, wherein the substrate 302 The surface is exposed to N ₂ , NF ₃ and NH ₃ plasmonic byproducts. The pre-clean process may be performed in a pre-clean chamber, such as the process chamber 122 or 120 shown in FIG. 1 .

In block 220, an interface formation process is performed to form an interface layer 304 on the pre-cleaned surface of the substrate 302, as shown in FIG. 3A. The interface formation process may include a suitable thermal oxidation process, such as an enhanced in-situ steam generation (eISSG) process using nitrous oxide (N ₂ O) gas. The interface layer 304 formed in block 220 is a thin amorphous silicon oxide (SiO ₂ ) layer having a thickness between about 3 Å and about 10 Å, such as about 5 Å, corresponding to one or more of the silicon oxide Monolayer. In some embodiments, the interface may be formed by an in-situ steam generation (ISSG) process using H ₂ and O ₂ gases or by a rapid thermal oxidation (RTO) process using NH ₃ and O ₂ gases layer 304 . The interface layer 304 may serve as a nucleation layer for the high-κ dielectric material layer to be deposited on the interface layer 304 and improve the quality of the interface between the substrate 302 and the high-κ dielectric material layer (eg, an interface such as an interface density of states (interface state density, accumulation capacitance, frequency dispersion, leakage current, etc.). The interface formation process may be performed in a processing chamber such as processing chambers 120, 122, 124, 126, 128, or 130 shown in FIG.

In some embodiments, the interface formation process in block 220 is omitted, and the interface layer 304 is not formed before the deposition of the high-κ dielectric material layer on the substrate 302 . In this case, the interface layer 304 is formed by the thermal oxidation process in block 250 or block 290 described below, which thermally oxidizes the substrate 302 via a layer of high-κ dielectric material deposited on the substrate 302 . Having a thickness between about 0.3 nm and about 1 nm, eg, about 0.5 nm, the interface layer 304 formed by the thermal oxidation process in block 250 or block 290 may be thick enough to ensure reliable device characteristics (eg, such as interfacial density of states, accumulated capacitance, dispersion, and leakage current) and reduce atomic diffusion from the high-κ dielectric material layer to the substrate 302 .

In block 230, a deposition process is performed to form the interface layer 304 on the exposed surface of the semiconductor structure 300 (ie, on the interface layer 304 in the case of forming the interface layer 304 in block 220, as shown in FIG. 3B, and in block 220). A high-κ gate dielectric layer 306 is deposited on the substrate 302 without forming the interface layer 304 in 220). The high-κ gate dielectric layer 306 may be composed of a high-κ dielectric material such as hafnium dioxide (HfO ₂ ), zirconium dioxide (ZrO ₂ ), ytterbium oxide (Y ₂ O ₃ ), aluminum oxide (Al ₂ ) _O3 ), ternary high-κ dielectric films (such as HfZrO, HfLaOx, HfTiO, etc.) with a third element incorporated into existing metal oxide high-κ dielectric host materials form. The deposition process may include an atomic layer deposition (ALD) process in which metal-containing precursors and oxygen-containing precursors are alternately delivered to the exposed surface of semiconductor structure 300 . In some embodiments, the metal-containing precursor is purged prior to delivery of the oxygen-containing precursor. The metal may be a transition metal such as hafnium (Hf), zirconium (Zr) or titanium (Ti), a rare earth metal such as lanthanum (La), ytterbium (Yb) or yttrium (Y), such as strontium (Sr) alkaline earth metals such as aluminum (Al) or other metals such as aluminum (Al). For the oxidant, any oxygen-containing precursor that can react with the metal can be used. For example, the oxygen-containing precursor may be or contain water, diatomic oxygen, ozone, hydroxyl-containing precursors or alcohols, nitrogen and oxygen-containing precursors, Either plasma enhanced oxygen of remote enhanced oxygen, or any other material containing oxygen that can be combined with metal to produce a layer of metal oxide over substrate 302 . In one example, the metal-containing precursor is hafnium tetrachloride (HfCl ₄ ) and the oxidant is water (H ₂ O) to form a hafnium dioxide (HfO ₂ ) layer. The ALD process can be performed at a temperature between 200°C and about 400°C (eg, about 270°C). The high-κ gate dielectric layer 306 may be amorphous and have a thickness between about 10 Å and about 30 Å as deposited by an ALD process. The deposition process may be performed in a processing chamber such as processing chambers 120, 122, 124, 126, 128, or 130 shown in FIG.

In block 240, an optional post-deposition annealing process is performed to harden and densify the deposited high-κ gate dielectric layer 306 . Crystallization of the deposited amorphous high-κ gate dielectric layer 306 may occur. The post-deposition annealing process may include a thermal annealing process in an inert environment, such as in a nitrogen ( _N2 ) and argon (Ar) environment, performed in a rapid thermal processing (RTP) chamber, the rapid thermal processing (RTP) A chamber such as the RADOX™ chamber available from Applied Materials, Santa Clara, CA, USA. Such an RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. 1 . This post-deposition annealing process can thermally harden and densify the interface layer 304 and the high-κ dielectric layer 306 .

The post-deposition annealing process may be performed at a temperature between about 500°C and about 800°C and a pressure between about 0.01 Torr and 100 Torr for a time between about 1 second and about 60 seconds.

In block 250, instead of the post-deposition annealing process in block 240, an optional re-oxidation process is performed to thermally oxidize the substrate 302. The re-oxidation process may include a thermal annealing process in an oxygen (O ₂ ), nitrous oxide (N ₂ O) and H ₂ environment performed in a rapid thermal processing (RTP) chamber, the rapid thermal processing (RTP) ) chamber such as the RADOX™ chamber available from Applied Materials, Inc. located in Santa Clara, CA. Such an RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. 1 . The re-oxidation process in block 250 may thermally oxidize the underlying layers through the high-κ gate dielectric layer 306, thereby thickening the interface layer 304 to between about 3 Å and about 30 Å with the interface layer 304 formed in block 220. A thickness of between 10 Å and an interface layer 304 is formed in the substrate 302 near the interface with the high-κ dielectric layer 306 without forming the interface layer 304 in block 220 .

The reoxidation process may be performed at a temperature between about 400°C and about 900°C and a pressure between about 0.01 Torr and 100 Torr for a time between about 1 second and about 30 seconds.

In block 260 , a plasma nitridation process is performed to insert nitrogen atoms into pores and defects in the high-κ gate dielectric layer 306 . The plasma nitridation process may be a DPN process performed in a decoupled plasma nitridation (DPN) chamber such as is available from Applications in Santa Clara, California, USA CENTURA® DPN chambers acquired by Materials. Such a DPN chamber may be any of the process chambers 120 , 122 , 124 , 126 , 128 and 130 shown in FIG. 1 . The plasma nitridation process exposes the high-κ gate dielectric layer 306 to a nitrogen plasma, which can enable nitrogen radicals or nitrogen atoms to be incorporated into the high-κ gate dielectric layer 306 throughout its thickness within the high-κ gate dielectric layer 306 . During the plasma nitridation process, nitrogen atoms can form metastable bonds with oxygen (O). Gases that may be used in the plasma process include nitrogen-containing gases such as nitrogen ( _N2 ), ammonia ( _NH3 ), or mixtures of these gases. In one example, the nitrogen-containing gas is ammonia gas (NH ₃ ) mixed with about 3% to about 8% nitrogen gas (N ₂ ). The plasma nitridation process may not alter the thickness of the high-κ gate dielectric layer 306 as a result of the incorporation of nitrogen into the pores and defects of the deposited high-κ gate dielectric layer 306 .

The nitridation process may be performed at a temperature between about 0°C and about 500°C for a time between about 10 seconds and about 300 seconds.

In block 270, an optional thermal nitridation process is performed to further insert nitrogen atoms into pores and defects in the plasma-nitrided high-κ gate dielectric layer 306 . The thermal nitriding process may include a thermal annealing process in an ammonia (NH ₃ ) environment performed in a rapid thermal processing (RTP) chamber such as one available from Santa, California, USA The RADOX™ chamber obtained by Clara's Applied Materials. Such an RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. 1 .

The thermal nitridation process may be performed at a temperature between about 700°C and about 900°C and a pressure between about 10 Torr and 740 Torr for a time between about 10 seconds and about 300 seconds.

In block 280, a post-nitridation anneal process is performed to passivate the remaining chemical bonds in the high-κ gate dielectric layer 306 after plasma nitridation. The post-nitridation annealing process may include a spike thermal anneal process in a nitrogen ( _N2 ) and argon (Ar) environment performed in a rapid thermal processing (RTP) chamber, the rapid thermal processing (RTP) A chamber such as the RADOX™ chamber available from Applied Materials, Santa Clara, CA, USA. Such an RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. 1 . The post-nitridation annealing process may passivate the metastable nitrogen bonds formed during the plasma nitridation process in block 240 and crystallization of the amorphous high-κ gate dielectric layer 306 may occur.

The spike thermal annealing process may be performed at a temperature between about 700°C and about 850°C and a pressure between about 10 Torr and 740 Torr for a time between about 1 second and about 30 seconds.

In block 290 , instead of the post-nitridation anneal process in block 280 , a post-nitridation anneal and re-oxidation process is performed to simultaneously passivate the remaining chemical bonds in the high-κ gate dielectric layer 306 as in block 280 and The substrate 302 is thermally oxidized as in block 250 . The post-nitridation annealing and re-oxidation process in block 290 is the same as the re-oxidation process in block 250 . Therefore, the details of the post-nitridation annealing and re-oxidation process in block 290 are omitted here.

4 is a process flow diagram of a method 400 of forming a metal gate structure 500 over a gate dielectric layer 306 in a semiconductor structure 300 in accordance with one or more embodiments of the present disclosure. 5A , 5B, and 5C are cross-sectional views of a portion of a metal gate structure 500 in the semiconductor structure 300 corresponding to various states of the method 400 . It should be understood that FIGS. 5A, 5B, and 5C show only partial schematic views of semiconductor structure 300, and semiconductor structure 300 may include any number of transistor sections and additional materials having multiple aspects as shown. It should also be noted that although the method steps shown in FIG. 4 are described sequentially, one or more of the steps have been omitted and/or added, and/or have been rearranged in another desired order. Other processing sequences of method steps or steps are also within the scope of the various embodiments of the present disclosure provided herein.

The method 400 begins with a deposition process in block 410 to deposit a high-κ dielectric capping layer 502 on the gate dielectric layer 306 of the semiconductor structure 300, as shown in FIG. 5A. The high-κ dielectric cap layer 502 may be composed of titanium (Ti) or tantalum ( Ta) metal nitride materials such as TiSiN, TaSiN, TiAlN, TaAlN, TiGaN, TaGaN, TiGeN, TaGeN, TiInN, TaInN, TiHfN or TaHfN. The high-κ dielectric capping layer 502 formed from the metal nitride material thus doped can prevent silicon (Si) migration during subsequent silicon deposition processes in block 430 . The deposition process in block 410 may include an atomic layer deposition (ALD) process in which a metal-containing precursor, a nitrogen-containing precursor, and a dopant-containing precursor including titanium (Ti) or tantalum (Ta) are delivered to The surface of the gate dielectric layer 306 . Examples of metal-containing precursors including titanium (Ti) or tantalum (Ta) and examples of nitrogen-containing precursors are listed in the description of block 420 . The dopant-containing precursor includes aluminum (Al), gallium (Ga), germanium (Ge), hafnium (Hf), indium (In), or silicon (Si). Examples of the dopant-containing precursor containing aluminum (Al) include inorganic compounds of aluminum (Al) and organometallic compounds of aluminum (Al) such as aluminum chloride ( AlCl ₃ ) and aluminum bromide (AlBr ₃ ), organometallic compounds of aluminum (Al) such as trimethylaluminum (TMA, (CH ₃ ) ₃ Al), dimethylaluminum hydride (DMAH, (CH ₃ ) ₂ AlH), tris(diethylamino)aluminum (TDEAA, Al(N(C ₂ H ₅ ) ₂ ) ₃ ), trimethylamine alane (TMAA, AlH _{3 )} -N(CH ₃ ) ₃ ), triethylamine alane (TEAA, AlH ₃ -N(C ₂ H ₅ ) ₃ ), dimethylethylamine alane (AlH ₃ -C ₂ H ₅ N(CH ₃ ) ₂ ), triisobutylaluminum (TiBA, [Al(CH ₃ ) ₂ CHCH ₂ ] ₃ ) ), triethylaluminum (TEAl, Al(C ₂ H ₅ ) ₃ ), dimethylaluminum hydride (DMAH, (CH ₃ ) ₂ AlH) and diethylaluminum chloride (DEAC, (C ₂ H ₅ ) ₂ AlCl). Examples of the dopant-containing precursor containing gallium (Ga) include inorganic compounds of gallium (Ga) such as gallium tribromide (GaBr ₃ ) and organometallic compounds of gallium (Ga) and gallium trichloride (GaCl ₃ ), organometallic compounds of gallium (Ga) such as trimethyl gallium (Ga(CH ₃ ) ₃ ), triethylgallium (Ga(C ₂ H ₅ ) ₃ ), triisopropylgallium (triisopropylgallium, Ga(CH(CH ₃ ) ₂ ) ₃ ), tris(dimethylamido) gallium (tris(dimethylamido) gallium, Ga(N(CH ₃ ) ₂ ) ₃ ) and tert-butylgallium (tri-tert-butylgallium, Ga(C(CH ₃ ) ₃ ) ₃ ). Examples of the dopant-containing precursor containing germanium (Ge) include inorganic compounds of germanium (Ge) such as digermane (Ge ₂ ) and organometallic compounds of germanium (Ge) H ₆ ) and germane (germane, GeH ₄ ), organometallic compounds of germanium (Ge) such as tetramethylgermanium ((CH ₃ ) ₄ Ge). Examples of the dopant-containing precursor containing hafnium (Hf) include inorganic compounds of hafnium (Hf) such as hafnium (tetravalent) chloride ( hafnium(IV) chloride, HfCl ₄ ), organometallic compounds of hafnium (Hf) such as hafnium(IV) tert-butoxide, Hf[OC(CH ₃ ) ₃ ] ₄ ), Tetrakis(diethylamido)hafnium(IV), [(CH ₂ CH ₃ ) ₂ N] ₄ Hf), tetrakis(diethylamido) hafnium(IV), tetrakis(diethylamido) hafnium(IV) (tetrakis(dimethylamido)hafnium(IV), [(CH ₃ ) ₂ N] ₄ Hf) and tetrakis(ethylmethylamido)hafnium(IV),TEMAH, [ (CH ₃ )(C ₂ H ₅ )N] ₄ Hf). Examples of the dopant-containing precursor containing indium (In) include inorganic compounds of indium (In) and organometallic compounds of indium (In) such as indium trichloride (indium trichloride, InCl ₃ ) and indium iodide (monovalent) (indium(I) iodide, InI), organometallic compounds of indium (In) such as triethylindium (In(CH ₂ CH ₃ ) ₃ ) and acetone Indium (III) acetylacetonate, In(OCCH ₃ CHOCCH ₃ ) ₃ ). Examples of the dopant-containing precursor including silicon (Si) include inorganic compounds of silicon (Si) and organometallic compounds of silicon (Si) such as silane (SiH ₄ ), Disilane (Si ₂ H ₆ ), organometallic compounds of silicon (Si) such as trimethylsilane (trimethyl, (CH ₃ ) ₃ SiH) and neopentasilane ((SiH ₃ ) ₄ Si).

The order in which the metal-containing precursor, nitrogen-containing precursor, and dopant-containing precursor are delivered can be varied. In some embodiments, metal-containing precursors, nitrogen-containing precursors, and dopant-containing precursors are alternately delivered. In some embodiments, the metal-containing precursor and the dopant-containing precursor are delivered simultaneously, and after purification, the nitrogen-containing precursor is delivered. Table 1 below shows several non-limiting sequence variations.

Table 1 Exemplary deposition sequence Options order 1 metal-containing precursor → purification → nitrogen-containing precursor → purification → dopant-containing precursor → purification → nitrogen-containing precursor → purification → repeat 2 dopant-containing precursor → purification → nitrogen-containing precursor → purification → metal-containing precursor → purification → nitrogen-containing precursor → purification → repeat 3 Metal-containing precursor → purification → (nitrogen-containing precursor + dopant-containing precursor) → purification → repeat 4 (metal-containing precursor + dopant-containing precursor) → purification → nitrogen-containing precursor → purification → repeat 5 metal-containing precursor → dopant-containing precursor → purification → nitrogen-containing precursor → purification → repeat 6 dopant-containing precursor → metal-containing precursor → purification → nitrogen-containing precursor → purification → repeat

The ALD process in block 410 may be performed at a temperature between about 200°C and about 700°C (eg, between about 300°C and about 600°C). As deposited by the ALD process in block 410, the high-κ dielectric cap layer 502 may be amorphous and have between about 2 Å and about 200 Å (eg, between about 10 Å and about 15 Å) thickness. The deposition process may be performed in a processing chamber such as processing chambers 120, 122, 124, 126, 128, or 130 shown in FIG.

In block 420, an optional metal cap annealing process is performed to harden and densify the deposited high-κ dielectric cap layer 502 . Crystallization of the deposited high-κ dielectric cap layer 502 may occur. The optional metal cap annealing process in block 420 may include a thermal annealing process performed in a rapid thermal processing (RTP) chamber in an inert environment, such as in a nitrogen ( _N2 ) and argon (Ar) environment , such a rapid thermal processing (RTP) chamber such as the RADOX™ chamber available from Applied Materials, Inc. located in Santa Clara, CA, USA. Such an RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. 1 .

The optional metal cap annealing process in block 420 may be performed for about 1 second and about 10 seconds at a temperature between about 700°C and about 850°C and a pressure between about 0.1 Torr and 100 Torr time between.

In block 430, a deposition process is performed to deposit the sacrificial silicon capping layer 504 on the high-κ dielectric capping layer 502, as shown in FIG. 5B. The sacrificial silicon cap layer 504 may physically and chemically protect the underlying high-κ gate dielectric layer 306 and high-κ dielectric cap layer 502 during subsequent annealing processes in block 440 . The sacrificial silicon cap layer 504 is formed of amorphous silicon, such as hydrogenated amorphous silicon (a-Si:H). Amorphous silicon can provide less atomic diffusion than polysilicon containing grain boundaries leading path for diffusion. The deposition process in block 430 may be an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process in which the semiconductor structure 300 with the high-κ dielectric cap layer 502 formed thereon is exposed to a silicon precursor. Examples of silicon precursors are poly-silanes _{( SixHy} ). For example, polysilanes include disilane (Si ₂ H ₆ ), trisilane (Si ₃ H ₈ ), tetrasilane (Si ₄ H ₁₀ ), isobutylsilane (isotetrasilane), neopentasilane (neopentasilane) , Si ₅ H ₁₂ ), cyclopentasilane (Si ₅ H ₁₀ ), _hexasilane (C ₆ H ₁₄ ), cyclohexasilane (Si ₆ H ₁₂ ) or in general Six H _y (where x=2 or greater), and their combinations.

The sacrificial silicon cap layer 504 may have a thickness between about 30 Å and about 50 Å. The deposition process in block 430 may be performed in a processing chamber such as processing chamber 120, 122, 124, 126, 128, or 130 shown in FIG.

In block 440, a post cap anneal (PCA) process is performed to harden and densify the deposited high-κ dielectric cap layer 502 . Crystallization of the deposited high-κ dielectric cap layer 502 and the deposited sacrificial silicon cap layer 504 may occur. The PCA process in block 440 may include a thermal annealing process in an inert environment, such as in a nitrogen ( _N2 ) and argon (Ar) environment, performed in a rapid thermal processing (RTP) chamber. RTP) chambers such as RADOX™ chambers available from Applied Materials, Inc. located in Santa Clara, CA. Such an RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. 1 .

The PCA process in block 440 may be performed at a temperature between about 900°C and about 1000°C (eg, about 900°C) and a pressure between about 0.1 Torr and 100 Torr for about 1 second and about time between 10 seconds.

In block 450 , a removal process is performed to strip the sacrificial silicon cap layer 504 . The removal process may include a dry plasma etching process.

Following the removal process in block 460, in block 460, a deposition process is performed to deposit a metal layer 506 over the hardened and densified high-κ dielectric cap layer 502, as shown in Figure 5C. The metal layer 506 may be formed of tungsten (W) or cobalt (Co). Metal layer 506 may be p-doped or n-doped. The deposition process in block 450 may include a chemical vapor deposition (CVD) process using a cobalt-containing precursor or a tungsten-containing precursor such as _WF6 .

The high-κ dielectric capping layer 502 described herein formed from doped metal nitride materials may be effective, for example, as a fluorine barrier in the deposition process in block 460 using a fluorine-containing precursor such as _WF6 ( fluorine barrier). The high-κ dielectric capping layer 502 described herein formed of doped metal nitride materials can also prevent aluminum (Al) migration, thereby alleviating the need for an aluminum barrier, while the A traditional high-κ dielectric cap layer formed of a metal nitride material allows aluminum to migrate. The high-κ dielectric capping layer 502 formed from the doped metal nitride materials described herein can also be used as a work function layer to increase the effective work function at the interface between the high-κ dielectric capping layer 502 and the metal layer 506 .

In some embodiments, the deposition process used to deposit the high-κ dielectric capping layer 502 in block 410 and block 430 are performed without disrupting the low pressure or vacuum environment in a processing system such as processing system 100 The deposition process used to deposit the sacrificial silicon cap layer 504 in FIG. Processes that do not disrupt the low pressure or vacuum environment can reduce contamination due to the introduction of moisture into the atmosphere.

In some embodiments, the deposition process used to deposit the high-κ dielectric capping layer 502 in block 410 , block 430 is performed without disrupting the low pressure or vacuum environment in the processing system, such as the processing system 100 . The deposition process used to deposit the sacrificial silicon cap layer 504 in block 440 and the cap back anneal (PCA) process in block 440 . A process that does not disrupt the low pressure or vacuum environment can reduce contamination due to moisture introduced in the atmospheric environment and further prevent thickening of the high-κ gate dielectric layer 306 .

In various embodiments described herein, systems and methods are provided for forming high quality thin layers of high-κ dielectric material and metal gate structures. The properties of such a high-κ dielectric material layer can be well controlled. For example, the nitridation process in blocks 260 and 270 may be controlled to provide between about 3 atomic % and about 20 atomic % nitrogen in the high-κ gate dielectric layer 306 to combine with higher nitrogen Higher κ values for the bound case, and better structural stability compared to the lower nitrogen bound case. The annealing process in blocks 240, 270, 280, and 290 may also be controlled to provide grains having dimensions greater than about 20 Å in the high-κ gate dielectric layer 306, thereby reducing flow through the high-κ gate dielectric layer 306 leakage current.

The metal gate structures described herein can exhibit reduced equivalent oxide thickness (EOT), reduced leakage current therethrough, and increased effective work function. The metal gate structures described herein can also exhibit aluminum (A) barrier properties, which enable the direct formation of aluminum layers on the metal gate structures. This metal gate structure can be advantageously used in any barrier application and/or any metal gate application in flash memory, dynamic random access memory (DRAM) and MOSFETs.

While the foregoing relates to various embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the essential scope of the present disclosure, and the scope of the present disclosure is determined by the accompanying application the scope of the patent.

100: Multi-chamber processing system 102: Factory interface 104: Load lock chamber 106: Load lock chamber 108: Transfer Chamber 110: Transfer Chamber 112: Teleport Manipulator 114: Teleport Manipulator 116: Keeping the chamber 118: Keeping the chamber 120: Processing Chamber 122: Processing Chamber 124: Processing Chamber 126: Processing Chamber 128: Processing Chamber 130: Processing Chamber 140: Dock 142: Factory Interface Robot 144: Front opening standard cabin 148: Blade 150: port 152: port 154: port 156: port 158: port 160: port 162: port 164: port 166: port 168: port 170: port 172: port 174: port 176: port 190: System Controller 192: Central Processing Unit 194: Memory 196: Support circuit 200: Method 210: Box 220: Box 230: Box 240: Box 250: Box 260: Box 270: Box 280: Box 290: Box 300: Semiconductor Structure 302: Substrate 304: interface layer 306: High-κ gate dielectric layer 400: Method 410: Box 420: Box 430: Box 440: Box 450: Box 460: Box 480: Box 500: Metal gate structure 502: High-κ dielectric capping layer 504: Sacrificial Silicon Cap Layer 506: Metal Layer

In order that the manner in which the above-described features of the present disclosure can be understood in detail, the present disclosure, briefly summarized above, may be described in more detail by reference to a number of embodiments, some of which are illustrated in the accompanying drawings. Way. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments.

1 is a schematic top view of an example multi-chamber processing system according to one embodiment.

2 is a process flow diagram of a method of forming a semiconductor structure according to one embodiment.

3A and 3B are schematic diagrams of a semiconductor structure according to one embodiment.

4 is a process flow diagram of a method of forming a semiconductor structure according to one embodiment.

5A, 5B, and 5C are schematic diagrams of semiconductor structures according to one embodiment.

To facilitate understanding, wherever possible, the same reference numerals have been used to refer to the same elements common to the various figures. It is contemplated that elements and features of one embodiment may be beneficially combined in other embodiments without further recitation.

Domestic storage information (please note in the order of storage institution, date and number) none Foreign deposit information (please note in the order of deposit country, institution, date and number) none

400: Method

410: Box

420: Box

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Claims (25)

A method of forming a semiconductor structure, the method comprising the steps of: A high-κ dielectric capping layer is formed on a semiconductor structure formed on a substrate, comprising: depositing the high-κ dielectric capping layer on the semiconductor structure; depositing a sacrificial silicon capping layer on the high-κ dielectric capping layer; performing a post-cap annealing process to harden and densify the deposited high-κ dielectric capping layer; and The sacrificial silicon capping layer is removed. The method of claim 1, wherein the step of forming the high-κ dielectric capping layer is performed in a processing system without breaking vacuum. The method according to claim 1, further comprising the following steps: Forming the semiconductor structure on the substrate includes: pre-cleaning a surface of the substrate; forming an interface layer on the pre-cleaned surface of the substrate; depositing a high-κ gate dielectric layer on the interface layer; performing a plasma nitridation process to insert nitrogen atoms into the deposited high-κ gate dielectric layer; and A post-nitridation annealing process is performed to passivate chemical bonds in the plasma-nitrided high-κ gate dielectric layer. The method of claim 3, wherein the interface layer comprises silicon oxide (SiO ₂ ), and the step of forming the interface layer comprises the steps of: irradiating the substrate with nitrous oxide (N ₂ O) gas Thermal oxidation. The method of claim 3, wherein the high-κ gate dielectric layer comprises hafnium oxide (HfO ₂ ). The method of claim 3, wherein the plasma nitridation process comprises: exposing the deposited high-κ gate dielectric layer to a process using a mixture of nitrogen (N ₂ ) and ammonia (NH ₃ ). Nitrogen plasma. The method of claim 3, wherein the post-nitridation annealing process comprises: at a temperature between 700°C and 850°C and in a nitrogen (N ₂ ) and argon (Ar) environment, The deposited high-κ gate dielectric layer is subjected to spike annealing. The method of claim 3, further comprising the step of: prior to the plasma nitridation process, performing a post-deposition annealing process to harden and densify the deposited high-κ gate dielectric layer, wherein the deposition The post-annealing process includes annealing the deposited high-κ gate dielectric layer at a temperature between 500°C and 800°C in a nitrogen ( _N2 ) and argon (Ar) environment . The method of claim 3, further comprising the steps of: before the post-nitridation annealing process, performing a thermal nitridation process to further insert nitrogen into the plasma-nitrided high-κ gate dielectric layer atom, wherein the thermal nitridation process includes: at a temperature between 700°C and 900°C and in an ammonia (NH ₃ ) environment, the high-κ gate dielectric after nitridation of the plasma layer is annealed. The method of claim 1, wherein the high-κ dielectric capping layer comprises TiSiN. The method of claim 1, further comprising the step of: before the step of depositing the sacrificial silicon cap layer, performing a metal cap annealing process at a temperature between 700°C and 850°C And the deposited high-κ dielectric capping layer is hardened and densified in a nitrogen ( _N2 ) environment. The method of claim 1, wherein the back cap annealing process comprises: the high-κ dielectric capping layer at a temperature between 900°C and 1000°C in a nitrogen (N ₂ ) environment Annealed. A method of forming a semiconductor structure, the method comprising the steps of: A high-κ dielectric capping layer is formed on a semiconductor structure formed on a substrate, comprising: depositing the high-κ dielectric capping layer on the semiconductor structure; depositing a sacrificial silicon capping layer on the high-κ dielectric capping layer; performing a post-cap annealing process to harden and densify the deposited high-κ dielectric capping layer; and The sacrificial silicon capping layer is removed. The method of claim 13, wherein the step of forming the high-κ dielectric capping layer is performed in a processing system without breaking vacuum. The method of claim 13, further comprising the following steps: Forming the semiconductor structure on the substrate includes: pre-cleaning a surface of the substrate; depositing a high-κ gate dielectric layer on the substrate; and A plasma nitridation process is performed to insert nitrogen atoms into the deposited high-κ gate dielectric layer. The method of claim 15, further comprising the steps of: forming an interface layer on the pre-cleaned surface of the substrate, comprising: thermally oxidizing the substrate with nitrous oxide (N ₂ O) gas , wherein the interface layer includes silicon oxide (SiO ₂ ). The method of claim 15, wherein the high-κ gate dielectric layer comprises hafnium oxide (HfO ₂ ). The method of claim 15, wherein the plasma nitridation process includes exposing the deposited high-κ gate dielectric layer to a process using a mixture of nitrogen (N ₂ ) and ammonia (NH ₃ ). Nitrogen plasma. The method of claim 15, further comprising the steps of: before the plasma nitridation process, performing a re-oxidation process to thermally oxidize the substrate; and after the plasma nitridation process, performing a nitridation back-off Fire process to passivate chemical bonds in the high-κ gate dielectric layer after plasma nitridation, wherein the re-oxidation process comprises: at a temperature between 400°C and 900°C and in an oxygen (O ₂ ), nitrous oxide (N ₂ O) and H ₂ , annealing the high-κ gate dielectric layer; and the post-nitridation annealing process includes: between 700 ° C and 850 ° C The plasma-nitrided high-κ gate dielectric layer is spike annealed in a nitrogen (N ₂ ) and argon (Ar) atmosphere at a temperature in between. The method of claim 15, further comprising the steps of: after the plasma nitridation process, performing a re-oxidation process to passivate the remaining chemical bonds in the high-k gate dielectric layer after the plasma nitridation and thermally oxidizing the substrate, wherein the re-oxidation process comprises: at a temperature between 400°C and 900°C and a mixture of oxygen (O ₂ ), nitrous oxide (N ₂ O) and H ₂ ambient, the high-κ gate dielectric layer is annealed. The method of claim 13, wherein the high-κ dielectric capping layer comprises TiSiN. The method of claim 13, further comprising the step of: performing a metal cap annealing process at a temperature between 700°C and 850°C prior to the step of depositing the sacrificial silicon cap layer And the deposited high-κ dielectric capping layer is hardened and densified in a nitrogen ( _N2 ) environment. The method of claim 13, wherein the back cap annealing process comprises: the high-κ dielectric capping layer at a temperature between 900°C and 1000°C in a nitrogen (N ₂ ) environment Annealed. A processing system comprising: a first processing chamber; a second processing chamber; a third processing chamber; a fourth processing chamber; and A system controller configured to: depositing a high-κ dielectric capping layer on a semiconductor structure formed on a substrate in the first processing chamber; depositing a sacrificial silicon capping layer on the high-κ dielectric capping layer in the second processing chamber; in the third processing chamber, performing a back cap annealing process to harden and densify the deposited high-κ dielectric capping layer; and In the fourth processing chamber, the sacrificial silicon capping layer is removed, Wherein, the substrate is transferred between the first processing chamber, the second processing chamber, the third processing chamber and the fourth processing chamber without breaking the vacuum environment in the processing system. The processing system of claim 24, further comprising: a fifth processing chamber; a sixth processing chamber; a seventh processing chamber; an eighth processing chamber; and a ninth processing chamber, wherein The system controller is further structured to: pre-cleaning a surface of the substrate in the fifth processing chamber; in the sixth processing chamber, forming an interface layer on the pre-cleaned surface of the substrate; in the seventh processing chamber, depositing a high-κ dielectric layer on the interface layer; in the eighth processing chamber, exposing the deposited high-κ gate dielectric layer to a nitrogen plasma; and In the ninth processing chamber, the plasma nitrided high-κ gate dielectric layer is annealed, and Transfer the substrate between the fifth processing chamber, the sixth processing chamber, the seventh processing chamber, the eighth processing chamber and the ninth processing chamber without breaking the vacuum in the processing system surroundings.

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