TW202224201A - Imaging element, stacked-type imaging element, solid-state imaging device, and driving method for solid-state imaging device - Google Patents

Imaging element, stacked-type imaging element, solid-state imaging device, and driving method for solid-state imaging device Download PDF

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TW202224201A
TW202224201A TW111102156A TW111102156A TW202224201A TW 202224201 A TW202224201 A TW 202224201A TW 111102156 A TW111102156 A TW 111102156A TW 111102156 A TW111102156 A TW 111102156A TW 202224201 A TW202224201 A TW 202224201A
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electrode
photoelectric conversion
imaging element
layer
potential
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富樫秀晃
古閑史彦
山口哲司
平田晉太郎
渡部泰一郎
安藤良洋
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日商新力股份有限公司
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Abstract

An imaging device is provided. The imaging device may include a substrate having a first photoelectric conversion unit and a second photoelectric conversion unit at a light-incident side of the substrate. The second photoelectric conversion unit may include a photoelectric conversion layer, a first electrode, a second electrode above the photoelectric conversion layer, a third electrode, and an insulating material between the third electrode and the photoelectric conversion layer, wherein a portion of the insulating material is between the first electrode and the third electrode.

Description

成像元件、堆疊型成像元件、固態成像裝置及用於固態成像裝置之驅動方法Imaging element, stacked imaging element, solid-state imaging device, and driving method for solid-state imaging device

本發明係關於一種成像元件、一種堆疊型成像元件、一種固態成像裝置及一種用於一固態成像裝置之驅動方法。The present invention relates to an imaging element, a stacked imaging element, a solid-state imaging device, and a driving method for a solid-state imaging device.

將有機半導體材料用於光電轉換層之成像元件可光電轉換特定色彩(波長頻帶)。此外，由於該特性，因此在將成像元件用作固態成像裝置中之成像元件之情形中，可能達成一子像素結構(堆疊型成像元件)，其中每一子像素組態為一晶片上彩色濾光器(OCCF)與一成像元件之一組合，且子像素以二維方式配置(舉例而言，參考JP 2011-138927 A)。另外，由於一去馬賽克程序係不必要的，因此存在不會發生偽色彩之一優點。注意，在下文中之說明中，在某些情形中，為方便說明而將設置於一半導體基板上或上方且包含一光電轉換單元之一成像元件稱為一「第一類型成像元件」；為方便說明而將構成第一類型成像元件之一光電轉換單元稱為一「第一類型光電轉換單元」；為方便說明而將設置於一半導體基板中之一成像元件稱為一「第二類型成像元件」；且為方便說明而將構成第二類型成像元件之一光電轉換單元稱為一「第二類型光電轉換單元」。 在圖49中圖解說明相關技術中之一堆疊型成像元件(堆疊型固態成像裝置)之一結構實例。在圖49中所圖解說明之實例中，一第三光電轉換單元331及一第二光電轉換單元321係分別構成一第三成像元件330及一第二成像元件320 (作為形成於一半導體基板370中之將被堆疊之第二類型成像元件)之第二類型光電轉換單元。另外，一第一光電轉換單元311係配置於半導體基板370上方(具體而言，第二成像元件320上方)之一第一類型光電轉換單元。第一光電轉換單元311經組態以包含一第一電極311、由一有機材料製成之一光電轉換層315及一第二電極316且構成一第一成像元件310作為一第一類型成像元件。由於吸收係數之一差異，因此第二光電轉換單元321及第三光電轉換單元331分別光電轉換(舉例而言)藍色光及紅色光。另外，第一光電轉換單元311光電轉換(舉例而言)綠色光。 透過第二光電轉換單元321及第三光電轉換單元331中之光電轉換產生之電荷被暫時儲存於第二光電轉換單元321及第三光電轉換單元331中，且在此之後分別藉由一垂直型電晶體(圖解說明閘極部分322)及一轉移電晶體(圖解說明閘極部分332)而被轉移至第二浮動擴散層(浮動擴散) FD 2及第三浮動擴散層FD 3。該等電荷進一步被輸出至一外部讀取電路(未展示)。電晶體以及浮動擴散層FD 2及FD 3亦形成於半導體基板370中。 透過第一光電轉換單元311中之光電轉換產生之電荷透過一接觸孔部分361及一導線層362而被儲存至形成於半導體基板370中之一第一浮動擴散層FD 1。第一光電轉換單元311亦透過接觸孔部分361及導線層362而連接至將一電荷量轉換為一電壓之一放大電晶體之一閘極部分318。此外，第一浮動擴散層FD 1構成一重設電晶體之一部分(圖解說明閘極部分317)。注意，元件符號371表示一元件隔離區域；元件符號372表示形成於半導體基板370之一表面上之一種氧化物膜；元件符號376及381表示層間絕緣層；元件符號383表示一保護層；且元件符號390表示一晶片上微透鏡。 [引證列表] [專利文獻] [PTL 1] JP 2011-138927 A An imaging element using an organic semiconductor material for a photoelectric conversion layer can photoelectrically convert a specific color (wavelength band). Furthermore, due to this characteristic, in the case of using an imaging element as an imaging element in a solid-state imaging device, it is possible to achieve a sub-pixel structure (stacked imaging element) in which each sub-pixel is configured as an on-wafer color filter An optical device (OCCF) is combined with one of an imaging element, and the sub-pixels are arranged in a two-dimensional manner (for example, refer to JP 2011-138927 A). In addition, since a demosaicing procedure is unnecessary, there is an advantage that false color does not occur. Note that in the following description, in some cases, an imaging element disposed on or above a semiconductor substrate and including a photoelectric conversion unit is referred to as a "first-type imaging element" for convenience of description; for convenience In the description, a photoelectric conversion unit constituting the first-type imaging element is referred to as a "first-type photoelectric conversion unit"; for the convenience of description, an imaging element disposed in a semiconductor substrate is referred to as a "second-type imaging element"”; and for the convenience of description, a photoelectric conversion unit constituting the second type imaging element is referred to as a “second type photoelectric conversion unit”. A structural example of a stack-type imaging element (stack-type solid-state imaging device) in the related art is illustrated in FIG. 49 . In the example illustrated in FIG. 49, a third photoelectric conversion unit 331 and a second photoelectric conversion unit 321 constitute a third imaging element 330 and a second imaging element 320, respectively (as formed on a semiconductor substrate 370 Among them, the second type photoelectric conversion unit of the second type imaging element to be stacked). In addition, a first photoelectric conversion unit 311 is disposed on a first-type photoelectric conversion unit above the semiconductor substrate 370 (specifically, above the second imaging element 320 ). The first photoelectric conversion unit 311 is configured to include a first electrode 311, a photoelectric conversion layer 315 made of an organic material, and a second electrode 316 and constitute a first imaging element 310 as a first type imaging element . Due to a difference in absorption coefficient, the second photoelectric conversion unit 321 and the third photoelectric conversion unit 331 photoelectrically convert, for example, blue light and red light, respectively. In addition, the first photoelectric conversion unit 311 photoelectrically converts, for example, green light. The charges generated by the photoelectric conversion in the second photoelectric conversion unit 321 and the third photoelectric conversion unit 331 are temporarily stored in the second photoelectric conversion unit 321 and the third photoelectric conversion unit 331, and thereafter, respectively by a vertical type The transistor (illustrating gate portion 322) and a transfer transistor (illustrating gate portion 332) are transferred to a second floating diffusion layer (floating diffusion) FD2 and a third floating diffusion layer FD3 . The charges are further output to an external readout circuit (not shown). Transistors and floating diffusion layers FD 2 and FD 3 are also formed in the semiconductor substrate 370 . Charges generated through photoelectric conversion in the first photoelectric conversion unit 311 are stored in a first floating diffusion layer FD 1 formed in the semiconductor substrate 370 through a contact hole portion 361 and a wire layer 362 . The first photoelectric conversion unit 311 is also connected to a gate portion 318 of an amplifying transistor that converts a charge amount into a voltage through the contact hole portion 361 and the wire layer 362 . Furthermore, the first floating diffusion layer FD1 forms part of a reset transistor (gate portion 317 is illustrated). Note that element numeral 371 denotes an element isolation region; element numeral 372 denotes an oxide film formed on a surface of the semiconductor substrate 370; element numerals 376 and 381 denote interlayer insulating layers; element numeral 383 denotes a protective layer; Reference numeral 390 denotes an on-wafer microlens. [Citation List] [Patent Literature] [PTL 1] JP 2011-138927 A

[技術問題] 然而，透過第二光電轉換單元321及第三光電轉換單元331中之光電轉換產生之電荷被暫時儲存於第二光電轉換單元321及第三光電轉換單元331中，且在此之後分別被轉移至第二浮動擴散層FD 2及第三浮動擴散層FD 3。因此，可能完全耗盡第二光電轉換單元321及第三光電轉換單元331。然而，透過第一光電轉換單元311中之光電轉換產生之電荷被直接儲存於第一浮動擴散層FD 1中。因此，難以完全耗盡第一光電轉換單元311。因此，kTC雜訊增加、隨機雜訊劣化且因此，成像中之影像品質劣化。 本發明提供一種成像元件(其中一光電轉換單元配置於一半導體基板上或上方且該成像元件具有能夠抑制成像品質之劣化之一組態及一結構)、一種組態有該成像元件之堆疊型成像元件、一種包含該成像元件或該堆疊型成像元件之固態成像裝置及一種用於一固態成像裝置之驅動方法。 [問題之解決方案] 根據本發明之一第一實施例，提供一種成像裝置。該成像裝置可包含：一基板，其包含一第一光電轉換單元；及一第二光電轉換單元，其位於該基板之一光入射側處。該第二光電轉換單元可包含：一光電轉換層；一第一電極；一第二電極，其位於該光電轉換層上方；一第三電極；及一絕緣材料，其介於該第三電極與該光電轉換層之間，其中該絕緣材料之一部分介於該第一電極與該第三電極之間。 根據本發明之一第二實施例，提供一種電子設備，該電子設備包含一成像裝置，該成像裝置包含：一基板，其包含一第一光電轉換單元；及一第二光電轉換單元，其位於該基板之一光入射側處。該第二光電轉換單元可包含：一光電轉換層；一第一電極；一第二電極，其位於該光電轉換層上方；一第三電極；及一絕緣材料，其介於該第三電極與該光電轉換層之間，其中該絕緣材料之一部分介於該第一電極與該第三電極之間；及一透鏡，其經組態以將光引導至該成像裝置之一表面上。 根據本發明之一第三實施例，提供一種驅動一成像裝置之方法。該方法可包含：在一充電週期期間將一第一電位施加至一電荷儲存電極；在一充電週期期間將一第二電位施加至一第一電極，其中該第一電位大於該第二電位；在一電荷轉移週期期間將一第三電位施加至該電荷儲存電極；及在該電荷轉移週期期間將一第四電位施加至該第一電極，其中該第四電位大於該第三電位。在一些實施例中，該成像裝置包含：一基板，其包含一第一光電轉換單元；及一第二光電轉換單元，其位於該基板之一光入射側處。該第二光電轉換單元可包含：一光電轉換層；該第一電極；一第二電極，其位於該光電轉換層上方；該電荷儲存電極；及一絕緣材料，其介於該電荷儲存電極與該光電轉換層之間，其中該絕緣材料之一部分介於該第一電極與該電荷儲存電極之間。 [本發明之有利效應] 在根據本發明之一實施例之一成像元件、構成根據本發明之一實施例之一堆疊型成像元件的根據本發明之一實施例之一成像元件或構成根據本發明之一第一或第二實施例之一固態成像裝置的根據本發明之一實施例之一成像元件(在某些情形中，在下文中將此等成像元件統稱為一「根據本發明之一實施例之成像元件或諸如此類」)中，由於包含一電荷儲存電極，該電荷儲存電極經配置以與一第一電極分離且經配置以面向一光電轉換層(其中一絕緣層插置於該電荷儲存電極與該光電轉換層之間)，因此當用光來照明光電轉換單元且在光電轉換單元中對該光進行光電轉換時，可儲存光電轉換層之電荷。因此，在一開始曝光時，藉由完全耗盡一電荷儲存單元，可能抹除電荷。因此，可能抑制kTC雜訊之一增加、隨機雜訊之劣化及成像中之影像品質之劣化之現象的發生。在用於根據本發明之一實施例之一固態成像裝置之一驅動方法中，每一成像元件具有一結構，在該結構中自一第二電極側入射之光並不入射於第一電極上，且因此，同時在所有成像元件中，將電荷儲存於光電轉換層中，且將第一電極之電荷射出至外部，使得可能同時在所有成像元件中可靠地執行重設第一電極。隨後，同時在所有成像元件中，將儲存於光電轉換層中之電荷轉移至第一電極，且在完成轉移之後，依序讀出轉移至各別成像元件中之第一電極之電荷。因此，可容易地實施一所謂的全域快門功能。注意，說明書中所揭示之效應係例示性效應而非限制性效應，且亦可存在額外效應。 [Technical Problem] However, charges generated through photoelectric conversion in the second photoelectric conversion unit 321 and the third photoelectric conversion unit 331 are temporarily stored in the second photoelectric conversion unit 321 and the third photoelectric conversion unit 331, and after that are transferred to the second floating diffusion layer FD 2 and the third floating diffusion layer FD 3 , respectively. Therefore, the second photoelectric conversion unit 321 and the third photoelectric conversion unit 331 may be completely depleted. However, the charges generated through the photoelectric conversion in the first photoelectric conversion unit 311 are directly stored in the first floating diffusion layer FD1. Therefore, it is difficult to completely deplete the first photoelectric conversion unit 311 . Therefore, kTC noise increases, random noise is degraded, and thus, image quality in imaging is degraded. The present invention provides an imaging element (in which a photoelectric conversion unit is disposed on or above a semiconductor substrate, and the imaging element has a configuration and a structure capable of suppressing deterioration of imaging quality), a stacked type in which the imaging element is configured An imaging element, a solid-state imaging device including the imaging element or the stacked imaging element, and a driving method for a solid-state imaging device. [Solution to Problem] According to a first embodiment of the present invention, there is provided an image forming apparatus. The imaging device may include: a substrate including a first photoelectric conversion unit; and a second photoelectric conversion unit located at a light incident side of the substrate. The second photoelectric conversion unit may include: a photoelectric conversion layer; a first electrode; a second electrode located above the photoelectric conversion layer; a third electrode; and an insulating material between the third electrode and the Between the photoelectric conversion layers, a part of the insulating material is interposed between the first electrode and the third electrode. According to a second embodiment of the present invention, an electronic device is provided, the electronic device includes an imaging device, and the imaging device includes: a substrate including a first photoelectric conversion unit; and a second photoelectric conversion unit located at at a light incident side of the substrate. The second photoelectric conversion unit may include: a photoelectric conversion layer; a first electrode; a second electrode located above the photoelectric conversion layer; a third electrode; and an insulating material between the third electrode and the between the photoelectric conversion layers, wherein a portion of the insulating material is interposed between the first electrode and the third electrode; and a lens configured to direct light onto a surface of the imaging device. According to a third embodiment of the present invention, a method of driving an imaging device is provided. The method may include: applying a first potential to a charge storage electrode during a charging cycle; applying a second potential to a first electrode during a charging cycle, wherein the first potential is greater than the second potential; A third potential is applied to the charge storage electrode during a charge transfer period; and a fourth potential is applied to the first electrode during the charge transfer period, wherein the fourth potential is greater than the third potential. In some embodiments, the imaging device includes: a substrate including a first photoelectric conversion unit; and a second photoelectric conversion unit located at a light incident side of the substrate. The second photoelectric conversion unit may include: a photoelectric conversion layer; the first electrode; a second electrode located above the photoelectric conversion layer; the charge storage electrode; and an insulating material between the charge storage electrode and the Between the photoelectric conversion layers, a portion of the insulating material is interposed between the first electrode and the charge storage electrode. [Advantageous Effects of the Present Invention] In an imaging element according to an embodiment of the present invention, an imaging element according to an embodiment of the present invention constituting a stacked imaging element according to an embodiment of the present invention, or an imaging element according to an embodiment of the present invention An imaging element according to one embodiment of the present invention of a solid-state imaging device of one of the first or second embodiments of the present invention (in some cases, these imaging elements are hereinafter collectively referred to as an "one according to the present invention"). In the imaging element or the like of the embodiment, since a charge storage electrode is included, the charge storage electrode is configured to be separated from a first electrode and configured to face a photoelectric conversion layer in which an insulating layer is interposed with the charge storage electrode. between the storage electrode and the photoelectric conversion layer), so when the photoelectric conversion unit is illuminated with light and the light is photoelectrically converted in the photoelectric conversion unit, the charge of the photoelectric conversion layer can be stored. Thus, by completely depleting a charge storage cell at the beginning of exposure, it is possible to erase charge. Therefore, it is possible to suppress the occurrence of phenomena such as an increase in kTC noise, deterioration of random noise, and deterioration of image quality in imaging. In a driving method for a solid-state imaging device according to an embodiment of the present invention, each imaging element has a structure in which light incident from a second electrode side is not incident on the first electrode , and therefore, in all imaging elements at the same time, the electric charges are stored in the photoelectric conversion layers, and the electric charges of the first electrodes are emitted to the outside, making it possible to reliably perform resetting of the first electrodes in all imaging elements at the same time. Subsequently, in all imaging elements simultaneously, the charges stored in the photoelectric conversion layers are transferred to the first electrodes, and after the transfer is completed, the charges transferred to the first electrodes in the respective imaging elements are sequentially read out. Therefore, a so-called global shutter function can be easily implemented. Note that the effects disclosed in the specification are illustrative rather than limiting, and additional effects may also exist.

[相關申請案交叉參考] 本申請案主張2016年9月30日提出申請之日本優先專利申請案JP 2016-193919之權益，該日本優先專利申請案之全部內容以引用之方式併入本文中。 在下文中，將參考圖式基於實例而闡述本發明。然而，本發明並不限於實例，且實例中之各種數值及材料係例示性的。注意，按如下次序進行說明。 1. 對根據本發明之一實施例之成像元件、根據本發明之一實施例之堆疊型成像元件、根據本發明之第一或第二實施例之固態成像裝置及根據本發明之一實施例之用於固態成像裝置之驅動方法的總體說明 2. 實例1 (根據本發明之一實施例之成像元件、根據本發明之一實施例之堆疊型成像元件及根據本發明之第二實施例之固態成像裝置) 3. 實例2 (實例1之修改) 4. 實例3 (實例1及2之修改) 5. 實例4 (實例1至3之修改，具有轉移控制電極之成像元件) 6. 實例5 (實例1至4之修改，具有電荷射出電極之成像元件) 7. 實例6 (實例1至5之修改，具有電荷儲存電極分段之成像元件) 8. 其他 ＜對根據本發明之一實施例之成像元件、根據本發明之一實施例之堆疊型成像元件、根據本發明之第一或第二實施例之固態成像裝置及根據本發明之一實施例之用於固態成像裝置之驅動方法的總體說明＞ 在根據本發明之一實施例之一成像元件或諸如此類中，成像元件可進一步包含一半導體基板，且一光電轉換單元可配置於半導體基板上方。注意，一第一電極、一電荷儲存電極及一第二電極連接至稍後所闡述之一驅動電路。 位於一光入射側中之第二電極可通常設置至複數個成像元件。亦即，第二電極可組態為一所謂的固體電極。光電轉換層可通常設置至複數個該等成像元件。亦即，光電轉換層之一個層可針對複數個該等成像元件而形成或可針對每個成像元件而形成。 此外，在根據本發明之一實施例之包含上文所闡述之各種例示性形式及組態之成像元件或諸如此類中，第一電極可經形成以延伸於設置至絕緣層之一開口部分中以連接至光電轉換層。另一選擇係，光電轉換層可經形成以延伸於設置至絕緣層之開口部分中以連接至第一電極。在此情形中，成像元件或諸如此類可經組態以具有一形式，在該形式中第一電極之一頂部表面之一邊緣覆蓋有絕緣層、第一電極曝露於開口部分之一底部表面，且當絕緣層之與第一電極之頂部表面接觸之一表面由一第一表面界定且絕緣層之與光電轉換層之一部分(其面向電荷儲存電極)接觸之一表面由一第二表面界定時，開口部分之一側表面具有自第一表面朝向第二表面擴展之一斜坡。此外，成像元件或諸如此類可經組態以具有一形式，在該形式中開口部分之具有自第一表面朝向第二表面擴展之斜坡之側表面位於一電荷儲存電極側中。另外，上文所闡述之形式包含其中另一層形成於光電轉換層與第一電極之間的一形式(舉例而言，其中適合於電荷儲存之一材料層形成於光電轉換層與第一電極之間的一形式)。 此外，在根據本發明之一實施例之包含上文所闡述之各種例示性形式及組態之成像元件或諸如此類中，成像元件或諸如此類可具有一組態，在該組態中成像元件進一步包含設置至半導體基板且具有一驅動電路之一控制單元，第一電極及電荷儲存電極連接至驅動電路，在一電荷儲存週期中，自驅動電路，將一電位V 11施加至第一電極且將一電位V 12施加至電荷儲存電極，使得電荷被儲存於光電轉換層中，且在一電荷轉移週期中，自驅動電路，將一電位V 21施加至第一電極且將一電位V 22施加至電荷儲存電極，使得儲存於光電轉換層中之電荷透過第一電極而被讀出至控制單元。本文中，在其中第一電極之電位高於第二電極之電位之情形中， V 12≥ V 11且V 22＜ V 21，且 在其中第一電極之電位低於第二電極之電位之情形中， V 12≤ V 11且V 22＞ V 21。 此外，在根據本發明之一實施例之包含上文所闡述之各種例示性形式及組態之成像元件或諸如此類中，成像元件或諸如此類可經組態以具有一形式，在該形式中進一步包含一轉移控制電極(電荷轉移電極)，該轉移控制電極配置於第一電極與電荷儲存電極之間、可與第一電極及電荷儲存電極分離且經配置以透過絕緣層而面向光電轉換層。注意，為方便說明而將根據本發明之一實施例之具有此一形式之成像元件或諸如此類稱為一「根據本發明之一實施例之具有一轉移控制電極之成像元件或諸如此類」。 另外，在根據本發明之一實施例之具有一轉移控制電極之成像元件或諸如此類中，成像元件或諸如此類可具有一組態，在該組態中包含一控制單元，該控制單元設置至一半導體基板且包含一驅動電路，在一電荷儲存週期中，第一電極、電荷儲存電極及轉移控制電極連接至驅動電路。自驅動電路，將一電位V 11施加至第一電極、將一電位V 12施加至電荷儲存電極且將一電位V 13施加至轉移控制電極，使得電荷被儲存於光電轉換層中。而且在一電荷轉移週期中，自驅動電路，將一電位V 21施加至第一電極、將一電位V 22施加至電荷儲存電極且將一電位V 23施加至轉移控制電極，使得儲存於光電轉換層中之電荷透過第一電極而被讀出至控制單元。本文中，在其中第一電極之一電位高於第二電極之一電位之情形中， V 12＞ V 13且V 22≤ V 23≤ V 21，且 在其中第一電極之電位低於第二電極之電位之情形中， V 12＜ V 13且V 22≥ V 23≥ V 21。 此外，在根據本發明之一實施例之包含上文所闡述之各種例示性形式及組態之成像元件或諸如此類中，成像元件或諸如此類可經組態以具有一形式，在該形式中進一步包含一電荷射出電極，該電荷射出電極連接至光電轉換層且經配置以與第一電極及電荷儲存電極分離。注意，為方便說明而將根據本發明之一實施例之具有此一形式之成像元件或諸如此類稱為一「根據本發明之一實施例之具有一電荷射出電極之成像元件或諸如此類」。此外，在根據本發明之一實施例之具有一電荷射出電極之成像元件或諸如此類中，成像元件或諸如此類可經組態以具有一形式，在該形式中電荷射出電極經配置以環繞第一電極及電荷儲存電極(亦即，呈一框架形狀)。電荷射出電極可由複數個成像元件共用(共同使用)。此外，在此情形中，成像元件可以一形式經組態，在該形式中光電轉換層延伸於設置至絕緣層之一第二開口部分中以連接至電荷射出電極、電荷射出電極之一頂部表面之一邊緣覆蓋有絕緣層、電荷射出電極曝露於第二開口部分之一底部表面，且當絕緣層之與電荷射出電極之頂部表面接觸之一表面由一第三表面界定且絕緣層之與光電轉換層之一部分(其面向電荷儲存電極)接觸之一表面由一第二表面界定時，則第二開口部分之一側表面具有自第三表面朝向第二表面擴展之一斜坡。 此外，在根據本發明之一實施例之具有一電荷射出電極之成像元件或諸如此類中，成像元件或諸如此類可具有一組態，在該組態中進一步包含一控制單元，該控制單元設置至一半導體基板且包含一驅動電路，第一電極、電荷儲存電極及電荷射出電極連接至驅動電路，在一電荷儲存週期中，自驅動電路，將一電位V 11施加至第一電極、將一電位V 12施加至電荷儲存電極且將一電位V 14施加至電荷射出電極，使得電荷被儲存於光電轉換層中。而且在一電荷轉移週期中，自驅動電路，將一電位V 21施加至第一電極、將一電位V 22施加至電荷儲存電極且將一電位V 24施加至電荷射出電極，使得儲存於光電轉換層中之電荷透過第一電極而被讀出至控制單元。本文中，在其中第一電極之一電位高於第二電極之一電位之情形中， V 14＞ V 11且V 24＜ V 21，且 在其中第一電極之電位低於第二電極之電位之情形中， V 14＜ V 11且V 24＞ V 21。 此外，在根據本發明之一實施例之包含上文所闡述之各種例示性形式及組態之成像元件或諸如此類中，成像元件或諸如此類可以一形式經組態，在該形式中電荷儲存電極組態有複數個電荷儲存電極分段。注意，為方便說明而將根據本發明之一實施例之具有此一形式之成像元件或諸如此類稱為一「根據本發明之一實施例之具有複數個電荷儲存電極分段之成像元件或諸如此類」。電荷儲存電極分段之數目可為兩個或兩個以上。此外，在根據本發明之一實施例之具有複數個電荷儲存電極分段之成像元件或諸如此類中，成像元件或諸如此類可經組態以具有一形式，使得在其中第一電極之一電位高於第二電極之一電位之情形中，在一電荷轉移週期中，施加至位於最接近於第一電極之位置處之電荷儲存電極分段之一電位高於施加至位於距第一電極最遠之位置處之電荷儲存電極分段之一電位。而且在其中第一電極之電位低於第二電極之電位之情形中，在電荷轉移週期中，施加至位於最接近於第一電極之位置處之電荷儲存電極分段之電位低於施加至位於距第一電極最遠之位置處之電荷儲存電極分段之電位。 在根據本發明之一實施例之包含上文所闡述之各種例示性形式及組態之成像元件或諸如此類中，成像元件或諸如此類可具有一組態，在該組態中構成一控制單元之至少一浮動擴散層及一放大電晶體設置至一半導體基板，且第一電極連接至浮動擴散層及放大電晶體之一閘極部分，在此情形中，構成控制單元之一重設電晶體及一選擇電晶體被進一步設置至半導體基板，浮動擴散層連接至重設電晶體之一個源極/汲極區域，且放大電晶體之一個源極/汲極區域連接至選擇電晶體之一個源極/汲極區域，且選擇電晶體之另一源極/汲極區域連接至一信號線。 此外，在根據本發明之一實施例之包含上文所闡述之各種例示性形式及組態之成像元件或諸如此類中，成像元件或諸如此類可經組態以具有其中電荷儲存電極大於第一電極之一形式。當電荷儲存電極之面積由S 1'表示且第一電極之面積由S 1表示時，雖然不限於此，但較佳地滿足以下關係。 4 ≤ S 1'/S 1此外，在根據本發明之一實施例之包含上文所闡述之各種例示性形式及組態之成像元件或諸如此類中，成像元件或諸如此類可經組態以具有其中光自一第二電極側入射且一光屏蔽層形成於第二電極之一光入射側中之一形式。另一選擇係，成像元件或諸如此類可經組態以具有其中光自一第二電極側入射、光並不入射於第一電極(在某些情形中，第一電極及轉移控制電極)上之一形式。在此情形中，成像元件或諸如此類可具有一組態，在該組態中一光屏蔽層形成於第一電極(在某些情形中，第一電極及轉移控制電極)上方作為第二電極之一光入射側。成像元件或諸如此類可具有一組態，在該組態中一晶片上微透鏡設置於電荷儲存電極及第二電極上方，且在電荷儲存電極中收集入射於晶片上微透鏡上之光。光屏蔽層可配置於第二電極之光入射側表面上方或可配置於第二電極之光入射側表面上。在某些情形中，光屏蔽層可形成於第二電極中。作為構成光屏蔽層之一材料，可例示鉻(Cr)、銅(Cu)、鋁(Al)、鎢(W)及不透射光之一樹脂(舉例而言，聚醯亞胺樹脂)。 作為根據本發明之一實施例之一成像元件，具體而言可例示對藍色敏感且包含吸收藍色光(具有425 nm至495 nm之一波長範圍之光)之一光電轉換層(為方便說明，稱為一「第一類型藍色光電轉換層」)之一成像元件(為方便說明，稱為一「第一類型藍色成像元件」)、對綠色敏感且包含吸收綠色光(具有495 nm至570 nm之一波長範圍之光)之一光電轉換層(為方便說明，稱為一「第一類型綠色光電轉換層」)之一成像元件(為方便說明，稱為一「第一類型綠色成像元件」)及對紅色敏感且包含吸收紅色光(具有620 nm至750 nm之一波長範圍之光)之一光電轉換層(為方便說明，稱為一「第一類型紅色光電轉換層」)之一成像元件(為方便說明，稱為一「第一類型紅色成像元件」)。另外，作為相關技術中之不具有電荷儲存電極之成像元件，為方便說明而將對藍色敏感之一成像元件稱為一「第二類型藍色成像元件」；為方便說明而將對綠色敏感之一成像元件稱為一「第二類型綠色成像元件」；為方便說明而將對紅色敏感之一成像元件稱為一「第二類型紅色成像元件」；為方便說明而將構成第二類型藍色成像元件之一光電轉換層稱為一「第二類型藍色光電轉換層」；為方便說明而將構成第二類型綠色成像元件之一光電轉換層稱為一「第二類型綠色光電轉換層」；且為方便說明而將構成第二類型紅色成像元件之一光電轉換層稱為一「第二類型紅色光電轉換層」。 根據本發明之一實施例之堆疊型成像元件包含根據本發明之一實施例之至少一個成像元件(光電轉換元件)。亦即，堆疊型成像元件可包含但不限於以下非限制性組態及結構。 [A]一組態及結構，其中第一類型藍色光電轉換單元、第一類型綠色光電轉換單元及第一類型紅色光電轉換單元在垂直方向上堆疊，且 第一類型藍色成像元件、第一類型綠色成像元件及第一類型紅色成像元件之各別控制單元設置於半導體基板中。 [B]一組態及結構，其中第一類型藍色光電轉換單元及第一類型綠色光電轉換單元在垂直方向上堆疊， 第二類型紅色光電轉換層配置於第一類型光電轉換單元之兩個層下方，且 第一類型藍色成像元件、第一類型綠色成像元件及第二類型紅色成像元件之各別控制單元設置於半導體基板中。 [C]一組態及結構，其中第二類型藍色光電轉換單元及第二類型紅色光電轉換單元配置於第一類型綠色光電轉換單元下方，且 第一類型綠色成像元件、第二類型藍色成像元件及第二類型紅色成像元件之各別控制單元設置於半導體基板中。 [D]一組態及結構，其中第二類型綠色光電轉換單元及第二類型紅色光電轉換單元配置於第一類型藍色光電轉換單元下方，且 第一類型藍色成像元件、第二類型綠色成像元件及第二類型紅色成像元件之各別控制單元設置於半導體基板中。注意，較佳地成像元件之光電轉換單元在垂直方向上之配置次序係自光入射方向為藍色光電轉換單元、綠色光電轉換單元及紅色光電轉換單元之一次序，或自光入射方向為綠色光電轉換單元、藍色光電轉換單元及紅色光電轉換單元之一次序。此乃因在入射表面側中較高效地吸收具有一較短波長之光。由於紅色光在三個色彩的光當中具有最長波長，因此較佳地在自光入射表面觀看時，紅色光電轉換單元位於最低層中。一個像素係以成像元件之堆疊結構而組態。亦可包含一第一類型紅外線光電轉換單元。本文中，較佳地以(舉例而言)一有機材料來組態第一類型紅外線光電轉換單元之一光電轉換層，且該光電轉換層位於第一類型成像元件之堆疊結構之最低層中並配置於第二類型成像元件上方。另外，亦可包含位於第一類型光電轉換單元下方之一第二類型紅外線光電轉換單元。 舉例而言，在第一類型成像元件中，第一電極形成於設置於半導體基板上之一層間絕緣層上。形成於半導體基板中之成像元件可經組態為係一背面照明型或一正面照明型。 在其中光電轉換層由一有機材料製成之情形中，光電轉換層可形成為以下非限制性形式中之任一者： (1)光電轉換層組態有一p型有機半導體； (2)光電轉換層組態有一n型有機半導體； (3)光電轉換層組態有一p型有機半導體層/一n型有機半導體層之一堆疊結構；(舉例而言，光電轉換層組態有一p型有機半導體層/一p型有機半導體與一n型有機半導體之一混合層(塊體異質結構)/一n型有機半導體層之一堆疊結構。光電轉換層組態有一p型有機半導體層/一p型有機半導體與一n型有機半導體之一混合層(塊體異質結構)之一堆疊結構。光電轉換層組態有一n型有機半導體層/一p型有機半導體與一n型有機半導體之一混合層(塊體異質結構)之一堆疊結構。) (4)光電轉換層組態有一p型有機半導體與一n型有機半導體之一混合層(塊體異質結構)。 本文中，堆疊次序可經組態以被任意地改變。 作為一p型有機半導體，可使用以下非限制性材料中之一或多者：萘衍生物、蒽衍生物、菲衍生物、芘衍生物、苝衍生物、稠四苯衍生物、稠五苯衍生物、喹吖酮衍生物、噻吩衍生物、噻吩并噻吩衍生物、苯并噻吩衍生物、苯并-噻吩并苯并噻吩衍生物、三烯丙基胺衍生物、咔唑衍生物、苝衍生物、苉衍生物、䓛(chrysene)衍生物、螢蒽衍生物、酞青素衍生物、亞酞青素衍生物、亞四氮雜卟啉(subporphyrazine)衍生物、具有雜環化合物作為配體之金屬錯合物、聚噻吩衍生物、聚苯并噻二唑衍生物、聚芴衍生物及諸如此類。作為一n型有機半導體，可使用以下非限制性材料中之一或多者：富勒烯及富勒烯衍生物＜舉例而言，諸如C60、C70及C74之富勒烯(高階富勒烯)、內嵌富勒烯或諸如此類，或者富勒烯衍生物(舉例而言，富勒烯氟化物、PCBM富勒烯化合物、富勒烯多聚體或諸如此類)＞、有機半導體(其具有比p型有機半導體之HOMO及LUMO大(深)之HOMO及LUMO)以及透明無機金屬氧化物。一n型有機半導體可包含但不限於以下各項中之一或多者：有機分子或有機金屬錯合物(其具有含雜環化合物氮原子、氧原子或硫原子作為分子骨架之一部分)，舉例而言，吡啶衍生物、吡嗪衍生物、嘧啶衍生物、三嗪衍生物、喹啉衍生物、喹喔啉衍生物、異喹啉衍生物、吖啶衍生物、吩嗪衍生物、啡啉衍生物、四唑衍生物、吡唑衍生物、咪唑衍生物、噻唑衍生物、噁唑衍生物、咪唑衍生物、苯并咪唑衍生物、苯并三唑衍生物、苯并噁唑衍生物、苯并噁唑衍生物、咔唑衍生物、苯并呋喃衍生物、二苯并呋喃衍生物、亞四氮雜卟啉衍生物、聚對苯乙烯衍生物、聚苯并噻二唑衍生物、聚芴衍生物或諸如此類，及亞酞青素衍生物。富勒烯衍生物中所含有之一基團或諸如此類可包含但不限於以下各項中之一或多者：鹵素原子；直鏈、支鏈或環狀烷基或者苯基；具有一直鏈或縮合環狀芳香族化合物之基團；具有一鹵化物之基團；部分氟烷基基團；過氟化烷基基團；甲矽烷基烷基基團；甲矽烷基烷氧基基團；芳基甲矽烷基基團；芳基硫烷基基團；烷基硫烷基基團；芳基磺醯基基團；烷基磺醯基基團；芳基硫化物基團；烷基硫化物基團；胺基基團；烷胺基基團；芳基胺基基團；羥基基團；烷氧基基團；醯基胺基基團；醯氧基基團；羰基基團；羧基基團；羧甲基甲醯胺(carboxymethyl kiso amide)基團；烷氧羰基基基團；醯基基團；磺醯基基團；氰基基團；硝基基團；具有一硫族化物之基團；磷化氫基團；磷酸鹽基團；及其衍生物。光電轉換層(在某些情形中，稱為一「有機光電轉換層」)之一厚度組態有一有機材料，雖然並不限於此，但該有機材料可包含以下非限制性範圍：1 × 10 -8m至5× 10 -7m、較佳地2.5× 10 -8m至3 × 10 -7m之一範圍、更佳地2.5 × 10 -8m至2 × 10 -7m之一範圍且極佳地1 × 10 -7m至1.8 × 10 -7m之一範圍。注意，在諸多情形中，將有機半導體分類成一p型及一n型。本文中，p型表示電洞可易於輸送，且n型表示電子可易於輸送。該等類型並不被限制性地解釋。 構成用於光電轉換具有一綠色波長之光之一有機光電轉換層之一材料可包含但不限於以下各項中之一或多者：基於羅丹明(rhodamine)之染料、基於梅拉什寧(merashianin)之染料、喹吖酮衍生物、亞酞青素染料(亞酞青素衍生物)及諸如此類。構成用於光電轉換具有一藍色波長之光之一有機光電轉換層之一材料可包含但不限於以下各項中之一或多者：香豆素酸染料、三-8-羥基喹啉鋁(Alq3)、基於梅拉什寧之染料及諸如此類。用於光電轉換具有一紅色波長之光之一有機光電轉換層之一材料可包含但不限於以下各項中之一或多者：酞青素染料、亞酞青素染料(亞酞青素衍生物)及諸如此類。 光電轉換層之一無機材料可包含但不限於以下各項中之一或多者：結晶矽、非晶矽、微晶矽、結晶硒、非晶硒之化合物半導體；一基於黃銅礦之化合物，諸如CIGS (CuInGaSe)、CIS (CuInSe 2)、CuInS 2、CuAlS 2、CuAlSe 2、CuGaS 2、CuGaSe 2、AgAlS 2、AgAlSe 2、AgInS 2或AgInSe 2；一III-V族化合物，諸如GaAs、InP、AlGaAs、InGaP、AlGaInP或InGaAsP、CdSe、CdS、In 2Se 3、In 2S 3、Bi 2Se 3、Bi 2S 3、ZnSe、ZnS、PbSe及PbS。由此等材料製成之量子點可用於光電轉換層。 另一選擇係，光電轉換層可經組態以具有一下部半導體層及一上部光電轉換層之一堆疊層結構。以此方式，藉由提供下部半導體層，可能在電荷儲存週期中防止重新耦合，使得可能增加儲存於光電轉換層中之電荷至第一電極之轉移效率，且可能抑制暗電流之發生。可在上文所闡述之構成光電轉換層之各種類型之材料當中適當地選擇構成上部層光電轉換層之材料。另一方面，較佳地作為構成下部半導體層之材料，使用具有一大帶隙值(舉例而言，3.0 eV或更大之一帶隙值)且具有高於構成光電轉換層之材料之遷移率之一遷移率之一材料。具體而言，該材料之非限制性實例可包含以下各項中之一或多者：氧化物半導體材料，諸如IGZO；過渡金屬晶粒硫族化物；碳化矽；金剛石；石墨烯；碳奈米管；及縮合多環碳氫化合物、縮合雜環化合物之有機半導體材料或諸如此類。作為構成下部半導體層之材料，在其中待被儲存電荷係電子之情形中，實例性材料包含但不限於具有高於構成光電轉換層之材料之離子化電位之一離子化電位之材料；且在其中待被儲存電荷係電洞之情形中，實例性材料包含但不限於具有小於構成光電轉換層之材料之電子親和力之一電子親和力之材料。較佳地，構成下部半導體層之材料中之雜質濃度係1 × 10 18cm -3或更小。下部半導體層可具有一單層組態或可為一多層組態。另外，構成位於電荷儲存電極上方之下部半導體層之材料及構成位於第一電極上方之下部半導體層之材料可經組態以係彼此不同的。 根據本發明之第一或第二實施例中之固態成像裝置，可組態一單板彩色固態成像裝置。 在根據本發明之第二實施例之具有一堆疊型成像元件之固態成像裝置中，不同於具有呈一拜耳(Bayer)陣列之成像元件(亦即，不藉由使用彩色濾光器而執行藍色光、綠色光及紅色光之光譜分離)之一固態成像裝置，藉由在一個像素中堆疊對在光入射方向上具有複數類型之波長之光敏感之成像元件而組態該同一像素，可能改良每單位體積之敏感度及像素密度。另外，由於一有機材料具有一高吸收係數，因此有機光電轉換層可經組態以具有比相關技術之一基於Si之光電轉換層小之一厚度，且減輕自毗鄰像素之光洩漏或對一光入射角度之限制。此外，在相關技術之基於Si之成像元件中，在三個色彩像素當中執行一內插程序，使得偽色彩發生以便產生一色彩信號。然而，在根據本發明之第二實施例之具有一堆疊型成像元件之固態成像裝置中，抑制偽色彩之發生。由於有機光電轉換層自身具有作為一彩色濾光器之一功能，因此可在不配置彩色濾光器之情況下獲得色彩分離。 另一方面，在根據本發明之第一實施例之其中使用彩色濾光器之固態成像裝置中，可減輕對針對藍色光、綠色光及紅色光之光譜分離特性之要求，且可獲得一高生產率。根據本發明之第一實施例之固態成像裝置中之成像元件之一陣列包含但不限於以下各項中之一或多者：一拜耳陣列、一行間配置、一G條帶RB棋盤式陣列、一G條帶RB完全棋盤式陣列、一棋盤式補色陣列、一條帶陣列、一對角線條帶配置、一原色色差陣列、一場色差順序陣列、一圖框色差順序陣列、一MOS型陣列、一經改良MOS型陣列、一圖框交錯陣列及一場交錯陣列。本文中，一個像素(或子像素)組態有一個成像元件。 其中配置根據本發明之一實施例之複數個成像元件或根據本發明之一實施例之複數個堆疊型成像元件之一像素區域組態有複數個像素，該複數個像素規則地配置成一個二維陣列形狀。像素區域通常經組態以包含一有效像素區域，該有效像素區域實際上接收光、放大透過光電轉換產生之信號電荷且將信號電荷讀出至一驅動電路及一黑色參考像素區域以用於輸出光學黑色作為一黑色位準之一參考。黑色參考像素區域通常配置於有效像素區域之外周邊中。 在根據本發明之一實施例之包含上文所闡述之各種例示性形式及組態之成像元件或諸如此類中，使光照明且在光電轉換層中發生光電轉換，使得電洞及電子分離為載子。然後，將其中電洞被提取之電極定義為一陽極，且將其中電子被提取之電極定義為一陰極。可存在其中第一電極構成陽極且第二電極構成陰極之一形式。相反，亦可存在其中第一電極構成陰極且第二電極構成陽極之一形式。 在構成堆疊型成像元件之情形中，第一電極、電荷儲存電極、轉移控制電極、電荷射出電極及第二電極可經組態以由一透明導電材料製成。注意，在某些情形中，第一電極、電荷儲存電極、轉移控制電極及電荷射出電極統稱為一「第一電極或諸如此類」。另一選擇係，在其中根據本發明之一實施例之成像元件或諸如此類配置於一平面中(舉例而言，如一拜耳陣列中)之情形中，第二電極可經組態以由一透明導電材料製成，且第一電極可經組態以由一金屬材料製成。在此情形中，具體而言，位於光入射側處之第二電極可經組態以由一透明導電材料製成，且第一電極及諸如此類可經組態以由(舉例而言) Al-Nd (鋁及釹之合金)或ASC (鋁、釤及銅之合金)製成。注意，在某些情形中，由一透明導電材料製成之一電極稱為一「透明電極」。透明導電材料之帶隙能量係2.5 eV或者更佳地3.1 eV或更大。作為構成透明電極之一透明導電材料，可例示一導電金屬氧化物；導電氧化物可包含但不限於以下各項中之一或多者：一種氧化銦、一種氧化銦錫(ITO—Sn摻雜之In 2O 3，包含一結晶ITO及一非晶ITO)、藉由將銦作為一摻雜劑添加至一種氧化鋅而形成之一種氧化銦鋅(IZO)、藉由將銦作為一摻雜劑添加至一種氧化鎵而形成之一種氧化銦鎵(IGO)、藉由將銦及鎵作為摻雜劑添加至一種氧化鋅而形成之一種氧化銦鎵鋅(IGZO—In-GaZnO 4)、藉由將錫作為一摻雜劑添加至一種氧化鋅而形成之一種氧化銦錫鋅(ITZO)、一IFO (F摻雜之In 2O 3)、一種氧化錫(SnO 2)、一ATO (Sb摻雜之SnO 2)、一FTO (F摻雜之SnO 2)、一種氧化鋅(包含摻雜有另一些元素之ZnO)、藉由將鋁作為一摻雜劑添加至一種氧化鋅而形成之一種氧化鋁鋅(AZO)、藉由將鎵作為一摻雜劑添加至一種氧化鋅而形成之一種氧化鎵鋅(GZO)、一種氧化鈦(TiO 2)、藉由將鈮作為一摻雜劑添加至一種氧化鈦而形成之一種氧化鈮鈦(TNO)、一種氧化銻、一尖晶石型氧化物及具有一YbFe 2O 4結構之一種氧化物。另一選擇係，可例示使用以下各項中之一或多者作為一母層之一透明電極：一種氧化鎵、一種氧化鈦、一種氧化鈮、一種氧化鎳或諸如此類。作為透明電極之一厚度，一非限制性範圍之一實例可為2 × 10 -8m至2 × 10 -7m，較佳地3 × 10 -8m至1 × 10 -7m之一範圍。在其中透明性對於第一電極為必要之情形中，自簡化製造程序之觀點來看，較佳地電荷射出電極亦由一透明導電材料製成。 在其中透明性並非必要之情形中，較佳地構成具有作為射出電洞之一電極之一功能之一正電極的一導電材料係具有一高功函數(舉例而言，ϕ = 4.5 eV至5.5 eV)之一導電材料。具體而言，導電材料可包含但不限於以下各項中之一或多者：金(Au)、銀(Ag)、鉻(Cr)、鎳(Ni)、鈀(Pd)、鉑(Pt)、鐵(Fe)、銥(Ir)、鍺(Ge)、鋨(Os)、錸(Re)或碲(Te)。另一方面，較佳地構成具有作為射出電子之一電極之一功能之一負電極的一導電材料係具有一低功函數(舉例而言，ϕ = 3.5 eV至4.5 eV)之一導電材料。具體而言，導電材料可包含但不限於以下各項中之一或多者：一鹼金屬(舉例而言Li、Na、K或諸如此類)及其一種氟化物或其一種氧化物、一鹼土金屬(舉例而言，Mg、Ca或諸如此類)及其一種氟化物或其一種氧化物、鋁(Al)、鋅(Zn)、錫(Sn)、鉈(Tl)、一鈉鉀合金、一鋁鋰合金、一鎂銀合金、銦、一稀土金屬(諸如鐿)或其合金。構成陽極或陰極之材料包含但不限於一或多種金屬，諸如鉑(Pt)、金(Au)、鈀(Pd)、鉻(Cr)、鎳(Ni)、鋁(Al)、銀(Ag)、鉭(Ta)、鎢(W)、銅(Cu)、鈦(Ti)、銦(In)、錫(Sn)、鐵(Fe)、鈷(Co)及鉬(Mo)、含有此等金屬原子之合金、由此等金屬製成之導電粒子、含有此等金屬之合金之導電粒子或導電材料(諸如含有雜質之多晶矽、基於碳之材料、氧化物半導體、碳奈米管及石墨烯)，且可使用含有此等原子之層之一堆疊結構。此外，構成陽極或陰極之材料包含但不限於以下各項中之一或多者：一有機材料(導電聚合物)，諸如聚(3,4-乙烯二氧噻吩)/聚苯乙烯磺酸[PEDOT/PSS]。另外，藉由混合導電材料與一黏合劑(聚合物)而獲得之一膏或墨之一固化材料可用作一電極。 作為用於第一電極或諸如此類或者第二電極(一陽極或一陰極)之一膜形成方法，可使用一乾式方法或一濕式方法。一乾式方法之實例包含但不限於一物理汽相沈積(PVD)方法及一化學汽相沈積(CVD)方法。使用PVD方法之原理之一膜形成方法之實例包含但不限於：使用電阻加熱或高頻率加熱之一真空汽相沈積方法、一EB (電子束)汽相沈積方法、各種濺鍍方法(一磁控管濺鍍方法、一RF-DC耦合類型偏壓濺鍍方法、一ECR濺鍍方法、一面向目標濺鍍方法及一高頻率濺鍍方法)、一離子電鍍方法、一雷射剝蝕方法、一分子束磊晶方法及一雷射轉印方法。另外，一CVD方法之實例包含但不限於：一電漿CVD方法、一熱CVD方法、一金屬有機(MO) CVD方法及一光CVD方法。另一方面，一濕式方法之實例包含但不限於：一電解電鍍方法或一無電式電鍍方法、一旋塗方法、一噴墨方法、一噴塗方法、一衝壓方法、一微接觸印刷方法、一柔版印刷方法、一平版印刷方法、一凹版印刷方法、一浸塗方法及諸如此類。一圖案化方法之實例包含但不限於化學蝕刻(諸如陰影遮罩、雷射轉印或光微影)及使用紫外線光、雷射或諸如此類之物理蝕刻。用於第一電極或諸如此類或者第二電極之平坦化技術可包含但不限於：一雷射平坦化方法、一回銲方法、一化學機械拋光(CMP)方法及諸如此類。 絕緣層可包含以下非限制性材料中之一或多者：除例示為金屬氧化物高介電絕緣材料(諸如一基於氧化矽之材料)之無機絕緣材料之外；一種氮化矽(SiN Y)；及一種氧化鋁(Al 2O 3)，諸如聚甲基丙烯酸甲酯(PMMA)；聚乙烯苯酚(PVP)；聚乙烯醇(PVA)；聚醯亞胺；聚碳酸酯(PC)；聚對苯二甲酸乙二酯(PET)；聚苯乙烯；一矽醇衍生物(矽烷耦合劑，諸如N-2 (胺乙基) 3-胺丙基三乙氧基矽烷(AEAPTMS)、3-巰丙基三甲氧基矽烷(MPTMS)或十八烷基三氯矽烷(OTS)；酚醛清漆類型酚醛樹脂；一基於氟之樹脂；及有機絕緣材料(有機聚合物)，例示為一直鏈碳氫化合物，該直鏈碳氫化合物在其一端中具有能夠結合至一控制電極之一官能基(諸如十八硫醇或十二烷基異氰酸酯)，且可使用其一組合。注意，作為一基於氧化矽之材料，非限制性實例包含但不限於：一種氧化矽(SiO X)、BPSG、PSG、BSG、AsSG、PbSG、一種氮氧化矽(SiON)、一SOG (旋塗玻璃)及一低介電常數材料(舉例而言，聚芳基醚、環全氟碳化物聚合物及苯并環丁烯、一環狀氟樹脂、聚四氟乙烯、一芳基醚氟化物、一聚醯亞胺氟化物、一非晶碳及一有機SOG)。亦可自前述材料適當地選擇構成各種層間絕緣層或絕緣膜之材料。 構成控制單元之浮動擴散層、放大電晶體、重設電晶體及選擇電晶體之組態及結構可經形成以類似於相關技術中之浮動擴散層、放大電晶體、重設電晶體及選擇電晶體之組態及結構。驅動電路亦可形成有一眾所周知之組態及結構。 第一電極連接至浮動擴散層及放大電晶體之閘極部分，且因此期望接觸孔部分經形成以用於第一電極與浮動擴散層之間以及第一電極與放大電晶體之閘極部分之間的連接。構成接觸孔部分之材料可包含但不限於以下各項中之一或多者：摻雜有雜質之多晶矽、一高熔點金屬或金屬矽化物(諸如鎢、Ti、Pt、Pd、Cu、TiW、TiN、TiNW、WSi 2及MoSi 2)及由此等材料製成之層之一堆疊結構(舉例而言，Ti/TiN/W)。 一第一載子阻擋層可設置於有機光電轉換層與第一電極之間，且一第二載子阻擋層可設置於有機光電轉換層與第二電極之間。另外，一第一電荷注入層可設置於第一載子阻擋層與第一電極之間，且一第二電荷注入層可設置於第二載子阻擋層與第二電極之間。構成電極注入層之材料可包含但不限於以下各項中之一或多者：鹼金屬(諸如鋰(Li)、鈉(Na)及鉀(K))、其氟化物、其氧化物，鹼土金屬(諸如鎂(Mg)及鈣(Ca))、其氟化物及其氧化物。 用於形成各種有機層之一方法可包含但不限於以下各項中之一或多者：一乾式膜形成方法及一濕式膜形成方法。一乾式膜形成方法之一實例包含但不限於以下各項中之一或多者：一電阻加熱或高頻率加熱方法、使用電子束加熱之一真空汽相沈積方法、一閃蒸汽相沈積方法、一電漿汽相沈積方法、一EB汽相沈積方法、各種濺鍍方法(一2極濺鍍方法、一DC濺鍍方法、一DC磁控管濺鍍方法、一高頻率濺鍍方法、一磁控管濺鍍方法、一RF-DC耦合類型偏壓濺鍍方法、一ECR濺鍍方法、一面向目標濺鍍方法、一高頻率濺鍍方法及一離子束濺鍍)、一直流(DC)方法、一RF方法、一多陰極方法、一活化反應方法、一電場汽相沈積方法、各種離子電鍍方法(諸如一高頻率離子電鍍方法及一反應離子電鍍方法)、一雷射剝蝕方法、一分子束磊晶方法、一雷射轉印方法及一分子束磊晶(MBE)方法。另外，一CVD方法之一實例包含但不限於：一電漿CVD方法、一熱CVD方法、一MOCVD方法及一光CVD方法。另一方面，一濕式方法之實例包含但不限於：一旋塗方法；一浸沒方法；一鑄造方法；一微接觸印刷方法；一滴鑄方法；各種印刷方法，諸如一絲網印刷方法、一噴墨印刷方法、一平版印刷方法、一凹版印刷方法及一柔版印刷方法；一衝壓方法；一噴霧方法；及各種塗佈方法，諸如一氣刀塗佈機方法、一刮刀塗佈機方法、一桿式(rod)塗佈機方法、一刀式塗佈機方法、一擠壓式塗佈機方法、一逆轉輥式塗佈機方法、一轉印輥式塗佈機方法、一凹版塗佈機方法、一吻合式(kiss)塗佈機方法、一流延(cast)塗佈機方法、一噴塗方法、一狹縫孔塗佈機方法及一壓延(calendar)塗佈機方法。注意，在塗佈方法中，可使用包含但不限於以下各項之一溶劑：不具有極性或具有低極性之有機溶劑，諸如甲苯、三氯甲烷、己烷及乙醇。一圖案化方法之一實例包含但不限於以下各項中之一或多者：化學蝕刻(諸如陰影遮罩、雷射轉印或光微影)及使用紫外線光、雷射或諸如此類之物理蝕刻。用於各種類型之有機層之一平坦化技術之一實例包含但不限於以下各項中之一或多者：一雷射平坦化方法、一回銲方法及諸如此類。 在如上文所闡述之成像元件或固態成像裝置中，若需要，則可提供一晶片上微透鏡或一光屏蔽層，且提供用於驅動成像元件之一驅動電路或一導線。若需要，則可提供用於控制光在成像元件上之入射之一快門，且固態成像裝置可根據其目的而包含一光學截止濾光器。 舉例而言，在其中堆疊一固態成像裝置及一讀出積體電路(ROIC)之情形中，允許其中形成讀出積體電路及由銅(Cu)製成之一連接部分之一驅動基板以及其中形成一連接部分之成像元件彼此重疊，使得該等連接部分彼此接觸，且然後藉由黏合連接部分而執行堆疊。另一選擇係，連接部分可藉由使用焊料凸塊或諸如此類而彼此黏合。 [實例1] 實例1係關於根據本發明之一實施例之一成像元件、根據本發明之一實施例之一堆疊型成像元件及根據本發明之一第二實施例之一固態成像裝置。 在圖1A中圖解說明實例1之成像元件及堆疊型成像元件之一部分之一示意性部分剖面圖。在圖2及圖3中圖解說明實例1之成像元件及堆疊型成像元件之等效電路圖。在圖4中圖解說明構成實例1之成像元件之第一電極及電荷儲存電極以及構成一控制單元之電晶體之一示意性佈局圖。在圖5中圖解說明處於實例1之成像元件之一操作週期中之組件之電位狀態。另外，在圖6中圖解說明構成實例1之成像元件之第一電極及電荷儲存電極之一示意性佈局圖。在圖7中圖解說明構成實例1之成像元件之第一電極、電荷儲存電極、一第二電極及一接觸孔部分之一示意性透視圖。在圖8中圖解說明實例1之固態成像裝置之一概念圖式。 實例1之成像元件(舉例而言，稍後所闡述之綠色成像元件)經組態以包含藉由堆疊一第一電極11、一光電轉換層15及一第二電極16而形成之一光電轉換單元。光電轉換單元經組態以包含一電荷儲存電極12，該電荷儲存電極經配置以與第一電極11分離且經配置以面向光電轉換層15，其中一絕緣層82插置於該電荷儲存電極與該光電轉換層之間。 如圖1B至圖1D中所繪示，絕緣層82可包含多個層82E及82F。舉例而言，可存在絕緣材料82之介於電荷儲存電極12與光電轉換層15之間的一第一區域，且可存在絕緣材料82之介於電荷儲存電極12與第一電極11之間的一第二區域。在某些實施例中，絕緣材料之第二區域包含一第一絕緣層82E (其包含絕緣材料)及一第二絕緣層82F (其包含絕緣材料)，且第一絕緣材料82F堆疊於第二絕緣材料82E上。圖1B至圖1D進一步繪示關於絕緣層82之各種組態(例如，層82E及82F之組態改變)。 另外，實例1之堆疊型成像元件包含實例1之至少一個成像元件。在實例1中，堆疊型成像元件包含實例1之一個成像元件。 此外，實例1之固態成像裝置包含實例1之複數個堆疊型成像元件。 此外，進一步包含一半導體基板(更具體而言，一矽半導體層) 70，且光電轉換單元配置於半導體基板70上方。另外，進一步包含一控制單元，該控制單元設置於半導體基板70中且具有第一電極11連接至的一驅動電路。本文中，半導體基板70之光入射側設定至「半導體基板上方」，且半導體基板70之相對側設定至「半導體基板下方」。組態有複數個導線之一導線層62設置於半導體基板70下方。半導體基板70設置有構成控制單元之至少一浮動擴散層FD 1及一放大電晶體TR1 amp，且第一電極11連接至浮動擴散層FD 1及放大電晶體TR1 amp之閘極部分。半導體基板70進一步設置有構成控制單元之一重設電晶體TR1 rst及一選擇電晶體TR1 sel。浮動擴散層FD 1連接至重設電晶體TR1 rst之一個源極/汲極區域，放大電晶體TR1 amp之一個源極/汲極區域連接至選擇電晶體TR1 sel之一個源極/汲極區域，且選擇電晶體TR1 sel之另一源極/汲極區域連接至一信號線VSL 1。放大電晶體TR1 amp、重設電晶體TR1 rst及選擇電晶體TR1 sel構成一驅動電路。 具體而言，實例1之成像元件及堆疊型成像元件係一背面照明型成像元件及一背面照明型堆疊型成像元件且包含如下三個成像元件之一堆疊結構：實例1之一第一類型綠色成像元件(下文中，稱為一「第一成像元件」)，其對綠色敏感且包含吸收綠色光之一第一類型綠色光電轉換層；相關技術之一第二類型藍色成像元件(下文中，稱為一「第二成像元件」)，其對藍色敏感且包含吸收藍色光之一第二類型藍色光電轉換層；及相關技術之一第二類型紅色成像元件(下文中，稱為一「第三成像元件」)，其對紅色敏感且包含吸收紅色光之一第二類型紅色光電轉換層。紅色成像元件(第三成像元件)及藍色成像元件(第二成像元件)設置於半導體基板70中，且第二成像元件經定位以比第三成像元件更接近於光入射側。另外，綠色成像元件(第一成像元件)設置於藍色成像元件(第二成像元件)上方。一個像素係以第一成像元件、第二成像元件及第三成像元件之一堆疊結構而組態。不提供彩色濾光器。 在第一成像元件中，第一電極11及電荷儲存電極12形成於一層間絕緣層81上以彼此分離。層間絕緣層81及電荷儲存電極12覆蓋有絕緣層82。光電轉換層15形成於絕緣層82上，且第二電極16形成於光電轉換層15上。在整個表面(包含第二電極16)中，形成一保護層83，且一晶片上微透鏡90設置於保護層83上。第一電極11、電荷儲存電極12及第二電極16組態有由(舉例而言) ITO製成之透明電極。光電轉換層15組態有含有對綠色敏感之一眾所周知之有機光電轉換材料(舉例而言，諸如但不限於一基於羅丹明之染料、一基於梅拉什寧之染料及喹吖酮之一有機材料)之一層。另外，光電轉換層15可進一步具有包含適合於電荷儲存之一材料層之一組態。亦即，適合於電荷儲存之材料層可形成於光電轉換層15與第一電極11之間(舉例而言，在連接部分67中)。層間絕緣層81、絕緣層82及保護層83組態有眾所周知之絕緣材料(舉例而言，SiO 2或SiN)。光電轉換層15與第一電極11藉由設置至絕緣層82之連接部分67而彼此連接。光電轉換層15延伸於連接部分67中。亦即，光電轉換層15延伸於設置至絕緣層82之一開口部分84中以連接至第一電極11。 電荷儲存電極12連接至驅動電路。具體而言，電荷儲存電極12透過設置於層間絕緣層81中之一連接孔66、一墊部分64及一導線V OA而連接至構成驅動單元之一垂直驅動電路112。 電荷儲存電極12大於第一電極11。當電荷儲存電極12之面積由S 1'表示且第一電極11之面積由S 1表示時，雖然並不限於此，但較佳地滿足以下關係， 4 ≤ S 1'/S 1而且在實例1中，雖然並不限於此，但(舉例而言)設定以下關係。 S 1'/S 1= 8 一元件隔離區域71形成於半導體基板70之一第一表面(前表面) 70A側中，且一種氧化物膜72形成於半導體基板70之第一表面70A上。此外，半導體基板70之第一表面側設置有構成第一成像元件之控制單元之重設電晶體TR1 rst、放大電晶體TR1 amp及選擇電晶體TR1 sel且進一步設置有第一浮動擴散層FD 1。 重設電晶體TR1 rst組態有一閘極部分51、一通道形成區域51A以及源極/汲極區域51B及51C。重設電晶體TR1 rst之閘極部分51連接至一重設線RST 1，重設電晶體TR1 rst之一個源極/汲極區域51C亦用作一第一浮動擴散層FD 1，且其另一源極/汲極區域51B連接至一電源V DD。 第一電極11透過設置於層間絕緣層81中之一連接孔65及一墊部分63、設置至半導體基板70及層間絕緣層76之一接觸孔部分61以及形成於層間絕緣層76中之導線層62而連接至重設電晶體TR1 rst之一個源極/汲極區域51C (第一浮動擴散層FD 1)。 放大電晶體TR1 amp組態有一閘極部分52、一通道形成區域52A以及源極/汲極區域52B及52C。閘極部分52透過導線層62而連接至第一電極11及重設電晶體TR1 rst之一個源極/汲極區域51C (第一浮動擴散層FD 1)。另外，一個源極/汲極區域52C與構成重設電晶體TR1 rst之另一源極/汲極區域51B共用區域且連接至電源V DD。 選擇電晶體TR1 sel組態有一閘極部分53、一通道形成區域53A以及源極/汲極區域53B及53C。閘極部分53連接至選擇線SEL 1。另外，一個源極/汲極區域53B與構成放大電晶體TR1 amp之另一源極/汲極區域52C共用區域，且另一源極/汲極區域53C連接至信號線(資料輸出線) VSL 1(117)。 第二成像元件包含作為一光電轉換層設置至半導體基板70之一n型半導體區域41。轉移電晶體TR2 trs之組態有一垂直型電晶體之一閘極部分45延伸至n型半導體區域41且連接至一轉移閘極線TG 2。另外，一第二浮動擴散層FD 2設置至半導體基板70之在轉移電晶體TR2 trs之閘極部分45附近之一區域45C。儲存於n型半導體區域41中之電荷透過沿著閘極部分45形成之一轉移通道而被讀出至第二浮動擴散層FD 2。 在第二成像元件中，在半導體基板70之第一表面側中，進一步提供構成第二成像元件之控制單元之一重設電晶體TR2 rst、一放大電晶體TR2 amp及一選擇電晶體TR2 sel。 重設電晶體TR2 rst組態有一閘極部分、一通道形成區域及源極/汲極區域。重設電晶體TR2 rst之閘極部分連接至重設線RST 2，重設電晶體TR2 rst之一個源極/汲極區域連接至電源V DD，且其另一源極/汲極區域用作一第二浮動擴散層FD 2。 放大電晶體TR2 amp組態有一閘極部分、一通道形成區域及源極/汲極區域。閘極部分連接至重設電晶體TR2 rst之另一源極/汲極區域(第二浮動擴散層FD 2)。另外，其一個源極/汲極區域與構成重設電晶體TR2 rst之另一源極/汲極區域共用區域且連接至電源V DD。 選擇電晶體TR2 sel組態有一閘極部分、一通道形成區域及源極/汲極區域。閘極部分連接至選擇線SEL 2。另外，其一個源極/汲極區域與構成放大電晶體TR2 amp之另一源極/汲極區域共用區域，且另一源極/汲極區域連接至信號線(資料輸出線) VSL 2。 第三成像元件包含作為一光電轉換層設置至半導體基板70之一n型半導體區域43。轉移電晶體TR3 trs之閘極部分46連接至轉移閘極線TG 3。另外，一第三浮動擴散層FD 3設置至半導體基板70之在轉移電晶體TR3 trs之閘極部分46附近之區域46C。儲存於n型半導體區域43中之電荷透過沿著閘極部分46形成之一轉移通道46A而被讀出至第三浮動擴散層FD 3。 在第三成像元件中，在半導體基板70之第一表面側中，進一步提供構成第三成像元件之控制單元之一重設電晶體TR3 rst、一放大電晶體TR3 amp及一選擇電晶體TR3 sel。 重設電晶體TR3 rst組態有一閘極部分、一通道形成區域及源極/汲極區域。重設電晶體TR3 rst之閘極部分連接至重設線RST 3，重設電晶體TR3 rst之一個源極/汲極區域連接至電源VDD，且其另一源極/汲極區域用作一第三浮動擴散層FD 3。 放大電晶體TR3 amp組態有一閘極部分、一通道形成區域及源極/汲極區域。閘極部分連接至重設電晶體TR3 rst之另一源極/汲極區域(第三浮動擴散層FD 3)。另外，其一個源極/汲極區域與構成重設電晶體TR3 rst之另一源極/汲極區域共用區域且連接至電源V DD。 選擇電晶體TR3 sel組態有一閘極部分、一通道形成區域及源極/汲極區域。閘極部分連接至選擇線SEL 3。另外，一個源極/汲極區域與構成放大電晶體TR3 amp之另一源極/汲極區域共用區域，且其另一源極/汲極區域連接至信號線(資料輸出線) VSL 3。 重設線RST 1、RST 2及RST 3、選擇線SEL 1、SEL 2及SEL 3以及轉移閘極線TG 2及TG 3連接至構成驅動電路之垂直驅動電路112，且信號線(資料輸出線) VSL 1、VSL 2及VSL 3連接至構成驅動電路之一行信號處理電路113。 一p+層44設置於n型半導體區域43與半導體基板70之表面70A之間，使得抑制暗電流之發生。一p+層42形成於n型半導體區域41與n型半導體區域43之間，且n型半導體區域43之側表面之一部分由p+層42環繞。一p+層73形成於半導體基板70之後表面70B側中，且一HfO 2膜74及一絕緣膜75形成於半導體基板70內側之一部分中，其中接觸孔部分61將由p+層73形成。在層間絕緣層76中，雖然導線形成於多個層上，但省略圖解說明。 HfO2膜74係具有負固定電荷之一膜，且藉由製備此一膜，可抑制暗電流之發生。注意，替代HfO 2膜，可使用一種氧化鋁(Al 2O 3)膜、一種氧化鋯(ZrO 2)膜、一種氧化鉭(Ta 2O 5)膜、一種氧化鈦(TiO 2)膜、一種氧化鑭(La 2O 3)膜、一種氧化鐠(Pr 2O 3)膜、一種氧化鈰(CeO 2)膜、一種氧化釹(Nd 2O 3)膜、一種氧化鉕(Pm 2O 3)膜、一種氧化釤(Sm 2O 3)膜、一種氧化銪(Eu 2O 3)膜、一種氧化釓(Gd 2O 3)膜、一種氧化鋱(Tb 2O 3)膜、一種氧化鏑(Dy 2O 3)膜、一種氧化鈥(Ho 2O 3)膜、一種氧化銩(Tm 2O 3)膜、一種氧化鐿(Yb 2O 3)膜、一種氧化鑥(Lu 2O 3)膜、一種氧化釔(Y 2O 3)膜、一種氮化鉿膜、一種氮化鋁膜、一種氮氧化鉿膜或一種氮氧化鋁膜。作為用於此等膜之一膜形成方法，可例示一CVD方法、一PVD方法及一ALD方法。 下文中，將參考圖5闡述實例1之成像元件(第一成像元件)之操作。本文中，將第一電極11之電位設定為高於第二電極之電位。亦即，舉例而言，當將第一電極11設定至一正電位且將第二電極設定至一負電位時，電子透過光電轉換層15中之光電轉換而被讀出至浮動擴散層。在其他實例中執行一類似操作。注意，在其中當將第一電極11設定至一負電位且將第二電極設定至一正電位時電洞透過光電轉換層15中之光電轉換而被讀出至浮動擴散層之一形式中，可將下文中所提及之電位之位準設定為相反的。 稍後闡述用於實例4中之圖5、圖20及圖21中之元件符號，且用於稍後所闡述之實例6中之圖32及圖33中之元件符號係如下。 PA ……光電轉換層15之面向電荷儲存電極12之區域之一點PA的電位或光電轉換層15之面向電荷儲存電極分段12C之區域之一點PA的電位； PB ……光電轉換層15之面向位於電荷儲存電極12與第一電極11之間的中間之一區域之區域之一點PB的電位、光電轉換層15之面向轉移控制電極(電荷轉移電極) 13之區域之一點PB的電位或光電轉換層15之面向電荷儲存電極分段12B之區域之一點PB的電位； PC ……光電轉換層15之面向第一電極11之區域之一點PC的電位或光電轉換層15之面向電荷儲存電極分段12A之區域之一點PC的電位； PD ……光電轉換層15之面向位於電荷儲存電極分段12C與第一電極11之間的中間之一區域之區域之一點PD的電位； FD ……第一浮動擴散層FD 1之電位； VOA ……電荷儲存電極12之電位。 VOA-A ……電荷儲存電極分段12A之電位； VOA-B ……電荷儲存電極分段12B之電位； VOA-C ……電荷儲存電極分段12C之電位； VOT ……轉移控制電極(電荷轉移電極) 13之電位； RST ……重設電晶體TR1 rst之閘極部分51之電位； VDD ……電源之電位； VSL_1 ……信號線(資料輸出線) VSL 1； TR1_rst ……重設電晶體TR1 rst； TR1_amp ……放大電晶體TR1 amp；及 TR1_sel ……選擇電晶體TR1 sel。 在一電荷儲存週期中，將一電位V 11自驅動電路施加至第一電極11，且將一電位V 12自驅動電路施加至電荷儲存電極12。藉由入射於光電轉換層15上之光，在光電轉換層15中發生光電轉換。透過光電轉換產生之電洞自第二電極16透過導線V OU而轉移至驅動電路。另一方面，由於將第一電極11之電位設定為高於之第二電極16電位，亦即，(舉例而言)由於將一正電位施加至第一電極11且將一負電位施加至第二電極16，因此設定V 12≥ V 11、較佳地V 12＞ V 11。因此，透過光電轉換產生之電子被電荷儲存電極12吸引，且因此電子停止於光電轉換層15之面向電荷儲存電極12之區域中。亦即，電荷被儲存於光電轉換層15中。由於V 12＞ V 11，因此光電轉換層15之內部分中所產生之電子並不朝向第一電極11移動。隨著光電轉換之時間逝去，光電轉換層15之面向電荷儲存電極12之區域之電位變為另一負值。 在電荷儲存週期之最後階段中，執行一重設操作。因此，重設第一浮動擴散層FD 1之電位，且第一浮動擴散層FD 1之電位變為電源之電位V DD。 在完成重設操作之後，執行電荷讀出。亦即，在電荷轉移週期中，自驅動電路，將一電位V 21施加至第一電極11且將一電位V 22施加至電荷儲存電極12。本文中，設定V 22＜ V 21。藉由進行此，可將已停止於光電轉換層15之面向電荷儲存電極12之區域中之電子讀出至第一電極11，此外讀出至第一浮動擴散層FD 1。亦即，將儲存於光電轉換層15中之電荷讀出至控制單元。 包含介於電荷儲存電極12與第一電極11之間的絕緣層82之結構可約束PB電位之變化。在不具有位於此一位置處之絕緣層82之情況下，絕緣層82之邊緣之各種位置可除導致電荷儲存電極12與第一電極11之間的一距離之變化之外亦導致PB電位之一變化。相反，絕緣層82在電荷儲存電極12與第一電極11之間的一開口中之存在允許電荷儲存電極12與第一電極11之間的距離來判定PB電位之效應。因此，藉由包含如上文所提及之絕緣層82，絕緣層82可致使最小PB電位增加，此使電子有效地侷限於PA位置且進一步減小一電流洩漏。 以目前為止所闡述之此方式，完成電荷儲存、重設操作及電荷轉移之一系列操作。 在將電子讀出至第一浮動擴散層FD 1之後的放大電晶體TR1 amp及選擇電晶體TR1 sel之操作與相關技術中之此等電晶體之操作相同。另外，第二成像元件及第三成像元件之電荷儲存、重設操作及電荷轉移之一系列操作類似於相關技術中之電荷儲存、重設操作及電荷轉移之一系列操作。另外，類似於相關技術，可藉由一相關雙取樣(CDS)程序而移除第一浮動擴散層FD 1之重設雜訊。 如上文所闡述，在實例1中，由於提供電荷儲存電極(其經配置以與第一電極分離且經配置以面向光電轉換層，其中絕緣層插置於該電荷儲存電極與該光電轉換層之間)，因此當用光來照明光電轉換單元且在光電轉換單元中執行光電轉換時，藉由光電轉換層、絕緣層及電荷儲存電極而形成一個種類的電容器，使得電荷可被儲存於光電轉換層中。因此，在開始曝光時，藉由完全耗盡一電荷儲存單元，可能抹除電荷。因此，可能抑制kTC雜訊之一增加、隨機雜訊之劣化及成像中之影像品質之一劣化之現象的發生。另外，由於可同時重設全部像素，因此可實施一所謂的全域快門功能。 在圖8中圖解說明實例1之一固態成像裝置之一概念圖式。實例1之固態成像裝置100經組態以包含一成像區域111 (其中堆疊型成像元件101配置成一個二維陣列形狀)及驅動電路(周邊電路) (諸如一垂直驅動電路112、一行信號處理電路113、一水平驅動電路114、一輸出電路115及一驅動控制電路116)。注意，此等電路可組態有眾所周知之電路。顯而易見，亦可使用其他電路組態(舉例而言，用於相關技術中之一CCD成像裝置或一CMOS成像裝置之各種電路)來組態此等電路。注意，在圖8中，僅一個列之堆疊型成像元件101由元件符號「101」指示。 驅動控制電路116產生一時脈信號及一控制信號，該時脈信號及該控制信號基於一垂直同步信號、一水平同步信號及一主時脈而變為垂直驅動電路112、行信號處理電路113及水平驅動電路114之操作之參考。然後，將所產生時脈信號或控制信號輸入至垂直驅動電路112、行信號處理電路113及水平驅動電路114。 舉例而言，垂直驅動電路112組態有移位暫存器且在垂直方向上以一列為單元依序選擇性地掃描成像區域111之堆疊型成像元件101。然後，將基於根據每一堆疊型成像元件101之一所接收光量產生之一電流(信號)之一像素信號(影像信號)穿過信號線(資料輸出線) 117及VSL傳輸至行信號處理電路113。 舉例而言，行信號處理電路113針對堆疊型成像元件101之每個行而配置且根據來自每個成像元件之一黑色參考像素(未展示但形成於一有效像素區域之周邊中)之一信號而對自堆疊型成像元件101之一個列輸出之影像信號執行一信號處理(諸如雜訊移除或信號放大)。 提供將連接於行信號處理電路113之輸出級與水平信號線118之間的一水平選擇開關(未展示)。 舉例而言，水平驅動電路114組態有移位暫存器且藉由依序輸出水平掃描脈衝而依序選擇行信號處理電路113以將行信號處理電路113之信號輸出至水平信號線118。 輸出電路115對透過水平信號線118自行信號處理電路113依序供應之信號執行一信號處理並輸出該等信號。 在圖9中圖解說明實例1之成像元件及堆疊型成像元件之一經修改實例之一等效電路圖。當在圖10中圖解說明構成實例1之成像元件之一經修改實例之一第一電極及一電荷儲存電極以及構成一控制單元之電晶體之一示意性佈局圖時，重設電晶體TR1 rst之另一源極/汲極區域51B可接地而非連接至電源V DD。 舉例而言，可藉由下文中所闡述之方法而製造實例1之成像元件及堆疊型成像元件。亦即，首先，製備一SOI基板。然後，基於一磊晶生長方法而在SOI基板之表面上形成一第一矽層，且在第一矽層上形成一p+層73及一n型半導體區域41。接下來，基於一磊晶生長方法而在第一矽層上形成一第二矽層，且在第二矽層上形成一元件隔離區域71、一種氧化物膜72、一p+層42、一n型半導體區域43及一p+層44。另外，在第二矽層中形成構成成像元件之一控制單元之各種電晶體及諸如此類，且在該等各種電晶體及諸如此類上形成一導線層62、一層間絕緣層76及各種導線。允許層間絕緣層76及一支撐基板(未展示)彼此黏合。在此之後，藉由移除SOI基板，使第一矽層曝露。注意，第二矽層之表面對應於半導體基板70之表面70A，且第一矽層之表面對應於半導體基板70之後表面70B。另外，將第一矽層及第二矽層共同地表達為半導體基板70。接下來，在半導體基板70之後表面70B側中，形成用於形成一接觸孔部分61之一開口部分；形成一HfO 2膜74、一絕緣膜75及接觸孔部分61；且形成墊部分63及64、一層間絕緣層81、連接孔65及66、一第一電極11、一電荷儲存電極12以及一絕緣層82。接下來，開通一連接部分67，且形成一光電轉換層15、一第二電極16、一保護層83及一晶片上微透鏡90。藉由進行此，可獲得實例1之成像元件及堆疊型成像元件。 [實例2] 實例2係實例1之一修改。實例2之一成像元件及一堆疊型成像元件(在圖11中圖解說明其一示意性部分剖面圖)係一正面照明型成像元件及一正面照明型堆疊型成像元件且具有如下三個成像元件之一堆疊結構：實例1之一第一類型綠色成像元件(第一成像元件)，其對綠色敏感且具有吸收綠色光之一第一類型綠色光電轉換層；相關技術之一第二類型藍色成像元件(第二成像元件)，其對藍色敏感且具有吸收藍色光之一第二類型藍色光電轉換層；及相關技術之一第二類型紅色成像元件(第三成像元件)，其對紅色敏感且具有吸收紅色光之一第二類型紅色光電轉換層。本文中，紅色成像元件(第三成像元件)及藍色成像元件(第二成像元件)設置於半導體基板70中，且第二成像元件經定位以比第三成像元件更接近於光入射側。另外，綠色成像元件(第一成像元件)設置於藍色成像元件(第二成像元件)上方。 類似於實例1，構成控制單元之各種電晶體設置於半導體基板70之表面70A側中。此等電晶體可形成有實質上與實例1中所闡述之電晶體之組態及結構類似之一組態及結構。另外，雖然第二成像元件及第三成像元件設置於半導體基板70中，但此等成像元件可形成有實質上與實例1中所闡述之第二成像元件及第三成像元件之組態及結構類似之一組態及結構。 在半導體基板70之表面70A上形成層間絕緣層77及78，且在層間絕緣層78上設置構成實例1之成像元件之光電轉換單元(第一電極11、光電轉換層15及第二電極16)、電荷儲存電極12及諸如此類。 以此方式，惟成像元件及堆疊型成像元件係正面照明型除外，由於實例2之成像元件及堆疊型成像元件之組態及結構可經形成以類似於實例1之成像元件及堆疊型成像元件之組態及結構，因此省略詳細說明。 [實例3] 實例3係實例1及2之一修改。 實例3之一成像元件及一堆疊型成像元件(在圖12中圖解說明其一示意性部分剖面圖)係一背面照明型成像元件及一背面照明型堆疊型成像元件且具有如下兩個成像元件之一堆疊結構：實例1之一第一類型第一成像元件及一第二類型第二成像元件。另外，實例3之成像元件及堆疊型成像元件之經修改實例(在圖13中圖解說明其一示意性部分剖面圖)係一正面照明型成像元件及一正面照明型堆疊型成像元件且具有如下兩個成像元件之一堆疊結構：實例1之一第一類型第一成像元件及一第二類型第二成像元件。本文中，第一成像元件吸收原色光，且第二成像元件吸收補色光。另一選擇係，第一成像元件吸收白色光，且第二成像元件吸收一紅外線。 實例3之成像元件之一經修改實例(在圖14中圖解說明其一示意性部分剖面圖)係一背面照明型成像元件且組態有實例1之一第一類型第一成像元件。另一選擇係，實例3之成像元件之一經修改實例(在圖15A中圖解說明其一示意性部分剖面圖)係一正面照明型成像元件且組態有實例1之一第一類型第一成像元件。本文中，第一成像元件組態有三種類型的成像元件：吸收紅色光之一成像元件；吸收綠色光之一成像元件；及吸收藍色光之一成像元件。此外，根據本發明之第一實施例之固態成像裝置組態有複數個成像元件。作為複數個成像元件之一陣列，可例示一拜耳陣列。若需要，將用於執行藍色光、綠色光及紅色光之光譜分離之彩色濾光器配置於每一成像元件之光入射側中。此外，且如圖15B至圖15D中所繪示，絕緣層82可包含多個層。如圖15B至圖15D中所繪示，絕緣層82可包含多個層82E及82F。舉例而言，可存在絕緣材料82之介於電荷儲存電極12與光電轉換層15之間的一第一區域，且可存在絕緣材料82之介於電荷儲存電極12與第一電極11之間的一第二區域。在某些實施例中，絕緣材料之第二區域包含一第一絕緣層82E (其包含絕緣材料)及一第二絕緣層82F (其包含絕緣材料)，且第一絕緣材料82F堆疊於第二絕緣材料82E上。圖15B至圖15D進一步繪示關於絕緣層82之各種組態(例如，層82E及82F之組態改變)。 注意，替代製備實例1之一個第一類型成像元件，可將兩個成像元件堆疊(亦即，將兩個光電轉換單元堆疊且在半導體基板中製備用於兩個成像元件之控制單元)，或可將三個成像元件堆疊(亦即，將三個光電轉換單元堆疊且在半導體基板中製備用於三個成像元件之控制單元)。在下表中列示第一類型成像元件及第二類型成像元件之經堆疊結構之實例。 [表1]    第一類型 第二類型 參考圖 背面照明型及正面照明型 1 2 圖1A至圖1D 綠色 藍色+紅色 圖11 1 1 圖12 原色 補色 圖13 1 1    白色 紅外線    1 0 圖14 藍色或綠色或紅色    圖15A至圖15D 2 2    綠色+紅外線光 藍色+紅色    2 1    綠色+藍色 紅色    2 0    白色+紅外線光       3 2    綠色+藍色+紅色 藍綠色(翡翠色)+紅外線光    3 1    綠色+藍色+紅色 紅外線光    3 0    藍色+綠色+紅色       [實例4] 實例4係實例1至3之一修改且係關於根據本發明之一實施例之具有轉移控制電極(電荷轉移電極)之一成像元件或諸如此類。在圖16中圖解說明實例4之成像元件及堆疊型成像元件之一部分之一示意性部分剖面圖。在圖17及圖18中圖解說明實例4之成像元件及堆疊型成像元件之等效電路圖。在圖19中圖解說明構成實例4之成像元件之一第一電極、一轉移控制電極及一電荷儲存電極以及構成一控制單元之電晶體之一示意性佈局圖。在圖20及圖21中圖解說明處於實例4之成像元件之一操作週期中之組件之電位狀態。另外，在圖22中圖解說明構成實例4之成像元件之第一電極、轉移控制電極及電荷儲存電極之一示意性佈局圖。在圖23中圖解說明構成實例4之成像元件之第一電極、轉移控制電極、電荷儲存電極、一第二電極及一接觸孔部分之一示意性透視圖。 實例4之成像元件及堆疊型成像元件經組態以進一步包含一轉移控制電極(電荷轉移電極) 13，該轉移控制電極配置於第一電極11與電荷儲存電極12之間、將與第一電極11及電荷儲存電極12分離且經配置以透過絕緣層82而面向光電轉換層15。轉移控制電極13透過設置於層間絕緣層81中之一連接孔68B、一墊部分68A及一導線V OT而連接至構成驅動電路之像素驅動電路。注意，為方便起見，由元件符號91共同地表示成像元件之位於層間絕緣層81下方之各種組件以便簡化圖式。 下文中，將參考圖20及圖21闡述實例4之成像元件(第一成像元件)之操作。注意，圖20及圖21彼此不同，特定而言在施加至電荷儲存電極12之電位及點PB之電位方面。 在電荷儲存週期中，自驅動電路，將一電位V 11施加至第一電極11、將一電位V 12施加至電荷儲存電極12且將一電位V 13施加至轉移控制電極13。藉由入射於光電轉換層15上之光，在光電轉換層15中發生光電轉換。透過光電轉換產生之電洞自第二電極16透過導線V OU而轉移至驅動電路。另一方面，由於將第一電極11之電位設定為高於之第二電極16電位，亦即，(舉例而言)由於將一正電位施加至第一電極11且將一負電位施加至第二電極16，因此設定V 12＞ V 13(舉例而言，V 12＞ V 11＞ V 13或V 11＞ V 12＞ V 13)。因此，透過光電轉換產生之電子被電荷儲存電極12吸引，且因此電子停止於光電轉換層15之面向電荷儲存電極12之區域中。亦即，電荷被儲存於光電轉換層15中。由於V 12＞ V 13，因此可能可靠地防止產生於光電轉換層15中之電子朝向第一電極11移動。隨著光電轉換之時間逝去，光電轉換層15之面向電荷儲存電極12之區域之電位變為另一負值。 在電荷儲存週期之最後階段中，執行一重設操作。因此，重設第一浮動擴散層FD 1之電位，且第一浮動擴散層FD 1之電位變為電源之電位V DD。 在完成重設操作之後，執行電荷讀出。亦即，在電荷轉移週期中，自驅動電路，將一電位V 21施加至第一電極11、將一電位V 22施加至電荷儲存電極12且將一電位V 23施加至轉移控制電極13。本文中，設定V 22≤ V 23≤ V 21。藉由進行此，可將已停止於光電轉換層15之面向電荷儲存電極12之區域中之電子可靠地讀出至第一電極11，且此外讀出至第一浮動擴散層FD 1。亦即，將儲存於光電轉換層15中之電荷讀出至控制單元。 以目前為止所闡述之此方式，完成電荷儲存、重設操作及電荷轉移之一系列操作。 在將電子讀出至第一浮動擴散層FD 1之後的放大電晶體TR1 amp及選擇電晶體TR1 sel之操作與相關技術中之此等電晶體之操作相同。另外，(舉例而言)第二成像元件及第三成像元件之電荷儲存、重設操作及電荷轉移之一系列操作類似於相關技術中之電荷儲存、重設操作及電荷轉移之一系列操作。 當在圖24中圖解說明構成實例4之成像元件之一經修改實例之第一電極及電荷儲存電極以及構成一控制單元之電晶體之一示意性佈局圖時，重設電晶體TR1 rst之另一源極/汲極區域51B可接地而非連接至電源V DD。 [實例5] 實例5係實例1至4之一修改且係關於根據本發明之一實施例之具有一電荷射出電極之一成像元件或諸如此類。在圖25中圖解說明實例5之成像元件及堆疊型成像元件之一部分之一示意性部分剖面圖。在圖26中圖解說明構成實例5之成像元件之一第一電極、一電荷儲存電極及一電荷射出電極之一示意性佈局圖。在圖27中圖解說明構成實例5之成像元件之第一電極、電荷儲存電極、電荷射出電極、一第二電極及一接觸孔部分之一示意性透視圖。 在實例5之成像元件及堆疊型成像元件中，成像元件經組態以進一步包含一電荷射出電極14，該電荷射出電極透過一連接部分69連接至一光電轉換層15且經配置以與第一電極11及電荷儲存電極12分離。電荷射出電極14經配置以環繞第一電極11及電荷儲存電極12 (亦即，呈一框架形狀)。電荷射出電極14連接至構成驅動電路之像素驅動電路。光電轉換層15延伸於連接部分69中。亦即，光電轉換層15延伸於設置於絕緣層82中之第二開口部分85中以連接至電荷射出電極14。電荷射出電極14由複數個成像元件共用(共同使用)。 在實例5中，在電荷儲存週期中，自驅動電路，將一電位V 11施加至第一電極11、將一電位V 12施加至電荷儲存電極12且將一電位V 14施加至電荷射出電極14，使得電荷被儲存於光電轉換層15中。藉由入射於光電轉換層15上之光，在光電轉換層15中發生光電轉換。透過光電轉換產生之電洞自第二電極16透過導線V OU而轉移至驅動電路。另一方面，由於將第一電極11之電位設定為高於之第二電極16電位，亦即，(舉例而言)由於將一正電位施加至第一電極11且將一負電位施加至第二電極16，因此設定V 14＞ V 11(舉例而言，V 12＞ V 14＞ V 11)。因此，透過光電轉換產生之電子被電荷儲存電極12吸引，且因此電子停止於光電轉換層15之面向電荷儲存電極12之區域中，使得可能可靠地防止電子朝向第一電極11移動。然而，未被電荷儲存電極12充分吸引或未儲存於光電轉換層15中之電子(所謂的溢流電子)透過電荷射出電極14而轉移至驅動電路。 在電荷儲存週期之最後階段中，執行一重設操作。因此，重設第一浮動擴散層FD 1之電位，且第一浮動擴散層FD 1之電位變為電源之電位V DD。 在完成重設操作之後，執行電荷讀出。亦即，在電荷轉移週期中，自驅動電路，將一電位V 21施加至第一電極11、將一電位V 22施加至電荷儲存電極12且將一電位V 24施加至電荷射出電極14。本文中，設定V 24＜ V 21(舉例而言，V 24＜ V 22＜ V 21)。藉由進行此，可將已停止於光電轉換層15之面向電荷儲存電極12之區域中之電子可靠地讀出至第一電極11，且此外讀出至第一浮動擴散層FD 1。亦即，將儲存於光電轉換層15中之電荷讀出至控制單元。 以目前為止所闡述之此方式，完成電荷儲存、重設操作及電荷轉移之一系列操作。 在將電子讀出至第一浮動擴散層FD 1之後的放大電晶體TR1 amp及選擇電晶體TR1 sel之操作與相關技術中之此等電晶體之操作相同。另外，(舉例而言)第二成像元件及第三成像元件之電荷儲存、重設操作及電荷轉移之一系列操作類似於相關技術中之電荷儲存、重設操作及電荷轉移之一系列操作。 在實例5中，由於溢流電子透過電荷射出電極14而轉移至驅動電路，因此可抑制向毗鄰像素之電荷儲存單元之洩漏，使得可能抑制模糊(blooming)之發生。此外，因此，可能改良成像元件之成像效能。 [實例6] 實例6係實例1至5之一修改且係關於根據本發明之一實施例之具有複數個電荷儲存電極分段之一成像元件或諸如此類。 在圖28中圖解說明實例6之成像元件之一部分之一示意性部分剖面圖。在圖29及圖30中圖解說明實例6之成像元件及堆疊型成像元件之等效電路圖。在圖31中圖解說明構成實例6之成像元件之一第一電極及一電荷儲存電極以及構成一控制單元之電晶體之一示意性佈局圖。在圖32及圖33中圖解說明處於實例6之成像元件之一操作週期中之組件之電位狀態。另外，在圖34中圖解說明構成實例6之成像元件之第一電極及電荷儲存電極之一示意性佈局圖。在圖35中圖解說明構成實例6之成像元件之第一電極、電荷儲存電極、一第二電極及一接觸孔部分之一示意性透視圖。 在實例6中，電荷儲存電極12組態有複數個電荷儲存電極分段12A、12B及12C。電荷儲存電極分段之數目可為兩個或兩個以上，且在實例6中，將該數目設定為「3」。然後，在實例6之成像元件及堆疊型成像元件中，由於第一電極11之電位高於第二電極16之電位，亦即，(舉例而言)由於將一正電位施加至第一電極11且將一負電位施加至第二電極16，因此在電荷轉移週期中，施加至位於最接近於第一電極11之位置處之電荷儲存電極分段12A之電位高於施加至位於距第一電極11最遠之位置處之電荷儲存電極分段12C之電位。以此方式，對電荷儲存電極12提供電位梯度，使得將已停止於光電轉換層15之面向電荷儲存電極12之區域中之電子可靠地讀出至第一電極11，且此外讀出至第一浮動擴散層FD 1。亦即，將儲存於光電轉換層15中之電荷讀出至控制單元。 在圖32中所圖解說明之實例中，在電荷轉移週期中，設定電荷儲存電極分段12C之電位＜電荷儲存電極分段12B之電位＜電荷儲存電極分段12A之電位，且因此，將已停止於光電轉換層15之區域中之電子同時讀出至第一浮動擴散層FD 1。另一方面，在圖33中所圖解說明之實例中，在電荷轉移週期中，允許電荷儲存電極分段12C之電位、電荷儲存電極分段12B之電位及電荷儲存電極分段12A之電位逐漸地改變(亦即，逐步或以一斜坡形狀改變)。因此，允許使已停止於光電轉換層15之面向電荷儲存電極分段12C之區域中之電子移動至面向電荷儲存電極分段12B之光電轉換層15。隨後，允許使已停止於光電轉換層15之面向電荷儲存電極分段12B之區域中之電子移動至面向電荷儲存電極分段12A之光電轉換層15。隨後，允許將已停止於光電轉換層15之面向電荷儲存電極分段12A之區域中之電子可靠地讀出至第一浮動擴散層FD 1。 當在圖36中圖解說明構成實例6之成像元件之一經修改實例之一第一電極及一電荷儲存電極以及構成一控制單元之電晶體之一示意性佈局圖時，重設電晶體TR1 rst之另一源極/汲極區域51B可接地而非連接至電源V DD。 目前為止，雖然基於較佳實例而闡述本發明，但本發明並不限於該等實例。實例中所闡述之成像元件、堆疊型成像元件及固態成像裝置之結構、組態、製造條件、製造方法及所使用材料係例示性的，且因此此等經適當地改變。除其中將一個浮動擴散層設置至一個成像元件之形式之外，亦可實施其中將一個浮動擴散層設置至複數個成像元件之一形式。亦即，藉由適當地控制電荷轉移週期之一時序，可允許複數個成像元件共用一個浮動擴散層。此外，在此情形中，亦可允許複數個成像元件共用一個接觸孔部分。 當在圖37中圖解說明實例1中所闡述之成像元件及堆疊型成像元件之一經修改實例時，第一電極11可經組態以延伸於設置至絕緣層82之一開口部分84A中以連接至光電轉換層15。 另一選擇係，當在圖38中圖解說明實例1中所闡述之成像元件及堆疊型成像元件之一經修改實例且在圖39A中圖解說明第一電極之一部分及諸如此類之一示意性放大部分剖面圖時，第一電極11之頂部表面之邊緣覆蓋有絕緣層82；第一電極11曝露於一開口部分84B之底部表面；且當絕緣層82之與第一電極11之頂部表面接觸之表面由一第一表面82a界定且絕緣層82之與光電轉換層15之部分(其面向電荷儲存電極12)接觸之表面由一第二表面82b界定時，開口部分84B之側表面具有自第一表面82a朝向第二表面82b擴展之一斜坡。以此方式，由於對開口部分84B之側表面提供一斜坡，因此電荷自光電轉換層15較平滑地移動至第一電極11。注意，在圖39A中所圖解說明之實例中，將開口部分84B之軸線用作一中心，且開口部分84B之側表面具有一旋轉對稱。然而，如圖39B中所圖解說明，開口部分84C可經設置使得開口部分84C之具有自第一表面82a朝向第二表面82b擴展之一斜坡之側表面位於電荷儲存電極12側中。因此，來自光電轉換層15之位於與電荷儲存電極12相對之側(其中開口部分84C插置於該側與該電荷儲存電極之間)處之部分的電荷難以移動。另外，雖然開口部分84B之側表面具有自第一表面82a朝向第二表面82b擴展之一斜坡，但開口部分84B之側表面之在第二表面82b中之邊緣可位於自第一電極11之邊緣之外側中(如圖39A中所圖解說明)，或可位於自第一電極11之邊緣以內之側中(如圖39C中所圖解說明)。藉由採用前一組態，可較容易地執行電荷轉移；且藉由採用後一組態，可減小在形成開口部分時之形狀不規則性。 可藉由對在絕緣層中形成開口部分(基於一蝕刻方法)時所形成之由一抗蝕劑材料製成之一蝕刻遮罩進行回銲以對一蝕刻遮罩之一開口部分之側表面提供一斜坡且藉由使用蝕刻遮罩來蝕刻絕緣層82而形成開口部分84B及84C。 另一選擇係，關於實例5中所闡述之電荷射出電極14，如圖40中所圖解說明，光電轉換層15可經形成以延伸於設置至絕緣層82之一第二開口部分85A中以連接至電荷射出電極14；電荷射出電極14之頂部表面之邊緣覆蓋有絕緣層82；電荷射出電極14曝露於第二開口部分85A之底部表面中；且當絕緣層82之與電荷射出電極14之頂部表面接觸之表面由一第三表面82c界定且絕緣層82之與光電轉換層15之部分(其面向電荷儲存電極12)接觸之表面由一第二表面82b界定時，第二開口部分85A之側表面具有自第三表面82c朝向第二表面82b擴展之一斜坡。 另一選擇係，當在圖41中圖解說明實例1中所闡述之成像元件及堆疊型成像元件之一經修改實例時，光可經組態以入射於第二電極16之側上，且一光屏蔽層92可經組態以形成於第二電極16之光入射側中。注意，可允許將經設置為與至光電轉換層相比更接近於光入射側之各種導線用作光屏蔽層。 注意，在圖41中所圖解說明之實例中，雖然光屏蔽層92形成於第二電極16上方，亦即，雖然光屏蔽層92形成於第一電極11上方作為第二電極16之光入射側，但如圖42中所圖解說明，光屏蔽層可配置於第二電極16之光入射側之表面上。另外，在某些情形中，如圖43中所圖解說明，光屏蔽層92可形成於第二電極16中。 另一選擇係，可提供其中光自第二電極16側入射且無光入射於第一電極11上之一結構。具體而言，如圖41中所圖解說明，光屏蔽層92形成於第一電極11上方作為第二電極16之光入射側。另一選擇係，如圖45中所圖解說明，可提供一結構，在該結構中一晶片上微透鏡90設置於電荷儲存電極12及第二電極16上方，且入射於晶片上微透鏡90上之光收集於電荷儲存電極12中，使得光可並不到達第一電極11。注意，如實例4中所闡述，在其中提供轉移控制電極13之情形中，可能實施其中光並不入射於第一電極11及轉移控制電極13上之一形式。具體而言，如圖44中所圖解說明，可提供其中光屏蔽層92形成於第一電極11及轉移控制電極13上方之一形式。另一選擇係，可提供其中入射於晶片上微透鏡90上之光並不到達第一電極11及轉移控制電極13之一結構。 藉由採用上文所闡述組態及結構，另一選擇係，提供光屏蔽層92使得光僅入射於光電轉換層15之位於電荷儲存電極12上方之部分上，或另一選擇係設計晶片上微透鏡90，由於光電轉換層15之位於第一電極11上方(或位於第一電極11及轉移控制電極13上方)之部分並不促成光電轉換，因此可能同時較可靠地重設全部像素，使得可能較容易地實施一全域快門功能。亦即，在用於包含具有上文所闡述組態及結構之複數個成像元件之一固態成像裝置之一驅動方法中，重複以下程序： 同時在所有成像元件中，將電荷儲存於光電轉換層15中，且將第一電極11之電荷射出至外部；及 同時在所有成像元件中，將儲存於光電轉換層15中之電荷轉移至第一電極11，且在完成轉移之後，將轉移至各別成像元件中之第一電極11之電荷依序讀出。 光電轉換層並不限於其中光電轉換層係一個層之組態。舉例而言，當在圖46A中圖解說明實例1中所闡述之成像元件及堆疊型成像元件之一經修改實例時，光電轉換層15可經組態以具有實例1中所闡述之(舉例而言)一下部半導體層15A (其由IGZO製成)及一上部光電轉換層15B (其由構成光電轉換層15之一材料製成)之一堆疊層結構。以此方式，藉由提供下部半導體層15A，可能在電荷儲存週期中防止重新耦合，使得可能增加儲存於光電轉換層15中之電荷至第一電極11之轉移效率，且可能抑制暗電流之發生。另外，作為實例4之一經修改實例，如圖47中所圖解說明，可自最接近於第一電極11之位置朝向電荷儲存電極12提供複數個轉移控制電極。注意，在圖47中圖解說明其中提供兩個轉移控制電極13A及13B之一實例。 如圖46B至圖46D中所繪示，絕緣層82可包含多個層82E及82F。舉例而言，可存在絕緣材料82之介於電荷儲存電極12與光電轉換層15之間的一第一區域，且可存在絕緣材料82之介於電荷儲存電極12與第一電極11之間的一第二區域。在某些實施例中，絕緣材料之第二區域包含一第一絕緣層82E (其包含絕緣材料)及一第二絕緣層82F (其包含絕緣材料)，且第一絕緣材料82F堆疊於第二絕緣材料82E上。圖46B至圖46D進一步繪示關於絕緣層82之各種組態(例如，層82E及82F之組態改變)。 在上文中所闡述之各種經修改實例可適當地應用於實例1或其他實例。 在實例中，雖然將電子設定為信號電荷且將形成於半導體基板中之光電轉換層之導電類型設定為n型，但本發明可應用於其中將電洞設定為信號電荷之一固態成像裝置。在此情形中，每一半導體區域可組態為具有相反導電類型之一半導體區域，且形成於半導體基板中之光電轉換層之導電類型可為p型。 另外，在實例中，雖然在說明中例示應用於CMOS型固態成像裝置(其中根據作為一物理量之入射光量而偵測信號電荷之單位像素被配置成一矩陣形狀)之情形，但本發明並不限於應用於CMOS型固態成像裝置，而是本發明可應用於一CCD型固態成像裝置。在後一情形中，信號電荷藉由具有CCD型結構之一垂直轉移暫存器而在垂直方向上轉移，且信號電荷藉由一水平轉移暫存器而在水平方向上轉移以被放大，使得輸出一像素信號(影像信號)。另外，本發明並不限於其中像素形成為一個二維矩陣形狀且針對各別像素行配置行信號處理電路之整體行型固態成像裝置。此外，在某些情形中，可省略選擇電晶體。 此外，本發明之成像元件及堆疊型成像元件並不限於應用於偵測可見光之入射光量之一分佈以將該分佈成像為一影像之固態成像裝置，而是本發明之成像元件及堆疊型成像元件亦可應用於將紅外線、X射線、粒子或諸如此類之入射量之一分佈成像為一影像之一固態成像裝置。另外，在一廣泛意義上，本發明之成像元件及堆疊型成像元件可應用於偵測另一物理量(諸如壓力或靜電電容)之一分佈以將該分佈成像為一影像之整體固態成像裝置(物理量分佈偵測裝置)，諸如一指紋偵測感測器。 此外，本發明並不限於以一列為單位依序掃描成像區域之單位像素以自單位像素讀出像素信號之一固態成像裝置。本發明可應用於以一像素為單位任意地選擇像素且以一像素為單位自選擇像素讀出像素信號之一X-Y位址類型固態成像裝置。固態成像裝置可形成一個晶片，或固態成像裝置可形成為具有一成像功能之一模組形狀，其中共同地封裝一成像區域、一驅動電路或一光學系統。 另外，本發明並不限於應用於固態成像裝置，而是本發明可應用於一成像裝置。本文中，成像裝置表示一相機系統(諸如一數位靜態相機或一視訊攝影機)或一電子設備(諸如具有一成像功能之一行動電話)。在某些情形中，本發明可實施為將被安裝於一電子設備上之一模組狀形式，亦即，一相機模組。 在圖48之一概念圖式中圖解說明其中將組態有本發明之成像元件或堆疊型成像元件之一固態成像裝置201用於一電子設備(相機) 200之一實例。電子設備200包含一固態成像裝置201、一光學透鏡210、一快門裝置211、一驅動電路212及一信號處理電路213。光學透鏡210在固態成像裝置201之一成像地點上形成來自一對象之影像光(入射光)之一影像。因此，信號電荷儲存於固態成像裝置201中達一特定週期。快門裝置211控制固態成像裝置201之一光照明週期及一光屏蔽週期。驅動電路212供應驅動信號以用於控制固態成像裝置201之一轉移操作及快門裝置211之一快門操作。根據自驅動電路212供應之驅動信號(時序信號)，執行固態成像裝置201之信號轉移。信號處理電路213執行各種信號處理。將經受信號處理之一影像信號儲存於一儲存媒體(諸如一記憶體)中或輸出至一監視器。在電子設備200中，由於改良固態成像裝置201之像素大小及轉移效率，因此可能達成其像素特性經改良之電子設備200。固態成像裝置201可應用於的電子設備200並不限於相機，而是電子設備可應用於用於一行動設備(諸如一行動電話)之一成像裝置(諸如一數位靜態相機或一相機模組)。 熟習此項技術者應理解，可取決於設計要求及其他因素做出各種修改、組合、子組合及變更，只要其屬於隨附申請專利範圍或其等效內容之範疇內。 此外，舉例而言，本技術可具有以下組態。 (1)一種成像裝置，其包含： 一基板，其包含一第一光電轉換單元；及一第二光電轉換單元，其位於該基板之一光入射側處，該第二光電轉換單元包含：一光電轉換層；一第一電極；一第二電極，其位於該光電轉換層上方；一第三電極；及一絕緣材料，其介於該第三電極與該光電轉換層之間，其中該絕緣材料之一部分介於該第一電極與該第三電極之間。 (2)根據上文(1)之成像裝置，其進一步包含：該絕緣材料之一第一區域，該第一區域介於該第三電極與該光電轉換層之間；該絕緣材料之一第二區域，該第二區域介於該第三電極與該第一電極之間，其中該絕緣材料之該第二區域包含具有該絕緣材料之一第一絕緣層及具有該絕緣材料之一第二絕緣層，且其中第一絕緣材料堆疊於第二絕緣材料上。 (3)根據上文(2)之成像裝置，其中該第二區域中之該第一絕緣層之一部分介於該第一電極與該光電轉換層之間。 (4)根據上文(3)之成像裝置，其中該第一區域與該第二區域包含不同數目個具有該絕緣材料之絕緣層。 (5)根據上文(1)至(4)中任一者之成像裝置，其進一步包含一轉移控制電極，該轉移控制電極介於該第一電極與該第三電極之間。 (6)根據上文(5)之成像裝置，其中在一電荷儲存操作期間，施加至該轉移控制電極之一電位小於施加至該第三電極之一電位。 (7)根據上文(5)至(6)中任一者之成像裝置，其中該基板包含一第三光電轉換單元，且其中該第一光電轉換單元、該第二光電轉換單元及該第三光電轉換單元中之每一者耦合至分開之信號線。 (8)根據上文(1)至(7)中任一者之成像裝置，其進一步包含一電荷射出電極，該電荷射出電極與該第一電極及該第三電極分離且分開，其中該光電轉換層接觸該電荷射出電極。 (9)根據上文(8)之成像裝置，其中該電荷射出電極環繞該第一電極及該第三電極。 (10)根據上文(1)至(9)中任一者之成像裝置，其進一步包含複數個第三電極分段。 (11)根據上文(10)之成像裝置，其中位於最接近於該第一電極之一位置處之一第三電極分段之一電位大於位於距該第一電極最遠之一位置處之一第三電極分段之一電位。 (12)根據上文(1)至(11)中任一者之成像裝置，其中該光電轉換層包含一堆疊層結構，該堆疊層結構包含一下部半導體層及一上部光電轉換層。 (13)根據上文(12)之成像裝置，其中位於該第三電極上方之該下部半導體層之一材料組合物不同於位於該第一電極上方之該下部半導體層之一材料組合物。 (14)根據上文(12)至(13)中任一者之成像裝置，其中該下部半導體層包含一種含銦氧化物。 (15)根據上文(1)至(14)中任一者之成像裝置，其中在一電荷儲存週期期間，施加至該第三電極之一電位大於施加至該第一電極之一電位。 (16)根據上文(1)至(15)中任一者之成像裝置，其中該絕緣材料之至少一部分安置於該第一電極上方。 (17)根據上文(16)之成像裝置，其中隨著該第一電極與該第三電極之間的一距離減小，介於該第一電極之上部表面與該光電轉換層之間的該絕緣材料之一厚度在該第一電極之一第三電極側處增加。 (18)根據上文(1)至(17)中任一者之成像裝置，其中該成像裝置係一背面照明型成像裝置。 (19)一種電子設備，其包含：一成像裝置，該成像裝置包含：一基板，其包含一第一光電轉換單元；及一第二光電轉換單元，其位於該基板之一光入射側處，該第二光電轉換單元包含：一光電轉換層；一第一電極；一第二電極，其位於該光電轉換層上方；一第三電極；及一絕緣材料，其介於該第三電極與該光電轉換層之間，其中該絕緣材料之一部分介於該第一電極與該第三電極之間；一透鏡，其經組態以將光引導至該成像裝置之一表面上；及電路，其經組態以控制來自該成像裝置之輸出信號。 (20)一種驅動一成像裝置之方法，該方法包含：在一充電週期期間將一第一電位施加至一電荷儲存電極；在一充電週期期間將一第二電位施加至一第一電極，其中該第一電位大於該第二電位；在一電荷轉移週期期間將一第三電位施加至該電荷儲存電極；及在該電荷轉移週期期間將一第四電位施加至該第一電極，其中該第四電位大於該第三電位，且其中，該成像裝置包含：一基板，其包含一第一光電轉換單元；及一第二光電轉換單元，其位於該基板之一光入射側處，該第二光電轉換單元包含：一光電轉換層；該第一電極；一第二電極，其位於該光電轉換層上方；該電荷儲存電極；及一絕緣材料，其介於該電荷儲存電極與該光電轉換層之間，其中該絕緣材料之一部分介於該第一電極與該電荷儲存電極之間。 (A01) ＜＜成像元件＞＞ 一種成像裝置，其包含： 一光電轉換單元，其藉由堆疊一第一電極、一光電轉換層及一第二電極而組態， 其中該光電轉換單元進一步包含一電荷儲存電極，該電荷儲存電極經配置以與該第一電極分離且經配置以透過一絕緣層而面向該光電轉換層。 (A02) 根據(A01)之成像元件，其進一步包含一半導體基板， 其中該光電轉換單元配置於該半導體基板上方。 (A03] 根據(A01)或(A02)之成像元件，其中該第一電極延伸於設置至該絕緣層之一開口部分中以連接至該光電轉換層。 (A04) 根據(A01)或(A02)之成像元件，其中該光電轉換層延伸於設置至該絕緣層之一開口部分中以連接至該第一電極。 (A05) 根據(A04)之成像元件， 其中該第一電極之一頂部表面之一邊緣覆蓋有該絕緣層， 該第一電極曝露於該開口部分之一底部表面，且 當該絕緣層之與該第一電極之該頂部表面接觸之一表面由一第一表面界定且該絕緣層之與該光電轉換層之一部分(其面向該電荷儲存電極)接觸之一表面由一第二表面界定時，該開口部分之一側表面具有自該第一表面朝向該第二表面擴展之一斜坡。 (A06) 根據(A05)之成像元件，其中該開口部分之具有自該第一表面朝向該第二表面擴展之該斜坡之該側表面位於一電荷儲存電極側中。 (A07) ＜＜對第一電極及電荷儲存電極之電位之控制＞＞ 根據(A01)至(A06)中任一者之成像元件，其進一步包含一控制單元，該控制單元設置至一半導體基板且包含一驅動電路， 其中該第一電極及該電荷儲存電極連接至該驅動電路， 在一電荷儲存週期中，自該驅動電路，將一電位V 11施加至該第一電極且將一電位V 12施加至該電荷儲存電極，使得電荷被儲存於該光電轉換層中，且 在一電荷轉移週期中，自該驅動電路，將一電位V 21施加至該第一電極且將一電位V 22施加至該電荷儲存電極，使得儲存於該光電轉換層中之該等電荷透過該第一電極而被讀出至該控制單元， 在其中該第一電極之一電位高於該第二電極之一電位之情形中， V 12≥ V 11，且V 22＜ V 21，且 在其中該第一電極之該電位低於該第二電極之該電位之情形中， V 12≤ V 11且V 22＞ V 21。 (A08) ＜＜轉移控制電極＞＞ 根據(A01)至(A06)中任一者之成像元件，其進一步包含一轉移控制電極，該轉移控制電極配置於該第一電極與該電荷儲存電極之間、將與該第一電極及該電荷儲存電極分離且經配置以透過該絕緣層而面向該光電轉換層。 (A09) ＜＜對第一電極、電荷儲存電極及轉移控制電極之電位之控制＞＞ 根據(A08)之成像元件，其進一步包含一控制單元，該控制單元設置至一半導體基板且包含一驅動電路， 其中該第一電極、該電荷儲存電極及該轉移控制電極連接至該驅動電路， 在一電荷儲存週期中，自該驅動電路，將一電位V 11施加至該第一電極、將一電位V 12施加至該電荷儲存電極且將一電位V 13施加至該轉移控制電極，使得電荷被儲存於該光電轉換層中，且 在一電荷轉移週期中，自該驅動電路，將一電位V 21施加至該第一電極、將一電位V 22施加至該電荷儲存電極且將一電位V 23施加至該轉移控制電極，使得儲存於該光電轉換層中之該等電荷透過該第一電極而被讀出至該控制單元， 在其中該第一電極之一電位高於該第二電極之一電位之情形中， V 12＞ V 13且V 22≤ V 23≤ V 21，且 在其中該第一電極之該電位低於該第二電極之該電位之情形中， V 12＜ V 13且V 22≥ V 23≥ V 21。 (A10) ＜＜電荷射出電極＞＞ 根據(A01)至(A09)中任一者之成像元件，其進一步包含一電荷射出電極，該電荷射出電極連接至該光電轉換層且經配置以與該第一電極及該電荷儲存電極分離。 (A11) 根據(A10)之成像元件，其中該電荷射出電極經配置以環繞該第一電極及該電荷儲存電極。 (A12) 根據(A10)或(A11)之成像元件， 其中該光電轉換層延伸於設置至該絕緣層之一第二開口部分中以連接至該電荷射出電極， 該電荷射出電極之一頂部表面之一邊緣覆蓋有該絕緣層， 該電荷射出電極曝露於該第二開口部分之一底部表面，且 當該絕緣層之與該電荷射出電極之該頂部表面接觸之一表面由一第三表面界定且該絕緣層之與該光電轉換層之一部分(其面向該電荷儲存電極)接觸之一表面由一第二表面界定時，該第二開口部分之一側表面具有自該第三表面朝向該第二表面擴展之一斜坡。 (A13) ＜＜對第一電極、電荷儲存電極及電荷射出電極之電位之控制＞＞ 根據(A10)至(A12)中任一者之成像元件，其進一步包含一控制單元，該控制單元設置至半導體基板且具有一驅動電路， 其中該第一電極、該電荷儲存電極及該電荷射出電極連接至該驅動電路， 在一電荷儲存週期中，自該驅動電路，將一電位V 11施加至該第一電極、將一電位V 12施加至該電荷儲存電極且將一電位V 14施加至該電荷射出電極，使得電荷被儲存於光電轉換層中， 在一電荷轉移週期中，自該驅動電路，將一電位V 21施加至該第一電極、將一電位V 22施加至該電荷儲存電極且將一電位V 24施加至該電荷射出電極，使得儲存於該光電轉換層中之該等電荷透過該第一電極而被讀出至該控制單元， 在其中該第一電極之一電位高於該第二電極之一電位之情形中， V 14＞ V 11且V 24＜ V 21，且 在其中該第一電極之該電位低於該第二電極之該電位之情形中， V 14＜ V 11且V 24＞ V 21. (A14) ＜＜電荷儲存電極分段＞＞ 根據(A01)至(A13)中任一者之成像元件，其中該電荷儲存電極組態有複數個電荷儲存電極分段。 (A15) 根據(A14)之成像元件，其中在其中該第一電極之一電位高於該第二電極之一電位之情形中，在一電荷轉移週期中，施加至位於最接近於該第一電極之位置處之該電荷儲存電極分段之一電位高於施加至位於距該第一電極最遠之位置處之該電荷儲存電極分段之一電位，且在其中該第一電極之該電位低於該第二電極之該電位之情形中，在電荷轉移週期中，施加至位於最接近於該第一電極之該位置處之該電荷儲存電極分段之該電位低於施加至位於距該第一電極最遠之該位置處之該電荷儲存電極分段之該電位。 (B01) 根據(A01)至(A15)中任一者之成像元件， 其中構成一控制單元之至少一浮動擴散層及一放大電晶體設置至一半導體基板，且 該第一電極連接至該浮動擴散層及該放大電晶體之一閘極部分。 (B02) 根據(B01)成像元件， 其中構成該控制單元之一重設電晶體及一選擇電晶體進一步設置至該半導體基板， 該浮動擴散層連接至該重設電晶體之一個源極/汲極區域，且 該放大電晶體之一個源極/汲極區域連接至該選擇電晶體　一個源極/汲極區域，且該選擇電晶體之另一源極/汲極區域連接至一信號線。 (B03) 根據(A01)至(B02)中任一者之成像元件，其中該電荷儲存電極大於該第一電極。 (B04) 根據(A01)至(B03)中任一者之成像元件，其中光自一第二電極側入射，且一光屏蔽層形成於該第二電極之一光入射側中。 (B05) 根據(A01)至(B03)中任一者之成像元件，其中光自一第二電極側入射，且光並不入射於該第一電極上。 (B06) 根據(B05)之成像元件，其中一光屏蔽層形成於該第一電極上方作為該第二電極之一光入射側。 (B07) 根據(B05)之成像元件， 其中一晶片上微透鏡設置於該電荷儲存電極及該第二電極上方，且 在該電荷儲存電極中收集入射於該晶片上微透鏡上之光。 (C01) ＜＜堆疊型成像元件＞＞ 一種堆疊型成像元件，其包含根據(A01)至(B07)中任一者之至少一個成像元件。 (D01) ＜＜固態成像裝置…第一實施例＞＞ 一種固態成像裝置，其包含根據(A01)至(B04)中任一者之複數個成像元件。 (D02) ＜＜固態成像裝置…第二實施例＞＞ 一種固態成像裝置，其包含根據(C01)之複數個堆疊型成像元件。 (E01) ＜＜用於固態成像裝置之驅動方法＞＞ 一種用於一固態成像裝置之驅動方法，該固態成像裝置具有複數個成像元件，該複數個成像元件具有一結構，其中 包含一光電轉換單元，其藉由堆疊一第一電極、一光電轉換層及一第二電極而組態， 該光電轉換單元進一步包含一電荷儲存電極，該電荷儲存電極經配置以與該第一電極分離且經配置以透過一絕緣層而面向該光電轉換層，且 光自一第二電極側入射，且光並不入射於該第一電極上，該驅動方法包含重複地進行以下操作： 同時在所有成像元件中，將電荷儲存於該光電轉換層中，且將該第一電極之電荷射出至外部； 同時在所有成像元件中，將儲存於該光電轉換層中之電荷轉移至該第一電極；及 在完成該轉移之後，將轉移至各別成像元件中之第一電極之電荷依序讀出。 [CROSS REFERENCE TO RELATED APPLICATIONS] This application claims the benefit of Japanese Priority Patent Application JP 2016-193919, filed on September 30, 2016, the entire contents of which are incorporated herein by reference. In the following, the invention will be explained based on examples with reference to the drawings. However, the present invention is not limited to the examples, and the various numerical values and materials in the examples are illustrative. Note that the description is made in the following order. 1. For an imaging element according to an embodiment of the present invention, a stacked imaging element according to an embodiment of the present invention, a solid-state imaging device according to the first or second embodiment of the present invention, and an embodiment of the present invention General description of driving method for solid-state imaging device 2. Example 1 (imaging element according to one embodiment of the present invention, stacked imaging element according to one embodiment of the present invention, and Solid-state imaging device) 3. Example 2 (modification of Example 1) 4. Example 3 (modification of Examples 1 and 2) 5. Example 4 (modification of Examples 1 to 3, imaging element with transfer control electrodes) 6. Example 5 (Modifications of Examples 1 to 4, Imaging Elements with Charge Ejecting Electrodes) 7. Example 6 (Modifications of Examples 1 to 5, Imaging Elements with Charge Storage Electrode Segments) 8. Others < For an embodiment according to the present invention of the imaging element, the stacked imaging element according to an embodiment of the present invention, the solid-state imaging device according to the first or second embodiment of the present invention, and the driving method for a solid-state imaging device according to an embodiment of the present invention General Description> In an imaging element or the like according to an embodiment of the present invention, the imaging element may further include a semiconductor substrate, and a photoelectric conversion unit may be disposed above the semiconductor substrate. Note that a first electrode, a charge storage electrode, and a second electrode are connected to a drive circuit described later. A second electrode located in a light incident side can be generally provided to a plurality of imaging elements. That is, the second electrode can be configured as a so-called solid electrode. The photoelectric conversion layer may generally be provided to a plurality of these imaging elements. That is, one layer of the photoelectric conversion layer may be formed for a plurality of these imaging elements or may be formed for each imaging element. Furthermore, in an imaging element or the like including the various exemplary forms and configurations set forth above, in accordance with one embodiment of the present invention, a first electrode may be formed to extend into an opening portion provided to the insulating layer to connected to the photoelectric conversion layer. Alternatively, the photoelectric conversion layer may be formed to extend in the opening portion provided to the insulating layer to be connected to the first electrode. In this case, the imaging element or the like may be configured to have a form in which an edge of a top surface of a first electrode is covered with an insulating layer, the first electrode is exposed on a bottom surface of the opening portion, and When a surface of the insulating layer in contact with the top surface of the first electrode is bounded by a first surface and a surface of the insulating layer in contact with a portion of the photoelectric conversion layer (which faces the charge storage electrode) is bounded by a second surface, A side surface of the opening portion has a slope extending from the first surface toward the second surface. Furthermore, the imaging element or the like may be configured to have a form in which the side surface of the opening portion having the slope extending from the first surface toward the second surface is located in a charge storage electrode side. In addition, the form described above includes a form in which another layer is formed between the photoelectric conversion layer and the first electrode (for example, in which a material layer suitable for charge storage is formed between the photoelectric conversion layer and the first electrode a form between). Furthermore, in an imaging element or the like comprising the various exemplary forms and configurations set forth above in accordance with one embodiment of the present invention, the imaging element or the like may have a configuration in which the imaging element further comprises A control unit disposed on the semiconductor substrate and having a drive circuit, the first electrode and the charge storage electrode are connected to the drive circuit, and in a charge storage period, from the drive circuit, a potential V 11 applied to the first electrode and a potential V 12 It is applied to the charge storage electrode, so that the charge is stored in the photoelectric conversion layer, and in a charge transfer cycle, the self-driving circuit changes a potential V twenty one applied to the first electrode and a potential V twenty two Applied to the charge storage electrode, so that the charge stored in the photoelectric conversion layer is read out to the control unit through the first electrode. Here, in the case where the potential of the first electrode is higher than the potential of the second electrode, V 12 ≥ V 11 and V twenty two < V twenty one , and in the case where the potential of the first electrode is lower than the potential of the second electrode, V 12 ≤ V 11 and V twenty two > V twenty one . Furthermore, in an imaging element or the like comprising the various exemplary forms and configurations set forth above in accordance with one embodiment of the present invention, the imaging element or the like may be configured to have a form that further includes A transfer control electrode (charge transfer electrode) disposed between the first electrode and the charge storage electrode, separable from the first electrode and the charge storage electrode, and configured to face the photoelectric conversion layer through the insulating layer. Note that, for convenience of description, an imaging element or the like having this form according to an embodiment of the present invention will be referred to as an "imaging element having a transfer control electrode or the like according to an embodiment of the present invention". Additionally, in an imaging element or the like having a transfer control electrode according to an embodiment of the present invention, the imaging element or the like may have a configuration that includes a control unit provided to a semiconductor The substrate also includes a drive circuit. During a charge storage period, the first electrode, the charge storage electrode and the transfer control electrode are connected to the drive circuit. Self-driving circuit, will be a potential V 11 applied to the first electrode, a potential V 12 applied to the charge storage electrode and a potential V 13 Applied to the transfer control electrode, so that charges are stored in the photoelectric conversion layer. In addition, in a charge transfer cycle, the self-driving circuit converts a potential V twenty one applied to the first electrode, a potential V twenty two applied to the charge storage electrode and a potential V twenty three Applied to the transfer control electrode, the charges stored in the photoelectric conversion layer are read out to the control unit through the first electrode. Here, in the case where one of the potential of the first electrode is higher than that of the second electrode, V 12 > V 13 and V twenty two ≤ V twenty three ≤ V twenty one , and in the case where the potential of the first electrode is lower than the potential of the second electrode, V 12 < V 13 and V twenty two ≥ V twenty three ≥ V twenty one . Furthermore, in an imaging element or the like comprising the various exemplary forms and configurations set forth above in accordance with one embodiment of the present invention, the imaging element or the like may be configured to have a form that further includes A charge exit electrode connected to the photoelectric conversion layer and configured to be separated from the first electrode and the charge storage electrode. Note that, for convenience of description, an imaging element having such a form or the like according to an embodiment of the present invention is referred to as an "imaging element having a charge emitting electrode or the like according to an embodiment of the present invention". Furthermore, in an imaging element or the like having a charge emitting electrode in accordance with one embodiment of the present invention, the imaging element or the like may be configured to have a form in which the charge emitting electrode is configured to surround the first electrode and charge storage electrodes (ie, in the shape of a frame). The charge extraction electrodes may be shared (commonly used) by a plurality of imaging elements. In addition, in this case, the imaging element may be configured in a form in which the photoelectric conversion layer extends in a second opening portion provided to the insulating layer to be connected to the charge exit electrode, a top surface of one of the charge exit electrodes An edge is covered with an insulating layer, the charge emitting electrode is exposed on a bottom surface of the second opening portion, and when a surface of the insulating layer in contact with the top surface of the charge emitting electrode is defined by a third surface and the insulating layer is connected to the photoelectric When a portion of the conversion layer (which faces the charge storage electrode) contacts a surface defined by a second surface, a side surface of the second opening portion has a slope extending from the third surface toward the second surface. Furthermore, in an imaging element or the like having a charge emitting electrode according to an embodiment of the present invention, the imaging element or the like may have a configuration in which it further includes a control unit configured to a The semiconductor substrate includes a drive circuit, the first electrode, the charge storage electrode and the charge emitting electrode are connected to the drive circuit, and in a charge storage period, from the drive circuit, a potential V 11 applied to the first electrode, a potential V 12 applied to the charge storage electrode and a potential V 14 Applied to the charge emitting electrode, so that the charge is stored in the photoelectric conversion layer. In addition, in a charge transfer cycle, the self-driving circuit converts a potential V twenty one applied to the first electrode, a potential V twenty two applied to the charge storage electrode and a potential V twenty four It is applied to the charge emitting electrode, so that the charge stored in the photoelectric conversion layer is read out to the control unit through the first electrode. Here, in the case where one of the potential of the first electrode is higher than that of the second electrode, V 14 > V 11 and V twenty four < V twenty one , and in the case where the potential of the first electrode is lower than the potential of the second electrode, V 14 < V 11 and V twenty four > V twenty one . Furthermore, in an imaging element or the like including the various exemplary forms and configurations set forth above in accordance with an embodiment of the present invention, the imaging element or the like may be configured in a form in which a set of charge storage electrodes The state has a plurality of charge storage electrode segments. Note that, for convenience of description, an imaging element having this form or the like according to an embodiment of the present invention will be referred to as an "imaging element having a plurality of charge storage electrode segments according to an embodiment of the present invention or the like" . The number of charge storage electrode segments may be two or more. Furthermore, in an imaging element or the like having a plurality of charge storage electrode segments according to one embodiment of the present invention, the imaging element or the like may be configured to have a form in which one of the first electrodes has a potential higher than In the case of a potential of the second electrode, in a charge transfer period, a potential applied to the segment of the charge storage electrode located closest to the first electrode is higher than that applied to the segment located farthest from the first electrode A potential of the charge storage electrode segment at the location. Also in the case where the potential of the first electrode is lower than the potential of the second electrode, in the charge transfer period, the potential applied to the segment of the charge storage electrode located at the position closest to the first electrode is lower than the potential applied to the segment located at the position closest to the first electrode. The potential of the charge storage electrode segment at the position furthest from the first electrode. In an imaging element or the like comprising the various exemplary forms and configurations set forth above in accordance with an embodiment of the present invention, the imaging element or the like may have a configuration in which at least one of the components constituting a control unit A floating diffusion layer and an amplifying transistor are disposed on a semiconductor substrate, and the first electrode is connected to the floating diffusion layer and a gate portion of the amplifying transistor, in this case, a reset transistor and a selection transistor constituting a control unit The transistor is further disposed to the semiconductor substrate, the floating diffusion layer is connected to a source/drain region of the reset transistor, and a source/drain region of the amplifying transistor is connected to a source/drain of the select transistor and the other source/drain region of the select transistor is connected to a signal line. Furthermore, in an imaging element or the like including the various exemplary forms and configurations set forth above in accordance with one embodiment of the present invention, the imaging element or the like may be configured to have a charge storage electrode that is larger than the first electrode a form. When the area of the charge storage electrode is reduced by S 1 ' denotes and the area of the first electrode is denoted by S 1 In the representation, although not limited to this, it is preferable to satisfy the following relationship. 4 ≤ S 1 '/S 1 Furthermore, in an imaging element or the like including the various exemplary forms and configurations set forth above, the imaging element or the like may be configured to have light in which light is incident from a second electrode side in accordance with one embodiment of the present invention And a light shielding layer is formed in a form on a light incident side of the second electrode. Alternatively, the imaging element or the like can be configured to have a pattern in which light is incident from the side of a second electrode and the light is not incident on the first electrode (in some cases, the first electrode and the transfer control electrode). a form. In this case, the imaging element or the like may have a configuration in which a light shielding layer is formed over the first electrode (in some cases, the first electrode and the transfer control electrode) as one of the second electrodes a light incident side. The imaging element or the like may have a configuration in which an on-wafer microlens is disposed over the charge storage electrode and the second electrode, and light incident on the on-wafer microlens is collected in the charge storage electrode. The light shielding layer may be disposed over the light incident side surface of the second electrode or may be disposed on the light incident side surface of the second electrode. In some cases, a light shielding layer may be formed in the second electrode. As a material constituting the light shielding layer, chromium (Cr), copper (Cu), aluminum (Al), tungsten (W), and a resin that does not transmit light (for example, a polyimide resin) can be exemplified. As an imaging element according to an embodiment of the present invention, specifically, a photoelectric conversion layer that is sensitive to blue and includes a photoelectric conversion layer that absorbs blue light (light having a wavelength range of 425 nm to 495 nm) can be exemplified (for convenience of description) , referred to as a "first-type blue photoelectric conversion layer"), an imaging element (for convenience of description, referred to as a "first-type blue imaging element"), sensitive to green and including absorbing green light (with 495 nm Light in a wavelength range to 570 nm), a photoelectric conversion layer (for convenience of description, referred to as a "first type green photoelectric conversion layer"), an imaging element (for convenience of description, referred to as a "first type green photoelectric conversion layer") Imaging element”) and a photoelectric conversion layer that is sensitive to red and includes a photoelectric conversion layer that absorbs red light (light having a wavelength range of 620 nm to 750 nm) (referred to as a “first type red photoelectric conversion layer” for convenience of description) An imaging element (for convenience of description, referred to as a "first type red imaging element"). In addition, as an imaging element without charge storage electrodes in the related art, an imaging element that is sensitive to blue is referred to as a "second-type blue imaging element" for the convenience of description; for the convenience of description, it is sensitive to green One imaging element is referred to as a "second-type green imaging element"; for convenience of description, the imaging element that is sensitive to red is referred to as a "second-type red imaging element"; for convenience of description, a second-type blue imaging element will be formed. A photoelectric conversion layer of the color imaging element is referred to as a "second type blue photoelectric conversion layer"; for convenience of description, a photoelectric conversion layer constituting the second type green imaging element is referred to as a "second type green photoelectric conversion layer"”; and for the convenience of description, a photoelectric conversion layer constituting the second-type red imaging element is referred to as a “second-type red photoelectric conversion layer”. A stacked imaging element according to an embodiment of the present invention includes at least one imaging element (photoelectric conversion element) according to an embodiment of the present invention. That is, stacked imaging elements may include, but are not limited to, the following non-limiting configurations and structures. [A] A configuration and structure in which a first type of blue photoelectric conversion unit, a first type of green photoelectric conversion unit, and a first type of red photoelectric conversion unit are stacked in a vertical direction, and the first type of blue imaging element, the first type of blue photoelectric conversion unit, the The respective control units of a type of green imaging element and a first type of red imaging element are disposed in the semiconductor substrate. [B] A configuration and structure in which the first type blue photoelectric conversion unit and the first type green photoelectric conversion unit are stacked in a vertical direction, and the second type red photoelectric conversion layer is disposed on two of the first type photoelectric conversion units Below the layer, the respective control units of the first type of blue imaging element, the first type of green imaging element and the second type of red imaging element are disposed in the semiconductor substrate. [C] A configuration and structure, wherein the second type blue photoelectric conversion unit and the second type red photoelectric conversion unit are arranged below the first type green photoelectric conversion unit, and the first type green imaging element, the second type blue photoelectric conversion unit The respective control units of the imaging element and the second-type red imaging element are disposed in the semiconductor substrate. [D] A configuration and structure, wherein the second type green photoelectric conversion unit and the second type red photoelectric conversion unit are arranged below the first type blue photoelectric conversion unit, and the first type blue imaging element, the second type green photoelectric conversion unit The respective control units of the imaging element and the second-type red imaging element are disposed in the semiconductor substrate. Note that, preferably, the arrangement order of the photoelectric conversion units of the imaging element in the vertical direction is the order of the blue photoelectric conversion unit, the green photoelectric conversion unit and the red photoelectric conversion unit from the light incident direction, or the green photoelectric conversion unit from the light incident direction A sequence of photoelectric conversion units, blue photoelectric conversion units, and red photoelectric conversion units. This is because light having a shorter wavelength is absorbed more efficiently in the incident surface side. Since red light has the longest wavelength among the three colors of light, it is preferable that the red photoelectric conversion unit is located in the lowest layer when viewed from the light incident surface. A pixel is configured in a stacked structure of imaging elements. A first-type infrared photoelectric conversion unit may also be included. Here, a photoelectric conversion layer of the first type infrared photoelectric conversion unit is preferably configured with, for example, an organic material, and the photoelectric conversion layer is located in the lowest layer of the stack structure of the first type imaging element and It is arranged above the imaging element of the second type. In addition, a second-type infrared photoelectric conversion unit located below the first-type photoelectric conversion unit may also be included. For example, in the first type of imaging element, the first electrode is formed on an interlayer insulating layer provided on the semiconductor substrate. The imaging element formed in the semiconductor substrate can be configured as a back-illuminated type or a front-illuminated type. In the case where the photoelectric conversion layer is made of an organic material, the photoelectric conversion layer may be formed in any of the following non-limiting forms: (1) the photoelectric conversion layer is configured with a p-type organic semiconductor; (2) the photoelectric conversion layer The conversion layer is configured with an n-type organic semiconductor; (3) the photoelectric conversion layer is configured with a stacked structure of a p-type organic semiconductor layer/an n-type organic semiconductor layer; (for example, the photoelectric conversion layer is configured with a p-type organic semiconductor layer) Semiconductor layer/a mixed layer of a p-type organic semiconductor and an n-type organic semiconductor (bulk heterostructure)/a stacked structure of a n-type organic semiconductor layer. The photoelectric conversion layer is configured with a p-type organic semiconductor layer/a p-type organic semiconductor layer A stacked structure of a mixed layer (bulk heterostructure) of an n-type organic semiconductor and an n-type organic semiconductor. The photoelectric conversion layer is configured with an n-type organic semiconductor layer/a mixture of a p-type organic semiconductor and an n-type organic semiconductor (4) The photoelectric conversion layer is configured with a mixed layer of a p-type organic semiconductor and an n-type organic semiconductor (bulk heterostructure). Herein, the stacking order can be configured to be arbitrarily changed. As a p-type organic semiconductor, one or more of the following non-limiting materials can be used: naphthalene derivatives, anthracene derivatives, phenanthrene derivatives, pyrene derivatives, perylene derivatives, fused tetraphenyl derivatives, fused pentaphenyl derivatives Derivatives, quinacridone derivatives, thiophene derivatives, thienothiophene derivatives, benzothiophene derivatives, benzo-thienobenzothiophene derivatives, triallylamine derivatives, carbazole derivatives, perylene Derivatives, licene derivatives, chrysene derivatives, fluoranthene derivatives, phthalocyanin derivatives, subphthalocyanin derivatives, subporphyrazine derivatives, with heterocyclic compounds as ligands Monomeric metal complexes, polythiophene derivatives, polybenzothiadiazole derivatives, polyfluorene derivatives and the like. As an n-type organic semiconductor, one or more of the following non-limiting materials can be used: fullerenes and fullerene derivatives <for example, fullerenes such as C60, C70 and C74 (higher order fullerenes ), embedded fullerenes or the like, or fullerene derivatives (for example, fullerene fluorides, PCBM fullerene compounds, fullerene multimers or the like)>, organic semiconductors (which have a ratio of HOMO and LUMO of p-type organic semiconductors (large (deep) HOMO and LUMO) and transparent inorganic metal oxides. An n-type organic semiconductor may include, but is not limited to, one or more of the following: organic molecules or organometallic complexes (which have heterocyclic compounds containing nitrogen, oxygen, or sulfur atoms as part of the molecular backbone), For example, pyridine derivatives, pyrazine derivatives, pyrimidine derivatives, triazine derivatives, quinoline derivatives, quinoxaline derivatives, isoquinoline derivatives, acridine derivatives, phenazine derivatives, phenanthrene derivatives Line derivatives, tetrazole derivatives, pyrazole derivatives, imidazole derivatives, thiazole derivatives, oxazole derivatives, imidazole derivatives, benzimidazole derivatives, benzotriazole derivatives, benzoxazole derivatives , benzoxazole derivatives, carbazole derivatives, benzofuran derivatives, dibenzofuran derivatives, porphyrazine derivatives, poly-p-styrene derivatives, polybenzothiadiazole derivatives , polyfluorene derivatives or the like, and subphthalocyanin derivatives. A group or the like contained in the fullerene derivative may include, but is not limited to, one or more of the following: halogen atoms; linear, branched or cyclic alkyl groups or phenyl groups; Groups of condensed cyclic aromatic compounds; groups with monohalides; partially fluoroalkyl groups; perfluorinated alkyl groups; silylalkyl groups; silylalkoxy groups; Arylsilyl Groups; Arylsulfanyl Groups; Alkylsulfanyl Groups; Aryl Sulfonyl Groups; Alkyl Sulfonyl Groups; group; amino group; alkylamino group; arylamino group; hydroxyl group; alkoxy group; acylamino group; acyloxy group; carbonyl group; carboxyl group group; carboxymethyl kiso amide group; alkoxycarbonyl group; acyl group; sulfonyl group; cyano group; nitro group; with a chalcogenide the group; the phosphine group; the phosphate group; and its derivatives. The photoelectric conversion layer (in some cases, referred to as an "organic photoelectric conversion layer") is configured with an organic material in a thickness, although not limited thereto, the organic material may include the following non-limiting range: 1 × 10 -8 m to 5×10 -7 m, preferably 2.5×10 -8 m to 3 × 10 -7 A range of one m, preferably 2.5 × 10 -8 m to 2 × 10 -7 range of one m and excellently 1 × 10 -7 m to 1.8 × 10 -7 A range of m. Note that in many cases, organic semiconductors are classified into a p-type and an n-type. Herein, p-type means that holes can be easily transported, and n-type means that electrons can be easily transported. These types are not to be interpreted restrictively. A material constituting an organic photoelectric conversion layer for photoelectric conversion of light having a green wavelength may include, but is not limited to, one or more of the following: rhodamine-based dyes, melashin-based ( merashianin) dyes, quinacridone derivatives, subphthalocyanin dyes (subphthalocyanin derivatives) and the like. A material constituting an organic photoelectric conversion layer for photoelectric conversion of light having a blue wavelength may include, but is not limited to, one or more of the following: coumaric acid dyes, tris-8-hydroxyquinoline aluminum (Alq3), melashin-based dyes and the like. A material for an organic photoelectric conversion layer for photoelectric conversion of light having a red wavelength may include, but is not limited to, one or more of the following: phthalocyanin dyes, subphthalocyanin dyes (subphthalocyanin-derived dyes) ) and the like. An inorganic material of the photoelectric conversion layer may include, but is not limited to, one or more of the following: crystalline silicon, amorphous silicon, microcrystalline silicon, crystalline selenium, amorphous selenium compound semiconductor; a chalcopyrite-based compound , such as CIGS (CuInGaSe), CIS (CuInSe 2 ), CuInS 2 , CuAlS 2 , CuAlSe 2 , CuGaS 2 , CuGaSe 2 , AgAlS 2 , AgAlSe 2 , AgInS 2 or AgInSe 2 ; a III-V compound such as GaAs, InP, AlGaAs, InGaP, AlGaInP or InGaAsP, CdSe, CdS, In 2 Se 3 , In 2 S 3 , Bi 2 Se 3 , Bi 2 S 3 , ZnSe, ZnS, PbSe and PbS. Quantum dots made of these materials can be used for photoelectric conversion layers. Alternatively, the photoelectric conversion layer may be configured to have a stacked layer structure of a lower semiconductor layer and an upper photoelectric conversion layer. In this way, by providing the lower semiconductor layer, it is possible to prevent recoupling during the charge storage period, making it possible to increase the transfer efficiency of the charge stored in the photoelectric conversion layer to the first electrode, and to suppress the occurrence of dark current. The material constituting the upper photoelectric conversion layer may be appropriately selected among the various types of materials constituting the photoelectric conversion layer described above. On the other hand, as the material constituting the lower semiconductor layer, it is preferable to use a material having a large band gap value (for example, a band gap value of 3.0 eV or more) and having a higher mobility than the material constituting the photoelectric conversion layer One mobility one material. Specifically, non-limiting examples of the material may include one or more of the following: oxide semiconductor materials, such as IGZO; transition metal grain chalcogenides; silicon carbide; diamond; tubes; and organic semiconductor materials of condensed polycyclic hydrocarbons, condensed heterocyclic compounds, or the like. As the material constituting the lower semiconductor layer, in the case where the charges to be stored are electrons, exemplary materials include, but are not limited to, materials having an ionization potential higher than that of the material constituting the photoelectric conversion layer; and In the case where the charges to be stored are holes, exemplary materials include, but are not limited to, materials having an electron affinity smaller than that of the material constituting the photoelectric conversion layer. Preferably, the impurity concentration in the material constituting the lower semiconductor layer is 1 × 10 18 cm -3 or smaller. The lower semiconductor layer may have a single-layer configuration or may be a multi-layer configuration. Additionally, the material constituting the lower semiconductor layer over the charge storage electrode and the material constituting the lower semiconductor layer over the first electrode may be configured to be different from each other. According to the solid-state imaging device in the first or second embodiment of the present invention, a single-panel color solid-state imaging device can be configured. In the solid-state imaging device having a stack-type imaging element according to the second embodiment of the present invention, unlike having an imaging element in a Bayer array (that is, blue light is not performed by using a color filter) Spectral separation of color, green, and red light) A solid-state imaging device that configures one pixel by stacking imaging elements sensitive to light having a plurality of types of wavelengths in the direction of light incidence in one pixel, it is possible to improve the Sensitivity and pixel density per unit volume. In addition, since an organic material has a high absorption coefficient, the organic photoelectric conversion layer can be configured to have a thickness smaller than that of a related art Si-based photoelectric conversion layer, and reduce light leakage from adjacent pixels or to a Limits on the angle of incidence of light. Furthermore, in the Si-based imaging element of the related art, an interpolation process is performed among three color pixels, so that false colors occur so as to generate a color signal. However, in the solid-state imaging device having a stack-type imaging element according to the second embodiment of the present invention, the occurrence of false colors is suppressed. Since the organic photoelectric conversion layer itself has a function as a color filter, color separation can be obtained without disposing a color filter. On the other hand, in the solid-state imaging device in which the color filter is used according to the first embodiment of the present invention, the requirement for spectral separation characteristics for blue light, green light, and red light can be alleviated, and a high level of productivity. An array of imaging elements in the solid-state imaging device according to the first embodiment of the present invention includes, but is not limited to, one or more of the following: a Bayer array, an inter-row arrangement, a G-strip RB checkerboard array, A G-striped RB complete checkerboard array, a checkerboard complementary color array, a stripe array, a diagonal stripe configuration, a primary color difference array, a field color difference sequential array, a frame color difference sequential array, a MOS type array, a Improved MOS type array, one frame staggered array and one field staggered array. Here, one pixel (or sub-pixel) is configured with one imaging element. A plurality of pixels are configured in a pixel area in which a plurality of imaging elements according to an embodiment of the present invention or a plurality of stacked imaging elements according to an embodiment of the present invention are arranged, and the plurality of pixels are regularly arranged into a two dimensional array shape. The pixel area is typically configured to include an active pixel area that actually receives light, amplifies the signal charge generated through photoelectric conversion, and reads the signal charge out to a driver circuit and a black reference pixel area for output Optical black serves as a reference for a black level. The black reference pixel area is usually arranged in the outer periphery of the effective pixel area. In an imaging element, or the like, including the various exemplary forms and configurations set forth above, in accordance with one embodiment of the present invention, light is illuminated and photoelectric conversion occurs in a photoelectric conversion layer such that holes and electrons are separated into carriers son. Then, the electrode in which holes are extracted is defined as an anode, and the electrode in which electrons are extracted is defined as a cathode. There may be a form in which the first electrode constitutes the anode and the second electrode constitutes the cathode. Conversely, there can also be a form in which the first electrode constitutes the cathode and the second electrode constitutes the anode. In the case of forming a stacked imaging element, the first electrode, the charge storage electrode, the transfer control electrode, the charge exit electrode, and the second electrode may be configured to be made of a transparent conductive material. Note that, in some cases, the first electrode, charge storage electrode, transfer control electrode, and charge ejection electrode are collectively referred to as a "first electrode or the like." Alternatively, in situations in which an imaging element or the like according to an embodiment of the present invention is configured in a plane (eg, as in a Bayer array), the second electrode may be configured to be electrically conductive from a transparent material, and the first electrode can be configured to be made of a metallic material. In this case, in particular, the second electrode at the light incident side can be configured to be made of a transparent conductive material, and the first electrode and the like can be configured to be made of, for example, Al- Made of Nd (alloy of aluminum and neodymium) or ASC (alloy of aluminum, samarium and copper). Note that, in some cases, an electrode made of a transparent conductive material is referred to as a "transparent electrode". The band gap energy of the transparent conductive material is 2.5 eV or more preferably 3.1 eV or more. As a transparent conductive material constituting the transparent electrode, a conductive metal oxide can be exemplified; the conductive oxide can include but is not limited to one or more of the following: an indium oxide, an indium tin oxide (ITO—Sn doped) In 2 O 3 , comprising a crystalline ITO and an amorphous ITO), an indium zinc oxide (IZO) formed by adding indium as a dopant to a zinc oxide, an indium zinc oxide (IZO) formed by adding indium as a dopant to an oxide an indium gallium oxide (IGO) formed from gallium, an indium gallium zinc oxide (IGZO—In-GaZnO) formed by adding indium and gallium as dopants to a zinc oxide 4 ), an indium tin zinc oxide (ITZO) formed by adding tin as a dopant to a zinc oxide, an IFO (F-doped In 2 O 3 ), a tin oxide (SnO 2 ), an ATO (Sb-doped SnO 2 ), one FTO (F-doped SnO 2 ), a zinc oxide (comprising ZnO doped with other elements), an aluminum oxide zinc (AZO) formed by adding aluminum as a dopant to a zinc oxide, by adding gallium as a dopant A gallium zinc oxide (GZO), a titanium oxide (TiO 2 ), a titanium niobium oxide (TNO) formed by adding niobium as a dopant to a titanium oxide, an antimony oxide, a spinel oxide, and a YbFe oxide 2 O 4 A structure of an oxide. Alternatively, one or more of the following may be exemplified as a parent layer for a transparent electrode: a gallium oxide, a titanium oxide, a niobium oxide, a nickel oxide, or the like. As a thickness of the transparent electrode, an example of a non-limiting range may be 2 × 10 -8 m to 2 × 10 -7 m, preferably 3 × 10 -8 m to 1 × 10 -7 A range of m. In the case where transparency is necessary for the first electrode, from the viewpoint of simplifying the manufacturing process, preferably the charge exit electrode is also made of a transparent conductive material. In situations where transparency is not necessary, a conductive material that preferably constitutes a positive electrode that functions as an electrode for emitting holes has a high work function (eg, ϕ = 4.5 eV to 5.5 eV) a conductive material. Specifically, the conductive material may include, but is not limited to, one or more of the following: gold (Au), silver (Ag), chromium (Cr), nickel (Ni), palladium (Pd), platinum (Pt) , iron (Fe), iridium (Ir), germanium (Ge), osmium (Os), rhenium (Re) or tellurium (Te). On the other hand, a conductive material preferably constituting a negative electrode having a function as an electrode for emitting electrons is a conductive material having a low work function (eg, ϕ = 3.5 eV to 4.5 eV). Specifically, the conductive material may include, but is not limited to, one or more of the following: an alkali metal (eg, Li, Na, K, or the like) and a fluoride or an oxide thereof, an alkaline earth metal (for example, Mg, Ca, or the like) and a fluoride or an oxide thereof, aluminum (Al), zinc (Zn), tin (Sn), thallium (Tl), monosodium potassium alloy, monolithium aluminum Alloy, a magnesium-silver alloy, indium, a rare earth metal such as ytterbium, or an alloy thereof. Materials that make up the anode or cathode include, but are not limited to, one or more metals such as platinum (Pt), gold (Au), palladium (Pd), chromium (Cr), nickel (Ni), aluminum (Al), silver (Ag) , tantalum (Ta), tungsten (W), copper (Cu), titanium (Ti), indium (In), tin (Sn), iron (Fe), cobalt (Co) and molybdenum (Mo), containing these metals Alloys of atoms, conductive particles made of such metals, conductive particles of alloys containing such metals, or conductive materials (such as polysilicon with impurities, carbon-based materials, oxide semiconductors, carbon nanotubes, and graphene) , and a stack of layers containing these atoms can be used. In addition, the materials constituting the anode or cathode include, but are not limited to, one or more of the following: an organic material (conductive polymer), such as poly(3,4-ethylenedioxythiophene)/polystyrenesulfonic acid[ PEDOT/PSS]. In addition, a paste or ink obtained by mixing a conductive material with a binder (polymer), a cured material can be used as an electrode. As a film forming method for the first electrode or the like or the second electrode (an anode or a cathode), a dry method or a wet method can be used. Examples of a dry method include, but are not limited to, a physical vapor deposition (PVD) method and a chemical vapor deposition (CVD) method. Examples of a film forming method using the principle of the PVD method include, but are not limited to: a vacuum vapor deposition method using resistance heating or high-frequency heating, an EB (electron beam) vapor deposition method, various sputtering methods (a magnetic Controlled sputtering method, an RF-DC coupling type bias sputtering method, an ECR sputtering method, a target-oriented sputtering method and a high frequency sputtering method), an ion plating method, a laser ablation method, A molecular beam epitaxy method and a laser transfer method. Additionally, examples of a CVD method include, but are not limited to, a plasma CVD method, a thermal CVD method, a metal organic (MO) CVD method, and a photo CVD method. On the other hand, examples of a wet method include, but are not limited to, an electrolytic plating method or an electroless plating method, a spin coating method, an inkjet method, a spraying method, a stamping method, a microcontact printing method, A flexographic printing method, a lithographic printing method, a gravure printing method, a dip coating method and the like. Examples of a patterning method include, but are not limited to, chemical etching (such as shadow masking, laser transfer, or photolithography) and physical etching using ultraviolet light, lasers, or the like. Planarization techniques for the first electrode or the like or the second electrode may include, but are not limited to, a laser planarization method, a reflow method, a chemical mechanical polishing (CMP) method, and the like. The insulating layer may comprise one or more of the following non-limiting materials: In addition to inorganic insulating materials exemplified as metal oxide high-k insulating materials, such as a silicon oxide based material; a silicon nitride (SiN Y ); and an alumina (Al 2 O 3 ), such as polymethyl methacrylate (PMMA); polyvinyl phenol (PVP); polyvinyl alcohol (PVA); polyimide; polycarbonate (PC); polyethylene terephthalate (PET) ; polystyrene; monosilanol derivatives (silane coupling agents, such as N-2 (aminoethyl) 3-aminopropyltriethoxysilane (AEAPTMS), 3-mercaptopropyltrimethoxysilane (MPTMS) or octadecyltrichlorosilane (OTS); novolac-type phenolic resin; a fluorine-based resin; and organic insulating materials (organic polymers), exemplified by linear hydrocarbons in which One end has a functional group capable of bonding to a control electrode (such as octadecyl thiol or dodecyl isocyanate), and a combination thereof can be used. Note that as a silica-based material, non-limiting examples include but Not limited to: a silicon oxide (SiO X ), BPSG, PSG, BSG, AsSG, PbSG, a silicon oxynitride (SiON), a SOG (spin on glass), and a low dielectric constant material (eg, polyaryl ether, cyclic perfluorocarbon polymer compound and benzocyclobutene, a cyclic fluororesin, polytetrafluoroethylene, an aryl ether fluoride, a polyimide fluoride, an amorphous carbon and an organic SOG). Materials constituting various interlayer insulating layers or insulating films can also be appropriately selected from the aforementioned materials. The configuration and structure of the floating diffusion layer, the amplification transistor, the reset transistor and the selection transistor constituting the control unit can be formed to be similar to the floating diffusion layer, the amplification transistor, the reset transistor and the selection transistor in the related art. Configuration and structure of crystals. The driver circuit may also be formed in a well-known configuration and structure. The first electrode is connected to the floating diffusion layer and the gate portion of the amplifying transistor, and it is therefore desirable that a contact hole portion be formed for between the first electrode and the floating diffusion layer and between the first electrode and the gate portion of the amplifying transistor connection between. The material constituting the contact hole portion may include, but is not limited to, one or more of the following: polysilicon doped with impurities, a refractory metal or metal silicide (such as tungsten, Ti, Pt, Pd, Cu, TiW, TiN, TiNW, WSi 2 and MoSi 2 ) and a stack of layers made of these materials (for example, Ti/TiN/W). A first carrier blocking layer may be disposed between the organic photoelectric conversion layer and the first electrode, and a second carrier blocking layer may be disposed between the organic photoelectric conversion layer and the second electrode. In addition, a first charge injection layer may be disposed between the first carrier blocking layer and the first electrode, and a second charge injection layer may be disposed between the second carrier blocking layer and the second electrode. Materials constituting the electrode injection layer may include, but are not limited to, one or more of the following: alkali metals such as lithium (Li), sodium (Na), and potassium (K), their fluorides, their oxides, alkaline earths Metals such as magnesium (Mg) and calcium (Ca), their fluorides and their oxides. A method for forming the various organic layers may include, but is not limited to, one or more of the following: a dry film formation method and a wet film formation method. An example of a dry film formation method includes, but is not limited to, one or more of the following: a resistance heating or high frequency heating method, a vacuum vapor deposition method using electron beam heating, a flash vapor deposition method, a A plasma vapor deposition method, an EB vapor deposition method, various sputtering methods (a 2-pole sputtering method, a DC sputtering method, a DC magnetron sputtering method, a high-frequency sputtering method, a magnetic Controlled sputtering method, an RF-DC coupling type bias sputtering method, an ECR sputtering method, a target-oriented sputtering method, a high frequency sputtering method and an ion beam sputtering), Direct Current (DC) method, an RF method, a multi-cathode method, an activation reaction method, an electric field vapor deposition method, various ion plating methods (such as a high frequency ion plating method and a reactive ion plating method), a laser ablation method, a Molecular beam epitaxy method, a laser transfer method and a molecular beam epitaxy (MBE) method. In addition, an example of a CVD method includes, but is not limited to, a plasma CVD method, a thermal CVD method, a MOCVD method, and an optical CVD method. On the other hand, examples of a wet method include, but are not limited to: a spin coating method; an immersion method; a casting method; a microcontact printing method; a drop casting method; Ink printing method, a lithographic printing method, a gravure printing method, and a flexographic printing method; a stamping method; a spray method; and various coating methods such as an air knife coater method, a doctor blade coater method, a rod coater method, one knife coater method, one extrusion coater method, one reverse roll coater method, one transfer roll coater method, one gravure coater Methods, a kiss coater method, a cast coater method, a spray coating method, a slot hole coater method, and a calendar coater method. Note that in the coating method, one of solvents including, but not limited to, organic solvents having no polarity or having low polarity, such as toluene, chloroform, hexane, and ethanol, may be used. An example of a patterning method includes, but is not limited to, one or more of the following: chemical etching (such as shadow masking, laser transfer, or photolithography) and physical etching using ultraviolet light, laser, or the like . An example of a planarization technique for various types of organic layers includes, but is not limited to, one or more of the following: a laser planarization method, a reflow method, and the like. In the imaging element or solid-state imaging device as set forth above, if necessary, an on-chip microlens or a light shielding layer may be provided, and a driving circuit or a wire for driving the imaging element may be provided. If desired, a shutter for controlling the incidence of light on the imaging element may be provided, and the solid-state imaging device may include an optical cutoff filter according to its purpose. For example, in the case where a solid-state imaging device and a readout integrated circuit (ROIC) are stacked, a drive substrate in which the readout integrated circuit and a connection portion made of copper (Cu) are formed is allowed, and The imaging elements in which a connecting portion is formed are overlapped with each other so that the connecting portions are in contact with each other, and then stacking is performed by adhering the connecting portions. Alternatively, the connecting portions may be bonded to each other by using solder bumps or the like. [Example 1] Example 1 relates to an imaging element according to an embodiment of the present invention, a stacked imaging element according to an embodiment of the present invention, and a solid-state imaging device according to a second embodiment of the present invention. A schematic partial cross-sectional view of a portion of the imaging element and stacked imaging element of Example 1 is illustrated in FIG. 1A. Equivalent circuit diagrams of the imaging element and the stacked imaging element of Example 1 are illustrated in FIGS. 2 and 3 . A schematic layout diagram of the first electrode and the charge storage electrode constituting the imaging element of Example 1 and the transistor constituting a control unit is illustrated in FIG. 4 . The potential states of the components during one cycle of operation of the imaging element of Example 1 are illustrated in FIG. 5 . In addition, a schematic layout diagram of a first electrode and a charge storage electrode constituting the imaging element of Example 1 is illustrated in FIG. 6 . A schematic perspective view of a first electrode, a charge storage electrode, a second electrode, and a contact hole portion constituting the imaging element of Example 1 is illustrated in FIG. 7 . A conceptual diagram of the solid-state imaging device of Example 1 is illustrated in FIG. 8 . The imaging element of Example 1 (eg, the green imaging element described later) was configured to include a photoelectric conversion formed by stacking a first electrode 11 , a photoelectric conversion layer 15 , and a second electrode 16 unit. The photoelectric conversion unit is configured to include a charge storage electrode 12 configured to be separated from the first electrode 11 and configured to face the photoelectric conversion layer 15, with an insulating layer 82 interposed between the charge storage electrode and the photoelectric conversion layer 15. between the photoelectric conversion layers. As shown in FIGS. 1B-1D , insulating layer 82 may include multiple layers 82E and 82F. For example, there may be a first region of the insulating material 82 between the charge storage electrode 12 and the photoelectric conversion layer 15 , and there may be a first region of the insulating material 82 between the charge storage electrode 12 and the first electrode 11 . a second area. In some embodiments, the second region of insulating material includes a first insulating layer 82E (which includes insulating material) and a second insulating layer 82F (which includes insulating material), and the first insulating material 82F is stacked on the second on insulating material 82E. 1B-1D further illustrate various configurations with respect to insulating layer 82 (eg, configuration changes of layers 82E and 82F). Additionally, the stacked imaging element of Example 1 includes at least one imaging element of Example 1. In Example 1, the stacked imaging element includes one imaging element of Example 1. Furthermore, the solid-state imaging device of Example 1 includes a plurality of stacked imaging elements of Example 1. In addition, a semiconductor substrate (more specifically, a silicon semiconductor layer) 70 is further included, and the photoelectric conversion unit is disposed above the semiconductor substrate 70 . In addition, a control unit is further included, the control unit is disposed in the semiconductor substrate 70 and has a driving circuit to which the first electrode 11 is connected. Herein, the light incident side of the semiconductor substrate 70 is set to "above the semiconductor substrate", and the opposite side of the semiconductor substrate 70 is set to "below the semiconductor substrate". A wire layer 62 configured with a plurality of wires is disposed under the semiconductor substrate 70 . The semiconductor substrate 70 is provided with at least one floating diffusion layer FD constituting the control unit 1 and an amplifier transistor TR1 amp , and the first electrode 11 is connected to the floating diffusion layer FD 1 and amplifying transistor TR1 amp gate part. The semiconductor substrate 70 is further provided with a reset transistor TR1 constituting one of the control units rst and a selection transistor TR1 sel . Floating Diffusion Layer FD 1 Connect to reset transistor TR1 rst One of the source/drain regions, amplifying transistor TR1 amp One of the source/drain regions is connected to select transistor TR1 sel one source/drain region, and select transistor TR1 sel The other source/drain region is connected to a signal line VSL 1 . Amplifying transistor TR1 amp , reset transistor TR1 rst and select transistor TR1 sel A drive circuit is formed. Specifically, the imaging element and the stacked imaging element of Example 1 are a back-illuminated imaging element and a back-illuminated stacked imaging element and include a stacked structure of one of the following three imaging elements: Example 1, a first type green An imaging element (hereinafter, referred to as a "first imaging element"), which is sensitive to green and includes a first-type green photoelectric conversion layer that absorbs green light; a second-type blue imaging element (hereinafter a related art) , referred to as a "second imaging element"), which is blue-sensitive and includes a second-type blue photoelectric conversion layer that absorbs blue light; and a second-type red imaging element of the related art (hereinafter, referred to as A "third imaging element") that is red sensitive and includes a second type of red photoelectric conversion layer that absorbs red light. A red imaging element (third imaging element) and a blue imaging element (second imaging element) are provided in the semiconductor substrate 70, and the second imaging element is positioned closer to the light incident side than the third imaging element. In addition, the green imaging element (first imaging element) is disposed above the blue imaging element (second imaging element). One pixel is configured in a stacked structure of a first imaging element, a second imaging element and a third imaging element. Color filters are not provided. In the first imaging element, the first electrode 11 and the charge storage electrode 12 are formed on the interlayer insulating layer 81 to be separated from each other. The interlayer insulating layer 81 and the charge storage electrode 12 are covered with the insulating layer 82 . The photoelectric conversion layer 15 is formed on the insulating layer 82 , and the second electrode 16 is formed on the photoelectric conversion layer 15 . In the entire surface (including the second electrode 16 ), a protective layer 83 is formed, and an on-wafer microlens 90 is disposed on the protective layer 83 . The first electrode 11, the charge storage electrode 12 and the second electrode 16 are configured with transparent electrodes made of, for example, ITO. The photoelectric conversion layer 15 is configured with an organic material containing a well-known organic photoelectric conversion material that is sensitive to green (eg, but not limited to, a rhodamine-based dye, a melashin-based dye, and quinacridone). ) one layer. In addition, the photoelectric conversion layer 15 may further have a configuration including a material layer suitable for charge storage. That is, a material layer suitable for charge storage may be formed between the photoelectric conversion layer 15 and the first electrode 11 (for example, in the connection portion 67 ). The interlayer insulating layer 81, the insulating layer 82 and the protective layer 83 are configured with a well-known insulating material (for example, SiO 2 or SiN). The photoelectric conversion layer 15 and the first electrode 11 are connected to each other by the connection portion 67 provided to the insulating layer 82 . The photoelectric conversion layer 15 extends in the connection portion 67 . That is, the photoelectric conversion layer 15 extends in an opening portion 84 provided to the insulating layer 82 to be connected to the first electrode 11 . The charge storage electrode 12 is connected to the drive circuit. Specifically, the charge storage electrode 12 passes through a connection hole 66 , a pad portion 64 and a wire V formed in the interlayer insulating layer 81 . OA It is connected to a vertical driving circuit 112 constituting a driving unit. The charge storage electrode 12 is larger than the first electrode 11 . When the area of the charge storage electrode 12 is reduced by S 1 ' denotes and the area of the first electrode 11 is denoted by S 1 When expressed, although not limited to this, it is preferable to satisfy the following relationship, 4 ≤ S 1 '/S 1 Also in Example 1, although not limited to this, for example, the following relationship is set. S 1 '/S 1 = 8 An element isolation region 71 is formed in a first surface (front surface) 70A side of the semiconductor substrate 70 , and an oxide film 72 is formed on the first surface 70A of the semiconductor substrate 70 . In addition, the first surface side of the semiconductor substrate 70 is provided with a reset transistor TR1 constituting a control unit of the first imaging element rst , Amplifying transistor TR1 amp and select transistor TR1 sel and further provided with a first floating diffusion layer FD 1 . Reset transistor TR1 rst A gate portion 51, a channel forming region 51A, and source/drain regions 51B and 51C are configured. Reset transistor TR1 rst The gate portion 51 is connected to a reset line RST 1 , reset transistor TR1 rst A source/drain region 51C is also used as a first floating diffusion layer FD 1 , and its other source/drain region 51B is connected to a power supply V DD . The first electrode 11 passes through a connection hole 65 and a pad portion 63 provided in the interlayer insulating layer 81 , a contact hole portion 61 provided to the semiconductor substrate 70 and the interlayer insulating layer 76 , and a wire layer formed in the interlayer insulating layer 76 . 62 connected to reset transistor TR1 rst One of the source/drain regions 51C (the first floating diffusion layer FD 1 ). Amplifying transistor TR1 amp A gate portion 52, a channel forming region 52A, and source/drain regions 52B and 52C are configured. The gate portion 52 is connected to the first electrode 11 and the reset transistor TR1 through the wire layer 62 rst One of the source/drain regions 51C (the first floating diffusion layer FD 1 ). In addition, a source/drain region 52C and constitute the reset transistor TR1 rst The other source/drain region 51B shares the area and is connected to the power supply V DD . Select transistor TR1 sel A gate portion 53, a channel forming region 53A, and source/drain regions 53B and 53C are configured. The gate portion 53 is connected to the select line SEL 1 . In addition, a source/drain region 53B is formed with the amplification transistor TR1 amp The other source/drain region 52C shares the area, and the other source/drain region 53C is connected to the signal line (data output line) VSL 1 (117). The second imaging element includes an n-type semiconductor region 41 provided to the semiconductor substrate 70 as a photoelectric conversion layer. Transfer transistor TR2 trs The configuration has a gate portion 45 of a vertical type transistor extending to the n-type semiconductor region 41 and connected to a transfer gate line TG 2 . In addition, a second floating diffusion layer FD 2 The transfer transistor TR2 provided to the semiconductor substrate 70 trs A region 45C in the vicinity of the gate portion 45. The charges stored in the n-type semiconductor region 41 are read out to the second floating diffusion layer FD through a transfer channel formed along the gate portion 45 2 . In the second imaging element, in the first surface side of the semiconductor substrate 70, a reset transistor TR2, which is one of the control units constituting the second imaging element, is further provided rst , an amplifier transistor TR2 amp and a selection transistor TR2 sel . Reset transistor TR2 rst A gate portion, a channel forming region and source/drain regions are configured. Reset transistor TR2 rst The gate part is connected to the reset line RST 2 , reset transistor TR2 rst One of the source/drain regions is connected to the power supply V DD , and its other source/drain region is used as a second floating diffusion layer FD 2 . Amplifying transistor TR2 amp A gate portion, a channel forming region and source/drain regions are configured. The gate part is connected to the reset transistor TR2 rst the other source/drain region (the second floating diffusion layer FD 2 ). In addition, one of its source/drain regions and constitute the reset transistor TR2 rst The other source/drain region shares the area and is connected to the power supply V DD . Select transistor TR2 sel A gate portion, a channel forming region and source/drain regions are configured. The gate part is connected to the select line SEL 2 . In addition, one of its source/drain regions is connected to the amplifier transistor TR2 amp The other source/drain area shares the area, and the other source/drain area is connected to the signal line (data output line) VSL 2 . The third imaging element includes an n-type semiconductor region 43 provided to the semiconductor substrate 70 as a photoelectric conversion layer. Transfer transistor TR3 trs The gate portion 46 is connected to the transfer gate line TG 3 . In addition, a third floating diffusion layer FD 3 The transfer transistor TR3 provided to the semiconductor substrate 70 trs region 46C near gate portion 46. The charges stored in the n-type semiconductor region 43 are read out to the third floating diffusion layer FD through a transfer channel 46A formed along the gate portion 46 3 . In the third imaging element, in the first surface side of the semiconductor substrate 70, a reset transistor TR3, which is one of the control units constituting the third imaging element, is further provided rst , an amplifier transistor TR3 amp and a selection transistor TR3 sel . Reset transistor TR3 rst A gate portion, a channel forming region and source/drain regions are configured. Reset transistor TR3 rst The gate part is connected to the reset line RST 3 , reset transistor TR3 rst One source/drain region is connected to the power supply VDD, and the other source/drain region thereof is used as a third floating diffusion layer FD 3 . Amplifying transistor TR3 amp A gate portion, a channel forming region and source/drain regions are configured. The gate part is connected to reset transistor TR3 rst the other source/drain region (the third floating diffusion layer FD 3 ). In addition, one of its source/drain regions and constitute the reset transistor TR3 rst The other source/drain region shares the area and is connected to the power supply V DD . Select transistor TR3 sel A gate portion, a channel forming region and source/drain regions are configured. The gate part is connected to the select line SEL 3 . In addition, a source/drain region is formed with the amplifier transistor TR3 amp The other source/drain region shares the area, and the other source/drain region thereof is connected to the signal line (data output line) VSL 3 . reset line RST 1 , RST 2 and RST 3 , select line SEL 1 , SEL 2 and SEL 3 and transfer gate line TG 2 and TG 3 Connected to the vertical drive circuit 112 constituting the drive circuit, and the signal line (data output line) VSL 1 , VSL 2 and VSL 3 Connected to a row signal processing circuit 113 constituting a driving circuit. A p+ layer 44 is disposed between the n-type semiconductor region 43 and the surface 70A of the semiconductor substrate 70 to suppress the occurrence of dark current. A p+ layer 42 is formed between the n-type semiconductor region 41 and the n-type semiconductor region 43 , and a portion of the side surface of the n-type semiconductor region 43 is surrounded by the p+ layer 42 . A p+ layer 73 is formed in the rear surface 70B side of the semiconductor substrate 70, and a HfO 2 The film 74 and an insulating film 75 are formed in a portion of the inner side of the semiconductor substrate 70 in which the contact hole portion 61 will be formed by the p+ layer 73 . In the interlayer insulating layer 76, although wires are formed on a plurality of layers, illustration is omitted. The HfO2 film 74 is a film having a negative fixed charge, and by preparing this film, the occurrence of dark current can be suppressed. Note that instead of HfO 2 film, an aluminum oxide (Al 2 O 3 ) film, a zirconia (ZrO 2 ) film, a tantalum oxide (Ta 2 O 5 ) film, a titanium oxide (TiO 2 ) film, a lanthanum oxide (La 2 O 3 ) film, a kind of ammonium oxide (Pr 2 O 3 ) film, a cerium oxide (CeO 2 ) film, a neodymium oxide (Nd 2 O 3 ) film, a kind of iron oxide (Pm 2 O 3 ) film, a samarium oxide (Sm 2 O 3 ) film, a europium oxide (Eu 2 O 3 ) film, a kind of gadolinium oxide (Gd 2 O 3 ) film, a kind of titanium oxide (Tb 2 O 3 ) film, a dysprosium oxide (Dy 2 O 3 ) film, a type of ─ (Ho) oxide 2 O 3 ) film, a tin oxide (Tm 2 O 3 ) film, a ytterbium oxide (Yb 2 O 3 ) film, a tin oxide (Lu 2 O 3 ) film, a yttrium oxide (Y 2 O 3 ) film, a hafnium nitride film, an aluminum nitride film, a hafnium oxynitride film, or an aluminum nitride oxide film. As a film formation method for these films, a CVD method, a PVD method, and an ALD method can be exemplified. Hereinafter, the operation of the imaging element (first imaging element) of Example 1 will be explained with reference to FIG. 5 . Here, the potential of the first electrode 11 is set to be higher than the potential of the second electrode. That is, for example, when the first electrode 11 is set to a positive potential and the second electrode is set to a negative potential, electrons are read out to the floating diffusion layer through photoelectric conversion in the photoelectric conversion layer 15 . A similar operation is performed in other instances. Note that in a form in which holes are read out to the floating diffusion layer through photoelectric conversion in the photoelectric conversion layer 15 when the first electrode 11 is set to a negative potential and the second electrode is set to a positive potential, The levels of the potentials mentioned below can be set to the opposite. The reference numerals used in Figures 5, 20, and 21 in Example 4 are described later, and the reference numerals used in Figures 32 and 33 in Example 6, described later, are as follows. PA ... the potential of a point PA of the region of the photoelectric conversion layer 15 facing the charge storage electrode 12 or the potential of a point PA of the region of the photoelectric conversion layer 15 facing the charge storage electrode segment 12C; PB ... the surface of the photoelectric conversion layer 15 The potential of a point PB of a region located in a region in the middle between the charge storage electrode 12 and the first electrode 11, the potential of a point PB of a region of the photoelectric conversion layer 15 facing the transfer control electrode (charge transfer electrode) 13, or the photoelectric conversion The potential of a point PB of the region of the layer 15 facing the charge storage electrode segment 12B; PC ... the potential of a point PC of the region of the photoelectric conversion layer 15 facing the first electrode 11 or the photoelectric conversion layer 15 facing the charge storage electrode segment Potential of a point PC in the region of 12A; PD ... potential of a point PD of the photoelectric conversion layer 15 facing a region located in the middle of a region between the charge storage electrode segment 12C and the first electrode 11; FD ... first Floating Diffusion Layer FD 1 The potential of ; VOA ... the potential of the charge storage electrode 12 . VOA-A...the potential of the charge storage electrode segment 12A; VOA-B...the potential of the charge storage electrode segment 12B; VOA-C...the potential of the charge storage electrode segment 12C; VOT...the transfer control electrode (charge transfer electrode) 13 potential; RST ...... reset transistor TR1 rst The potential of the gate portion 51 of ; VDD ... the potential of the power supply; VSL_1 ... the signal line (data output line) VSL 1 ;TR1_rst ......Reset transistor TR1 rst ; TR1_amp ......amplifier transistor TR1 amp ; and TR1_sel ... select transistor TR1 sel . During a charge storage period, a potential V 11 The self-driving circuit is applied to the first electrode 11, and a potential V is applied 12 A self-driving circuit is applied to the charge storage electrode 12 . Photoelectric conversion occurs in the photoelectric conversion layer 15 by light incident on the photoelectric conversion layer 15 . The holes generated by photoelectric conversion pass from the second electrode 16 through the wire V OU and transferred to the drive circuit. On the other hand, since the potential of the first electrode 11 is set higher than the potential of the second electrode 16, that is, since a positive potential is applied to the first electrode 11 and a negative potential is applied to the second electrode 16, for example, Two electrodes 16, so set V 12 ≥ V 11 , preferably V 12 > V 11 . Therefore, the electrons generated through the photoelectric conversion are attracted by the charge storage electrode 12 , and thus the electrons stop in the region of the photoelectric conversion layer 15 facing the charge storage electrode 12 . That is, charges are stored in the photoelectric conversion layer 15 . Since V 12 > V 11 , so the electrons generated in the inner portion of the photoelectric conversion layer 15 do not move toward the first electrode 11 . As the photoelectric conversion time elapses, the potential of the region of the photoelectric conversion layer 15 facing the charge storage electrode 12 becomes another negative value. In the final stage of the charge storage period, a reset operation is performed. Therefore, the first floating diffusion layer FD is reset 1 potential, and the first floating diffusion layer FD 1 The potential becomes the potential of the power supply V DD . After the reset operation is completed, charge readout is performed. That is, in the charge transfer period, the self-driving circuit will change a potential V twenty one applied to the first electrode 11 and a potential V twenty two applied to the charge storage electrode 12 . In this paper, set V twenty two < V twenty one . By doing this, the electrons that have stopped in the region of the photoelectric conversion layer 15 facing the charge storage electrode 12 can be read out to the first electrode 11 and further to the first floating diffusion layer FD 1 . That is, the charges stored in the photoelectric conversion layer 15 are read out to the control unit. The structure including the insulating layer 82 between the charge storage electrode 12 and the first electrode 11 can restrain the variation of the PB potential. Without the insulating layer 82 at such a position, various positions of the edge of the insulating layer 82 can cause a change in the PB potential in addition to a change in a distance between the charge storage electrode 12 and the first electrode 11 a change. Conversely, the presence of the insulating layer 82 in an opening between the charge storage electrode 12 and the first electrode 11 allows the distance between the charge storage electrode 12 and the first electrode 11 to determine the effect of the PB potential. Thus, by including the insulating layer 82 as mentioned above, the insulating layer 82 can cause an increase in the minimum PB potential, which effectively confines electrons to the PA sites and further reduces a current leakage. In the manner described so far, a series of operations of charge storage, reset operation, and charge transfer is accomplished. After reading out electrons to the first floating diffusion layer FD 1 After the amplification transistor TR1 amp and select transistor TR1 sel The operation is the same as that of these transistors in the related art. In addition, the series of operations of charge storage, reset operation, and charge transfer of the second imaging element and the third imaging element are similar to the series of operations of charge storage, reset operation, and charge transfer in the related art. In addition, similar to the related art, the first floating diffusion layer FD can be removed by a correlated double sampling (CDS) process 1 The reset noise. As set forth above, in Example 1, since the charge storage electrode (which is configured to be separated from the first electrode and configured to face the photoelectric conversion layer is provided, wherein the insulating layer is interposed between the charge storage electrode and the photoelectric conversion layer time), so when the photoelectric conversion unit is illuminated with light and photoelectric conversion is performed in the photoelectric conversion unit, a kind of capacitor is formed by the photoelectric conversion layer, the insulating layer, and the charge storage electrode, so that the charge can be stored in the photoelectric conversion unit in the layer. Thus, by completely depleting a charge storage cell at the start of exposure, it is possible to erase charge. Therefore, it is possible to suppress the occurrence of phenomena such as an increase in kTC noise, a deterioration in random noise, and a deterioration in image quality in imaging. In addition, since all pixels can be reset at the same time, a so-called global shutter function can be implemented. A conceptual diagram of a solid-state imaging device of Example 1 is illustrated in FIG. 8 . The solid-state imaging device 100 of Example 1 is configured to include an imaging region 111 in which the stacked imaging elements 101 are arranged in a two-dimensional array shape and driving circuits (peripheral circuits) such as a vertical driving circuit 112, a line of signal processing circuits 113, a horizontal drive circuit 114, an output circuit 115 and a drive control circuit 116). Note that these circuits can be configured with well-known circuits. Obviously, other circuit configurations (eg, various circuits used in a CCD imaging device or a CMOS imaging device in the related art) can also be used to configure these circuits. Note that in FIG. 8, only one column of the stacked imaging element 101 is indicated by the reference numeral "101". The driving control circuit 116 generates a clock signal and a control signal, and the clock signal and the control signal become the vertical driving circuit 112, the horizontal signal processing circuit 113 and the Reference for the operation of the horizontal drive circuit 114 . Then, the generated clock signal or control signal is input to the vertical driving circuit 112 , the horizontal signal processing circuit 113 and the horizontal driving circuit 114 . For example, the vertical driving circuit 112 is configured with a shift register and selectively scans the stacked imaging element 101 of the imaging area 111 in a row unit in a vertical direction. Then, a pixel signal (image signal) based on a current (signal) generated according to an amount of light received by one of the stacked imaging elements 101 is transmitted to the line signal processing circuit through the signal line (data output line) 117 and VSL 113. For example, row signal processing circuit 113 is configured for each row of stacked imaging element 101 and based on a signal from a black reference pixel (not shown but formed in the perimeter of an active pixel area) of each imaging element Instead, a signal processing (such as noise removal or signal amplification) is performed on the image signal output from one column of the stacked imaging element 101 . A horizontal selection switch (not shown) is provided to be connected between the output stage of the row signal processing circuit 113 and the horizontal signal line 118 . For example, the horizontal driving circuit 114 is configured with a shift register and sequentially selects the row signal processing circuit 113 by sequentially outputting horizontal scan pulses to output the signal of the row signal processing circuit 113 to the horizontal signal line 118 . The output circuit 115 performs a signal processing on the signals sequentially supplied from the signal processing circuit 113 through the horizontal signal line 118 and outputs the signals. An equivalent circuit diagram of the imaging element of Example 1 and a modified example of the stacked imaging element is illustrated in FIG. 9 . When a schematic layout of a first electrode and a charge storage electrode and a transistor constituting a control unit constituting a modified example of the imaging element of Example 1 are illustrated in FIG. 10, the reset transistor TR1 rst The other source/drain region 51B can be grounded instead of being connected to the power supply V DD . For example, the imaging elements and stacked imaging elements of Example 1 can be fabricated by the methods set forth below. That is, first, an SOI substrate is prepared. Then, a first silicon layer is formed on the surface of the SOI substrate based on an epitaxial growth method, and a p+ layer 73 and an n-type semiconductor region 41 are formed on the first silicon layer. Next, a second silicon layer is formed on the first silicon layer based on an epitaxial growth method, and an element isolation region 71, an oxide film 72, a p+ layer 42, an n layer are formed on the second silicon layer type semiconductor region 43 and a p+ layer 44 . In addition, various transistors and the like constituting a control unit of the imaging element are formed in the second silicon layer, and a wiring layer 62, an interlayer insulating layer 76, and various wirings are formed on the various transistors and the like. The interlayer insulating layer 76 and a support substrate (not shown) are allowed to adhere to each other. After this, the first silicon layer is exposed by removing the SOI substrate. Note that the surface of the second silicon layer corresponds to the surface 70A of the semiconductor substrate 70 , and the surface of the first silicon layer corresponds to the rear surface 70B of the semiconductor substrate 70 . In addition, the first silicon layer and the second silicon layer are collectively expressed as the semiconductor substrate 70 . Next, in the rear surface 70B side of the semiconductor substrate 70, an opening portion for forming a contact hole portion 61 is formed; an HfO is formed 2 film 74, an insulating film 75, and a contact hole portion 61; Next, a connection portion 67 is opened, and a photoelectric conversion layer 15 , a second electrode 16 , a protective layer 83 and an on-chip microlens 90 are formed. By doing this, the imaging element and the stacked imaging element of Example 1 were obtained. [Example 2] Example 2 is a modification of one of Example 1. An imaging element and a stacked imaging element of Example 2 (a schematic partial cross-sectional view of which is illustrated in FIG. 11 ) is a front-illuminated imaging element and a front-illuminated stacked imaging element and has the following three imaging elements One stack structure: Example 1 One first type green imaging element (first imaging element) which is sensitive to green and has a first type green photoelectric conversion layer that absorbs green light; one related art second type blue Imaging element (second imaging element), which is blue-sensitive and has a second-type blue photoelectric conversion layer that absorbs blue light; and a second-type red imaging element (third imaging element), one of the related art, which is A second type red photoelectric conversion layer that is red sensitive and has one that absorbs red light. Here, the red imaging element (third imaging element) and the blue imaging element (second imaging element) are provided in the semiconductor substrate 70, and the second imaging element is positioned closer to the light incident side than the third imaging element. In addition, the green imaging element (first imaging element) is disposed above the blue imaging element (second imaging element). Similar to Example 1, various transistors constituting the control unit are provided in the surface 70A side of the semiconductor substrate 70 . These transistors can be formed with a configuration and structure substantially similar to that of the transistors described in Example 1. Additionally, although the second and third imaging elements are disposed in the semiconductor substrate 70, these imaging elements may be formed with substantially the same configuration and structure as the second and third imaging elements described in Example 1 A similar configuration and structure. The interlayer insulating layers 77 and 78 are formed on the surface 70A of the semiconductor substrate 70, and the photoelectric conversion unit (the first electrode 11, the photoelectric conversion layer 15, and the second electrode 16) constituting the imaging element of Example 1 is provided on the interlayer insulating layer 78. , charge storage electrodes 12 and the like. In this way, except that the imaging element and the stacked imaging element are front-illuminated, since the configuration and structure of the imaging element and stacked imaging element of Example 2 can be formed to be similar to the imaging element and stacked imaging element of Example 1 Therefore, the detailed description is omitted. [Example 3] Example 3 is a modification of one of Examples 1 and 2. An imaging element and a stacked imaging element of Example 3 (a schematic partial cross-sectional view of which is illustrated in FIG. 12 ) is a back-illuminated imaging element and a back-illuminated stacked imaging element and has the following two imaging elements A stacked structure: Example 1 A first imaging element of a first type and a second imaging element of a second type. In addition, a modified example of the imaging element and stacked imaging element of Example 3 (a schematic partial cross-sectional view of which is illustrated in FIG. 13 ) is a front-illuminated imaging element and a front-illuminated stacked imaging element and has the following Stacked structure of one of two imaging elements: Example 1 a first imaging element of a first type and a second imaging element of a second type. Herein, the first imaging element absorbs primary color light, and the second imaging element absorbs complementary color light. Alternatively, the first imaging element absorbs white light and the second imaging element absorbs an infrared light. A modified example of the imaging element of Example 3 (a schematic partial cross-sectional view of which is illustrated in FIG. 14 ) is a backside illuminated imaging element configured with a first type of first imaging element of Example 1. Alternatively, a modified example of the imaging element of Example 3 (a schematic partial cross-sectional view of which is illustrated in FIG. 15A ) is a front-illuminated imaging element configured with a first-type first imaging element of Example 1 element. Here, the first imaging element is configured with three types of imaging elements: an imaging element that absorbs red light; an imaging element that absorbs green light; and an imaging element that absorbs blue light. Furthermore, the solid-state imaging device according to the first embodiment of the present invention is configured with a plurality of imaging elements. As an array of a plurality of imaging elements, a Bayer array can be exemplified. If necessary, color filters for performing spectral separation of blue, green, and red light are arranged in the light incident side of each imaging element. Additionally, and as depicted in FIGS. 15B-15D, the insulating layer 82 may comprise multiple layers. As shown in FIGS. 15B-15D, insulating layer 82 may include multiple layers 82E and 82F. For example, there may be a first region of the insulating material 82 between the charge storage electrode 12 and the photoelectric conversion layer 15 , and there may be a first region of the insulating material 82 between the charge storage electrode 12 and the first electrode 11 . a second area. In some embodiments, the second region of insulating material includes a first insulating layer 82E (which includes insulating material) and a second insulating layer 82F (which includes insulating material), and the first insulating material 82F is stacked on the second on insulating material 82E. 15B-15D further illustrate various configurations with respect to insulating layer 82 (eg, configuration changes of layers 82E and 82F). Note that instead of preparing one first-type imaging element of Example 1, two imaging elements may be stacked (that is, two photoelectric conversion units are stacked and a control unit for both imaging elements is prepared in a semiconductor substrate), or Three imaging elements may be stacked (that is, three photoelectric conversion units are stacked and a control unit for the three imaging elements is prepared in a semiconductor substrate). Examples of stacked structures of the first type of imaging element and the second type of imaging element are listed in the following table. [Table 1]    first type Type II Reference map Back-illuminated and front-illuminated 1 2 1A to 1D green blue+red Figure 11 1 1 Figure 12 primary color Complementary color Figure 13 1 1    White infrared    1 0 Figure 14 blue or green or red    15A to 15D 2 2    green + infrared light blue+red    2 1    green + blue red    2 0    white + infrared light       3 2    green+blue+red Blue Green (Emerald) + Infrared Light    3 1    green+blue+red infrared light    3 0    blue+green+red       [Example 4] Example 4 is a modification of Examples 1 to 3 and relates to an imaging element having transfer control electrodes (charge transfer electrodes) or the like according to an embodiment of the present invention. A schematic partial cross-sectional view of a portion of the imaging element of Example 4 and a portion of the stacked imaging element is illustrated in FIG. 16 . Equivalent circuit diagrams of the imaging element and the stacked imaging element of Example 4 are illustrated in FIGS. 17 and 18 . A schematic layout diagram of a first electrode, a transfer control electrode, and a charge storage electrode constituting the imaging element of Example 4 and a transistor constituting a control unit is illustrated in FIG. 19 . The potential states of components during one cycle of operation of the imaging element of Example 4 are illustrated in FIGS. 20 and 21 . In addition, a schematic layout diagram of a first electrode, a transfer control electrode, and a charge storage electrode constituting the imaging element of Example 4 is illustrated in FIG. 22 . A schematic perspective view of a first electrode, transfer control electrode, charge storage electrode, a second electrode, and a contact hole portion constituting the imaging element of Example 4 is illustrated in FIG. 23 . The imaging element and the stacked imaging element of Example 4 are configured to further include a transfer control electrode (charge transfer electrode) 13 disposed between the first electrode 11 and the charge storage electrode 12 and to be connected to the first electrode 11 and the charge storage electrode 12 are separated and configured to face the photoelectric conversion layer 15 through the insulating layer 82 . The transfer control electrode 13 passes through a connection hole 68B, a pad portion 68A and a wire V formed in the interlayer insulating layer 81 OT and connected to the pixel driving circuit constituting the driving circuit. Note that, for convenience, various components of the imaging element located under the interlayer insulating layer 81 are collectively denoted by reference numeral 91 in order to simplify the drawing. Hereinafter, the operation of the imaging element (first imaging element) of Example 4 will be explained with reference to FIGS. 20 and 21 . Note that FIGS. 20 and 21 are different from each other, particularly in the potential applied to the charge storage electrode 12 and the potential of the point PB. During the charge storage period, the self-driving circuit will convert a potential V 11 Applied to the first electrode 11, a potential V 12 applied to the charge storage electrode 12 and a potential V 13 applied to the transfer control electrode 13 . Photoelectric conversion occurs in the photoelectric conversion layer 15 by light incident on the photoelectric conversion layer 15 . The holes generated by photoelectric conversion pass from the second electrode 16 through the wire V OU and transferred to the drive circuit. On the other hand, since the potential of the first electrode 11 is set higher than the potential of the second electrode 16, that is, since a positive potential is applied to the first electrode 11 and a negative potential is applied to the first electrode 11, for example, Two electrodes 16, so set V 12 > V 13 (For example, V 12 > V 11 > V 13 or V 11 > V 12 > V 13 ). Therefore, the electrons generated through the photoelectric conversion are attracted by the charge storage electrode 12 , and thus the electrons stop in the region of the photoelectric conversion layer 15 facing the charge storage electrode 12 . That is, charges are stored in the photoelectric conversion layer 15 . Since V 12 > V 13 , it is therefore possible to reliably prevent electrons generated in the photoelectric conversion layer 15 from moving toward the first electrode 11 . As the photoelectric conversion time elapses, the potential of the region of the photoelectric conversion layer 15 facing the charge storage electrode 12 becomes another negative value. In the final stage of the charge storage cycle, a reset operation is performed. Therefore, the first floating diffusion layer FD is reset 1 potential, and the first floating diffusion layer FD 1 The potential becomes the potential of the power supply V DD . After the reset operation is completed, charge readout is performed. That is, in the charge transfer period, the self-driving circuit will change a potential V twenty one Applied to the first electrode 11, a potential V twenty two applied to the charge storage electrode 12 and a potential V twenty three applied to the transfer control electrode 13 . In this paper, set V twenty two ≤ V twenty three ≤ V twenty one . By doing this, the electrons that have stopped in the region of the photoelectric conversion layer 15 facing the charge storage electrode 12 can be reliably read out to the first electrode 11 and also to the first floating diffusion layer FD 1 . That is, the charges stored in the photoelectric conversion layer 15 are read out to the control unit. In the manner described so far, a series of operations of charge storage, reset operation, and charge transfer is accomplished. After reading out electrons to the first floating diffusion layer FD 1 After the amplification transistor TR1 amp and select transistor TR1 sel The operation is the same as that of these transistors in the related art. In addition, for example, the series of operations of charge storage, reset operation, and charge transfer of the second and third imaging elements are similar to those of the related art. When a schematic layout diagram of the first electrode and the charge storage electrode constituting a modified example of the imaging element of Example 4 and a transistor constituting a control unit is illustrated in FIG. 24, the reset transistor TR1 rst The other source/drain region 51B can be grounded instead of being connected to the power supply V DD . [Example 5] Example 5 is a modification of Examples 1 to 4 and relates to an imaging element having a charge emitting electrode or the like according to an embodiment of the present invention. A schematic partial cross-sectional view of a portion of the imaging element and stacked imaging element of Example 5 is illustrated in FIG. 25 . A schematic layout of a first electrode, a charge storage electrode, and a charge emitting electrode constituting the imaging element of Example 5 is illustrated in FIG. 26 . A schematic perspective view of a first electrode, a charge storage electrode, a charge emitting electrode, a second electrode, and a contact hole portion constituting the imaging element of Example 5 is illustrated in FIG. 27 . In the imaging element and the stacked imaging element of Example 5, the imaging element is configured to further include a charge emitting electrode 14 connected to a photoelectric conversion layer 15 through a connecting portion 69 and configured to communicate with the first The electrode 11 and the charge storage electrode 12 are separated. The charge exit electrode 14 is configured to surround the first electrode 11 and the charge storage electrode 12 (ie, in a frame shape). The charge emitting electrode 14 is connected to a pixel driving circuit constituting a driving circuit. The photoelectric conversion layer 15 extends in the connection portion 69 . That is, the photoelectric conversion layer 15 extends in the second opening portion 85 provided in the insulating layer 82 to be connected to the charge emitting electrode 14 . The charge extraction electrode 14 is shared (commonly used) by a plurality of imaging elements. In Example 5, during the charge storage period, the self-driving circuit will change a potential V 11 Applied to the first electrode 11, a potential V 12 applied to the charge storage electrode 12 and a potential V 14 Application to the charge emitting electrode 14 causes the charge to be stored in the photoelectric conversion layer 15 . Photoelectric conversion occurs in the photoelectric conversion layer 15 by light incident on the photoelectric conversion layer 15 . The holes generated by photoelectric conversion pass from the second electrode 16 through the wire V OU and transferred to the drive circuit. On the other hand, since the potential of the first electrode 11 is set higher than the potential of the second electrode 16, that is, since a positive potential is applied to the first electrode 11 and a negative potential is applied to the second electrode 16, for example, Two electrodes 16, so set V 14 > V 11 (For example, V 12 > V 14 > V 11 ). Therefore, electrons generated through photoelectric conversion are attracted by the charge storage electrode 12 and thus the electrons stop in the region of the photoelectric conversion layer 15 facing the charge storage electrode 12 , making it possible to reliably prevent the electrons from moving toward the first electrode 11 . However, electrons (so-called overflow electrons) not sufficiently attracted by the charge storage electrode 12 or not stored in the photoelectric conversion layer 15 are transferred to the driving circuit through the charge exit electrode 14 . In the final stage of the charge storage cycle, a reset operation is performed. Therefore, the first floating diffusion layer FD is reset 1 potential, and the first floating diffusion layer FD 1 The potential becomes the potential of the power supply V DD . After the reset operation is completed, charge readout is performed. That is, in the charge transfer period, the self-driving circuit will change a potential V twenty one Applied to the first electrode 11, a potential V twenty two applied to the charge storage electrode 12 and a potential V twenty four applied to the charge extraction electrode 14 . In this paper, set V twenty four < V twenty one (For example, V twenty four < V twenty two < V twenty one ). By doing this, the electrons that have stopped in the region of the photoelectric conversion layer 15 facing the charge storage electrode 12 can be reliably read out to the first electrode 11 and further to the first floating diffusion layer FD 1 . That is, the charges stored in the photoelectric conversion layer 15 are read out to the control unit. In the manner described so far, a series of operations of charge storage, reset operation, and charge transfer is accomplished. After reading out electrons to the first floating diffusion layer FD 1 After the amplification transistor TR1 amp and select transistor TR1 sel The operation is the same as that of these transistors in the related art. In addition, for example, the series of operations of charge storage, reset operation, and charge transfer of the second and third imaging elements is similar to the series of operations of charge storage, reset operation, and charge transfer in the related art. In Example 5, since the overflow electrons are transferred to the driving circuit through the charge emitting electrode 14, the leakage to the charge storage unit of the adjacent pixel can be suppressed, making it possible to suppress the occurrence of blooming. In addition, therefore, it is possible to improve the imaging performance of the imaging element. [Example 6] Example 6 is a modification of Examples 1 to 5 and relates to an imaging element having a plurality of charge storage electrode segments or the like according to an embodiment of the present invention. A schematic partial cross-sectional view of a portion of the imaging element of Example 6 is illustrated in FIG. 28 . Equivalent circuit diagrams of the imaging element and the stacked imaging element of Example 6 are illustrated in FIGS. 29 and 30 . A schematic layout diagram of a first electrode and a charge storage electrode constituting the imaging element of Example 6 and a transistor constituting a control unit is illustrated in FIG. 31 . The potential states of components during one cycle of operation of the imaging element of Example 6 are illustrated in FIGS. 32 and 33 . In addition, a schematic layout diagram of the first electrode and the charge storage electrode constituting the imaging element of Example 6 is illustrated in FIG. 34 . A schematic perspective view of a first electrode, a charge storage electrode, a second electrode, and a contact hole portion constituting the imaging element of Example 6 is illustrated in FIG. 35 . In Example 6, the charge storage electrode 12 is configured with a plurality of charge storage electrode segments 12A, 12B, and 12C. The number of charge storage electrode segments can be two or more, and in Example 6, the number is set to "3". Then, in the imaging element and the stacked imaging element of Example 6, since the potential of the first electrode 11 is higher than the potential of the second electrode 16 , that is, because, for example, a positive potential is applied to the first electrode 11 And a negative potential is applied to the second electrode 16, so in the charge transfer period, the potential applied to the charge storage electrode segment 12A located closest to the first electrode 11 is higher than that applied to the charge storage electrode segment 12A located at a distance from the first electrode 11. 11 The potential of the charge storage electrode segment 12C at the furthest position. In this way, a potential gradient is provided to the charge storage electrode 12, so that electrons that have stopped in the region of the photoelectric conversion layer 15 facing the charge storage electrode 12 are reliably read out to the first electrode 11, and furthermore, to the first electrode 11. Floating Diffusion Layer FD 1 . That is, the charges stored in the photoelectric conversion layer 15 are read out to the control unit. In the example illustrated in FIG. 32, in the charge transfer period, the potential of charge storage electrode segment 12C is set to < the potential of charge storage electrode segment 12B < the potential of charge storage electrode segment 12A, and thus, the already Electrons stopped in the region of the photoelectric conversion layer 15 are simultaneously read out to the first floating diffusion layer FD 1 . On the other hand, in the example illustrated in FIG. 33, during the charge transfer period, the potential of charge storage electrode segment 12C, the potential of charge storage electrode segment 12B, and the potential of charge storage electrode segment 12A are allowed to gradually increase change (ie, gradually or in a ramp shape). Therefore, electrons that have stopped in the region of the photoelectric conversion layer 15 facing the charge storage electrode segment 12C are allowed to move to the photoelectric conversion layer 15 facing the charge storage electrode segment 12B. Subsequently, electrons that have stopped in the region of the photoelectric conversion layer 15 facing the charge storage electrode segment 12B are allowed to move to the photoelectric conversion layer 15 facing the charge storage electrode segment 12A. Subsequently, electrons that have stopped in the region of the photoelectric conversion layer 15 facing the charge storage electrode segment 12A are allowed to be reliably read out to the first floating diffusion layer FD 1 . When a schematic layout of a first electrode and a charge storage electrode and a transistor constituting a control unit constituting a modified example of the imaging element of Example 6 is illustrated in FIG. 36, the reset transistor TR1 rst The other source/drain region 51B can be grounded instead of being connected to the power supply V DD . So far, although the present invention has been described based on preferred examples, the present invention is not limited to these examples. The structures, configurations, manufacturing conditions, manufacturing methods, and materials used of the imaging element, the stacked imaging element, and the solid-state imaging device described in the examples are exemplary, and thus these are appropriately changed. In addition to a form in which one floating diffusion layer is provided to one imaging element, a form in which one floating diffusion layer is provided to a plurality of imaging elements may also be implemented. That is, by appropriately controlling a timing of the charge transfer period, a floating diffusion layer can be allowed to be shared by a plurality of imaging elements. In addition, in this case, it is also possible to allow a plurality of imaging elements to share one contact hole portion. When a modified example of the imaging element and the stacked imaging element set forth in Example 1 is illustrated in FIG. 37 , the first electrode 11 may be configured to extend in an opening portion 84A provided to the insulating layer 82 for connection to the photoelectric conversion layer 15 . Alternatively, when a modified example of the imaging element set forth in Example 1 and a stacked imaging element is illustrated in Figure 38 and a schematic enlarged partial cross-section of a portion of the first electrode and the like is illustrated in Figure 39A In the drawing, the edge of the top surface of the first electrode 11 is covered with the insulating layer 82; the first electrode 11 is exposed on the bottom surface of an opening portion 84B; and the surface of the insulating layer 82 in contact with the top surface of the first electrode 11 is covered by When a first surface 82a is defined and a surface of the insulating layer 82 in contact with a portion of the photoelectric conversion layer 15 (which faces the charge storage electrode 12 ) is defined by a second surface 82b, the side surface of the opening portion 84B has a surface from the first surface 82a A slope extends toward the second surface 82b. In this way, since a slope is provided to the side surface of the opening portion 84B, the charges move from the photoelectric conversion layer 15 to the first electrode 11 more smoothly. Note that in the example illustrated in FIG. 39A, the axis of the opening portion 84B is used as a center, and the side surface of the opening portion 84B has a rotational symmetry. However, as illustrated in FIG. 39B, the opening portion 84C may be disposed such that the side surface of the opening portion 84C having a slope extending from the first surface 82a toward the second surface 82b is in the charge storage electrode 12 side. Therefore, the charge from the portion of the photoelectric conversion layer 15 located at the side opposite to the charge storage electrode 12 where the opening portion 84C is interposed between the side and the charge storage electrode is difficult to move. In addition, although the side surface of the opening portion 84B has a slope extending from the first surface 82a toward the second surface 82b, the edge of the side surface of the opening portion 84B in the second surface 82b may be located from the edge of the first electrode 11 In the outer side (as illustrated in FIG. 39A ), or may be located in the side from the inside of the edge of the first electrode 11 (as illustrated in FIG. 39C ). By adopting the former configuration, charge transfer can be performed more easily; and by adopting the latter configuration, shape irregularities in forming the opening portion can be reduced. The side surface of an opening portion of an etching mask can be reflowed by reflowing an etching mask made of a resist material formed when the opening portion is formed in the insulating layer (based on an etching method) A slope is provided and opening portions 84B and 84C are formed by etching insulating layer 82 using an etch mask. Alternatively, with regard to the charge exit electrode 14 set forth in Example 5, as illustrated in FIG. 40 , the photoelectric conversion layer 15 may be formed to extend in a second opening portion 85A provided to the insulating layer 82 for connection to the charge exit electrode 14; the edge of the top surface of the charge exit electrode 14 is covered with the insulating layer 82; the charge exit electrode 14 is exposed in the bottom surface of the second opening portion 85A; When the surface in contact with the surface is defined by a third surface 82c and the surface of the insulating layer 82 in contact with the portion of the photoelectric conversion layer 15 (which faces the charge storage electrode 12) is defined by a second surface 82b, the side of the second opening portion 85A The surface has a slope extending from the third surface 82c towards the second surface 82b. Alternatively, when a modified example of the imaging element and the stacked imaging element set forth in Example 1 is illustrated in FIG. 41, the light may be configured to be incident on the side of the second electrode 16, and a light The shielding layer 92 may be configured to be formed in the light incident side of the second electrode 16 . Note that various wires disposed closer to the light incident side than to the photoelectric conversion layer can be allowed to be used as the light shielding layer. Note that in the example illustrated in FIG. 41 , although the light shielding layer 92 is formed over the second electrode 16 , that is, although the light shielding layer 92 is formed over the first electrode 11 as the light incident side of the second electrode 16 , but as illustrated in FIG. 42 , the light shielding layer may be disposed on the surface of the light incident side of the second electrode 16 . Additionally, in some cases, as illustrated in FIG. 43 , a light shielding layer 92 may be formed in the second electrode 16 . Alternatively, a structure may be provided in which light is incident from the second electrode 16 side and no light is incident on the first electrode 11 . Specifically, as illustrated in FIG. 41 , the light shielding layer 92 is formed over the first electrode 11 as the light incident side of the second electrode 16 . Alternatively, as illustrated in Figure 45, a structure may be provided in which an on-wafer microlens 90 is disposed over the charge storage electrode 12 and the second electrode 16 and is incident upon the on-wafer microlens 90 The light is collected in the charge storage electrode 12 so that the light cannot reach the first electrode 11 . Note that, as set forth in Example 4, in the case where the transfer control electrode 13 is provided, it is possible to implement a form in which light is not incident on the first electrode 11 and the transfer control electrode 13 . Specifically, as illustrated in FIG. 44 , a form in which the light shielding layer 92 is formed over the first electrode 11 and the transfer control electrode 13 may be provided. Alternatively, a structure may be provided in which light incident on the on-wafer microlenses 90 does not reach the first electrode 11 and the transfer control electrode 13 . By employing the configurations and structures described above, another option is to provide the light shielding layer 92 so that light is incident only on the portion of the photoelectric conversion layer 15 that is above the charge storage electrode 12, or another option is to design the wafer In the microlens 90, since the part of the photoelectric conversion layer 15 above the first electrode 11 (or above the first electrode 11 and the transfer control electrode 13) does not contribute to photoelectric conversion, it is possible to reset all the pixels more reliably at the same time, so that It may be easier to implement a global shutter function. That is, in a driving method for a solid-state imaging device including a plurality of imaging elements having the above-described configuration and structure, the following procedure is repeated: In all imaging elements simultaneously, charge is stored in the photoelectric conversion layer 15, and the charge of the first electrode 11 is emitted to the outside; and at the same time in all imaging elements, the charge stored in the photoelectric conversion layer 15 is transferred to the first electrode 11, and after the transfer is completed, it will be transferred to each The charges of the first electrodes 11 in the different imaging elements are sequentially read out. The photoelectric conversion layer is not limited to the configuration in which the photoelectric conversion layer is one layer. For example, when a modified example of the imaging element and the stacked imaging element set forth in Example 1 is illustrated in FIG. 46A, the photoelectric conversion layer 15 may be configured to have that set forth in Example 1 (for example, ) a stacked layer structure of a lower semiconductor layer 15A (which is made of IGZO) and an upper photoelectric conversion layer 15B (which is made of a material constituting the photoelectric conversion layer 15 ). In this way, by providing the lower semiconductor layer 15A, it is possible to prevent recoupling during the charge storage period, making it possible to increase the transfer efficiency of the charge stored in the photoelectric conversion layer 15 to the first electrode 11, and to suppress the occurrence of dark current . Additionally, as a modified example of Example 4, as illustrated in FIG. 47 , a plurality of transfer control electrodes may be provided from a position closest to the first electrode 11 toward the charge storage electrode 12 . Note that an example in which two transfer control electrodes 13A and 13B are provided is illustrated in FIG. 47 . As shown in FIGS. 46B-46D, insulating layer 82 may include multiple layers 82E and 82F. For example, there may be a first region of the insulating material 82 between the charge storage electrode 12 and the photoelectric conversion layer 15 , and there may be a first region of the insulating material 82 between the charge storage electrode 12 and the first electrode 11 . a second area. In some embodiments, the second region of insulating material includes a first insulating layer 82E (which includes insulating material) and a second insulating layer 82F (which includes insulating material), and the first insulating material 82F is stacked on the second on insulating material 82E. 46B-46D further illustrate various configurations with respect to insulating layer 82 (eg, configuration changes of layers 82E and 82F). The various modified examples set forth above may be applied to Example 1 or other examples as appropriate. In the example, although electrons are set as signal charges and the conductivity type of the photoelectric conversion layer formed in the semiconductor substrate is set as n-type, the present invention can be applied to a solid-state imaging device in which holes are set as signal charges. In this case, each semiconductor region may be configured as a semiconductor region having an opposite conductivity type, and the conductivity type of the photoelectric conversion layer formed in the semiconductor substrate may be p-type. In addition, in the example, although the description exemplifies the application to a CMOS type solid-state imaging device in which unit pixels that detect signal charges according to the amount of incident light as a physical quantity are arranged in a matrix shape, the present invention is not limited to Applied to a CMOS-type solid-state imaging device, the present invention can be applied to a CCD-type solid-state imaging device. In the latter case, the signal charges are transferred in the vertical direction by a vertical transfer register having a CCD type structure, and the signal charges are transferred in the horizontal direction by a horizontal transfer register to be amplified, so that A pixel signal (image signal) is output. In addition, the present invention is not limited to an integral line-type solid-state imaging device in which pixels are formed in a two-dimensional matrix shape and line signal processing circuits are arranged for respective pixel lines. Furthermore, in some cases, the selection transistor may be omitted. In addition, the imaging element and the stacked imaging element of the present invention are not limited to being applied to a solid-state imaging device for detecting a distribution of incident light amount of visible light to image the distribution as an image, but the imaging element and the stacked imaging element of the present invention The device can also be applied to a solid-state imaging device that images a distribution of incident amounts of infrared rays, X-rays, particles, or the like into an image. In addition, in a broad sense, the imaging element and the stacked imaging element of the present invention can be applied to an overall solid-state imaging device ( physical quantity distribution detection device), such as a fingerprint detection sensor. In addition, the present invention is not limited to a solid-state imaging device in which the unit pixels of the imaging area are sequentially scanned in units of a column to read out pixel signals from the unit pixels. The present invention can be applied to an XY address type solid-state imaging device in which pixels are arbitrarily selected in units of one pixel and pixel signals are read out from the selected pixels in units of one pixel. The solid-state imaging device may be formed into one wafer, or the solid-state imaging device may be formed in the shape of a module having an imaging function in which an imaging area, a driving circuit, or an optical system are collectively packaged. In addition, the present invention is not limited to being applied to a solid-state imaging device, but the present invention can be applied to an imaging device. Herein, the imaging device refers to a camera system (such as a digital still camera or a video camera) or an electronic device (such as a mobile phone with an imaging function). In some cases, the present invention may be implemented in a module-like form to be mounted on an electronic device, ie, a camera module. An example in which a solid-state imaging device 201 configured with an imaging element or a stacked imaging element of the present invention is used for an electronic apparatus (camera) 200 is illustrated in a conceptual diagram of FIG. 48 . The electronic device 200 includes a solid-state imaging device 201 , an optical lens 210 , a shutter device 211 , a driving circuit 212 and a signal processing circuit 213 . The optical lens 210 forms an image of image light (incident light) from an object on an imaging site of the solid-state imaging device 201 . Therefore, the signal charges are stored in the solid-state imaging device 201 for a certain period. The shutter device 211 controls a light illumination period and a light shielding period of the solid-state imaging device 201 . The drive circuit 212 supplies drive signals for controlling a transfer operation of the solid-state imaging device 201 and a shutter operation of the shutter device 211 . Signal transfer of the solid-state imaging device 201 is performed according to the drive signal (timing signal) supplied from the drive circuit 212 . The signal processing circuit 213 performs various kinds of signal processing. An image signal subjected to signal processing is stored in a storage medium (such as a memory) or output to a monitor. In the electronic apparatus 200, since the pixel size and transfer efficiency of the solid-state imaging device 201 are improved, it is possible to achieve the electronic apparatus 200 whose pixel characteristics are improved. The electronic device 200 to which the solid-state imaging device 201 can be applied is not limited to a camera, but the electronic device can be applied to an imaging device (such as a digital still camera or a camera module) for a mobile device (such as a mobile phone) . It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may be made depending on design requirements and other factors insofar as they are within the scope of the appended claims or their equivalents. Also, for example, the present technology may have the following configurations. (1) An imaging device comprising: a substrate including a first photoelectric conversion unit; and a second photoelectric conversion unit located at a light incident side of the substrate, the second photoelectric conversion unit including: a a photoelectric conversion layer; a first electrode; a second electrode located above the photoelectric conversion layer; a third electrode; and an insulating material between the third electrode and the photoelectric conversion layer, wherein the insulating material A portion of the material is interposed between the first electrode and the third electrode. (2) The imaging device according to (1) above, further comprising: a first region of the insulating material, the first region being interposed between the third electrode and the photoelectric conversion layer; a first region of the insulating material Two regions, the second region is between the third electrode and the first electrode, wherein the second region of the insulating material includes a first insulating layer with the insulating material and a second insulating layer with the insulating material an insulating layer, wherein the first insulating material is stacked on the second insulating material. (3) The imaging device according to (2) above, wherein a portion of the first insulating layer in the second region is interposed between the first electrode and the photoelectric conversion layer. (4) The image forming apparatus according to (3) above, wherein the first region and the second region include different numbers of insulating layers having the insulating material. (5) The imaging device according to any one of (1) to (4) above, further comprising a transfer control electrode interposed between the first electrode and the third electrode. (6) The image forming apparatus according to (5) above, wherein a potential applied to the transfer control electrode is smaller than a potential applied to the third electrode during a charge storage operation. (7) The imaging device according to any one of (5) to (6) above, wherein the substrate includes a third photoelectric conversion unit, and wherein the first photoelectric conversion unit, the second photoelectric conversion unit, and the first photoelectric conversion unit Each of the three photoelectric conversion units is coupled to a separate signal line. (8) The imaging device according to any one of (1) to (7) above, further comprising a charge emitting electrode separated and separated from the first electrode and the third electrode, wherein the photoelectric The conversion layer contacts the charge exit electrode. (9) The imaging device according to (8) above, wherein the charge emitting electrode surrounds the first electrode and the third electrode. (10) The imaging device according to any one of (1) to (9) above, further comprising a plurality of third electrode segments. (11) The imaging device according to (10) above, wherein a potential of a third electrode segment located at a position closest to the first electrode is greater than that of a third electrode segment located at a position farthest from the first electrode A potential of a third electrode segment. (12) The imaging device according to any one of (1) to (11) above, wherein the photoelectric conversion layer includes a stacked layer structure including a lower semiconductor layer and an upper photoelectric conversion layer. (13) The image forming apparatus according to (12) above, wherein a material composition of the lower semiconductor layer over the third electrode is different from a material composition of the lower semiconductor layer over the first electrode. (14) The imaging device according to any one of (12) to (13) above, wherein the lower semiconductor layer includes an indium-containing oxide. (15) The imaging device according to any one of (1) to (14) above, wherein a potential applied to the third electrode is greater than a potential applied to the first electrode during a charge storage period. (16) The imaging device according to any one of (1) to (15) above, wherein at least a portion of the insulating material is disposed over the first electrode. (17) The image forming device according to (16) above, wherein as a distance between the first electrode and the third electrode decreases, a surface between the upper surface of the first electrode and the photoelectric conversion layer is A thickness of the insulating material increases at a third electrode side of the first electrode. (18) The imaging device according to any one of (1) to (17) above, wherein the imaging device is a backside illumination type imaging device. (19) An electronic device comprising: an imaging device comprising: a substrate including a first photoelectric conversion unit; and a second photoelectric conversion unit located at a light incident side of the substrate, The second photoelectric conversion unit includes: a photoelectric conversion layer; a first electrode; a second electrode located above the photoelectric conversion layer; a third electrode; and an insulating material between the third electrode and the between photoelectric conversion layers, wherein a portion of the insulating material is interposed between the first electrode and the third electrode; a lens configured to direct light onto a surface of the imaging device; and circuitry, which is configured to control output signals from the imaging device. (20) A method of driving an imaging device, the method comprising: applying a first potential to a charge storage electrode during a charging cycle; applying a second potential to a first electrode during a charging cycle, wherein the first potential is greater than the second potential; a third potential is applied to the charge storage electrode during a charge transfer period; and a fourth potential is applied to the first electrode during the charge transfer period, wherein the The fourth potential is greater than the third potential, and wherein the imaging device includes: a substrate including a first photoelectric conversion unit; and a second photoelectric conversion unit located at a light incident side of the substrate, the second photoelectric conversion unit The photoelectric conversion unit comprises: a photoelectric conversion layer; the first electrode; a second electrode located above the photoelectric conversion layer; the charge storage electrode; and an insulating material between the charge storage electrode and the photoelectric conversion layer wherein a portion of the insulating material is interposed between the first electrode and the charge storage electrode. (A01) <<Imaging Element>> An imaging device comprising: a photoelectric conversion unit configured by stacking a first electrode, a photoelectric conversion layer, and a second electrode, wherein the photoelectric conversion unit further includes A charge storage electrode configured to be separated from the first electrode and configured to face the photoelectric conversion layer through an insulating layer. (A02) The imaging element according to (A01), further comprising a semiconductor substrate, wherein the photoelectric conversion unit is disposed above the semiconductor substrate. (A03) The imaging element according to (A01) or (A02), wherein the first electrode extends in an opening portion arranged to the insulating layer to be connected to the photoelectric conversion layer. (A04) According to (A01) or (A02 ), wherein the photoelectric conversion layer extends in an opening portion provided to the insulating layer to be connected to the first electrode. (A05) The imaging element according to (A04), wherein a top surface of the first electrode An edge is covered with the insulating layer, the first electrode is exposed on a bottom surface of the opening portion, and when a surface of the insulating layer in contact with the top surface of the first electrode is defined by a first surface and the When a surface of the insulating layer in contact with a portion of the photoelectric conversion layer (which faces the charge storage electrode) is defined by a second surface, a side surface of the opening portion has a surface extending from the first surface toward the second surface. A slope. (A06) The imaging element according to (A05), wherein the side surface of the opening portion having the slope extending from the first surface toward the second surface is located in a charge storage electrode side. (A07) <<Control of the potential of the first electrode and the charge storage electrode>> The imaging element according to any one of (A01) to (A06), further comprising a control unit provided to a semiconductor substrate and comprising a driver circuit, wherein the first electrode and the charge storage electrode are connected to the drive circuit, during a charge storage cycle, from the drive circuit, a potential V 11 applied to the first electrode and a potential V 12 Applied to the charge storage electrode, so that the charge is stored in the photoelectric conversion layer, and in a charge transfer cycle, from the drive circuit, a potential V twenty one applied to the first electrode and a potential V twenty two applied to the charge storage electrode, so that the charges stored in the photoelectric conversion layer are read out to the control unit through the first electrode, wherein a potential of the first electrode is higher than that of the second electrode In the case of potential, V 12 ≥ V 11 , and V twenty two < V twenty one , and in the case where the potential of the first electrode is lower than the potential of the second electrode, V 12 ≤ V 11 and V twenty two > V twenty one . (A08) <<Transfer Control Electrode>> The imaging element according to any one of (A01) to (A06), further comprising a transfer control electrode disposed between the first electrode and the charge storage electrode and is separated from the first electrode and the charge storage electrode and configured to face the photoelectric conversion layer through the insulating layer. (A09) <<Control of the potentials of the first electrode, the charge storage electrode and the transfer control electrode>> The imaging element according to (A08), further comprising a control unit provided to a semiconductor substrate and comprising a driver circuit, wherein the first electrode, the charge storage electrode and the transfer control electrode are connected to the drive circuit, and in a charge storage period, from the drive circuit, a potential V 11 Applied to the first electrode, a potential V 12 applied to the charge storage electrode and a potential V 13 applied to the transfer control electrode, so that charges are stored in the photoelectric conversion layer, and in a charge transfer cycle, from the drive circuit, a potential V twenty one Applied to the first electrode, a potential V twenty two applied to the charge storage electrode and a potential V twenty three applied to the transfer control electrode, so that the charges stored in the photoelectric conversion layer are read out to the control unit through the first electrode, wherein a potential of the first electrode is higher than that of the second electrode In the case of potential, V 12 > V 13 and V twenty two ≤ V twenty three ≤ V twenty one , and in the case where the potential of the first electrode is lower than the potential of the second electrode, V 12 < V 13 and V twenty two ≥ V twenty three ≥ V twenty one . (A10) <<Charge extraction electrode>> The imaging element according to any one of (A01) to (A09), further comprising a charge extraction electrode connected to the photoelectric conversion layer and configured to communicate with the photoelectric conversion layer The first electrode and the charge storage electrode are separated. (A11) The imaging element according to (A10), wherein the charge emitting electrode is configured to surround the first electrode and the charge storage electrode. (A12) The imaging element according to (A10) or (A11), wherein the photoelectric conversion layer extends in a second opening portion provided to the insulating layer to be connected to the charge emitting electrode, a top surface of the charge emitting electrode An edge is covered with the insulating layer, the charge emitting electrode is exposed on a bottom surface of the second opening portion, and a surface of the insulating layer in contact with the top surface of the charge emitting electrode is defined by a third surface And when a surface of the insulating layer in contact with a portion of the photoelectric conversion layer (which faces the charge storage electrode) is defined by a second surface, a side surface of the second opening portion has a direction from the third surface toward the first surface. One of the two surface extensions slopes. (A13) <<Control of the potentials of the first electrode, the charge storage electrode, and the charge emitting electrode>> The imaging element according to any one of (A10) to (A12), further comprising a control unit configured to to the semiconductor substrate and has a drive circuit, wherein the first electrode, the charge storage electrode and the charge emitting electrode are connected to the drive circuit, during a charge storage period, from the drive circuit, a potential V 11 Applied to the first electrode, a potential V 12 applied to the charge storage electrode and a potential V 14 Applied to the charge emitting electrode, so that the charge is stored in the photoelectric conversion layer, in a charge transfer cycle, from the driving circuit, a potential V twenty one Applied to the first electrode, a potential V twenty two applied to the charge storage electrode and a potential V twenty four applied to the charge emitting electrode, so that the charges stored in the photoelectric conversion layer are read out to the control unit through the first electrode, wherein a potential of the first electrode is higher than that of the second electrode In the case of potential, V 14 > V 11 and V twenty four < V twenty one , and in the case where the potential of the first electrode is lower than the potential of the second electrode, V 14 < V 11 and V twenty four > V twenty one . (A14) <<Charge Storage Electrode Segments>> The imaging element according to any one of (A01) to (A13), wherein the charge storage electrode is configured with a plurality of charge storage electrode segments. (A15) The imaging element according to (A14), wherein in a case where a potential of the first electrode is higher than a potential of the second electrode, in a charge transfer period, applied to A potential of the charge storage electrode segment at the location of the electrode is higher than a potential applied to the charge storage electrode segment at a location furthest from the first electrode, and in which the potential of the first electrode In the case of being lower than the potential of the second electrode, the potential applied to the segment of the charge storage electrode at the position closest to the first electrode during the charge transfer period is lower than the potential applied to the segment of the charge storage electrode at the position closest to the first electrode. the potential of the charge storage electrode segment at the location furthest from the first electrode. (B01) The imaging element according to any one of (A01) to (A15), wherein at least a floating diffusion layer and an amplification transistor constituting a control unit are provided to a semiconductor substrate, and the first electrode is connected to the floating The diffusion layer and a gate portion of the amplifying transistor. (B02) The imaging device according to (B01), wherein a reset transistor and a selection transistor constituting the control unit are further provided to the semiconductor substrate, and the floating diffusion layer is connected to a source/drain of the reset transistor region, and a source/drain region of the amplifying transistor is connected to a source/drain region of the selection transistor, and the other source/drain region of the selection transistor is connected to a signal line. (B03) The imaging element according to any one of (A01) to (B02), wherein the charge storage electrode is larger than the first electrode. (B04) The imaging element according to any one of (A01) to (B03), wherein light is incident from a second electrode side, and a light shielding layer is formed in a light incident side of the second electrode. (B05) The imaging element according to any one of (A01) to (B03), wherein light is incident from a second electrode side, and light is not incident on the first electrode. (B06) The imaging element according to (B05), wherein a light shielding layer is formed over the first electrode as a light incident side of the second electrode. (B07) The imaging device according to (B05), wherein an on-wafer microlens is disposed over the charge storage electrode and the second electrode, and light incident on the on-wafer microlens is collected in the charge storage electrode. (C01) <<Stacked Imaging Element>> A stacked imaging element including at least one imaging element according to any one of (A01) to (B07). (D01) <<Solid-state imaging device ... first embodiment>> A solid-state imaging device including a plurality of imaging elements according to any one of (A01) to (B04). (D02) <<Solid-State Imaging Device...Second Embodiment>> A solid-state imaging device including a plurality of stacked imaging elements according to (C01). (E01) <<Driving Method for Solid-State Imaging Device>> A driving method for a solid-state imaging device having a plurality of imaging elements having a structure including a photoelectric conversion a unit configured by stacking a first electrode, a photoelectric conversion layer, and a second electrode, the photoelectric conversion unit further comprising a charge storage electrode configured to be separated from the first electrode and Configured to face the photoelectric conversion layer through an insulating layer, and light is incident from a second electrode side, and light is not incident on the first electrode, the driving method includes repeatedly performing the following operations: Simultaneously on all imaging elements In the photoelectric conversion layer, the electric charge is stored in the photoelectric conversion layer, and the electric charge of the first electrode is emitted to the outside; meanwhile, in all imaging elements, the electric charge stored in the photoelectric conversion layer is transferred to the first electrode; and in the After the transfer is completed, the charges transferred to the first electrodes in the respective imaging elements are sequentially read out.

11:第一電極 12:電荷儲存電極 12A:電荷儲存電極分段 12B:電荷儲存電極分段 12C:電荷儲存電極分段 13:轉移控制電極/電荷轉移電極 13A:轉移控制電極/電荷轉移電極 13B:轉移控制電極/電荷轉移電極 14:電荷射出電極 15:光電轉換層 15A:下部半導體層 15B:上部光電轉換層 16:第二電極 41:n型半導體區域/構成第二成像元件之n型半導體區域 42:p+層 43:n型半導體區域/構成第三成像元件之n型半導體區域 44:p+層 45:閘極部分/轉移電晶體之閘極部分 45C:區域/浮動擴散層 46:閘極部分/轉移電晶體之閘極部分 46A:轉移通道 46C:區域/浮動擴散層 51:閘極部分/重設電晶體TR1 rst之閘極部分 51A:通道形成區域/重設電晶體TR1 rst之通道形成區域 51B:源極/汲極區域/重設電晶體TR1 rst之源極/汲極區域 51C:源極/汲極區域/重設電晶體TR1 rst之源極/汲極區域 52:閘極部分/放大電晶體TR1 amp之閘極部分 52A:通道形成區域/放大電晶體TR1 amp之通道形成區域 52B:源極/汲極區域/放大電晶體TR1 amp之源極/汲極區域 52C:源極/汲極區域/放大電晶體TR1 amp之源極/汲極區域 53:閘極部分/選擇電晶體TR1 sel之閘極部分 53A:通道形成區域/選擇電晶體TR1 sel之通道形成區域 53B:源極/汲極區域/選擇電晶體TR1 sel之源極/汲極區域 53C:源極/汲極區域/選擇電晶體TR1 sel之源極/汲極區域 61:接觸孔部分 62:導線層 63:墊部分 64:墊部分 65:連接孔 66:連接孔 67:連接部分 68A:墊部分 68B:連接孔 69:連接部分 70:半導體基板/矽半導體層 70A:第一表面/前表面/表面/第一表面(前表面)半導體基板 70B:後表面/第二表面(後表面)半導體基板 71:元件隔離區域 72:氧化物膜 73:p+層 74:HfO 2膜 75:絕緣膜 76:層間絕緣層 77:層間絕緣層 78:層間絕緣層 81:層間絕緣層 82:絕緣層/絕緣材料 82a:第一表面/絕緣層之第一表面 82b:第二表面/絕緣層之第二表面 82c:第三表面/絕緣層之第三表面 82E:層/第一絕緣層/絕緣層 82F:層/第二絕緣層 83:保護層 84:開口部分 84B:開口部分 84C:開口部分 85:第二開口部分 85A:第二開口部分 90:晶片上微透鏡 91:成像元件之位於層間絕緣層81下方之各種組件 92:光屏蔽層 100:固態成像裝置 101:堆疊型成像元件 111:成像區域 112:垂直驅動電路 113:行信號處理電路 114:水平驅動電路 115:輸出電路 116:驅動控制電路 117:信號線/資料輸出線 118:水平信號線 200:電子設備/相機 201:固態成像裝置 210:光學透鏡 211:快門裝置 212:驅動電路 213:信號處理電路 310:第一成像元件 311:第一光電轉換單元/第一電極 315:光電轉換層 316:第二電極 317:閘極部分 318:閘極部分 320:第二成像元件 321:第二光電轉換單元 322:閘極部分 330:第三成像元件 331:第三光電轉換單元 332:閘極部分 361:接觸孔部分 362:導線層 370:半導體基板 371:元件隔離區域 372:氧化物膜 376:層間絕緣層 381:層間絕緣層 383:保護層 390:晶片上微透鏡 FD:電位 FD 1:第一浮動擴散層/浮動擴散層 FD 2:第二浮動擴散層/浮動擴散層 FD 3:第三浮動擴散層/浮動擴散層 PA:點/電位 PB:點/電位 PC:點/電位 PD:點/電位 RST:電位 RST 1:重設線 RST 2:重設線 RST 3:重設線 SEL 1:選擇線 SEL 2:選擇線 SEL 3:選擇線 TG 2:轉移閘極線 TG 3:轉移閘極線 TR1_amp:放大電晶體TR1 ampTR1_rst:重設電晶體TR1 rstTR1_sel:選擇電晶體TR1 selTR1 amp:放大電晶體 TR1 rst:重設電晶體 TR1 sel:選擇電晶體 TR1 SEL:選擇電晶體 TR2 amp:放大電晶體 TR2 rst:重設電晶體 TR2 sel:選擇電晶體 TR2 trs:轉移電晶體 TR3 amp:放大電晶體 TR3 rst:重設電晶體 TR3 sel:選擇電晶體 TR3 trs:轉移電晶體 V DD:電源 VDD:電位 V OA:導線 VOA:電位 VOA-A:電位 VOA-B:電位 VOA-C:電位 V OT:導線 VOT:電位 V OU:導線 VSL_1:信號線(資料輸出線) VSL 1VSL 1:信號線/資料輸出線 VSL 2:信號線/資料輸出線 VSL 3:信號線/資料輸出線 11: first electrode 12: charge storage electrode 12A: charge storage electrode segment 12B: charge storage electrode segment 12C: charge storage electrode segment 13: transfer control electrode/charge transfer electrode 13A: transfer control electrode/charge transfer electrode 13B : transfer control electrode/charge transfer electrode 14: charge emitting electrode 15: photoelectric conversion layer 15A: lower semiconductor layer 15B: upper photoelectric conversion layer 16: second electrode 41: n-type semiconductor region/n-type semiconductor constituting the second imaging element Region 42: p+ layer 43: n-type semiconductor region/n-type semiconductor region constituting the third imaging element 44: p+ layer 45: gate portion/gate portion of transfer transistor 45C: region/floating diffusion layer 46: gate part/gate part 46A of transfer transistor: transfer channel 46C: region/floating diffusion layer 51: gate part/gate part 51A of reset transistor TR1 rst : channel forming region/channel of reset transistor TR1 rst Formation area 51B: source/drain area/source/drain area of reset transistor TR1 rst 51C: source/drain area/source/drain area of reset transistor TR1 rst 52: gate Part/Gate part 52A of amplifier transistor TR1 amp : channel formation area/channel formation area 52B of amplifier transistor TR1 amp : source/drain area/source/drain area of amplifier transistor TR1 amp 52C: source electrode/drain region/source/drain region 53 of amplifying transistor TR1 amp : gate part/gate part 53A of selection transistor TR1 sel : channel formation region/channel formation region 53B of selection transistor TR1 sel : source/drain region/source/drain region 53C of selection transistor TR1 sel : source/drain region/source/drain region of selection transistor TR1 sel 61: contact hole portion 62: wire layer 63 : pad part 64: pad part 65: connection hole 66: connection hole 67: connection part 68A: pad part 68B: connection hole 69: connection part 70: semiconductor substrate/silicon semiconductor layer 70A: first surface/front surface/surface/ First surface (front surface) semiconductor substrate 70B: rear surface/second surface (rear surface) semiconductor substrate 71: element isolation region 72: oxide film 73: p+ layer 74: HfO 2 film 75: insulating film 76: interlayer insulation Layer 77: interlayer insulating layer 78: interlayer insulating layer 81: interlayer insulating layer 82: insulating layer/insulating material 82a: first surface/first surface of insulating layer 82b: second surface/second surface of insulating layer 82c: first surface Three surfaces/third surface of insulating layer 82E: layer/first insulating layer/insulating layer 82F: layer/second insulating layer 83: protective layer 84: opening portion 84B: opening portion 84C: opening portion 85: second opening portion 85A: Second opening portion 90: On-wafer microlens 91: Imaging element on the interlayer insulating layer 8 1. Various components below 92: Light shielding layer 100: Solid-state imaging device 101: Stacked imaging element 111: Imaging area 112: Vertical drive circuit 113: Line signal processing circuit 114: Horizontal drive circuit 115: Output circuit 116: Drive control circuit 117: signal line/data output line 118: horizontal signal line 200: electronic equipment/camera 201: solid-state imaging device 210: optical lens 211: shutter device 212: driving circuit 213: signal processing circuit 310: first imaging element 311: first A photoelectric conversion unit/first electrode 315: photoelectric conversion layer 316: second electrode 317: gate portion 318: gate portion 320: second imaging element 321: second photoelectric conversion unit 322: gate portion 330: third Imaging element 331: Third photoelectric conversion unit 332: Gate portion 361: Contact hole portion 362: Wire layer 370: Semiconductor substrate 371: Element isolation region 372: Oxide film 376: Interlayer insulating layer 381: Interlayer insulating layer 383: Protection Layer 390: On-wafer microlenses FD: Potential FD 1 : First floating diffusion layer/Floating diffusion layer FD 2 : Second floating diffusion layer/Floating diffusion layer FD 3 : Third floating diffusion layer/Floating diffusion layer PA: Dot/ Potential PB: Dot/potential PC: Dot/potential PD: Dot/potential RST: Potential RST 1 : Reset line RST 2 : Reset line RST 3 : Reset line SEL 1 : Select line SEL 2 : Select line SEL 3 : Selection line TG2: Transfer gate line TG3: Transfer gate line TR1_amp : Amplifying transistor TR1 amp TR1_rst : Reset transistor TR1 rst TR1_sel: Selecting transistor TR1 sel TR1 amp : Amplifying transistor TR1 rst : Reset transistor Transistor TR1 sel : Select transistor TR1 SEL : Select transistor TR2 amp : Amplify transistor TR2 rst : Reset transistor TR2 sel : Select transistor TR2 trs : Transfer transistor TR3 amp : Amplify transistor TR3 rst : Reset transistor Crystal TR3 sel : Selection transistor TR3 trs : Transfer transistor V DD : Power supply VDD: Potential V OA : Wire VOA: Potential VOA-A: Potential VOA-B: Potential VOA-C: Potential V OT : Wire VOT: Potential V OU : Conductor VSL_1: Signal Line (Data Output Line) VSL 1 VSL 1 : Signal Line/Data Output Line VSL 2 : Signal Line/Data Output Line VSL 3 : Signal Line/Data Output Line

[圖1A至圖1D] 圖1A至圖1D係實例1之一成像元件及一堆疊型成像元件之示意性部分剖面圖。 [圖2] 圖2係實例1之成像元件及堆疊型成像元件之一等效電路圖。 [圖3] 圖3係實例1之成像元件及堆疊型成像元件之一等效電路圖。 [圖4] 圖4係構成實例1之成像元件之一第一電極及一電荷儲存電極以及構成一控制單元之電晶體之一示意性佈局圖。 [圖5] 圖5係圖解說明處於實例1之成像元件之一操作週期中之組件之電位狀態的一圖式。 [圖6] 圖6係構成實例1之成像元件之第一電極及電荷儲存電極之一示意性佈局圖。 [圖7] 圖7係構成實例1之成像元件之第一電極、電荷儲存電極、一第二電極及一接觸孔部分之一示意性透視圖。 [圖8] 圖8係實例1之一固態成像裝置之一概念圖式。 [圖9] 圖9係實例1之成像元件及堆疊型成像元件之一經修改實例之一等效電路圖。 [圖10] 圖10係圖9中所圖解說明之構成實例1之成像元件之經修改實例之一第一電極及一電荷儲存電極以及構成一控制單元之電晶體之一示意性佈局圖。 [圖11] 圖11係實例2之一成像元件及一堆疊型成像元件之一示意性部分剖面圖。 [圖12] 圖12係實例3之一成像元件及一堆疊型成像元件之一示意性部分剖面圖。 [圖13] 圖13係實例3之成像元件及堆疊型成像元件之一經修改實例之一示意性部分剖面圖。 [圖14] 圖14係實例3之成像元件之另一經修改實例之一示意性部分剖面圖。 [圖15A至圖15D] 圖15A至圖15D係實例3之成像元件之另一經修改實例之示意性部分剖面圖。 [圖16] 圖16係實例4之一成像元件及一堆疊型成像元件之一部分之一示意性部分剖面圖。 [圖17] 圖17係實例4之成像元件及堆疊型成像元件之一等效電路圖。 [圖18] 圖18係實例4之成像元件及堆疊型成像元件之一等效電路圖。 [圖19] 圖19係構成實例4之成像元件之一第一電極、一轉移控制電極及一電荷儲存電極以及構成一控制單元之電晶體之一示意性佈局圖。 [圖20] 圖20係圖解說明處於實例4之成像元件之一操作週期中之組件之電位狀態的一圖式。 [圖21] 圖21係圖解說明處於實例4之成像元件之另一操作週期中之組件之電位狀態的一圖式。 [圖22] 圖22係構成實例4之成像元件之第一電極、轉移控制電極及電荷儲存電極之一示意性佈局圖。 [圖23] 圖23係構成實例4之成像元件之第一電極、轉移控制電極、電荷儲存電極及一第二電極以及一接觸孔部分之一示意性透視圖。 [圖24] 圖24係構成實例4之成像元件之一經修改實例之一第一電極、一轉移控制電極及一電荷儲存電極以及構成一控制單元之電晶體之一示意性佈局圖。 [圖25] 圖25係實例5之一成像元件及一堆疊型成像元件之一部分之一示意性部分剖面圖。 [圖26] 圖26係構成實例5之成像元件之一第一電極、一電荷儲存電極及一電荷射出電極之一示意性佈局圖。 [圖27] 圖27係構成實例5之成像元件之第一電極、電荷儲存電極、電荷射出電極、一第二電極及一接觸孔部分之一示意性透視圖。 [圖28] 圖28係實例6之一成像元件及一堆疊型成像元件之一部分之一示意性部分剖面圖。 [圖29] 圖29係實例6之成像元件及堆疊型成像元件之一等效電路圖。 [圖30] 圖30係實例6之成像元件及堆疊型成像元件之一等效電路圖。 [圖31] 圖31係構成實例6之成像元件之一第一電極及一電荷儲存電極以及構成一控制單元之電晶體之一示意性佈局圖。 [圖32] 圖32係圖解說明處於實例6之成像元件之一操作週期中之組件之電位狀態的一圖式。 [圖33] 圖33係圖解說明處於實例6之成像元件之另一操作週期(轉移週期)中之組件之電位狀態的一圖式。 [圖34] 圖34係構成實例6之成像元件之第一電極及電荷儲存電極之一示意性佈局圖。 [圖35] 圖35係構成實例6之成像元件之第一電極、電荷儲存電極、一第二電極及一接觸孔部分之一示意性透視圖。 [圖36] 圖36係構成實例6之成像元件之一經修改實例之一第一電極及一電荷儲存電極之一示意性佈局圖。 [圖37] 圖37係實例1之成像元件及堆疊型成像元件之另一經修改實例之一示意性部分剖面圖。 [圖38] 圖38係實例1之成像元件及堆疊型成像元件之另一經修改實例之一示意性部分剖面圖。 [圖39A至圖39C] 圖39A、圖39B及圖39C係實例1之成像元件及堆疊型成像元件之另一經修改實例之一第一電極及諸如此類之一部分的示意性放大部分剖面圖。 [圖40] 圖40係實例5之成像元件及堆疊型成像元件之另一經修改實例之一電荷射出電極及諸如此類之一部分的一示意性放大部分剖面圖。 [圖41] 圖41係實例1之成像元件及堆疊型成像元件之另一經修改實例之一示意性部分剖面圖。 [圖42] 圖42係實例1之成像元件及堆疊型成像元件之另一經修改實例之一示意性部分剖面圖。 [圖43] 圖43係實例1之成像元件及堆疊型成像元件之另一經修改實例之一示意性部分剖面圖。 [圖44] 圖44係實例4之成像元件及堆疊型成像元件之另一經修改實例之一示意性部分剖面圖。 [圖45] 圖45係實例1之成像元件及堆疊型成像元件之另一經修改實例之一示意性部分剖面圖。 [圖46A至圖46D] 圖46A至圖46D係實例1之成像元件及堆疊型成像元件之另一經修改實例之示意性部分剖面圖。 [圖47] 圖47係實例4之成像元件及堆疊型成像元件之另一經修改實例之一示意性部分剖面圖。 [圖48] 圖48係根據本發明之一實施例之使用組態有成像元件及堆疊型成像元件之一固態成像裝置之一電子設備(相機)之一實例的一概念圖式。 [圖49] 圖49係相關技術中之一堆疊型成像元件(堆疊型固態成像裝置)之一概念圖式。 [Fig. 1A to Fig. 1D] 1A to 1D are schematic partial cross-sectional views of an imaging element and a stacked imaging element of Example 1. FIG. [figure 2] FIG. 2 is an equivalent circuit diagram of the imaging element and the stacked imaging element of Example 1. FIG. [image 3] 3 is an equivalent circuit diagram of the imaging element and the stacked imaging element of Example 1. FIG. [Figure 4] 4 is a schematic layout diagram of a first electrode and a charge storage electrode constituting the imaging element of Example 1 and a transistor constituting a control unit. [Figure 5] 5 is a diagram illustrating the potential states of components during one cycle of operation of the imaging element of Example 1. FIG. [Image 6] 6 is a schematic layout diagram of the first electrode and the charge storage electrode constituting the imaging element of Example 1. FIG. [Figure 7] 7 is a schematic perspective view of a first electrode, a charge storage electrode, a second electrode, and a contact hole portion constituting the imaging element of Example 1. FIG. [Figure 8] FIG. 8 is a conceptual diagram of a solid-state imaging device of Example 1. FIG. [Figure 9] 9 is an equivalent circuit diagram of the imaging element of Example 1 and a modified example of the stacked imaging element. [Figure 10] 10 is a schematic layout diagram of a first electrode and a charge storage electrode and a transistor constituting a control unit of a modified example of the imaging element constituting Example 1 illustrated in FIG. 9 . [Figure 11] 11 is a schematic partial cross-sectional view of an imaging element and a stacked imaging element of Example 2. FIG. [Figure 12] 12 is a schematic partial cross-sectional view of an imaging element and a stacked imaging element of Example 3. FIG. [Figure 13] 13 is a schematic partial cross-sectional view of the imaging element of Example 3 and a modified example of the stacked imaging element. [Figure 14] 14 is a schematic partial cross-sectional view of another modified example of the imaging element of Example 3. FIG. [Fig. 15A to Fig. 15D] 15A-15D are schematic partial cross-sectional views of another modified example of the imaging element of Example 3. FIG. [Figure 16] 16 is a schematic partial cross-sectional view of an imaging element of Example 4 and a portion of a stacked imaging element. [Figure 17] FIG. 17 is an equivalent circuit diagram of the imaging element and the stacked imaging element of Example 4. FIG. [Figure 18] 18 is an equivalent circuit diagram of the imaging element and the stacked imaging element of Example 4. FIG. [Figure 19] 19 is a schematic layout diagram of a first electrode, a transfer control electrode, and a charge storage electrode constituting the imaging element of Example 4, and a transistor constituting a control unit. [Figure 20] 20 is a diagram illustrating the potential states of components during one cycle of operation of the imaging element of Example 4. FIG. [Figure 21] 21 is a diagram illustrating the potential states of components in another cycle of operation of the imaging element of Example 4. FIG. [Figure 22] 22 is a schematic layout diagram of a first electrode, a transfer control electrode, and a charge storage electrode constituting the imaging element of Example 4. FIG. [Figure 23] 23 is a schematic perspective view of the first electrode, the transfer control electrode, the charge storage electrode, and a second electrode and a contact hole portion constituting the imaging element of Example 4. FIG. [Figure 24] 24 is a schematic layout diagram of a first electrode, a transfer control electrode, and a charge storage electrode, and transistors constituting a control unit, constituting a modified example of the imaging element of Example 4. FIG. [Figure 25] 25 is a schematic partial cross-sectional view of an imaging element of Example 5 and a portion of a stacked imaging element. [Figure 26] 26 is a schematic layout diagram of a first electrode, a charge storage electrode, and a charge emitting electrode constituting the imaging element of Example 5. FIG. [Figure 27] 27 is a schematic perspective view of a first electrode, a charge storage electrode, a charge emitting electrode, a second electrode, and a contact hole portion constituting the imaging element of Example 5. FIG. [Figure 28] 28 is a schematic partial cross-sectional view of an imaging element of Example 6 and a portion of a stacked imaging element. [Figure 29] FIG. 29 is an equivalent circuit diagram of the imaging element and the stacked imaging element of Example 6. FIG. [Figure 30] 30 is an equivalent circuit diagram of the imaging element and the stacked imaging element of Example 6. FIG. [Figure 31] 31 is a schematic layout diagram of a first electrode and a charge storage electrode constituting the imaging element of Example 6 and a transistor constituting a control unit. [Figure 32] 32 is a graph illustrating the potential states of components during one cycle of operation of the imaging element of Example 6. FIG. [Figure 33] 33 is a diagram illustrating potential states of components in another operation cycle (transfer cycle) of the imaging element of Example 6. FIG. [Figure 34] 34 is a schematic layout diagram of the first electrode and the charge storage electrode constituting the imaging element of Example 6. FIG. [Figure 35] 35 is a schematic perspective view of a first electrode, a charge storage electrode, a second electrode, and a contact hole portion constituting the imaging element of Example 6. FIG. [Figure 36] 36 is a schematic layout diagram of a first electrode and a charge storage electrode constituting a modified example of the imaging element of Example 6. FIG. [Figure 37] 37 is a schematic partial cross-sectional view of another modified example of the imaging element of Example 1 and the stacked imaging element. [Figure 38] 38 is a schematic partial cross-sectional view of the imaging element of Example 1 and another modified example of the stacked imaging element. [Fig. 39A to Fig. 39C] 39A, 39B, and 39C are schematic enlarged partial cross-sectional views of a portion of a first electrode and the like of the imaging element of Example 1 and another modified example of the stacked imaging element. [Figure 40] 40 is a schematic enlarged partial cross-sectional view of a portion of a charge emitting electrode and the like of the imaging element of Example 5 and another modified example of the stacked imaging element. [Figure 41] 41 is a schematic partial cross-sectional view of the imaging element of Example 1 and another modified example of the stacked imaging element. [Figure 42] 42 is a schematic partial cross-sectional view of the imaging element of Example 1 and another modified example of the stacked imaging element. [Figure 43] 43 is a schematic partial cross-sectional view of the imaging element of Example 1 and another modified example of the stacked imaging element. [Figure 44] 44 is a schematic partial cross-sectional view of the imaging element of Example 4 and another modified example of the stacked imaging element. [Figure 45] 45 is a schematic partial cross-sectional view of the imaging element of Example 1 and another modified example of the stacked imaging element. [Fig. 46A to Fig. 46D] 46A-46D are schematic partial cross-sectional views of the imaging element of Example 1 and another modified example of the stacked imaging element. [Figure 47] 47 is a schematic partial cross-sectional view of the imaging element of Example 4 and another modified example of the stacked imaging element. [Figure 48] 48 is a conceptual diagram of an example of an electronic device (camera) using a solid-state imaging device configured with an imaging element and a stacked imaging element according to an embodiment of the present invention. [Figure 49] FIG. 49 is a conceptual diagram of a stack-type imaging element (stack-type solid-state imaging device) in the related art.

11:第一電極 11: The first electrode

12:電荷儲存電極 12: Charge storage electrode

15:光電轉換層 15: Photoelectric conversion layer

16:第二電極 16: Second electrode

41:n型半導體區域/構成第二成像元件之n型半導體區域 41: n-type semiconductor region/n-type semiconductor region constituting the second imaging element

42:p+層 42:p+ layer

43:n型半導體區域/構成第三成像元件之n型半導體區域 43: n-type semiconductor region/n-type semiconductor region constituting the third imaging element

44:p+層 44:p+ layer

45:閘極部分/轉移電晶體之閘極部分 45: gate part/gate part of transfer transistor

45C:區域/浮動擴散層 45C: Area/Floating Diffusion Layer

46:閘極部分/轉移電晶體之閘極部分 46: gate part/gate part of transfer transistor

46A:轉移通道 46A: Transfer channel

46C:區域/浮動擴散層 46C: Area/Floating Diffusion Layer

51:閘極部分/重設電晶體TR1rst之閘極部分 51: gate part/gate part of reset transistor TR1 rst

51A:通道形成區域/重設電晶體TR1rst之通道形成區域 51A: channel formation area/channel formation area of reset transistor TR1 rst

51B:源極/汲極區域/重設電晶體TR1rst之源極/汲極區域 51B: source/drain area/source/drain area of reset transistor TR1 rst

51C:源極/汲極區域/重設電晶體TR1rst之源極/汲極區域 51C: source/drain area/reset source/drain area of transistor TR1 rst

52:閘極部分/放大電晶體TR1amp之閘極部分 52: gate part/gate part of amplifier transistor TR1 amp

52A:通道形成區域/放大電晶體TR1amp之通道形成區域 52A: Channel forming area/channel forming area of amplifier transistor TR1 amp

52B:源極/汲極區域/放大電晶體TR1amp之源極/汲極區域 52B: source/drain area/source/drain area of amplifying transistor TR1 amp

52C:源極/汲極區域/放大電晶體TR1amp之源極/汲極區域 52C: source/drain area/source/drain area of amplifying transistor TR1 amp

53:閘極部分/選擇電晶體TR1sel之閘極部分 53: gate part/gate part of selection transistor TR1 sel

53A:通道形成區域/選擇電晶體TR1sel之通道形成區域 53A: Channel formation area/channel formation area of selection transistor TR1 sel

53B:源極/汲極區域/選擇電晶體TR1sel之源極/汲極區域 53B: source/drain area/source/drain area of selection transistor TR1 sel

53C:源極/汲極區域/選擇電晶體TR1sel之源極/汲極區域 53C: source/drain area/source/drain area of selection transistor TR1 sel

61:接觸孔部分 61: Contact hole part

62:導線層 62: wire layer

63:墊部分 63: Pad part

64:墊部分 64: Pad part

65:連接孔 65: Connection hole

66:連接孔 66: Connection hole

67:連接部分 67: Connection part

70:半導體基板/矽半導體層 70: Semiconductor substrate/silicon semiconductor layer

70A:第一表面/前表面/表面/第一表面(前表面)半導體基板 70A: First Surface/Front Surface/Surface/First Surface (Front Surface) Semiconductor Substrate

70B:後表面/第二表面(後表面)半導體基板 70B: Back Surface/Second Surface (Back Surface) Semiconductor Substrate

71:元件隔離區域 71: Component isolation area

72:氧化物膜 72: oxide film

73:p+層 73: p+ layer

74:HfO2膜 74: HfO 2 film

75:絕緣膜 75: insulating film

76:層間絕緣層 76: Interlayer insulating layer

81:層間絕緣層 81: interlayer insulating layer

82:絕緣層/絕緣材料 82: Insulation layer/insulation material

82E:層/第一絕緣層/絕緣層 82E: layer/first insulating layer/insulating layer

82F:層/第二絕緣層 82F: Layer/Second insulating layer

83:保護層 83: Protective layer

84:開口部分 84: Opening part

90:晶片上微透鏡 90: On-wafer microlens

TR1amp:放大電晶體 TR1 amp : Amplifying transistor

TR1rst:重設電晶體 TR1 rst : reset transistor

TR1SEL:選擇電晶體 TR1 SEL : select transistor

TR2trs:轉移電晶體 TR2 trs : transfer transistor

TR3trs:轉移電晶體 TR3 trs : transfer transistor

Claims (18)

一種光偵測裝置，其包括： 一基板，其包含一第一光電轉換單元；及 一第二光電轉換單元，其位於該基板之一光入射側處，該第二光電轉換單元包含： 一光電轉換層， 一第一電極， 一第二電極，其位於該光電轉換層上方， 一第三電極， 一絕緣材料，其介於該第三電極與該光電轉換層之間，及 一轉移控制電極，其介於該第一電極與該第三電極之間， 其中該絕緣材料之一部分介於該第一電極與該第三電極之間。 A light detection device, comprising: a substrate including a first photoelectric conversion unit; and A second photoelectric conversion unit located at a light incident side of the substrate, the second photoelectric conversion unit comprising: a photoelectric conversion layer, a first electrode, a second electrode located above the photoelectric conversion layer, a third electrode, an insulating material interposed between the third electrode and the photoelectric conversion layer, and a transfer control electrode between the first electrode and the third electrode, A portion of the insulating material is interposed between the first electrode and the third electrode. 如請求項1之光偵測裝置，其進一步包括： 該絕緣材料之一第一區域，該第一區域介於該第三電極與該光電轉換層之間；及 該絕緣材料之一第二區域，該第二區域介於該第三電極與該第一電極之間，其中該絕緣材料之該第二區域包含具有該絕緣材料之一第一絕緣層及具有該絕緣材料之一第二絕緣層，且其中第一絕緣材料堆疊於第二絕緣材料上。 The light detection device of claim 1, further comprising: a first region of the insulating material, the first region is between the third electrode and the photoelectric conversion layer; and A second region of the insulating material, the second region is between the third electrode and the first electrode, wherein the second region of the insulating material includes a first insulating layer having the insulating material and having the A second insulating layer of insulating material, wherein the first insulating material is stacked on the second insulating material. 如請求項2之光偵測裝置，其中該第二區域中之該第一絕緣層之一部分介於該第一電極與該光電轉換層之間。The light detection device of claim 2, wherein a portion of the first insulating layer in the second region is interposed between the first electrode and the photoelectric conversion layer. 如請求項2之光偵測裝置，其中該第一區域與該第二區域包含不同數目個具有該絕緣材料之絕緣層。The light detection device of claim 2, wherein the first region and the second region comprise different numbers of insulating layers having the insulating material. 如請求項1之光偵測裝置，其中在一電荷儲存操作期間，施加至該轉移控制電極之一電位小於施加至該第三電極之一電位。The light detection device of claim 1, wherein a potential applied to the transfer control electrode is smaller than a potential applied to the third electrode during a charge storage operation. 如請求項1之光偵測裝置，其中該基板包含一第三光電轉換單元，且其中該第一光電轉換單元、該第二光電轉換單元及該第三光電轉換單元中之每一者耦合至分開之信號線。The light detection device of claim 1, wherein the substrate includes a third photoelectric conversion unit, and wherein each of the first photoelectric conversion unit, the second photoelectric conversion unit, and the third photoelectric conversion unit is coupled to separate signal lines. 如請求項1之光偵測裝置，其進一步包括： 一電荷射出電極，其與該第一電極及該第三電極分離且分開，其中該光電轉換層接觸該電荷射出電極。 The light detection device of claim 1, further comprising: A charge emitting electrode, which is separated and separated from the first electrode and the third electrode, wherein the photoelectric conversion layer contacts the charge emitting electrode. 如請求項7之光偵測裝置，其中該電荷射出電極環繞該第一電極及該第三電極。The light detection device of claim 7, wherein the charge emitting electrode surrounds the first electrode and the third electrode. 如請求項1之光偵測裝置，其進一步包括： 複數個第三電極分段。 The light detection device of claim 1, further comprising: a plurality of third electrode segments. 如請求項9之光偵測裝置，其中位於最接近於該第一電極之一位置處之一第三電極分段之一電位大於位於距該第一電極最遠之一位置處之一第三電極分段之一電位。The light detection device of claim 9, wherein a third electrode segment at a position closest to the first electrode has a potential greater than a third electrode segment at a position farthest from the first electrode A potential of one of the electrode segments. 如請求項1之光偵測裝置，其中該光電轉換層包含一堆疊層結構，該堆疊層結構包含一下部半導體層及一上部光電轉換層。The light detection device of claim 1, wherein the photoelectric conversion layer includes a stacked layer structure, and the stacked layer structure includes a lower semiconductor layer and an upper photoelectric conversion layer. 如請求項11之光偵測裝置，其中位於該第三電極上方之該下部半導體層之一材料組合物不同於位於該第一電極上方之該下部半導體層之一材料組合物。The light detection device of claim 11, wherein a material composition of the lower semiconductor layer over the third electrode is different from a material composition of the lower semiconductor layer over the first electrode. 如請求項1之光偵測裝置，其中在一電荷儲存週期期間，施加至該第三電極之一電位大於施加至該第一電極之一電位。The light detection device of claim 1, wherein a potential applied to the third electrode is greater than a potential applied to the first electrode during a charge storage period. 如請求項1之光偵測裝置，其中該絕緣材料之至少一部分安置於該第一電極上方。The light detection device of claim 1, wherein at least a portion of the insulating material is disposed over the first electrode. 如請求項14之光偵測裝置，其中隨著該第一電極與該第三電極之間的一距離減小，介於該第一電極之上部表面與該光電轉換層之間的該絕緣材料之一厚度在該第一電極之一第三電極側處增加。The light detection device of claim 14, wherein as a distance between the first electrode and the third electrode decreases, the insulating material between the upper surface of the first electrode and the photoelectric conversion layer A thickness increases at a third electrode side of the first electrode. 如請求項1之光偵測裝置，其中該光偵測裝置係一背面照明型光偵測裝置。The light detection device of claim 1, wherein the light detection device is a back-illuminated light detection device. 一種電子設備，其包括： 一光偵測裝置，其包含： 一基板，其包含一第一光電轉換單元，及 一第二光電轉換單元，其位於該基板之一光入射側處，該第二光電轉換單元包含： 一光電轉換層， 一第一電極， 一第二電極，其位於該光電轉換層上方， 一第三電極， 一絕緣材料，其介於該第三電極與該光電轉換層之間，及 一轉移控制電極，其介於該第一電極與該第三電極之間， 其中該絕緣材料之一部分介於該第一電極與該第三電極之間；及 一透鏡，其經組態以將光引導至該光偵測裝置之一表面上；以及 電路，其經組態以控制來自該光偵測裝置之輸出信號。 An electronic device comprising: A light detection device, which includes: a substrate including a first photoelectric conversion unit, and A second photoelectric conversion unit located at a light incident side of the substrate, the second photoelectric conversion unit comprising: a photoelectric conversion layer, a first electrode, a second electrode located above the photoelectric conversion layer, a third electrode, an insulating material interposed between the third electrode and the photoelectric conversion layer, and a transfer control electrode between the first electrode and the third electrode, wherein a portion of the insulating material is interposed between the first electrode and the third electrode; and a lens configured to direct light onto a surface of the light detection device; and A circuit configured to control the output signal from the light detection device. 一種驅動一光偵測裝置之方法，該方法包括： 在一充電週期期間將一第一電位施加至一電荷儲存電極； 在一充電週期期間將一第二電位施加至一第一電極，其中該第一電位大於該第二電位； 在一電荷轉移週期期間將一第三電位施加至該電荷儲存電極；及 在該電荷轉移週期期間將一第四電位施加至該第一電極，其中該第四電位大於該第三電位，且 其中， 該光偵測裝置包含： 一基板，其包含一第一光電轉換單元；及 一第二光電轉換單元，其位於該基板之一光入射側處，該第二光電轉換單元包含： 一光電轉換層， 該第一電極， 一第二電極，其位於該光電轉換層上方， 該電荷儲存電極， 一絕緣材料，其介於該電荷儲存電極與該光電轉換層之間，及 一轉移控制電極，其介於該第一電極與該第三電極之間， 其中該絕緣材料之一部分介於該第一電極與該電荷儲存電極之間。 A method of driving a light detection device, the method comprising: applying a first potential to a charge storage electrode during a charging cycle; applying a second potential to a first electrode during a charging cycle, wherein the first potential is greater than the second potential; applying a third potential to the charge storage electrode during a charge transfer period; and A fourth potential is applied to the first electrode during the charge transfer period, wherein the fourth potential is greater than the third potential, and in, The light detection device includes: a substrate including a first photoelectric conversion unit; and A second photoelectric conversion unit located at a light incident side of the substrate, the second photoelectric conversion unit comprising: a photoelectric conversion layer, the first electrode, a second electrode located above the photoelectric conversion layer, The charge storage electrode, an insulating material interposed between the charge storage electrode and the photoelectric conversion layer, and a transfer control electrode between the first electrode and the third electrode, A portion of the insulating material is interposed between the first electrode and the charge storage electrode.
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