TW202222034A - Filter circuit - Google Patents

Filter circuit Download PDF

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TW202222034A
TW202222034A TW109141774A TW109141774A TW202222034A TW 202222034 A TW202222034 A TW 202222034A TW 109141774 A TW109141774 A TW 109141774A TW 109141774 A TW109141774 A TW 109141774A TW 202222034 A TW202222034 A TW 202222034A
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resistor
switch
coupled
operational amplifier
terminal
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TW109141774A
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Chinese (zh)
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TWI738575B (en
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劉宇華
李彥鋒
智利 王
鎮杰 林
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達發科技股份有限公司
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Priority to CN202011576142.4A priority patent/CN114553168A/en
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Publication of TW202222034A publication Critical patent/TW202222034A/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01—Frequency selective two-port networks
    • H03H7/06—Frequency selective two-port networks including resistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/38—Impedance-matching networks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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Abstract

The present invention discloses a filter circuit. The filter circuit includes a first filter unit, a second filter unit and a third filter unit. The first filter unit and the second filter unit include an operation amplifier, a number of resistors, a number of capacitors and a number of switches. A combination of turned-on and turned-off of the switches may switch the filter circuit between a first mode and a second mode. The first mode is a narrowband mode, and the filter circuit has a narrower filter band. The second mode is a wideband mode, and the filter circuit has a wider filter band.

Description

濾波電路filter circuit

本發明是有關於一種濾波電路，特別是關於一種用於多頻段接收器的濾波電路。The present invention relates to a filter circuit, in particular to a filter circuit for a multi-band receiver.

濾波電路是組成接收器重要電路之一。一般而言，濾波電路會根據接收器所要接收的頻段進行設計。不同的國家或系統使用的頻段會有所差異，常見的頻段例如包括窄頻(2.7MHz)、寬頻(15MHz)及超寬頻(27MHz)等。隨著接收器被要求接收的頻段越來越多，濾波電路也必須隨之改進。如何在增加接收頻段的同時兼顧低雜訊與低功率消耗是研發的重要目標。The filter circuit is one of the important circuits that make up the receiver. Generally speaking, the filter circuit is designed according to the frequency band that the receiver wants to receive. Different countries or systems use different frequency bands. Common frequency bands include narrowband (2.7MHz), wideband (15MHz), and ultra-wideband (27MHz). As the receiver is required to receive more and more frequency bands, the filtering circuit must also improve. How to take into account low noise and low power consumption while increasing the receiving frequency band is an important goal of research and development.

本發明實施例係揭露一種濾波電路，包括一第一濾波模組及一第二濾波模組。第一濾波模組用以接收一第一輸入訊號及一第二輸入訊號，且包括一第一運算放大器、一第一開關及一第二開關。第二濾波模組耦接至第一濾波模組，且包括一第二運算放大器、一第三開關、一第四開關、一第五開關、一第六開關、一第七開關及一第八開關。濾波電路具有一第一模式及一第二模式。在第一模式下，藉由第一開關、第二開關、第三開關及第四開關的不導通且第五開關、第六開關、第七開關及第八開關的導通，第二運算放大器的一正輸出端及一負輸出端分別耦接至第一運算放大器的一反相輸入端及一非反相輸入端並且第一濾波模組與第二濾波模組的一階數總和為一第一階數。在第二模式下，藉由第一開關、第二開關、第三開關及第四開關的導通且第五開關、第六開關、第七開關及第八開關的不導通，該第二運算放大器的正輸出端及負輸出端不耦接至第一運算放大器，且第一濾波模組與第二濾波模組的階數總和為大於第一階數的一第二階數。An embodiment of the present invention discloses a filter circuit including a first filter module and a second filter module. The first filter module is used for receiving a first input signal and a second input signal, and includes a first operational amplifier, a first switch and a second switch. The second filter module is coupled to the first filter module and includes a second operational amplifier, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch and an eighth switch switch. The filter circuit has a first mode and a second mode. In the first mode, by the non-conduction of the first switch, the second switch, the third switch and the fourth switch and the conduction of the fifth switch, the sixth switch, the seventh switch and the eighth switch, the second operational amplifier A positive output terminal and a negative output terminal are respectively coupled to an inverting input terminal and a non-inverting input terminal of the first operational amplifier, and the sum of the first orders of the first filter module and the second filter module is a first first order. In the second mode, with the first switch, the second switch, the third switch and the fourth switch being turned on and the fifth switch, the sixth switch, the seventh switch and the eighth switch being turned off, the second operational amplifier The positive output terminal and the negative output terminal of the first operational amplifier are not coupled to the first operational amplifier, and the sum of the orders of the first filter module and the second filter module is a second order greater than the first order.

本發明另一實施例係揭露濾波電路，包括一第一濾波模組及一第二濾波模組。第一濾波模組包括一第一運算放大器、一第一開關及一第二開關。第二濾波模組耦接至第一濾波模組，且包括一第二運算放大器、一第三開關、一第四開關、一第五開關、一第六開關、一第七開關及一第八開關，且用以輸出一第一輸出訊號及一第二輸出訊號。在第一模式下，藉由第一開關、第二開關、第三開關及第四開關的不導通且第五開關、第六開關、第七開關及第八開關的導通，第二運算放大器的一正輸出端及一負輸出端分別耦接至第一運算放大器的一反相輸入端及一非反相輸入端並且第一濾波模組與第二濾波模組的一階數總和為一第一階數。在第二模式下，藉由第一開關、第二開關、第三開關及第四開關的導通且第五開關、第六開關、第七開關及第八開關的不導通，第二運算放大器的正輸出端及負輸出端不耦接至第一運算放大器，且第一濾波模組與第二濾波模組的階數總和為大於第一階數的一第二階數。Another embodiment of the present invention discloses a filter circuit including a first filter module and a second filter module. The first filter module includes a first operational amplifier, a first switch and a second switch. The second filter module is coupled to the first filter module and includes a second operational amplifier, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch and an eighth switch The switch is used for outputting a first output signal and a second output signal. In the first mode, by the non-conduction of the first switch, the second switch, the third switch and the fourth switch and the conduction of the fifth switch, the sixth switch, the seventh switch and the eighth switch, the second operational amplifier A positive output terminal and a negative output terminal are respectively coupled to an inverting input terminal and a non-inverting input terminal of the first operational amplifier, and the sum of the first orders of the first filter module and the second filter module is a first first order. In the second mode, with the first switch, the second switch, the third switch and the fourth switch being turned on and the fifth switch, the sixth switch, the seventh switch and the eighth switch being turned off, the second operational amplifier has a The positive output terminal and the negative output terminal are not coupled to the first operational amplifier, and the sum of the orders of the first filter module and the second filter module is a second order greater than the first order.

為了對本發明之上述及其他方面有更佳的瞭解，下文特舉實施例，並配合所附圖式詳細說明如下：In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific examples are given and described in detail in conjunction with the accompanying drawings as follows:

第1圖繪示根據本發明一實施例的濾波電路10的方塊圖。請參照第1圖，濾波電路10包括一第一濾波模組102、一第二濾波模組104以及一第三濾波模組106。FIG. 1 is a block diagram of a filter circuit 10 according to an embodiment of the present invention. Referring to FIG. 1 , the filter circuit 10 includes a first filter module 102 , a second filter module 104 and a third filter module 106 .

第一濾波模組102包括一運算放大器OPA1、多個電阻器R1及R2、多個電容器C1及C2以及多個開關S1及S2。The first filter module 102 includes an operational amplifier OPA1, a plurality of resistors R1 and R2, a plurality of capacitors C1 and C2, and a plurality of switches S1 and S2.

在第一濾波模組102中，運算放大器OPA1的一反相輸入端用以接收一第一輸入訊號S-in1。運算放大器OPA1的一非反相輸入端用以接收一第二輸入訊號S-in2。電阻器R1的一第一端耦接至運算放大器OPA1的反相輸入端。電阻器R1的一第二端耦接至開關S1的一第一端。電容器C1的一第一端耦接至運算放大器OPA1的反相輸入端。電容器C1的一第二端耦接至開關S1的一第二端及運算放大器OPA1的一正輸出端。電阻器R2的一第一端耦接至運算放大器OPA1的非反相輸入端。電阻器R2的一第二端耦接至開關S2的一第一端。電容器C2的一第一端耦接至運算放大器OPA1的非反相輸入端。電容器C2的一第二端耦接至開關S2的一第二端及運算放大器OPA1的一負輸出端。In the first filter module 102, an inverting input terminal of the operational amplifier OPA1 is used for receiving a first input signal S-in1. A non-inverting input terminal of the operational amplifier OPA1 is used for receiving a second input signal S-in2. A first end of the resistor R1 is coupled to the inverting input end of the operational amplifier OPA1. A second end of the resistor R1 is coupled to a first end of the switch S1. A first terminal of the capacitor C1 is coupled to the inverting input terminal of the operational amplifier OPA1. A second terminal of the capacitor C1 is coupled to a second terminal of the switch S1 and a positive output terminal of the operational amplifier OPA1. A first end of the resistor R2 is coupled to the non-inverting input end of the operational amplifier OPA1. A second end of the resistor R2 is coupled to a first end of the switch S2. A first terminal of the capacitor C2 is coupled to the non-inverting input terminal of the operational amplifier OPA1. A second terminal of the capacitor C2 is coupled to a second terminal of the switch S2 and a negative output terminal of the operational amplifier OPA1.

第二濾波模組104包括一運算放大器OPA2、多個電阻器R3、R4、R5、R6、R7及R8、多個電容器C3、C4及C5以及多個開關S3、S4、S5、S6、S7及S8。The second filter module 104 includes an operational amplifier OPA2, a plurality of resistors R3, R4, R5, R6, R7 and R8, a plurality of capacitors C3, C4 and C5, and a plurality of switches S3, S4, S5, S6, S7 and S8.

在第二濾波模組104中，電阻器R3的一第一端耦接至運算放大器OPA1的負輸出端。電阻器R4的一第一端耦接至運算放大器OPA1的正輸出端。電容器C3的一第一端耦接至開關S3的一第一端。開關S3的一第二端耦接至電阻器R3的一第二端。電容器C3一第二端耦接至開關S4的一第一端。開關S4的一第二端耦接至電阻器R4的一第二端。電阻器R5的一第一端耦接至電阻器R3的第二端。電阻器R7的一第一端耦接至開關S5的一第一端。電阻器R7的一第二端耦接至開關S7的一第一端及運算放大器OPA2的一正輸出端。開關S7的一第二端耦接至電阻器R1的第二端。電容器C4的一第一端耦接至開關S5的一第二端。電容器C4的一第二端耦接至運算放大器OPA2的正輸出端。開關S5的第二端耦接至電阻器R5的一第二端及運算放大器OPA2的一反相輸入端。電阻器R6的一第一端耦接至電阻器R4的第二端。電阻器R8的一第一端耦接至開關S6的一第一端。電阻器R8的一第二端耦接至開關S8的一第一端及運算放大器OPA2的一負輸出端。開關S8的一第二端耦接至電阻器R2的第二端。電容器C5的一第一端耦接至開關S6的一第二端。電容器C5的一第二端耦接至運算放大器OPA2的負輸出端。開關S6的第二端耦接至電阻器R6的一第二端及運算放大器OPA2的一非反相輸入端。In the second filter module 104, a first end of the resistor R3 is coupled to the negative output end of the operational amplifier OPA1. A first end of the resistor R4 is coupled to the positive output end of the operational amplifier OPA1. A first end of the capacitor C3 is coupled to a first end of the switch S3. A second end of the switch S3 is coupled to a second end of the resistor R3. A second end of the capacitor C3 is coupled to a first end of the switch S4. A second end of the switch S4 is coupled to a second end of the resistor R4. A first end of the resistor R5 is coupled to a second end of the resistor R3. A first end of the resistor R7 is coupled to a first end of the switch S5. A second terminal of the resistor R7 is coupled to a first terminal of the switch S7 and a positive output terminal of the operational amplifier OPA2. A second terminal of the switch S7 is coupled to the second terminal of the resistor R1. A first terminal of the capacitor C4 is coupled to a second terminal of the switch S5. A second terminal of the capacitor C4 is coupled to the positive output terminal of the operational amplifier OPA2. The second terminal of the switch S5 is coupled to a second terminal of the resistor R5 and an inverting input terminal of the operational amplifier OPA2. A first end of the resistor R6 is coupled to the second end of the resistor R4. A first end of the resistor R8 is coupled to a first end of the switch S6. A second terminal of the resistor R8 is coupled to a first terminal of the switch S8 and a negative output terminal of the operational amplifier OPA2. A second terminal of the switch S8 is coupled to the second terminal of the resistor R2. A first terminal of the capacitor C5 is coupled to a second terminal of the switch S6. A second terminal of the capacitor C5 is coupled to the negative output terminal of the operational amplifier OPA2. The second terminal of the switch S6 is coupled to a second terminal of the resistor R6 and a non-inverting input terminal of the operational amplifier OPA2.

第三濾波模組106包括一運算放大器OPA3、多個電阻器R9、R10、R11及R12以及多個電容器C6及C7。The third filter module 106 includes an operational amplifier OPA3, a plurality of resistors R9, R10, R11 and R12, and a plurality of capacitors C6 and C7.

在第三濾波模組106中，電阻器R9的一第一端耦接至運算放大器OPA2的負輸出端。電阻器R11的一第一端耦接至電阻器R9的一第二端及運算放大器OPA3的一反相輸入端。電阻器R11的一第二端耦接至運算放大器OPA3的一正輸出端。電容器C6的一第一端耦接至運算放大器OPA3的反相輸入端。電容器C6的一第二端耦接至運算放大器OPA3的正輸出端。電阻器R10的一第一端耦接至運算放大器OPA2的正輸出端。電阻器R12的一第一端耦接至電阻器R10的一第二端及運算放大器OPA3的一非反相輸入端。電阻器R12的一第二端耦接至運算放大器OPA3的一負輸出端。電容器C7的一第一端耦接至運算放大器OPA3的非反相輸入端。電容器C7的一第二端耦接至運算放大器OPA3的負輸出端。運算放大器OPA3的正輸出端用以輸出一第一輸出訊號S-out1。運算放大器OPA3的負輸出端用以輸出一第二輸出訊號S-out2。In the third filter module 106, a first end of the resistor R9 is coupled to the negative output end of the operational amplifier OPA2. A first end of the resistor R11 is coupled to a second end of the resistor R9 and an inverting input end of the operational amplifier OPA3. A second terminal of the resistor R11 is coupled to a positive output terminal of the operational amplifier OPA3. A first terminal of the capacitor C6 is coupled to the inverting input terminal of the operational amplifier OPA3. A second terminal of the capacitor C6 is coupled to the positive output terminal of the operational amplifier OPA3. A first terminal of the resistor R10 is coupled to the positive output terminal of the operational amplifier OPA2. A first end of the resistor R12 is coupled to a second end of the resistor R10 and a non-inverting input end of the operational amplifier OPA3. A second terminal of the resistor R12 is coupled to a negative output terminal of the operational amplifier OPA3. A first terminal of the capacitor C7 is coupled to the non-inverting input terminal of the operational amplifier OPA3. A second terminal of the capacitor C7 is coupled to the negative output terminal of the operational amplifier OPA3. The positive output terminal of the operational amplifier OPA3 is used for outputting a first output signal S-out1. The negative output terminal of the operational amplifier OPA3 is used for outputting a second output signal S-out2.

在一實施例中，電阻器R1及R2的電阻值彼此相同。電阻器R3及R4的電阻值彼此相同。電阻器R5及R6的電阻值彼此相同。電阻器R7及R8的電阻值彼此相同。電阻器R9及R10的電阻值彼此相同。電阻器R11及R12的電阻值彼此相同。電容器C1及C2的電容值彼此相同。電容器C4及C5的電容值彼此相同。電容器C6及C7的電容值彼此相同。In one embodiment, the resistance values of the resistors R1 and R2 are the same as each other. The resistance values of the resistors R3 and R4 are the same as each other. The resistance values of the resistors R5 and R6 are the same as each other. The resistance values of the resistors R7 and R8 are the same as each other. The resistance values of the resistors R9 and R10 are the same as each other. The resistance values of the resistors R11 and R12 are the same as each other. The capacitance values of the capacitors C1 and C2 are the same as each other. The capacitance values of the capacitors C4 and C5 are the same as each other. The capacitance values of the capacitors C6 and C7 are the same as each other.

濾波電路10具有一第一模式及一第二模式。第一模式與第二模式之間的切換可藉由改變開關S1至S8的導通與不導通的組合來實現，詳細說明於第3A圖及第3B圖的實施例中。在一實施例中，開關S1至S8可受控於一控制單元(未繪示)。控制單元可根據使用者下達的一模式切換命令來發送控制訊號至開關S1至S8以分別控制開關S1至S8導通或不導通。The filter circuit 10 has a first mode and a second mode. The switching between the first mode and the second mode can be realized by changing the combination of conduction and non-conduction of the switches S1 to S8 , which are described in detail in the embodiments of FIGS. 3A and 3B . In one embodiment, the switches S1 to S8 may be controlled by a control unit (not shown). The control unit can send control signals to the switches S1 to S8 according to a mode switching command issued by the user to control the switches S1 to S8 to be turned on or off, respectively.

第3A圖的電路圖圖示出第1圖的濾波電路10操作在第一模式下的電路架構。參照第3A圖，當開關S1至S4不導通且開關S5至S8導通時，濾波電路10會被切換至第一模式。在本實施例中，第一模式為窄頻模式。在第一模式下，第二濾波模組104的運算放大器OPA2的正輸出端及負輸出端會分別透過電阻器R1及電阻器R2耦接至第一濾波模組102的反相輸入端及非反相輸入端。此外，電阻器R7與電容器C4並聯於運算放大器OPA2的反向輸入端及正輸出端之間，以及類似地，電阻器R8與電容器C5並聯於運算放大器OPA2的非反向輸入端及負輸出端之間。又，因應於開關S3及S4的不導通，電容器C3不電性連接至第二濾波模組104的其他電子元件，因而電容器C3不參與對第一輸入訊號S-in1及第二輸入訊號S-in2的濾波操作。The circuit diagram of FIG. 3A illustrates the circuit architecture of the filter circuit 10 of FIG. 1 operating in the first mode. Referring to FIG. 3A , when the switches S1 to S4 are turned off and the switches S5 to S8 are turned on, the filter circuit 10 is switched to the first mode. In this embodiment, the first mode is a narrowband mode. In the first mode, the positive output terminal and the negative output terminal of the operational amplifier OPA2 of the second filter module 104 are respectively coupled to the inverting input terminal and the non-inverting input terminal of the first filter module 102 through the resistor R1 and the resistor R2. Inverting input. In addition, resistor R7 and capacitor C4 are connected in parallel between the inverting input and positive output of operational amplifier OPA2, and similarly, resistor R8 and capacitor C5 are connected in parallel between the non-inverting input and negative output of operational amplifier OPA2 between. In addition, due to the non-conduction of switches S3 and S4, the capacitor C3 is not electrically connected to other electronic components of the second filter module 104, so the capacitor C3 does not participate in the control of the first input signal S-in1 and the second input signal S- The filtering operation of in2.

第一濾波模組102與第二濾波模組104共同貢獻的階數(order)總和為一第一階數，在本實施例中第一階數為二階。在一些實施例中，在第一模式下的第一濾波模組102與第二濾波模組104的組合的等效電路可等同於Tow-Thomas二階濾波器。又，第三濾波模組106獨自貢獻的階數為二階。據此，操作在第一模式下的濾波電路10可等效為四階濾波器。The sum of the orders jointly contributed by the first filter module 102 and the second filter module 104 is a first order, and in this embodiment, the first order is a second order. In some embodiments, the equivalent circuit of the combination of the first filter module 102 and the second filter module 104 in the first mode may be equivalent to a Tow-Thomas second-order filter. In addition, the order contributed by the third filter module 106 alone is the second order. Accordingly, the filter circuit 10 operating in the first mode can be equivalent to a fourth-order filter.

第3B圖的電路圖圖示出第1圖的濾波電路10操作在第二模式下的電路架構。參照第3B圖，當開關S1至S4導通且開關S5至S8不導通時，濾波電路10會被切換為第二模式。在本實施例中，第二模式為寬頻模式。在第二模式下，第二濾波模組104的運算放大器OPA2的正輸出端及負輸出端不回授至第一濾波模組102的反相輸入端及非反相輸入端。據此，第一濾波模組102與第二濾波模組104共同貢獻的階數總和為大於第一階數的一第二階數，在本實施例中第二階數為三階。在一些實施例中，在第二模式下的第一濾波模組102貢獻一階的濾波效果，並且在第二模式下的第二濾波模組104可等同於二階多重回授濾波器。又，第三濾波模組106獨自貢獻的階數為二階。據此，操作在第二模式下的濾波電路10可等效為五階濾波器。The circuit diagram of FIG. 3B illustrates the circuit architecture of the filter circuit 10 of FIG. 1 operating in the second mode. Referring to FIG. 3B , when the switches S1 to S4 are turned on and the switches S5 to S8 are not turned on, the filter circuit 10 is switched to the second mode. In this embodiment, the second mode is the broadband mode. In the second mode, the positive output terminal and the negative output terminal of the operational amplifier OPA2 of the second filter module 104 are not fed back to the inverting input terminal and the non-inverting input terminal of the first filtering module 102 . Accordingly, the sum of the orders contributed by the first filter module 102 and the second filter module 104 is a second order greater than the first order, and in this embodiment, the second order is the third order. In some embodiments, the first filter module 102 in the second mode contributes a first-order filtering effect, and the second filter module 104 in the second mode may be equivalent to a second-order multiple feedback filter. In addition, the order contributed by the third filter module 106 alone is the second order. Accordingly, the filter circuit 10 operating in the second mode can be equivalent to a fifth-order filter.

一般來說，濾波器的階數正相關於濾波器輸出的訊號的頻寬。因此，在第一模式下為四階的濾波電路10的頻寬窄於在第二模式下為五階的濾波電路10。又，一般來說，濾波電路的頻寬正相關於可濾波的頻段數量。因此，濾波電路10在第一模式下可濾波的頻段數量少於在第二模式下。例如在一實施例中，濾波電路10在第一模式下可包括濾波窄頻(2MHz(mega hertz))及寬頻(15MHz)的兩個頻段的訊號，或者可濾波包括寬頻(15MHz)及超寬頻(27MHz)的兩個頻段的訊號。另一方面，濾波電路10在第二模式下可濾波包括窄頻(2MHz)、寬頻(15MHz)及超寬頻(27MHz)的三個頻段的訊號。也就是說，濾波電路10可藉由調整開關S1至S8的導通與不導通的組合來調整第一濾波模組102與第二濾波模組104共同貢獻的階數總和，據以改變濾波電路10的頻寬。Generally speaking, the order of the filter is positively related to the bandwidth of the signal output by the filter. Therefore, the frequency bandwidth of the filter circuit 10 of the fourth order in the first mode is narrower than that of the filter circuit 10 of the fifth order in the second mode. Also, in general, the bandwidth of the filter circuit is positively related to the number of frequency bands that can be filtered. Therefore, the number of frequency bands that can be filtered by the filter circuit 10 in the first mode is less than that in the second mode. For example, in one embodiment, the filtering circuit 10 in the first mode may filter signals in two frequency bands of narrow frequency (2 MHz (mega hertz)) and wide frequency (15 MHz), or may filter signals including wide frequency (15 MHz) and ultra wide frequency (27MHz) signals in two frequency bands. On the other hand, in the second mode, the filter circuit 10 can filter signals in three frequency bands including narrow frequency (2MHz), wide frequency (15MHz) and ultra-wide frequency (27MHz). That is to say, the filter circuit 10 can adjust the sum of orders contributed by the first filter module 102 and the second filter module 104 by adjusting the combination of on and off of the switches S1 to S8, so as to change the filter circuit 10 bandwidth.

通常，相較於低階的濾波電路，構成高階的濾波電路的運算放大器的最低需求的總數量比較多，其將導致高階的濾波電路的功率消耗大於低階的濾波電路，因而此高階的濾波電路相對不適合應用在低功耗應用中。Generally, compared with the low-order filter circuit, the total number of the minimum requirements of the operational amplifiers constituting the high-order filter circuit is relatively large, which will cause the power consumption of the high-order filter circuit to be greater than that of the low-order filter circuit. The circuit is relatively unsuitable for use in low-power applications.

為了能夠符合低功耗應用的需求，會盡量至少減少濾波電路的運算放大器的總量。在本揭露中，即使在寬頻模式下，本揭露的濾波電路10的操作放大器的總量也保持與在低頻模式下操作放大器的總量相同。換言之，本揭露的濾波電路10沒有因操作在寬頻模式下而使用比在窄頻模式下更多的操作放大器。本揭露的濾波電路10是藉由開關S1至S8來重新組態原本提供低階濾波器功能的濾波電路10，以使經組態濾波電路10能夠提供高階濾波器的功能。因此，本揭露的濾波電路10的功率消耗的效率相對較佳。In order to be able to meet the needs of low-power applications, at least the total number of op amps in the filter circuit is minimized. In the present disclosure, even in the broadband mode, the total number of operational amplifiers of the filter circuit 10 of the present disclosure remains the same as the total number of operational amplifiers in the low frequency mode. In other words, the filter circuit 10 of the present disclosure does not use more operational amplifiers when operating in the wideband mode than in the narrowband mode. In the filter circuit 10 of the present disclosure, the filters S1 to S8 are used to reconfigure the filter circuit 10 originally providing the function of the low-order filter, so that the configured filter circuit 10 can provide the function of the high-order filter. Therefore, the power consumption efficiency of the filter circuit 10 of the present disclosure is relatively good.

在一實施例中，第三濾波模組106可做為可編程增益放大器(programmable-gain amplifier，PGA)。在此實施例中，電阻器R9、R10、R11及R12為可變電阻器，電阻器R9的電阻值與電阻器R11的電阻值的比值可決定一增益。電阻器R9的電阻值與電阻器R10的電阻值相同，電阻器R11的電阻值與電阻器R12的電阻值相同，因此上述增益也等同於由電阻器R10的電阻值與電阻器R12的電阻值的比值來決定。In one embodiment, the third filter module 106 can be used as a programmable-gain amplifier (PGA). In this embodiment, the resistors R9, R10, R11 and R12 are variable resistors, and the ratio of the resistance value of the resistor R9 to the resistance value of the resistor R11 can determine a gain. Resistor R9 has the same resistance value as resistor R10, and resistor R11 has the same resistance value as resistor R12, so the above gain is also equivalent to the difference between the resistance value of resistor R10 and the resistance value of resistor R12. ratio is determined.

在另一實施例中，電阻器R9、R10、R11及R12為可變電阻器且電容器C6及C7為可變電容器。電阻器R9至R12的電阻值及電容器C6至C7的電容值可受控制控制單元，控制單元可根據濾波電路10所處的模式為第一模式或第二模式調整電阻器R9至R12的電阻值及電容器C6至C7的電容值以優化濾波電路10的濾波效果。In another embodiment, resistors R9, R10, R11 and R12 are variable resistors and capacitors C6 and C7 are variable capacitors. The resistance values of the resistors R9 to R12 and the capacitance values of the capacitors C6 to C7 can be controlled by the control unit. The control unit can adjust the resistance values of the resistors R9 to R12 according to whether the filter circuit 10 is in the first mode or the second mode. and the capacitance values of the capacitors C6 to C7 to optimize the filtering effect of the filtering circuit 10 .

第2圖繪示根據本發明另一實施例的濾波電路20的方塊圖。請參照第2圖，濾波電路20是透過將圖1的第三濾波模組106移至第二濾波模組104前方來實現。換言之，第三濾波模組106是作為濾波電路20的輸入級。據此，第二濾波模組104適應性地作為濾波電路20的輸出級，並且第一濾波模組102作為濾波電路20的中間級以耦接於濾波電路20的第三濾波模組106及第二濾波模組104之間。FIG. 2 is a block diagram of a filter circuit 20 according to another embodiment of the present invention. Please refer to FIG. 2 , the filter circuit 20 is realized by moving the third filter module 106 of FIG. 1 to the front of the second filter module 104 . In other words, the third filter module 106 is used as the input stage of the filter circuit 20 . Accordingly, the second filter module 104 is adaptively used as the output stage of the filter circuit 20 , and the first filter module 102 is used as an intermediate stage of the filter circuit 20 to be coupled to the third filter module 106 and the third filter module 106 of the filter circuit 20 . between the two filter modules 104 .

為了簡潔，以下僅就連接差異處進行描述。參照第2圖，電阻器R11的第二端、電容器C6的第二端及運算放大器OPA3的正輸出端耦接至第一濾波模組202的電阻器R2的第一端、電容器C2的第一端及運算放大器OPA1的非反向輸入端。類似地，電阻器R12的第二端、電容器C7的第二端及運算放大器OPA3的負輸出端耦接至第一濾波模組202的電阻器R1的第一端、電容器C1的第一端及運算放大器OPA1的反向輸入端。此外，運算放大器OPA2的正輸出端用以輸出一第一輸出訊號S-out1。運算放大器OPA2的負輸出端用以輸出一第二輸出訊號S-out2。For brevity, only the connection differences are described below. Referring to FIG. 2 , the second end of the resistor R11 , the second end of the capacitor C6 and the positive output end of the operational amplifier OPA3 are coupled to the first end of the resistor R2 of the first filter module 202 and the first end of the capacitor C2 terminal and the non-inverting input terminal of the operational amplifier OPA1. Similarly, the second end of the resistor R12 , the second end of the capacitor C7 and the negative output end of the operational amplifier OPA3 are coupled to the first end of the resistor R1 of the first filter module 202 , the first end of the capacitor C1 and the Inverting input of operational amplifier OPA1. In addition, the positive output terminal of the operational amplifier OPA2 is used for outputting a first output signal S-out1. The negative output terminal of the operational amplifier OPA2 is used for outputting a second output signal S-out2.

需要注意的是，第一濾波模組102與第二濾波模組104中的電阻器的電阻值及電容器的電容值可根據實際需求進行設計，本發明不加以限定。It should be noted that the resistance values of the resistors and the capacitance values of the capacitors in the first filter module 102 and the second filter module 104 can be designed according to actual requirements, which are not limited in the present invention.

本發明提出的濾波電路具有二種不同的模式，即第一模式及第二模式。在濾波電路的階數上，處於第一模式下的四階係小於處於第二模式下的五階。在濾波電路的頻寬上，處於第一模式下的濾波電路的頻寬係窄於處於第二模式下。藉由調整濾波器電路中開關的導通與不導通的組合來調整第一濾波模組與第二濾波模組共同貢獻的階數總和而切換於第一模式與第二模式之間，據以改變濾波電路的頻寬。因此，本揭露的濾波電路的功率消耗的效率相對較佳。The filter circuit proposed by the present invention has two different modes, namely a first mode and a second mode. In terms of the order of the filter circuit, the fourth order in the first mode is smaller than the fifth order in the second mode. In terms of the bandwidth of the filter circuit, the bandwidth of the filter circuit in the first mode is narrower than that in the second mode. By adjusting the combination of conduction and non-conduction of switches in the filter circuit to adjust the sum of the orders contributed by the first filter module and the second filter module to switch between the first mode and the second mode, change the The bandwidth of the filter circuit. Therefore, the power consumption efficiency of the filter circuit of the present disclosure is relatively good.

綜上所述，雖然本發明已以實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application.

10、20:濾波電路 OPA1至OPA3:運算放大器 R1至R12:電阻器 C1至C7:電容器 S1至S8:開關 10, 20: Filter circuit OPA1 to OPA3: Operational Amplifiers R1 to R12: Resistors C1 to C7: Capacitors S1 to S8: Switch

第1圖繪示根據本發明一實施例的濾波電路的方塊圖。 第2圖繪示根據本發明另一實施例的濾波電路的方塊圖。 第3A圖的電路圖圖示出第1圖的濾波電路操作在第一模式下的電路架構。 第3B圖的電路圖圖示出第1圖的濾波電路操作在第二模式下的電路架構。 FIG. 1 is a block diagram of a filter circuit according to an embodiment of the present invention. FIG. 2 is a block diagram of a filter circuit according to another embodiment of the present invention. The circuit diagram of FIG. 3A illustrates the circuit architecture of the filter circuit of FIG. 1 operating in a first mode. The circuit diagram of FIG. 3B illustrates the circuit architecture of the filter circuit of FIG. 1 operating in the second mode.

10:濾波電路 10: Filter circuit

102:第一濾波模組 102: The first filter module

104:第二濾波模組 104: Second filter module

106:第三濾波模組 106: The third filter module

OPA1至OPA3:運算放大器 OPA1 to OPA3: Operational Amplifiers

R1至R12:電阻器 R1 to R12: Resistors

C1至C7:電容器 C1 to C7: Capacitors

S1至S8:開關 S1 to S8: Switch

Claims (12)

一種濾波電路，包括： 一第一濾波模組，用以接收一第一輸入訊號及一第二輸入訊號，且包括一第一運算放大器、一第一開關及一第二開關；以及 一第二濾波模組，耦接至該第一濾波模組，且包括一第二運算放大器、一第三開關、一第四開關、一第五開關、一第六開關、一第七開關及一第八開關， 其中該濾波電路具有一第一模式及一第二模式， 其中，在該第一模式下，藉由該第一開關、該第二開關、該第三開關及該第四開關的不導通且該第五開關、該第六開關、該第七開關及該第八開關的導通，該第二運算放大器的一正輸出端及一負輸出端分別耦接至該第一運算放大器的一反相輸入端及一非反相輸入端並且該第一濾波模組與該第二濾波模組的一階數總和為一第一階數，以及 其中，在該第二模式下，藉由該第一開關、該第二開關、該第三開關及該第四開關的導通且該第五開關、該第六開關、該第七開關及該第八開關的不導通，該第二運算放大器的該正輸出端及該負輸出端不耦接至該第一運算放大器，且該第一濾波模組與該第二濾波模組的該階數總和為大於該第一階數的一第二階數。 A filter circuit, comprising: a first filter module for receiving a first input signal and a second input signal, and comprising a first operational amplifier, a first switch and a second switch; and A second filter module is coupled to the first filter module and includes a second operational amplifier, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch and an eighth switch, wherein the filter circuit has a first mode and a second mode, Wherein, in the first mode, by the non-conduction of the first switch, the second switch, the third switch and the fourth switch and the fifth switch, the sixth switch, the seventh switch and the When the eighth switch is turned on, a positive output terminal and a negative output terminal of the second operational amplifier are respectively coupled to an inverting input terminal and a non-inverting input terminal of the first operational amplifier, and the first filter module summing with the first order of the second filter module is a first order, and Wherein, in the second mode, through the conduction of the first switch, the second switch, the third switch and the fourth switch and the fifth switch, the sixth switch, the seventh switch and the fourth switch The eight switches are non-conductive, the positive output terminal and the negative output terminal of the second operational amplifier are not coupled to the first operational amplifier, and the sum of the order of the first filter module and the second filter module is a second order greater than the first order. 如申請專利範圍第1項所述之濾波電路，更包括： 一第三濾波模組，耦接至該第二濾波模組，且用以輸出一第一輸出訊號及一第二輸出訊號。 The filter circuit described in item 1 of the patent application scope further includes: A third filter module is coupled to the second filter module and used for outputting a first output signal and a second output signal. 如申請專利範圍第2項所述之濾波電路， 其中該第一濾波模組更包括一第一電阻器、一第二電阻器、一第一電容器及一第二電容器， 其中該第一運算放大器的該反相輸入端用以接收該第一輸入訊號，該第一運算放大器的該非反相輸入端用以接收該第二輸入訊號，該第一電阻器的一第一端耦接至該第一運算放大器的該反相輸入端，該第一電阻器的一第二端耦接至該第一開關的一第一端，該第一電容器的一第一端耦接至該第一運算放大器的該反相輸入端，該第一電容器的一第二端耦接至該第一開關的一第二端及該第一運算放大器的一正輸出端，該第二電阻器的一第一端耦接至該第一運算放大器的該非反相輸入端，該第二電阻器的一第二端耦接至該第二開關的一第一端，該第二電容器的一第一端耦接至該第一運算放大器的該非反相輸入端，該第二電容器的一第二端耦接至該第二開關的一第二端及該第一運算放大器的一負輸出端，以及 其中該第二濾波模組更包括一第三電阻器、一第四電阻器、一第五電阻器、一第六電阻器、一第七電阻器、一第八電阻器、一第三電容器、一第四電容器及一第五電容器， 其中該第三電阻器的一第一端耦接至該第一運算放大器的該負輸出端，該第四電阻器的一第一端耦接至該第一運算放大器的該正輸出端，該第三電容器一第一端耦接至該第三開關的一第一端，該第三開關的一第二端耦接至該第三電阻器的一第二端，該第三電容器的一第二端耦接至該第四開關的一第一端，該第四開關的一第二端耦接至該第四電阻器的一第二端，該第五電阻器的一第一端耦接至該第三電阻器的該第二端，該第七電阻器的一第一端耦接至該第五開關的一第一端，該第七電阻器的一第二端耦接至該第七開關的一第一端及該第二運算放大器的該正輸出端，該第七開關的一第二端耦接至該第一電阻器的第二端，該第四電容器的一第一端耦接至該第五開關的一第二端，該第四電容器的一第二端耦接至該第二運算放大器的該正輸出端，該第五開關的該第二端耦接至該第五電阻器的一第二端及該第二運算放大器的一反相輸入端，該第六電阻器的一第一端耦接至該第四電阻器的該第二端，該第八電阻器的一第一端耦接至該第六開關的一第一端，該第八電阻器的一第二端耦接至該第八開關的一第一端及該第二運算放大器的該負輸出端，該第八開關的一第二端耦接至該第二電阻器的該第二端，該第五電容器的一第一端耦接至該第六開關的一第二端，該第五電容器的一第二端耦接至該第二運算放大器的該負輸出端，該第六開關的該第二端耦接至該第六電阻器的一第二端及該第二運算放大器的一非反相輸入端。 As the filter circuit described in item 2 of the scope of the patent application, The first filter module further includes a first resistor, a second resistor, a first capacitor and a second capacitor, The inverting input terminal of the first operational amplifier is used for receiving the first input signal, the non-inverting input terminal of the first operational amplifier is used for receiving the second input signal, and a first resistor of the first resistor is used for receiving the second input signal. The terminal is coupled to the inverting input terminal of the first operational amplifier, a second terminal of the first resistor is coupled to a first terminal of the first switch, and a first terminal of the first capacitor is coupled to to the inverting input terminal of the first operational amplifier, a second terminal of the first capacitor is coupled to a second terminal of the first switch and a positive output terminal of the first operational amplifier, the second resistor A first end of the resistor is coupled to the non-inverting input end of the first operational amplifier, a second end of the second resistor is coupled to a first end of the second switch, and a second end of the second capacitor A first end is coupled to the non-inverting input end of the first operational amplifier, a second end of the second capacitor is coupled to a second end of the second switch and a negative output end of the first operational amplifier ,as well as The second filter module further includes a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a third capacitor, a fourth capacitor and a fifth capacitor, A first end of the third resistor is coupled to the negative output end of the first operational amplifier, a first end of the fourth resistor is coupled to the positive output end of the first operational amplifier, the A first end of the third capacitor is coupled to a first end of the third switch, a second end of the third switch is coupled to a second end of the third resistor, and a first end of the third capacitor Two terminals are coupled to a first terminal of the fourth switch, a second terminal of the fourth switch is coupled to a second terminal of the fourth resistor, and a first terminal of the fifth resistor is coupled to to the second end of the third resistor, a first end of the seventh resistor is coupled to a first end of the fifth switch, and a second end of the seventh resistor is coupled to the first end A first end of seven switches and the positive output end of the second operational amplifier, a second end of the seventh switch is coupled to the second end of the first resistor, and a first end of the fourth capacitor is coupled to a second end of the fifth switch, a second end of the fourth capacitor is coupled to the positive output end of the second operational amplifier, and the second end of the fifth switch is coupled to the first A second end of the five resistors and an inverting input end of the second operational amplifier, a first end of the sixth resistor is coupled to the second end of the fourth resistor, and the eighth resistor A first end of the eighth resistor is coupled to a first end of the sixth switch, a second end of the eighth resistor is coupled to a first end of the eighth switch and the negative output of the second operational amplifier terminal, a second terminal of the eighth switch is coupled to the second terminal of the second resistor, a first terminal of the fifth capacitor is coupled to a second terminal of the sixth switch, the fifth A second end of the capacitor is coupled to the negative output end of the second operational amplifier, the second end of the sixth switch is coupled to a second end of the sixth resistor and a second end of the second operational amplifier Non-inverting input. 如申請專利範圍第3項所述之濾波電路，其中： 該第三濾波模組，包括一第三運算放大器、一第九電阻器、一第十電阻器、一第十一電阻器、一第十二電阻器、一第六電容器及一第七電容器， 其中該第九電阻器的一第一端耦接至該第二運算放大器的該負輸出端，該第十一電阻器的一第一端耦接至該第九電阻器的一第二端及該第三運算放大器的一反相輸入端，該第十一電阻器的一第二端耦接至該第三運算放大器的一正輸出端，該第六電容器的一第一端耦接至該第三運算放大器的該反相輸入端，該第六電容器的一第二端耦接至該第三運算放大器的該正輸出端，該第十電阻器的一第一端耦接至該第二運算放大器的該正輸出端，該第十二電阻器的一第一端耦接至該第十電阻器的一第二端及該第三運算放大器的一非反相輸入端，該第十二電阻器的一第二端耦接至該第三運算放大器的一負輸出端，該第七電容器的一第一端耦接至該第三運算放大器的該非反相輸入端，該第七電容器的一第二端耦接至該第三運算放大器的該負輸出端，該運算放大器的該正輸出端用以輸出該第一輸出訊號，該第三運算放大器的該負輸出端用以輸出該第二輸出訊號。 The filter circuit as described in item 3 of the scope of the application, wherein: The third filter module includes a third operational amplifier, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a sixth capacitor and a seventh capacitor, A first end of the ninth resistor is coupled to the negative output end of the second operational amplifier, a first end of the eleventh resistor is coupled to a second end of the ninth resistor and An inverting input terminal of the third operational amplifier, a second terminal of the eleventh resistor is coupled to a positive output terminal of the third operational amplifier, and a first terminal of the sixth capacitor is coupled to the The inverting input terminal of the third operational amplifier, a second terminal of the sixth capacitor is coupled to the positive output terminal of the third operational amplifier, and a first terminal of the tenth resistor is coupled to the second The positive output end of the operational amplifier, a first end of the twelfth resistor is coupled to a second end of the tenth resistor and a non-inverting input end of the third operational amplifier, the twelfth resistor A second end of the resistor is coupled to a negative output end of the third operational amplifier, a first end of the seventh capacitor is coupled to the non-inverting input end of the third operational amplifier, and the seventh capacitor is A second terminal is coupled to the negative output terminal of the third operational amplifier, the positive output terminal of the operational amplifier is used for outputting the first output signal, and the negative output terminal of the third operational amplifier is used for outputting the first output signal Two output signals. 如申請專利範圍第4項所述之濾波電路，其中該第九電阻器、該第十電阻器、該第十一電阻器及該第十二電阻器為可變電阻器，該第六電容器及該第七電容器為可變電容器，該第九電阻器、該第十電阻器、該第十一電阻器及該第十二電阻器的電阻值及該第六電容器及該第七電容器的電容值係依據該濾波電路處於的一模式為該第一模式或該第二模式決定。The filter circuit as described in claim 4, wherein the ninth resistor, the tenth resistor, the eleventh resistor and the twelfth resistor are variable resistors, the sixth capacitor and The seventh capacitor is a variable capacitor, the resistance values of the ninth resistor, the tenth resistor, the eleventh resistor and the twelfth resistor and the capacitance values of the sixth capacitor and the seventh capacitor It is determined according to a mode in which the filter circuit is in the first mode or the second mode. 如申請專利範圍第4項所述之濾波電路，其中該第九電阻器及該第十一電阻器為可變電阻器，該第三濾波模組的一增益係根據該第九電阻器的電阻值與該第十一電阻器的電阻值決定。The filter circuit of claim 4, wherein the ninth resistor and the eleventh resistor are variable resistors, and a gain of the third filter module is based on the resistance of the ninth resistor The value is determined by the resistance value of the eleventh resistor. 一種濾波電路，包括： 一第一濾波模組，包括一第一運算放大器、一第一開關及一第二開關；以及 一第二濾波模組，耦接至該第一濾波模組，且包括一第二運算放大器、一第三開關、一第四開關、一第五開關、一第六開關、一第七開關及一第八開關，且用以輸出一第一輸出訊號及一第二輸出訊號； 其中，在該第一模式下，藉由該第一開關、該第二開關、該第三開關及該第四開關的不導通且該第五開關、該第六開關、該第七開關及該第八開關的導通，該第二運算放大器的一正輸出端及一負輸出端分別耦接至該第一運算放大器的一反相輸入端及一非反相輸入端並且該第一濾波模組與該第二濾波模組的一階數總和為一第一階數，以及 其中，在該第二模式下，藉由該第一開關、該第二開關、該第三開關及該第四開關的導通且該第五開關、該第六開關、該第七開關及該第八開關的不導通，該第二運算放大器的該正輸出端及該負輸出端不耦接至該第一運算放大器，且該第一濾波模組與該第二濾波模組的該階數總和為大於該第一階數的一第二階數。 A filter circuit, comprising: a first filter module including a first operational amplifier, a first switch and a second switch; and A second filter module is coupled to the first filter module and includes a second operational amplifier, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch and an eighth switch for outputting a first output signal and a second output signal; Wherein, in the first mode, by the non-conduction of the first switch, the second switch, the third switch and the fourth switch and the fifth switch, the sixth switch, the seventh switch and the When the eighth switch is turned on, a positive output terminal and a negative output terminal of the second operational amplifier are respectively coupled to an inverting input terminal and a non-inverting input terminal of the first operational amplifier, and the first filter module summing with the first order of the second filter module is a first order, and Wherein, in the second mode, through the conduction of the first switch, the second switch, the third switch and the fourth switch and the fifth switch, the sixth switch, the seventh switch and the fourth switch The eight switches are non-conductive, the positive output terminal and the negative output terminal of the second operational amplifier are not coupled to the first operational amplifier, and the sum of the order of the first filter module and the second filter module is a second order greater than the first order. 如申請專利範圍第7項所述之濾波電路，更包括： 一第三濾波模組，耦接至該第一濾波模組，且用以接收一第一輸入訊號及一第二輸入訊號。 The filter circuit as described in item 7 of the patent application scope further includes: A third filter module is coupled to the first filter module and used for receiving a first input signal and a second input signal. 如申請專利範圍第8項所述之濾波電路，其中： 該第一濾波模組更包括一第一電阻器、一第二電阻器、一第四電阻器、一第一電容器及一第二電容器， 其中該第一電阻器的一第一端耦接至該第一運算放大器的該反相輸入端，該第一電阻器的一第二端耦接至該第一開關的一第一端，該第一電容器的一第一端耦接至該第一運算放大器的該反相輸入端，該第一電容器的一第二端耦接至該第一開關的一第二端及該第一運算放大器的一正輸出端，該第二電阻器的一第一端耦接至該第一運算放大器的該非反相輸入端，該第二電阻器的一第二端耦接至該第二開關的一第一端，該第二電容器的一第一端耦接至該第一運算放大器的該非反相輸入端，該第二電容器的一第二端耦接至該第二開關的一第二端及該第一運算放大器的一負輸出端；以及 該第二濾波模組更包括一第三電阻器、一第五電阻器、一第六電阻器、一第七電阻器、一第八電阻器、一第三電容器、一第四電容器及一第五電容器， 其中該第三電阻器的一第一端耦接至該第一運算放大器的該負輸出端，該第四電阻器的一第一端耦接至該第一運算放大器的該正輸出端，該第三電容器一第一端耦接至該第三開關的一第一端，該第三開關的一第二端耦接至該第三電阻器的一第二端，該第三電容器的一第二端耦接至該第四開關的一第一端，該第四開關的一第二端耦接至該第四電阻器的一第二端，該第五電阻器的一第一端耦接至該第三電阻器的該第二端，該第七電阻器的一第一端耦接至該第五開關的一第一端，該第七電阻器的一第二端耦接至該第七開關的一第一端及該第二運算放大器的該正輸出端，該第七開關的一第二端耦接至該第一電阻器的第二端，該第四電容器的一第一端耦接至該第五開關的一第二端，該第四電容器的一第二端耦接至該第二運算放大器的該正輸出端，該第五開關的該第二端耦接至該第五電阻器的一第二端及該第二運算放大器的一反相輸入端，該第六電阻器的一第一端耦接至該第四電阻器的該第二端，該第八電阻器的一第一端耦接至該第六開關的一第一端，該第八電阻器的一第二端耦接至該第八開關的一第一端及該第二運算放大器的該負輸出端，該第八開關的一第二端耦接至該第二電阻器的該第二端，該第五電容器的一第一端耦接至該第六開關的一第二端，該第五電容器的一第二端耦接至該第二運算放大器的該負輸出端，該第六開關的該第二端耦接至該第六電阻器的一第二端及該第二運算放大器的一非反相輸入端，該第二運算放大器的該正輸出端用以輸出該第一輸出訊號，該第二運算放大器的該負輸出端用以輸出該第二輸出訊號。 The filter circuit as described in claim 8, wherein: The first filter module further includes a first resistor, a second resistor, a fourth resistor, a first capacitor and a second capacitor, A first end of the first resistor is coupled to the inverting input end of the first operational amplifier, a second end of the first resistor is coupled to a first end of the first switch, the A first end of the first capacitor is coupled to the inverting input end of the first operational amplifier, and a second end of the first capacitor is coupled to a second end of the first switch and the first operational amplifier a positive output end of the second resistor, a first end of the second resistor is coupled to the non-inverting input end of the first operational amplifier, a second end of the second resistor is coupled to a a first end, a first end of the second capacitor is coupled to the non-inverting input end of the first operational amplifier, a second end of the second capacitor is coupled to a second end of the second switch and a negative output terminal of the first operational amplifier; and The second filter module further includes a third resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a third capacitor, a fourth capacitor and a first Five capacitors, A first end of the third resistor is coupled to the negative output end of the first operational amplifier, a first end of the fourth resistor is coupled to the positive output end of the first operational amplifier, the A first end of the third capacitor is coupled to a first end of the third switch, a second end of the third switch is coupled to a second end of the third resistor, and a first end of the third capacitor Two terminals are coupled to a first terminal of the fourth switch, a second terminal of the fourth switch is coupled to a second terminal of the fourth resistor, and a first terminal of the fifth resistor is coupled to to the second end of the third resistor, a first end of the seventh resistor is coupled to a first end of the fifth switch, and a second end of the seventh resistor is coupled to the first end A first end of seven switches and the positive output end of the second operational amplifier, a second end of the seventh switch is coupled to the second end of the first resistor, and a first end of the fourth capacitor is coupled to a second end of the fifth switch, a second end of the fourth capacitor is coupled to the positive output end of the second operational amplifier, and the second end of the fifth switch is coupled to the first A second end of the five resistors and an inverting input end of the second operational amplifier, a first end of the sixth resistor is coupled to the second end of the fourth resistor, and the eighth resistor A first end of the eighth resistor is coupled to a first end of the sixth switch, a second end of the eighth resistor is coupled to a first end of the eighth switch and the negative output of the second operational amplifier terminal, a second terminal of the eighth switch is coupled to the second terminal of the second resistor, a first terminal of the fifth capacitor is coupled to a second terminal of the sixth switch, the fifth A second end of the capacitor is coupled to the negative output end of the second operational amplifier, the second end of the sixth switch is coupled to a second end of the sixth resistor and a second end of the second operational amplifier a non-inverting input terminal, the positive output terminal of the second operational amplifier is used for outputting the first output signal, and the negative output terminal of the second operational amplifier is used for outputting the second output signal. 如申請專利範圍第9項所述之濾波電路，其中： 該第三濾波模組，包括一第三運算放大器、一第九電阻器、一第十電阻器、一第十一電阻器、一第十二電阻器、一第六電容器及一第七電容器，其中該第九電阻器的一第一端用以接收該第一輸入訊號，該第十一電阻器的一第一端耦接至該第九電阻器的一第二端及該第三運算放大器的一反相輸入端該第十一電阻器的一第二端耦接至該第三運算放大器的一正輸出端，該第六電容器的一第一端耦接至該第三運算放大器的該反相輸入端，該第六電容器的一第二端耦接至該第三運算放大器的該正輸出端，該第十電阻器的一第一端用以接收該第二輸入訊號，該第十二電阻器的一第一端耦接至該第十電阻器的一第二端及該第三運算放大器的一非反相輸入端，該第十二電阻器的一第二端耦接至該第三運算放大器的一負輸出端，該第七電容器的一第一端耦接至該第三運算放大器的該非反相輸入端，該第七電容器的一第二端耦接至該第三運算放大器的該負輸出端，該運算放大器的該正輸出端耦接至該第一運算放大器的該非反相輸入端，該第三運算放大器的該負輸出端耦接至該第一運算放大器的該反相輸入端。 The filter circuit as described in item 9 of the scope of the application, wherein: The third filter module includes a third operational amplifier, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a sixth capacitor and a seventh capacitor, A first end of the ninth resistor is used for receiving the first input signal, and a first end of the eleventh resistor is coupled to a second end of the ninth resistor and the third operational amplifier An inverting input end of the eleventh resistor is coupled to a positive output end of the third operational amplifier, and a first end of the sixth capacitor is coupled to the third operational amplifier an inverting input end, a second end of the sixth capacitor is coupled to the positive output end of the third operational amplifier, a first end of the tenth resistor is used for receiving the second input signal, the tenth A first end of the two resistors is coupled to a second end of the tenth resistor and a non-inverting input end of the third operational amplifier, and a second end of the twelfth resistor is coupled to the A negative output terminal of the third operational amplifier, a first terminal of the seventh capacitor is coupled to the non-inverting input terminal of the third operational amplifier, and a second terminal of the seventh capacitor is coupled to the third operational amplifier The negative output terminal of the amplifier, the positive output terminal of the operational amplifier is coupled to the non-inverting input terminal of the first operational amplifier, the negative output terminal of the third operational amplifier is coupled to the first operational amplifier Inverting input. 如申請專利範圍第10項所述之濾波電路，其中該第九電阻器、該第十電阻器、該第十一電阻器及該第十二電阻器為可變電阻器，該第六電容器及該第七電容器為可變電容器，該第九電阻器、該第十電阻器、該第十一電阻器及該第十二電阻器的電阻值及該第六電容器及該第七電容器的電容值係依據該濾波電路處於的一模式為該第一模式或該第二模式決定。The filter circuit as described in claim 10, wherein the ninth resistor, the tenth resistor, the eleventh resistor and the twelfth resistor are variable resistors, the sixth capacitor and The seventh capacitor is a variable capacitor, the resistance values of the ninth resistor, the tenth resistor, the eleventh resistor and the twelfth resistor and the capacitance values of the sixth capacitor and the seventh capacitor It is determined according to a mode in which the filter circuit is in the first mode or the second mode. 如申請專利範圍第10項所述之濾波電路，其中中該第九電阻器及該第十一電阻器為可變電阻器，該第三濾波模組的一增益係根據該第九電阻器的電阻值與該第十一電阻器的電阻值決定。The filter circuit as described in claim 10, wherein the ninth resistor and the eleventh resistor are variable resistors, and a gain of the third filter module is based on a gain of the ninth resistor The resistance value is determined by the resistance value of the eleventh resistor.
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TWI783808B (en) * 2021-12-02 2022-11-11 瑞昱半導體股份有限公司 Signal receiving apparatus and programmable gain amplifier having mode-switching mechanism
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Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5168461A (en) * 1989-08-21 1992-12-01 Industrial Technology Research Institute Switched capacitor differentiators and switched capacitor differentiator-based filters
US5391999A (en) * 1993-12-02 1995-02-21 Motorola Inc. Glitchless switched-capacitor biquad low pass filter
US6172630B1 (en) * 1998-08-18 2001-01-09 Tektronix, Inc. Extended common mode input range for a delta-sigma converter
TW427053B (en) * 1999-03-10 2001-03-21 Nat Science Council Low voltage switched capacitor integrator having offset voltage compensation and the filter using the same
JP2008544601A (en) * 2005-06-10 2008-12-04 テレフオンアクチーボラゲット エル エム エリクソン（パブル） Phase shift device
US8260212B2 (en) * 2009-05-19 2012-09-04 Broadcom Corporation Method and system for a reconfigurable filter that is utilized by a RF transmitter and a RF receiver which are integrated on a single substrate
JP5270488B2 (en) * 2009-08-03 2013-08-21 ルネサスエレクトロニクス株式会社 Filter circuit and receiving circuit using the same
JP5846840B2 (en) * 2011-10-14 2016-01-20 ルネサスエレクトロニクス株式会社 Filter circuit and receiver
CN104283521A (en) * 2013-07-03 2015-01-14 核芯科技股份有限公司 Switching type capacitive filter and filtering method thereof
CN103956989B (en) * 2014-05-23 2018-01-26 武汉大学 A kind of multimode multi-frequency restructural Gm C complex filters
CN204707103U (en) * 2015-07-15 2015-10-14 上海玮舟微电子科技有限公司 Configurable low pass filter and the multiple band pass filter that is suitable for
US9912311B2 (en) * 2015-07-22 2018-03-06 Samsung Electronics Co., Ltd Multimode reconfigurable amplifier and analog filter including the same
CN106411287B (en) * 2016-10-28 2019-01-15 桂林电子科技大学 A kind of tunable complex intermediate frequency filter of low-power consumption double mode
CN108322237B (en) * 2017-01-14 2020-09-29 鸿富锦精密工业（深圳）有限公司 Interference suppression system and method
CN106849988B (en) * 2017-03-27 2022-04-12 辽宁工程技术大学 UHF-RFID reader-writer channel selection filter supporting double protocols
US10608601B2 (en) * 2017-05-31 2020-03-31 Qualcomm Incorporated Active biquad filter with oscillator circuit
CN111835383B (en) * 2019-04-17 2022-04-01 达发科技(苏州)有限公司 Echo and near-end crosstalk elimination system

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