TW202221804A - Packaging piece and method of forming the same - Google Patents

Abstract

The embodiment of the invention provides a method of forming a packaging piece. The method comprises the following steps: placing a first chip layer over a carrier, wherein the first chip layer includes a plurality of first chips with a front side facing upward; placing and assembling a second chip layer on the first chip layer, wherein the second chip layer includes a plurality of second chips with the front side facing upward and a plurality of chip couplers, the upper surfaces of the plurality of second chips and the plurality of chip couplers have a plurality of first bumps; molding the first chip layer and the second chip layer above the carrier to form a plastic package structure; thinning the plastic package structure so as to expose the plurality of first bumps; adding a rewiring layer and a plurality of second bumps above the second chip layer; removing the carrier to form a packaging piece main body; and segmenting the packaging piece main body to form a plurality of the packaging pieces.

Description

Package and method of forming the same

The present invention relates to the technical field of semiconductors, and in particular, to a package and a method for forming the same.

At present, more and more functions are required for semiconductor integrated circuits, and the required computing speed is getting faster and faster. Under this situation, the industry has begun to increase investment in the research and development of wafer stacking technology to explore the use of wafer stacking technology. more efficient solutions. However, conventional wafer-level packaging (WLP) technology cannot achieve stacking of wafers. In the traditional chip stacking technology, the stacking is mostly completed in the final assembly, and it is necessary to use through silicon vias (TSV, Through Silicon Via), glass substrate vias (TGV, Through Glass Via), plastic packaging layer through holes (TMV, Through Mold Via) or wire bonding (Wire-bond) and other technologies to achieve vertical connection between stacked wafers. The packaging process of the traditional stacking technology is complex and expensive.

Embodiments of the present invention provide a solution for forming a package including a plurality of stacked dies.

One aspect of the present invention provides a method of forming a package, which may include: placing a plurality of first wafer layers over a carrier, each first wafer layer including a face-down plurality of first wafers and a a plurality of wafer couplers between a plurality of first wafers; placing and assembling a second wafer layer on the plurality of first wafer layers, the second wafer layer including a face-down plurality of second wafers; in molding the plurality of first wafer layers and the second wafer layers above the carrier; removing the carrier to form a package body, and adding a redistribution layer and a redistribution layer below the package body bumps; and dividing the package body to form a plurality of the packages.

The plurality of wafer connectors may be active or passive coupling devices.

The plurality of wafer couplers may be arranged to include at least one through hole in the vertical direction.

In a stack formed of multiple wafer couplers located in different first wafer layers, the vertical center axis of each wafer coupler may not exactly coincide.

In a stack formed of a plurality of wafer couplers located in different first wafer layers, the central axis in the vertical direction of each wafer coupler can be coupled to a wafer in a first wafer layer that is one first wafer layer apart The central axis of the device in the vertical direction coincides.

In a stack formed of a plurality of wafer couplers located in different first wafer layers, the central axis of each wafer coupler in the vertical direction may not coincide with each other.

The package may include a first wafer stack formed by stacking a plurality of first wafers together, a second wafer placed over the first wafer stack, and two wafers formed by stacking together a plurality of diced wafer connectors. a stack of wafer couplers, wherein the second wafer is assembled over the two stacks of wafer couplers, wherein the second wafer can be electrically coupled to the redistribution layer through the stack of wafer couplers to the first wafer stack, or the second wafer can be electrically coupled to the first wafer stack through the wafer coupler stack.

Another aspect of the present invention provides a method of forming a package, which may include: placing a plurality of first wafer layers over a carrier, each first wafer layer including a face-down plurality of first wafers and a plurality of first wafer couplers and a plurality of second wafer couplers between the plurality of first wafers; placing and assembling a second wafer layer on the plurality of first wafer layers, the second wafer layer comprising face down a plurality of second wafers; molding the plurality of first wafer layers and the second wafer layers over the carrier; removing the carrier to form a package body, and adding a redistribution layer and bumps below the package body; and dividing the package body to form a plurality of the packages.

The plurality of first wafer connectors may be active or passive coupling devices, and the plurality of second wafer connectors may be active or passive coupling devices.

The plurality of first wafer couplers and the plurality of second wafer couplers may be arranged to include at least one through hole in the vertical direction.

In each first wafer layer, a first wafer coupler and a second wafer coupler may be respectively disposed between each first wafer and two adjacent first wafers.

In a stack formed by a plurality of first wafer couplers and a plurality of second wafer couplers located in different first wafer layers, the same wafer couplers may not be adjacent to each other.

The package may include a first wafer stack formed by stacking a plurality of first wafers together, a second wafer placed over the first wafer stack, and two wafers formed by stacking together a plurality of diced wafer connectors. a stack of wafer couplers, wherein the second wafer is assembled over the two stacks of wafer couplers, wherein the second wafer can be electrically coupled to the redistribution layer through the stack of wafer couplers to the first wafer stack, or the second wafer can be electrically coupled to the first wafer stack through the wafer coupler stack.

Yet another aspect of the present invention provides a package including: a redistribution layer including a first side and a second side; a plurality of bumps disposed on the first side of the redistribution layer; a first die stack , which is assembled on the second side of the redistribution layer, the first wafer stack includes a plurality of first wafers placed face down; a first wafer coupler stack and a second wafer coupler stack, which are placed and assembled on the second side of the redistribution layer and placed horizontally and assembled on both sides of the first wafer stack, respectively; and a second wafer placed over the first wafer stack and assembled on Above the first die coupler stack and the second die coupler stack, wherein the package is molded into an overmolded structure.

The first and second wafer coupler stacks may each include a plurality of first wafer couplers and a plurality of second wafer couplers.

The first wafer connector may be an active connector device or a passive connector device, and the second wafer connector may be an active connector device or a passive connector device.

The first wafer coupler and the second wafer coupler may be arranged to include at least one through hole in the vertical direction.

The same wafer couplers may not be adjacent to each other in the first wafer coupler stack and the second wafer coupler stack.

In the package, identical die couplers in different die coupler stacks may not be at the same vertical height from each other.

The first wafer coupler stack and the second wafer coupler stack may each include a plurality of wafer couplers, and each of the multiple wafer couplers may have a different area in the horizontal direction.

Each of the plurality of wafer couplers may be an active link device or a passive link device.

Each of the plurality of wafer couplers may be arranged to include at least one through hole in the vertical direction.

Embodiments of the present invention utilize a wafer coupler and a one-stop WLP process to achieve stacking of wafers, without the need to use technologies such as TSV to vertically couple wafers in functional wafers. Therefore, the complexity and manufacturing cost of the three-dimensional multilayer chip package is reduced.

In addition, the embodiments of the present invention can also make the specifications and dimensions of the wafers and wafer connectors as unified and standardized as possible through a reasonable layout, thereby reducing the manufacturing time of the wafers and wafer connectors before implementing the method of forming the package. cost.

The above description is only an overview of the technical solutions of the present invention, in order to be able to understand the technical means of the present invention more clearly, it can be implemented according to the content of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand , the following specific embodiments of the present invention are given.

The following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are only examples and are not intended to limit the invention. For example, in the following description, forming the first part over or on the second part may include embodiments in which the first part and the second part are formed in direct contact, and may also include additionally forming between the first part and the second part. parts so that the first part and the second part may not be in direct contact. Furthermore, the present disclosure may repeat reference numerals and/or characters in various embodiments. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate a relationship between the various embodiments and/or configurations discussed.

Also, for ease of description, spatially relative terms such as "below", "below", "lower", "above", "upper", "above" and the like may be used herein to Describe the relationship of one element or component to another (or other) elements or components as shown. In addition to the orientation shown in the figures, spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Also, as used herein, the term "assembled" refers to the realization of circuit coupling between various electronic devices. The term "wafer" may refer to various types of wafers, such as logic wafers, memory wafers, and the like.

FIG. 1 shows a flowchart of a method of forming a package according to an embodiment of the present invention. The method includes the following four steps:

Step 100: Place and assemble wafer layers on a carrier.

Step 200: Molding the wafer layer.

Step 300: Remove the carrier to form the package body, and add redistribution layers and bumps.

Step 400: Divide the package body to form the package.

In some embodiments, the carrier is a very flat surface component on which at least one wafer layer can be stacked. After molding the wafer layers, a molding structure can be formed on the carrier. In some embodiments, the materials used for the molding process may include solid or liquid molding materials based on epoxy resins, organic polymers, or other compounds with or without the addition of silicon-based or glass fillers.

In some embodiments, the steps of removing the carrier, adding the redistribution layers and bumps, and dividing the package body are steps known in wafer level packaging (WLP).

Various embodiments of the present invention will be described below based on the above method and with reference to the accompanying drawings.

2 to 4 illustrate schematic cross-sectional views of forming a package according to a first embodiment of the present invention. FIG. 2 shows a schematic diagram of the package structure after steps 100 and 200 are implemented.

As shown in FIG. 2 , five wafer layers are placed and assembled on the carrier 10 , wherein the lower four wafer layers are the first wafer layer, and the uppermost wafer layer is the second wafer layer. The first wafer layer may include a plurality of first wafers 11 and a plurality of wafer couplers 13 . The second wafer layer may include a plurality of second wafers 12 . In some embodiments, there may be at least two first wafer layers, not limited to four first wafer layers.

The first wafer 11 and the wafer couplers 13 may be firstly placed on the carrier 10 at intervals in the horizontal direction to form a first wafer layer, then a plurality of first wafer layers may be stacked on the first wafer layer, and finally A second wafer layer is placed and assembled on the uppermost first wafer layer. The wafer includes a front side and a back side. In the art, a surface with, for example, bumps is considered a front face. In some embodiments, the first wafer 11 and the second wafer 12 are placed face down.

In this context, a wafer coupler may be used to electrically couple different electronic devices including, for example, a variety of devices including wafers, redistribution layers, and other wafer couplers; the wafer coupler typically connects electronic devices that are not coupled to the wafer are in the same wafer layer. In some embodiments, the wafer connector may be made of materials such as glass or silicon. In some embodiments, the wafer coupler may be an active link device or a passive link device. For example, the wafer coupler may have several through holes 14 in the vertical direction. A conductive medium may be filled in the vias 14 . In some embodiments, conductive traces may be provided on both the upper and lower surfaces of the wafer connector to electrically connect different vias on one surface.

Adhesive dots, such as the adhesive dots 18 shown in FIG. 2 , may also be provided between the different wafer layers. Bond points are used to isolate and secure different wafer layers. In some embodiments, the bond points are made of a non-conductive medium. In some embodiments, the description of the bonding point will be omitted.

After the individual wafer layers are placed and assembled, the individual wafer layers may also be molded to form the plastic encapsulation structure 15 .

In addition, as shown in FIG. 2, in any stack formed by a plurality of wafer couplers located in different first wafer layers, the vertical center axis of each wafer coupler does not exactly coincide. For example, the center axis of the lowermost wafer coupler in any wafer coupler stack does not coincide with the center axis above the wafer coupler, but does coincide with the center axis of the wafer coupler in a first wafer layer apart.

In other embodiments, in any stack formed from a plurality of wafer couplers located in different first wafer layers, the vertical center axis of each wafer coupler does not coincide. For example, the center axis of each wafer coupler is spaced a predetermined distance in the horizontal direction from the center axis of the wafer coupler above it.

FIG. 3 shows the structure of the package body after step 300 is implemented.

As shown in FIG. 3 , five wafer layers have been molded to form an encapsulated structure 15 . After removal of carrier 10 , redistribution layer 16 may be added under the package body, and bumps 17 may be added under redistribution layer 16 .

FIG. 4 shows the structure of the package after step 400 is implemented.

The package includes two wafer coupler stacks formed of eight diced wafer couplers, a first wafer stack formed of four first wafers 11 , and a second wafer 12 .

The second wafer 12 may be electrically coupled to the first wafer stack through two wafer coupler stacks and redistribution layers, respectively, or through two wafer coupler stacks, respectively. In some embodiments, the second wafer 12 may be electrically coupled to any one of the first wafers 11 in the first wafer stack via any one of the wafer coupler stacks and redistribution layers, or the second wafer 12 may be via any one of the wafer couplers The stack is electrically coupled to any one of the first wafers 11 in the first wafer stack.

Of course, since the number of first wafer layers may be at least two, the number of first wafers 11 in the first wafer stack and the number of wafer couplers in each wafer coupler stack may also be at least two.

In some embodiments, since the center axes in the vertical direction of each wafer coupler in each wafer coupler stack in FIGS. In any stack formed by the wafer couplers, each divided wafer coupler has the same area in the horizontal direction as the wafer coupler separated by one wafer coupler.

In other embodiments, multiple die couplers in each package may Various forms of wafer connector stacks are formed, such as trapezoidal stacks or inverted trapezoidal stacks. This results in a different area in the horizontal direction for each of the plurality of wafer couplers in each wafer coupler stack.

According to the first embodiment of the present invention, by rationally arranging the wafers and the wafer connectors, the specifications or sizes of the plurality of first wafers and the plurality of wafer connectors can be unified, thereby reducing the number of wafers manufactured before implementing the method of forming the package. and wafer coupler cost.

5 to 7 illustrate schematic cross-sectional views of forming a package according to a second embodiment of the present invention. The second embodiment is a modification of the first embodiment. FIG. 5 shows a schematic diagram of the package structure after steps 100 and 200 are implemented.

As shown in FIG. 5 , five wafer layers are placed and assembled on the carrier 20 , wherein the lower four wafer layers are the first wafer layer, and the uppermost wafer layer is the second wafer layer. The first wafer layer may include a plurality of first wafers 21 , a plurality of first wafer couplers 23 and a plurality of second wafer couplers 28 . The second wafer layer may include a plurality of second wafers 22 . In some embodiments, there may be at least two first wafer layers, not limited to four first wafer layers.

The first wafer 21 , the first wafer coupler 23 and the second wafer coupler 28 may be firstly placed on the carrier 20 at intervals in the horizontal direction to form a first wafer layer. For example, the left and right sides of any one of the first wafers are different wafer couplers.

A plurality of first wafer layers may then be stacked on the first wafer layer. In some embodiments, the placement positions of the wafer couplers in each of the first wafer layers are not identical. For example, the placement positions of wafer couplers in adjacent first wafer layers are diametrically opposed, so that in the wafer coupler stack formed by the first wafer coupler 23 and the second wafer coupler 28, the first wafer coupler 23 Between the two second wafer couplers 28 and the second wafer coupler 28 between the two first wafer couplers 23 , as shown in FIG. 5 .

Finally the second wafer layer can be placed and assembled on the uppermost first wafer layer. The wafer includes a front side and a back side. In the art, a surface with, for example, bumps is considered a front face. In some embodiments, the first wafer 21 and the second wafer 22 are placed face down.

After the individual wafer layers are placed and assembled, the individual wafer layers can also be molded to form the plastic encapsulation structure 25 .

FIG. 6 shows the structure of the package body after step 300 is implemented.

As shown in FIG. 6 , five wafer layers have been molded and an overmolded structure 25 is formed. After removal of carrier 20 , redistribution layer 26 may be added under the package body, and bumps 27 may be added under redistribution layer 26 .

FIG. 7 shows the structure of the package after step 400 is implemented.

The package includes two die coupler stacks formed from eight diced die couplers, a first die stack formed from four first die 21 , and one second die 22 . Each wafer coupler stack includes two segmented first wafer couplers 23 and two segmented second wafer couplers 28 spaced apart such that identical wafer couplers are not adjacent to each other. In some embodiments, identical wafer couplers in different wafer coupler stacks are not at the same vertical height from each other.

The second wafer 22 may be electrically coupled to the first wafer stack through two wafer coupler stacks and redistribution layers, respectively, or through two wafer coupler stacks, respectively. In some embodiments, the second wafer 22 may be electrically coupled to any one of the first wafers 21 in the first wafer stack through any one of the wafer coupler stacks and redistribution layers, or the second wafer 22 may be through any one of the wafer couplers The stack is electrically coupled to any one of the first wafers 21 in the first wafer stack.

Of course, since the number of first wafer layers may be at least two, the number of first wafers in the first wafer stack and the number of wafer couplers in each wafer coupler stack may also be at least two.

According to the second embodiment of the present invention, by rationally arranging the wafers and the wafer connectors, the specifications or sizes of the plurality of first wafers and part of the wafer connectors can be unified, thereby reducing the number of wafers and chips produced before implementing the method of forming the package. The cost of the wafer coupler.

The features of several embodiments have been outlined above so that those skilled in the art may better understand aspects of the invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present invention.

Step 100: Place and Assemble the Wafer Layers on the Carrier Step 200: Molding the wafer layer STEP 300: Remove carrier to form package body and add redistribution layers and bumps STEP 400: Divide the package body to form the package 10: Carrier 11: The first wafer 12: Second chip 13: Wafer Connector 14: Through hole 15: Plastic structure 16: Redistribution layer 17: bump 18: Bonding point 20: Carrier 21: The first wafer 22: Second wafer 23: First wafer connector 25: Plastic structure 26: Rewiring layer 27: bump 28: Second wafer connector

The above and other objects, features and advantages of exemplary embodiments of the present invention will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present invention are shown by way of example and not limitation, wherein:

In the drawings, the same or corresponding reference numerals denote the same or corresponding parts.

[ FIG. 1 ] A flowchart showing a method of forming a package according to an embodiment of the present invention. 2 to 4 are schematic cross-sectional views showing the formation of the package according to the first embodiment of the present invention. [ FIGS. 5 to 7 ] are schematic cross-sectional views showing the formation of a package according to a second embodiment of the present invention.

Step 100: Place and Assemble the Wafer Layers on the Carrier

Step 200: Molding the wafer layer

STEP 300: Remove carrier to form package body and add redistribution layers and bumps

STEP 400: Divide the package body to form the package

Claims (22)

A method of forming a package, the method comprising: placing a plurality of first wafer layers over the carrier, each first wafer layer including a face-down plurality of first wafers and a plurality of wafer couplers between the plurality of first wafers; placing and assembling a second wafer layer on the plurality of first wafer layers, the second wafer layer including a face-down plurality of second wafers; molding the plurality of first wafer layers and the second wafer layers over the carrier; removing the carrier to form a package body, and adding a redistribution layer and bumps beneath the package body; and The package body is divided to form a plurality of the packages. The method of claim 1, wherein the plurality of wafer connectors are active or passive coupling devices. The method of claim 1, wherein the plurality of wafer couplers are arranged to include at least one through hole in the vertical direction. The method of claim 1, wherein, in the stack formed of a plurality of wafer couplers located in different first wafer layers, the vertical center axis of each wafer coupler does not exactly coincide. The method of claim 4, wherein, in a stack formed from a plurality of wafer couplers located in different first wafer layers, each wafer coupler has a vertical center axis that is one first wafer apart The central axes in the vertical direction of the wafer couplers in the first wafer layer of the layers coincide. The method of claim 1 wherein, in the stack formed of a plurality of wafer couplers located in different first wafer layers, the vertical center axes of each wafer coupler do not coincide with each other. The method of claim 1, wherein the package includes a first wafer stack formed by stacking a plurality of first wafers together, a second wafer placed over the first wafer stack, and a plurality of Two wafer coupler stacks formed by stacking split wafer couplers together, wherein the second wafer is assembled over the two wafer coupler stacks, wherein the second wafer can pass through the The wafer coupler stack and the redistribution layer are electrically coupled to the first wafer stack, or the second wafer can be electrically coupled to the first wafer stack through the wafer coupler stack. A method of forming a package, the method comprising: A plurality of first wafer layers are placed over the carrier, each first wafer layer including a face-down plurality of first wafers and a plurality of first wafer couplers and a plurality of first wafers between the plurality of first wafers a second wafer coupler; placing and assembling a second wafer layer on the plurality of first wafer layers, the second wafer layer including a face-down plurality of second wafers; molding the plurality of first wafer layers and the second wafer layers over the carrier; removing the carrier to form a package body, and adding a redistribution layer and bumps beneath the package body; and The package body is divided to form a plurality of the packages. The method of claim 8, wherein the plurality of first wafer connectors are active or passive coupling devices and the plurality of second wafer connectors are active or passive coupling devices device. The method of claim 8, wherein the plurality of first wafer couplers and the plurality of second wafer couplers are arranged to include at least one through hole in the vertical direction. The method of claim 8, wherein, in each of the first wafer layers, a first wafer coupler and a first wafer are respectively disposed between each first wafer and two adjacent first wafers Two wafer connector. The method of claim 8, wherein in a stack formed of a plurality of first wafer couplers and a plurality of second wafer couplers located in different first wafer layers, the same wafer couplers are not mutually exclusive adjacent. The method of claim 8, wherein the package includes a first wafer stack formed by stacking a plurality of first wafers together, a second wafer placed over the first wafer stack, and a plurality of two wafer coupler stacks formed by stacking split wafer couplers together, wherein the second wafer is assembled over the two wafer coupler stacks, wherein the second wafer can pass through the The wafer coupler stack and the redistribution layer are electrically coupled to the first wafer stack, or the second wafer can be electrically coupled to the first wafer stack through the wafer coupler stack. A package comprising: a redistribution layer including a first side and a second side; a plurality of bumps disposed on the first side of the redistribution layer; a first wafer stack assembled on the second side of the redistribution layer, the first wafer stack including a plurality of first wafers placed face down; a first stack of wafer connectors and a second stack of wafer connectors placed and assembled on the second side of the redistribution layer and placed and assembled horizontally on both sides of the first wafer stack, respectively; and a second wafer placed over the first wafer stack and assembled over the first wafer coupler stack and the second wafer coupler stack, Wherein, the package is molded into a plastic package structure. The method of claim 14, wherein the first wafer coupler stack and the second wafer coupler stack each include a plurality of first wafer couplers and a plurality of second wafer couplers. The method of claim 15, wherein the first wafer coupler is an active or passive coupler device and the second wafer coupler is an active or passive coupler device. The method of claim 15, wherein the first wafer coupler and the second wafer coupler are arranged to include at least one through hole in the vertical direction. The method of claim 15, wherein the same wafer couplers are not adjacent to each other in the first wafer coupler stack and the second wafer coupler stack. 19. The method of claim 18, wherein, in the package, identical die couplers in different die coupler stacks are not at the same vertical height from each other. The method of claim 14, wherein the first wafer coupler stack and the second wafer coupler stack each include a plurality of wafer couplers, each of the plurality of wafer couplers in a horizontal orientation different areas. The method of claim 20, wherein each of the plurality of wafer connectors is an active coupling device or a passive coupling device. The method of claim 21, wherein each of the plurality of wafer couplers is configured to include at least one through hole in the vertical direction.

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