TW202220071A - Chip package method capable of simplifying the packaging process and improving the transmission efficiency. - Google Patents

Abstract

The chip package method provided by the present invention includes firstly fixing a chip on the top surface of a carrier, then covering the chip with a molding compound, then drilling holes on the molding compound from the top of the molding compound to make the molding compound have a through hole adjacent to the chip, and finally planting a conductive metal respectively between the chip and the through hole and on the hole wall of the through hole, so that the chip is electrically connected to the carrier through the conductive metal. In this way, the chip package method provided by the present invention can solve the problems of the traditional wire bonding process, thereby achieving the effects of simplifying the packaging process and improving the transmission efficiency.

Description

Chip packaging method

The present invention relates to a chip packaging method, in particular to a chip packaging method which can simplify the manufacturing process and improve the transmission efficiency.

The traditional packaging process is to use glue to fix the chip on the carrier board, then use a plurality of metal wires to connect the chip and the carrier board, so that the two are connected to each other, and finally use packaging glue (such as epoxy resin) to cover the chip. , so that the entire packaging process is completed.

However, the metal wire is connected between the chip and the carrier by wire bonding, which is complicated for the packaging process. In addition, due to the length of the metal wire, it will not only cause a long transmission path and affect the performance, but also make it difficult for the product size to meet the ideal requirements, resulting in a lack of competitiveness when applied to products.

The main purpose of the present invention is to provide a chip packaging method, which can simplify the packaging process and improve the transmission efficiency.

In order to achieve the above-mentioned main purpose, the chip packaging method of the present invention includes the following steps: fixing a chip on the top surface of a carrier board; covering the chip with an encapsulating compound; facing the encapsulating compound from the top of the encapsulating compound Drilling is carried out so that the encapsulant has a first through hole adjacent to the chip; a layer is respectively plated between the top surface of the chip and the top of the first through hole and the hole wall of the first through hole The conductive metal enables the chip to be electrically connected to the carrier through the conductive metal.

As can be seen from the above, the chip packaging method provided by the present invention electrically conducts the chip and the carrier through the conductive metal, without the need to pass through the metal wire, so it can solve various problems caused by the traditional wire bonding process, thereby simplifying the packaging process. and improve the transmission efficiency.

Preferably, the carrier can be used on both sides to improve the utilization rate, that is, according to the above steps, the chip, the encapsulant, the first through hole and the Conductive metal, and then cut the carrier board into two upper and lower parts from the middle, and finally cut according to the number of the chips to form a plurality of chip packaging structures, which can improve the process efficiency.

Preferably, the first through hole can penetrate through the encapsulant and the carrier, and then the carrier is drilled from the bottom of the carrier so that the carrier has a second through hole adjacent to the chip. Then, between the bottom surface of the carrier plate and the bottom end of the first through hole, between the bottom surface of the carrier plate and the bottom end of the second through hole, and the hole wall of the second through hole, a layer is respectively plated with a layer Conductive metal, so that the entire chip package structure does not need to be turned upside down by 180 degrees when electrically connecting with the printed circuit board, so as to increase the convenience in use.

The detailed structure, features, assembly or usage of the chip packaging method provided by the present invention will be described in the detailed description of the following embodiments. However, those with ordinary knowledge in the field of the present invention should understand that these detailed descriptions and specific embodiments for implementing the present invention are only used to illustrate the present invention, not to limit the scope of the patent application of the present invention.

The applicant first explains that in the entire specification, including the embodiments described below and the claims of the scope of the patent application, the terms related to the directionality are based on the directions in the drawings. Next, in the embodiments and drawings to be introduced below, the same element numbers represent the same or similar elements or their structural features.

Please refer to FIG. 1A and FIG. 1B first, the chip packaging method according to the first embodiment of the present invention includes the following steps:

a): In step S1 shown in FIG. 1A , a chip 30 is fixed on the top surface of a carrier board 20 by an adhesive 32 . The aforementioned carrier board 20 is used as a bridge between the chip 30 and the printed circuit board (not shown in the figure), and at the same time provides the functions of protecting the circuit and dissipating heat.

b): In step S2 shown in FIG. 1A , a layer of encapsulating compound 40 (eg, epoxy resin) is used to cover the chip 30 to provide a protective effect to the chip 30 .

c): as shown in FIG. 1A in step S3, the encapsulating compound 40 is drilled from the top surface of the encapsulating compound 40 from top to bottom, so that the encapsulating compound 40 has a first through hole 42 adjacent to the chip 30, and the first through hole 42 is adjacent to the chip 30. The through hole 42 penetrates through the top and bottom surfaces of the encapsulant 40 .

d): As shown in FIG. 1B in step S4, a layer of conductive metal 50 (eg copper) is plated between the top surface of the wafer 30 and the top of the first through hole 42 and the hole wall of the first through hole 42, respectively, so that The chip 30 is electrically connected to the carrier 20 through the conductive metal 50 , wherein the conductive metal 50 between the top surface of the chip 30 and the top of the first through hole 42 covers the encapsulant 40 .

e): as shown in FIG. 1B in step S5, a layer of solder mask 54 (solder mask) for protecting the conductive metal 50 is provided on the top surface of the encapsulant 40, and the solder mask 54 has an opening 56 to allow the conductive metal 50 to A portion is exposed so that the chip 30 can be electrically connected to a printed circuit board (not shown) using the exposed portion of the conductive metal 50 .

As can be seen from the above, the chip packaging method provided by the present invention electrically conducts the chip 30 and the carrier 20 through the design of the first through hole 42 and the conductive metal 50, and the whole process does not need to pass through the metal wire, so the traditional wire bonding process can be solved. The resulting problems, thereby achieving the effect of simplifying the packaging process and improving the transmission efficiency.

Please continue to refer to FIG. 2A and FIG. 2B , the chip packaging method provided by the second embodiment of the present invention is substantially the same as the above-mentioned first embodiment, and the main difference is that the chip packaging structure 10 made by the above-mentioned first embodiment When the circuit board is electrically connected, since the conductive metal 50 is located above the chip 30, the entire chip package structure 10 needs to be turned upside down by 180 degrees. As for the chip package structure 60 made of the second embodiment, the conductive metal 50 is disposed on the chip 30 below, so it does not need to be turned upside down 180 degrees when making electrical connections to the printed circuit board. In detail:

a): In step S1 shown in FIG. 2A , the chip 30 is fixed on the top surface of the carrier board 20 by the adhesive 32 .

b): In step S2 shown in FIG. 2A , the chip 30 is covered with an encapsulant 40 (eg, epoxy resin), so as to provide a protective effect to the chip 30 .

c): step S3 as shown in FIG. 2A , on the one hand, the encapsulating compound 40 is drilled from the top surface of the encapsulating compound 40 from top to bottom, so that the encapsulating compound 40 has a first through hole 42 adjacent to the chip 30 , the first through holes 42 penetrate through the top and bottom surfaces of the encapsulant 40 and the top and bottom surfaces of the carrier board 20 . There is a second through hole 22 adjacent to the wafer 30 , and the second through hole 22 penetrates through the top and bottom surfaces of the carrier board 20 .

d): Step S4 as shown in FIG. 2B , between the top surface of the wafer 30 and the top end of the first through hole 42 , the hole wall of the first through hole 42 , the bottom surface of the carrier plate 20 and the second through hole 22 . A layer of conductive metal 50 (eg copper) is respectively plated between the bottom ends and the hole wall of the second through hole 22. On the one hand, the circuit on the top surface of the chip 30 is connected to the first through hole 42 plated with the conductive metal 50. On the bottom surface of the carrier board 20 , on the other hand, ground protection is provided to the chip 30 through the second through hole 22 plated with the conductive metal 50 .

e): step S5 as shown in FIG. 2B, a layer of solder mask 54 (solder mask) for protecting the conductive metal 52 is provided on the bottom surface of the carrier board 20, and the solder mask 54 has an opening 56 to allow the lower conductive metal 50 A part is exposed, and the exposed part can be further subjected to anti-oxidation treatment (eg gold plating).

It can be seen from the above that the chip package structure 60 made by the second embodiment of the present invention utilizes the exposed part of the conductive metal 50 below to be electrically connected to the printed circuit board (not shown in the figure), and does not need to be turned upside down 180 degrees during use. , thus increasing the convenience of use.

On the other hand, referring to FIGS. 3A to 3C , the chip packaging method provided by the third embodiment of the present invention is substantially the same as that of the above-mentioned first embodiment. In the packaging process, the third embodiment performs the packaging process on both sides of the carrier board 24 according to the chip packaging method of the first embodiment, so as to improve the utilization rate of the carrier board 24 and improve the process efficiency. In detail:

a): As shown in FIG. 3A in step S1, a plurality of chips 30 (for the convenience of description, the upper and lower 3 chips are taken as an example in the figure, and not limited to this) are attached with the adhesive 32 in a way that the upper and lower sides correspond to each other. It is fixed on the top and bottom sides of the same carrier board 24 .

b): As shown in FIG. 3A in step S2, the upper and lower layers of encapsulation colloid 40 (eg epoxy resin) are used to cover the chips 30 to provide protection for the chips 30.

c): As shown in FIG. 3A in step S3, the upper and lower layers of the encapsulant 40 are drilled respectively, so that each layer of the encapsulant 40 has a plurality of first through holes 42, and each first through hole 42 is adjacent to a 30 wafers.

d): as shown in FIG. 3B in step S4, a layer is respectively plated between the top surface of each wafer 30 and the top of the first through hole 42 adjacent to it and the hole wall of each first through hole 42 The conductive metal 50 (eg, copper) enables each chip 30 to be electrically connected to the carrier 20 through a layer of conductive metal 50 .

e): step S5 as shown in FIG. 3B , a layer of solder mask 54 (solder mask) for protecting the conductive metal 50 is respectively provided on the top surface of the upper layer of the encapsulation compound 40 and the bottom surface of the lower layer of the encapsulation compound 40, and the upper and lower layers of the solder mask The solder layer 54 has a plurality of openings 56 respectively, and each opening 56 corresponds to a layer of conductive metal 50 and exposes a part of the corresponding conductive metal 50 .

f): In step S6 shown in FIG. 3C , the carrier board 24 is cut from the middle into two upper and lower parts, and then cut according to the number of chips 30 to form a plurality of chip package structures 10 .

As can be seen from the above, the chip packaging method of the third embodiment of the present invention can not only improve the utilization rate of the carrier board 24, but also can manufacture a plurality of chip packaging structures 10 at one time, so as to achieve the purpose of improving the process efficiency.

10: Chip package structure 20: Carrier board 22: Second through hole 24: carrier board 30: Wafer 32: Viscose 40: Encapsulating colloid 42: The first through hole 50: Conductive metal 54: Solder mask 56: Opening 60: Chip package structure S1: Step S2: Step S3: Step S4: Steps S5: Steps S6: Steps

1A and 1B are flowcharts of a chip packaging method according to a first embodiment of the present invention. 2A and 2B are flowcharts of a chip packaging method according to a second embodiment of the present invention. 3A to 3C are flowcharts of a chip packaging method according to a third embodiment of the present invention.

10: Chip package structure

20: Carrier board

30: Wafer

40: Encapsulating colloid

42: The first through hole

50: Conductive metal

54: Solder mask

56: Opening

S4: Steps

S5: Steps

Claims (4)

A chip packaging method, comprising the following steps: a) Fix a chip on the top surface of a carrier; b) Encapsulate the chip with an encapsulating colloid; c) drilling the encapsulant from the top of the encapsulant so that the encapsulant has a first through hole adjacent to the chip; d) A conductive metal is respectively plated between the top surface of the chip and the top of the first through hole and the hole wall of the first through hole, so that the chip is electrically connected to the carrier through the conductive metal; and e) A solder resist layer is arranged on the bottom surface of the carrier board, and the solder resist layer has an opening to expose a part of the conductive metal. The chip packaging method according to claim 1, wherein the first through hole penetrates the top and bottom surfaces of the encapsulant. The chip packaging method according to claim 1, in step c), drilling is performed on the carrier from the bottom of the carrier, so that the carrier has a second through hole adjacent to the chip, the carrier is The second through hole penetrates through the top and bottom surfaces of the carrier; in step d), between the bottom surface of the carrier and the bottom end of the first through hole, and between the bottom surface of the carrier and the second through hole Another conductive metal is plated between the bottom ends and the hole wall of the second through hole respectively. The chip packaging method as claimed in claim 1, wherein the first through hole penetrates through the encapsulant and the carrier.

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