TW202218371A - Parallel algorithm encryption and decryption system, transmitting device thereof, and receiving device thereof - Google Patents

Abstract

The present invention provides a parallel algorithm encryption and decryption system, which comprises a transmitting device and a receiving device. The transmitting device comprises a data generating module and a data encryption module. The data encryption module receives a data packet from the data generating module. The data encryption module encrypts the data packet via a 5-stage parallel encoder to output an encrypted sequence. The receiving device comprises a data destination module and a data decryption module. The data decryption module obtains the encrypted sequence from the transmitting device. The data decryption module decrypts the encrypted sequence via a 5-stage parallel decoder to obtain the original data packet and outputs to the data destination module.

Description

Parallel computing encryption and decryption system, its transmitter device, and its receiver device

The present invention provides an encryption and decryption system, its sending end device, and its receiving end device, especially a parallel operation encryption and decryption system capable of switching internal/external encryption keys, its sending end device, and its receiving end device.

Advanced Encryption Standard (AES), also known as Rijndael encryption in cryptography, is a segment encryption standard adopted by the US federal government. This standard is used to replace the original DES, which has been analyzed by many parties and is widely used all over the world. As of 2006, the only successful attack against AES was a side-channel or social engineering attack. The NSA audited all the finalists for the AES campaign and believed they could meet the U.S. government's security needs for delivering unclassified files.

The Advanced Encryption Standard has been cracked many times so far. In AES, the 128-bit key version has 10 encryption loops, the 192-bit key version has 12 encryption loops, and the 256-bit key version has 14 encryption loops. encryption loop. As of 2006, the most famous attacks were against the 128-bit key version of AES with 7 encryption loops, the 192-bit key version with 8 encryption loops, and the 256-bit key version with 9 encryption loops. key version attack. As the efficiency of hardware equipment increases, it is estimated that the days of completely breaking AES with brute force attacks are not far away.

In addition, with the continuous upgrading of hardware equipment, artificial intelligence is now sufficient to reach the stage of commercialization. Through the processing performance of hardware devices and the powerful computing power of artificial intelligence, the encryption standards widely used today are likely to be cracked by artificial intelligence through a large number of calculations. For the above reasons, it is necessary to improve the existing encryption technology.

In order to solve the above problems, the present invention provides a parallel computing encryption and decryption system, which includes a transmitter device and a receiver device. The sending end device includes a data generation module and a data encryption module. The data encryption module includes an encryption key setter and a five-layer parallel encryption device. The encryption key setter includes an internal key encryption mode and an external key encryption mode. The encryption key setter is used to select The internal key encryption mode or the external key encryption mode, the data encryption module obtains at least one data packet from the data generation module, and the internal key encryption mode or the external key encryption mode selected by the five-layer parallel encryptor The key encryption mode encrypts the data packet and outputs an encrypted sequence. The receiver device includes a data destination module and a data decryption module. The data decryption module includes a decryption key setter and a five-layer parallel decryptor. The decryption key setter includes an internal key decryption mode and an external key decryption mode. The decryption key setter is based on a preset Setting or selecting the internal key decryption mode or the external key decryption mode according to the mode selected by the encryption key setter, the data decryption module obtains the encryption sequence from the sender device, and passes through the five-layer parallel decryptor The selected internal key decryption mode or the external key decryption mode decrypts the encrypted sequence and outputs the restored data packet to the data destination module.

The present invention further provides a transmitter device, which includes a data generation module and a data encryption module. The data encryption module includes an encryption key setter and a five-layer parallel encryption device. The encryption key setter includes an internal key encryption mode and an external key encryption mode. The encryption key setter is used to select The internal key encryption mode or the external key encryption mode, the data encryption module obtains at least one data packet from the data generation module, and the internal key encryption mode or the external key encryption mode selected by the five-layer parallel encryptor The key encryption mode encrypts the data packet and outputs an encrypted sequence.

The present invention further provides a receiver device, which includes a data destination module and a data decryption module. The data decryption module includes a decryption key setter and a five-layer parallel decryptor. The decryption key setter includes an internal key decryption mode and an external key decryption mode. The decryption key setter is based on a preset Setting or selecting an internal key decryption mode or an external key decryption mode according to a mode selected by an encryption key setter, the data decryption module obtains an encryption sequence from a sender device, and passes through the five-layer parallel decryptor The selected internal key decryption mode or the external key decryption mode decrypts the encrypted sequence and outputs the restored data packet to the data destination module.

Therefore, compared with the prior art, the present invention can switch the used key to the internal key or the external key according to the required encryption method, and can realize different encryption methods through a set of hardware.

The detailed description and technical content of the present invention are described below with reference to the drawings. One of the preferred embodiments of the present invention will be described below. Please refer to FIG. 1 , which is a block diagram of the parallel computing encryption and decryption system of the present invention, as shown in the figure:

This embodiment mainly discloses a parallel operation encryption and decryption system 100, which is used for encrypting and decrypting data transmitted by a plurality of devices when data is transmitted to each other. The devices that generate or receive data can be computers, servers, mobile devices, IoT devices (such as monitors, TVs, cloud drives, lamps, etc.), a large number of Manufacturing equipment or machines, etc., are not limited in the present invention. In the present invention, these devices are defined as the transmitting end device 10 serving as the data transmission source and the receiving end device 20 corresponding to the transmitting end device 10 for receiving the data of the transmitting end device 10 according to the signal transmission and reception relationship. It should be noted that the present invention is not limited to the transmitting end device 10 only performing the data encryption function and the receiving end device 20 only performing the data decryption function. Specifically, the transmitting end device 10 and the receiving end device described herein are not limited. 20 generally have both encryption and decryption functions to ensure that the data is encrypted or decrypted with each other's key in the process of bidirectional transmission, which must be explained here.

Data can be transmitted between the sender device 10 and the receiver device 20 through a wired or wireless network. In one of the preferred embodiments, the sender device 10 and the receiver device 20 can transmit data through the Internet, a local area network, or between any wired or wireless communication ports, Not limited in the present invention. In order to complete the functions of data encryption, decryption and transmission, the sender device 10 and the receiver device 20 should at least include a processor, a storage unit, and a communication unit to cooperate with each other to complete the corresponding functions, such as a physical line network card, wireless Network card, Bluetooth module (Bluetooth), Zigbee module (Zigbee), etc., the transmission method and transmission interface of these signals are not within the scope of the present invention.

In one embodiment, the combination of "module", "device", or unit described in the parallel computing encryption and decryption system 100 of the present invention and their corresponding functions can be performed cooperatively by a single chip or a combination of multiple chips. , the number of these wafer configurations is not within the scope of the present invention. In addition, the chip can be, but is not limited to, a processor, a central processing unit (CPU), a microprocessor (Microprocessor), a digital signal processor (DSP), a special application integrated circuit (Application Specific Integrated Circuits, ASIC), Programmable Logic Device (Programmable Logic Device, PLD) and other similar devices that can process, convert or special use information or signals or other similar devices or combinations of these devices are not included in the present invention. be restricted.

In one embodiment, the sending end device 10 mainly includes a data generation module 12 and a data encryption module 14 . The data generation module 12 may be, for example, a cache memory, a dynamic random access memory (DRAM), or a persistent memory (Persistent Memory) for storing and managing data to be transmitted and encrypted. The data encryption module 14 obtains at least one data packet from the data generation module 12. The data encryption module 14 may be a processor or a microprocessor for performing encryption calculation processing, which is not limited in the present invention. Finally, the data encryption module 14 outputs the encrypted data packet to the receiving end device 20, where the encrypted data packet output by the data encryption module 14 is defined as an encryption sequence.

In one embodiment, please refer to FIG. 2 together, the data encryption module 14 includes an encryption key setter 142 and a five-layer parallel encryptor 144 . The input end of the five-layer parallel encryptor 144 is connected to the output end of the encryption key setter 142 . The encryption key setter 142 includes an internal key encryption mode and an external key encryption mode, and the encryption key setter 142 is used to select an internal key encryption mode or an external key encryption mode according to a user or a preset value . The five-layer parallel encryptor 144 includes an 8-bit encryption operator generator 1441, a 16-bit encryption operator generator 1442, a 32-bit encryption operator generator 1443, and a 64-bit encryption operator. The element generator 1444, the one-two-octet encryption operation element generator 1445, the external encryption key input device 1446, the internal encryption key storage 1447, and the first logical operator G1. (The eight-bit encryption operand generator 1441, the sixteen-bit encryption operand generator 1442, the thirty-two-bit encryption operand generator 1443, the sixty-four-bit encryption operand generator 1444, The upper-level of the one-two-octet encryption operand generator 1445 is collectively referred to as "encryption operand generator"). The input terminal of the external encryption key input unit 1446 is connected to the output terminal of the encryption key setter 142, and the output terminal of the external encryption key input unit 1446 is connected to the input terminal of the encryption operator generator. The input terminal of the internal encryption key storage 1447 is connected to the other output terminal of the encryption key setter 142, and the output terminals of the internal encryption key storage 1447 are respectively connected to the other input terminal of the encryption operation element generator. The encryption key setter 142 is used for enabling the external encryption key input device 1446 according to the external key encryption mode and outputting the external encryption key, and for enabling the internal encryption key storage 1447 according to the internal key encryption mode and outputting the internal encryption key. Among them, the 8-bit encryption operator generator 1441, the 16-bit encryption operator generator 1442, the 32-bit encryption operator generator 1443, the 64-bit encryption operator generator 1444, the one-two The octet encryption operator generator 1445 generates encryption operators according to the external encryption key generated by the external encryption key input device 1446 or the internal encryption key stored in the internal encryption key storage 1447, respectively. The encrypted sequence ES is obtained after the operation element and the data packet are operated by the first logical operator G1.

In one embodiment, please refer to FIG. 3 , the external encryption key input device 1446 includes an encryption key generator 14462 and an encryption controller 14464 . The encryption key generator 14462 can be (but not limited to) a key generator (Key Generator), a random number generator (Random Number Generator, RNG) or a pseudorandom number generator (Pseudorandom Number Generator, PRNG) Such devices that can generate various sequences are not limited in the present invention. The encryption key generator 14462 generates an external encryption key according to the external key encryption mode. The encryption controller 14464 may be (but not limited to) a controller or other devices capable of controlling signal output, which is not limited in the present invention. The encryption controller 14464 outputs the external encryption key to the encryption operator generator according to the external key encryption mode. In another embodiment, please refer to FIG. 4 , the external encryption key input device 1446 is the encryption input controller 30 , and the encryption input controller includes the encryption input device 32 and the encryption controller 34 . The encrypted input device 32 can be (but not limited to) an input device (Input Device), a keyboard (Keyboard), a computer (Computer) or other devices that can be used for providing data and control signals, which are not limited in the present invention. The encryption inputter 32 is used for inputting an external encryption key. The encryption controller 34 can be (but not limited to) a controller or other devices capable of controlling signal output. The encryption controller 34 outputs the external encryption key to the encryption operator generator according to the input external encryption key and the external key encryption mode.

In an embodiment, please refer to FIG. 2 again, the internal encryption key storage 1447 may be (but not limited to) a device such as a persistent memory (Persistent Memory) that can be used to store and manage data, Not limited in the present invention. The input terminal of the internal encryption key storage 1447 is connected to the output terminal of the encryption key setter 142, and the output terminal of the internal encryption key storage 1447 is connected to the encryption operator generator. The internal encryption key storage 1447 Output the internal encryption key of the encryption operator generator according to the internal encryption key mode.

In one embodiment, please refer to FIG. 5 , the octet encryption operand generator 1441 includes an encryption linear feedback shift register 1441L (which stores the octet encryption keys a[1] to a[8]. ], a[n] is the nth bit of the octet encryption key) and the generation encryption logic gate 1441G, the 16-bit encryption operator generator 1442 includes an encryption linear feedback shift register 1442L (stored in There are 16-bit encryption keys b[1] to b[16], b[n] is the nth bit of the 16-bit encryption key) and generate encryption logic gate 1442G, 32-bit encryption The operand generator 1443 includes an encrypted linear feedback shift register 1443L (which stores 32-bit encryption keys c[1] to c[32], and c[n] is the 32-bit encryption key. The nth bit of the encryption key) and the generation encryption logic gate 1443G, the 64-bit encryption operator generator 1444 includes an encryption linear feedback shift register 1444L (which stores the 64-bit encryption key d[1] ] to d[64], where d[n] is the nth bit of the 64-bit encryption key) and the generation encryption logic gate 1444G, a 28-bit encryption operand generator 1445 includes encryption linear feedback Shift register 1445L (stores one or two octet encryption keys e[1] to e[128], e[n] is the nth bit of the 128-bit encryption key) and generates encryption keys Logic gate 1445G, where the octet encryption key, the 16-bit encryption key, the 32-bit encryption key, the 64-bit encryption key, and the 128-bit encryption key may be Internal encryption key or external encryption key. The encrypted linear feedback shift register 1441L performs logical operations on a plurality of encrypted bit taps of the 8-bit encryption key through the generated encryption logic gate 1441G to obtain an encrypted operator 1441E; the encrypted linear feedback shift register 1442L The encryption operator 1442E is obtained by performing logical operations on a plurality of encrypted bit taps of the sixteen-bit encryption key through the generated encryption logic gate 1442G; the encryption linear feedback shift register 1443L stores the thirty-two-bit encryption key. A plurality of encrypted bit taps of the encrypted operation element 1443E are obtained after the logic operation is performed through the generated encryption logic gate 1443G. The encrypted linear feedback shift register 1444L performs a logical operation on a plurality of encrypted bit taps of the 64-bit encryption key through the generated encryption logic gate 1444G to obtain an encrypted operator 1444E; the encrypted linear feedback shift register 1444E The controller 1445L performs a logical operation on a plurality of encrypted bit taps of the one-two-octet encryption key through the generated encryption logic gate 1445G to obtain an encryption operation element 1445E. In one embodiment, the generating encryption logic gates 1441G, 1442G, 1443G, 1444G, 1445G and the logic operations all use exclusive OR (XOR) as operations. In other embodiments, the generated encryption logic gates 1441G, 1442G, 1443G, 1444G, 1445G and the logic operations can be implemented by AND gates, OR gates, other logic gates, or a combination of a plurality of logic gates, in the present invention Not restricted. In one embodiment, the number of bits of the encrypted bit tap is two. In other embodiments, the number of encrypted bit taps may be an even number.

In an embodiment, please refer to FIG. 2 again, the first logic operator G1 includes an encryption logic operation module G12 and a data encryption logic gate G14. The input end of the encryption logic operation module G12 is connected to the output end of the encryption operation unit generator, and the encryption logic operation module G12 receives the encryption operation units 1441E, 1442E, 1443E, 1444E, 1445E and operates to obtain a parallel encryption operation unit. The encryption logic operation module G12 includes a plurality of logic gates. In one embodiment, the encryption logic operation module G12 includes a first encryption logic gate, a second encryption logic gate, and a third encryption logic gate. , and a fourth encryption logic gate (not shown), the output of the eight-bit encryption operation element generator 1441 and the output of a sixteen-bit encryption operation element generator 1442 are connected to the first encryption logic gate , the output terminal of the first encryption logic gate and the output terminal of the thirty-two-bit encryption operation element generator 1443 are connected to the input terminal of the second encryption logic gate, the output terminal of the second encryption logic gate and the sixty-four The output terminal of the bit encryption operation element generator 1444 is connected to the input terminal of the third encryption logic gate, the output terminal of the third encryption logic gate and the output terminal of the 28-bit encryption operation element generator 1445 are connected to the fourth encryption logic gate. The input terminal of the logic gate and the output terminal of the fourth encryption logic gate are connected to the data encryption logic gate G14. The arrangement and number of the first encrypted logic gate, the second encrypted logic gate, the third encrypted logic gate, and the fourth encrypted logic gate in the encrypted logic operation module G12 are not within the scope of the present invention. The input end of the data encryption logic gate G14 is connected to the output end of the encryption logic operation module G12 to receive the parallel encryption operation element, and the other input end of the data encryption logic gate G14 is connected to the output end of the data generation module 12 to receive data packets , the data encryption logic gate G14 is used for encrypting the data packet through the parallel encryption operation unit and outputting the encryption sequence ES. In one embodiment, the first encryption logic gate, the second encryption logic gate, the third encryption logic gate, the fourth encryption logic gate, and the data encryption logic gate G14 all use an exclusive OR (XOR) gate. ) as an operation. In other embodiments, the first logic gate, the second logic gate, the third logic gate, the fourth logic gate, and the data encryption logic gate G14 can be AND gates, OR gates, other logic gates, or a plurality of logic gates The combination of the gates realizes the operation, which is not limited in the present invention.

In an embodiment, please refer to FIG. 1 again, the receiving end device 20 includes a data destination module 22 and a data decryption module 24 . The data destination module 22 can also be a cache memory, a dynamic random access memory (DRAM), or a persistent memory (Persistent Memory) for storing and managing the received data. The data decryption module 24 can be a processor or a microprocessor for performing decryption calculation processing, which is not limited in the present invention. Finally, the data decryption module 24 is used for decrypting the received encrypted sequence ES through the internal key decryption mode and the external key encryption mode corresponding to the internal key encryption mode and the external key encryption mode. The original data packets are output to the data destination module 22 for storage.

In an embodiment, please refer to FIG. 6 together, the data decryption module 24 includes a decryption key setter 242 and a five-layer parallel decryptor 244 . The input end of the five-layer parallel decryptor 244 is connected to the output end of the decryption key setter 242 . The decryption key setter 242 includes an internal key decryption mode and an external key decryption mode, and the decryption key setter 242 is used to select the internal key according to a preset or a mode selected by the encryption key setter 142. Key decryption mode or external key decryption mode. The five-layer parallel decryptor 244 includes an 8-bit decryption operator generator 2441, a 16-bit decryption operator generator 2442, a 32-bit decryption operator generator 2443, and a 64-bit decryption operator. An operand generator 2444, a two-octet decryption operand generator 2445, an external decryption key inputter 2446, an internal decryption key storage 2447, and a second logical operator G2. (The eight-bit decryption operand generator 2441, the sixteen-bit decryption operand generator 2442, the thirty-two-bit decryption operand generator 2443, the sixty-four-bit decryption operand generator 2444, The upper-level of the one-two-octet decryption operand generator 2445 is collectively referred to as "decryption operand generator"). The input terminal of the external decryption key input unit 2446 is connected to the output terminal of the decryption key setter 242, and the output terminal of the external decryption key input unit 2446 is connected to the input terminal of the decryption operator generator. The input terminal of the internal decryption key storage 2447 is connected to the other output terminal of the decryption key setter 242, and the output terminals of the internal decryption key storage 2447 are respectively connected to the other input terminal of the decryption operator generator. The decryption key setter 242 is used to activate the external decryption key input device 2446 according to the internal decryption key mode and output the external decryption key, and to activate the internal decryption key storage 2447 according to the internal decryption key mode and output the internal decryption key. Among them, the eight-bit decryption operand generator 2441, the sixteen-bit decryption operand generator 2442, the thirty-two-bit decryption operand generator 2443, the sixty-four-bit decryption operand generator 2444, the one-two The octet decryption operand generator 2445 generates decryption operands according to the external decryption key generated by the external decryption key inputter 2446 or the internal decryption key stored in the internal decryption key storage 2447, respectively. The operand and the encrypted sequence ES are decrypted by the second logic operator G2 and output the restored data packet to the data destination module 22 .

In one embodiment, please refer to FIG. 7 , the external decryption key input device 2446 includes a decryption key generator 24462 and a decryption controller 24464 . The decryption key generator 24462 can be (but not limited to) a key generator (Key Generator), a random number generator (Random Number Generator, RNG) or a pseudorandom number generator (Pseudorandom Number Generator, PRNG) Such devices that can generate various sequences are not limited in the present invention. The decryption key generator 24462 generates an external decryption key according to the external key decryption mode. The decryption controller 24464 can be (but not limited to) a controller or other devices capable of controlling signal output, which is not limited in the present invention. The decryption controller 24464 outputs the external decryption key to the decryption operator generator according to the external key decryption mode. In another embodiment, please refer to FIG. 8 , the external decryption key input device 2446 is the decryption input controller 40 , and the decryption input controller 40 includes the decryption input device 42 and the decryption controller 44 . The decryption input device 42 can be (but not limited to) an input device (Input Device), a keyboard (Keyboard), a computer (Computer) or other devices that can be used to provide data and control signals, which are not limited in the present invention. The decryption inputter 42 is used to input an external decryption key. The decryption controller 44 may be (but not limited to) a controller or other devices capable of controlling signal output. The decryption controller 44 outputs the external decryption key to the decryption operator generator according to the external key decryption mode.

In one embodiment, please refer to FIG. 6 again, the internal decryption key storage 2447 may be (but not limited to) a device that can store and manage data such as persistent memory (Persistent Memory) , is not limited in the present invention. The input terminal of the internal decryption key storage 2447 is connected to the output terminal of the decryption key setter 242, and the output terminal of the internal decryption key storage 2447 is connected to the decryption operator generator. The internal decryption key storage 2447 Output the internal encryption key of the decryption operator generator according to the internal decryption key mode.

In one embodiment, please refer to FIG. 9 , the octet decryption operand generator 2441 includes a decryption linear feedback shift register 2441L (which stores the octet decryption keys a[1] to a[8]. ], a[n] is the nth bit of the octet decryption key) and the generation and decryption logic gate 2441G, the 16-bit decryption operator generator 2442 includes a decryption linear feedback shift register 2442L (stored in There are sixteen-bit decryption keys b[1] to b[16], b[n] is the nth bit of the sixteen-bit decryption key) and the decryption logic gate 2442G is generated, and the thirty-two-bit decryption The operand generator 2443 includes a decryption linear feedback shift register 2443L (which stores 32-bit decryption keys c[1] to c[32], and c[n] is the 32-bit decryption key. The nth bit of the key) and the generation decryption logic gate 2443G, the 64-bit decryption operand generator 2444 includes a decryption linear feedback shift register 2444L (which stores the 64-bit decryption key d[1 ] to d[64], where d[n] is the nth bit of the sixty-four-bit decryption key) and generates decryption logic gate 2444G, a two-octet decryption operand generator 2445 including decryption linear feedback Shift register 2445L (stores one or two octets of decryption keys e[1] to e[128], e[n] is the nth bit of the 128-bit decryption key) and generates decryption keys Logic Gate 2445G. Wherein, the 8-bit decryption key, the 16-bit decryption key, the 32-bit decryption key, the 64-bit decryption key, and the 128-bit decryption key may be internal decryption keys or an external decryption key. In principle, the 8-bit decryption key, the 16-bit decryption key, the 32-bit decryption key, the 64-bit decryption key, and the 128-bit decryption key will be the same as the 8-bit decryption key. Encryption key, 16-bit encryption key, 32-bit encryption key, 64-bit encryption key, and 128-bit encryption key use the same key (for example: 8-bit encryption key When the encryption key is the internal encryption key, the octet decryption key is the same as the internal decryption key, and the key data of the internal encryption key and the internal decryption key are the same, so the octet encryption operator generator 1441 is: In the internal key encryption mode, the octet decryption operator generator 2441 is also in the internal key decryption mode). in. The decryption linear feedback shift register 2441L obtains a decryption operator 2441E by performing logical operations on a plurality of decryption bit taps of the octet decryption key through the generation and decryption logic gate 2441G; the decryption linear feedback shift register 2442L The decryption operator 2442E is obtained by performing logical operations on a plurality of decryption bit taps of the sixteen-bit decryption key through the generation and decryption logic gate 2442G; the decryption linear feedback shift register 2443L stores the thirty-two-bit decryption key. The decryption operator 2443E is obtained by performing logical operations on the multiple decryption bit taps of the decryption logic gate 2443G. The decryption linear feedback shift register 2444L obtains a decryption operator 2444E by performing logical operations on a plurality of decryption bit taps of the sixty-four-bit decryption key through the generating decryption logic gate 2444G; the decryption linear feedback shift register The processor 2445L performs a logical operation on the plurality of decryption bit taps of the one-two-octet decryption key through the generated decryption logic gate 2445G to obtain a decryption operator 2445E. In principle, the generation and decryption logic gates 2441G, 2442G, 2443G, 2444G, and 2445G in the five-layer parallel decryptor 244 must perform reverse logic operations with the five-layer parallel encryptor 144 (for example, the five-layer parallel encryptor 144 is AND) , the five-layer parallel decryptor 244 is NAND). In one embodiment, the number of bits of the decrypted bit tap is two. In other embodiments, the number of decryption bit taps may be an even number.

In an embodiment, please refer to FIG. 6 again, the second logic operator G2 includes a decryption logic operation module G22 and a data decryption logic gate G24. The input end of the decryption logic operation module G22 is connected to the decryption operation unit generator, and the decryption logic operation module G22 receives the decryption operation unit and operates to obtain a parallel decryption operation unit. The decryption logic operation module G22 includes a plurality of logic gates. In one embodiment, the decryption logic operation module G22 includes a first decryption logic gate, a second decryption logic gate, a third decryption logic gate, and a third decryption logic gate. Four decryption logic gates (not shown), the output end of the eight-bit decryption operator generator 2441 and the output end of the sixteen-bit decryption operator generator 2442 are connected to the input end of the first decryption logic gate , the output end of the first decryption logic gate and the output end of the 32-bit decryption operator generator 2443 are connected to the input end of the second decryption logic gate, the output end of the second decryption logic gate and the 64-bit decryption logic gate The output of the operand generator 2444 is connected to the input of the third decryption gate, the output of the third decryption gate and the output of the one-two-octet decryption operand generator 2445 are connected to the fourth decryption gate. The input terminal, the output terminal of the fourth decryption logic gate is connected to the data decryption logic gate G24. The arrangement, combination and quantity of the logic gates in the decryption logic operation module G22 are not within the scope of the present invention. In principle, the second decryption logic gate, the second decryption logic gate, the third decryption logic gate, the fourth decryption logic gate, and the data decryption logic gate G24 must perform reverse logic operations with the five-layer parallel encryptor 144 ( For example, the five-layer parallel encryptor 144 is AND, and the five-layer parallel decryptor 244 is NAND). The input end of the data decryption logic gate G24 is connected to the output end of the decryption logic operation module G22 to receive the parallel decryption operation element, the other input end of the data decryption logic gate G24 receives the encryption sequence ES, and the data decryption logic gate G24 is used for encrypting The sequence ES is decrypted through the parallel decryption operator and outputs the restored data packet to the data destination module 22 . In other embodiments, the first decryption logic gate, the second decryption logic gate, the third decryption logic gate, the fourth decryption logic gate, and the data decryption logic gate G24 may be AND gates, OR gates, or other logic gates. Or the combination of a plurality of logic gates can realize the operation, which is not limited in the present invention.

The above describes a specific embodiment of the hardware architecture of the present invention. The working program of the present invention will be further described below. Please refer to FIG. 10 , which is a schematic flowchart of the parallel computing encryption and decryption system of the present invention:

Before data transmission, the encryption key setter 142 and the decryption key setter 242 will set the same external key encryption/decryption mode and internal key encryption/decryption mode according to user setting/automatic configuration. For example, when the encryption key setter 142 selects the 8-bit encryption operator generator 1441 in the five-layer parallel encryptor 144 to be the external key encryption mode, and the 16-bit encryption operator generator 1442 to be the external key encryption mode , the 32-bit encryption operator generator 1443 is an external key encryption mode, the 64-bit encryption operator generator 1444 is an internal key encryption mode, and the 128-bit encryption operator generator 1445 is an internal key encryption mode. In the key encryption mode (three external key encryption modes and two internal key encryption modes are set), the decryption key setter 242 selects the octet decryption operator generator 2441 in the five-layer parallel decryptor 244 as the external key encryption mode. Key decryption mode, 16-bit decryption operand generator 2442 is external key decryption mode, 32-bit decryption operand generator 2443 is external key decryption mode, 64-bit decryption operand generator 2444 is the internal key decryption mode, and the one-two-octet decryption operator generator 2445 is the internal key decryption mode (three external key decryption modes and two internal key decryption modes are set).

Specifically, the encryption operator generators can be various permutations and combinations of the external key encryption mode and the internal key encryption mode; the decryption operator generator can be the external key decryption mode and the internal key encryption mode matched with the encryption operator generator. Various permutations and combinations of key decryption modes, specifically, any one or more of the encryption operand generators can be set to the external encryption key mode or the internal encryption key mode according to the aforementioned permutations; One or more of them can be set to the external decryption key mode or the internal decryption key mode according to the combination of the encryption operator generator. When the external key encryption mode and three internal key encryption modes are set correspondingly, two external key decryption modes and three internal key decryption modes, and one external key encryption mode and four internal key encryption modes are set correspondingly. When setting one external key decryption mode and four internal key decryption modes, four external key encryption modes and one internal key encryption mode, four external key decryption modes and one internal key decryption mode will be set correspondingly. When one external key encryption mode is used, five external key decryption modes are set correspondingly, and when five internal key encryption modes are set, five internal key decryption modes are set accordingly).

First, in the sender device 10, the data packet is output from the data generation module 12 to the data encryption module 14 (step S201).

The data packet PK is received by the five-layer parallel encryptor 144 of the data encryption module 14 and encrypted according to the external key encryption mode or the internal encryption key mode set by the encryption key setter 142 (step S202 ).

The encrypted data packet PK is outputted by the five-layer parallel encryptor 144 as an encrypted sequence ES to the receiving end device 20 (step S203 ).

The encrypted sequence ES is processed by the five-layer parallel decryptor 244 in the data decryption module 24 according to the external key decryption mode or the internal decryption key mode of the decryption key setter 242 corresponding to the external key encryption mode or the internal encryption key mode. The encrypted sequence ES is decrypted (step S204).

The decrypted encrypted sequence ES is output by the five-layer parallel decryptor 244 to restore the data packet to the data destination module 22 for storage (step S205 ).

An embodiment is specifically listed below. The five-layer parallel encryptor 144 has an eight-bit encryption operand generator 1441, a sixteen-bit encryption operand generator 1442, a thirty-two-bit encryption operand generator 1443, A sixty-four-bit encryption operator generator 1444, a one-two-eight-bit encryption operator generator 1445, an external encryption key input device 1446, an internal encryption key storage 1447, and the first logical operator G1 perform encryption; The five-layer parallel decryptor 244 has an 8-bit decryption operator generator 2441, a 16-bit decryption operator generator 2442, a 32-bit decryption operator generator 2443, and a 64-bit decryption operator. In the case where the element generator 2444, the one-two-octet decryption operation element generator 2445, the external decryption key inputter 2446, the internal decryption key storage 2447, and the second logical operator G2 perform decryption. 11 , and FIG. 12 , which are a schematic diagram of the encryption flow diagram of the five-layer parallel encryptor 144 and the decryption flow diagram of the five-layer parallel decryptor 244 of the present invention.

The aforementioned step S202 can be replaced by the steps of steps S2021-S2022 according to the encryption level; step S204 can be replaced by the steps of steps S2041-S2042 according to the decryption level.

In this embodiment, the logical operations of the five-layer parallel encryptor 144 are all XOR; the logical operations described in the five-layer parallel decryptor 244 are all XOR (corresponding to the logical operations of the five-layer parallel encryptor 144 ). In other embodiments, the aforementioned logical operations can be other logical operations such as AND, NAND, etc., which are not limited in the present invention; in this embodiment, the two encrypted tap bits selected by the linear feedback shift register are encrypted. The two decryption tap bits and the number selected by the decryption feedback shift register are only an embodiment, and the encryption/decryption tap bits can be selected according to actual needs, and the number can be changed (for example: selecting the first One bit and the seventh bit are used as the encryption/decryption tap bit; the fourth bit and the 34th bit are selected as the encryption/decryption tap bit; 2 bits, seventy-ninth bits, etc.), the selection of the encryption/decryption tap bits is not within the scope of the present invention. The aforementioned decryption tap bits are selected corresponding to the encryption tap bits for decryption.

Steps S2021-S2022 will be described below, please refer to "FIG. 5" and "FIG. 11" together. The five-layer parallel encryptor 144 generates an encryption operator according to the internal key encryption mode or the external key encryption mode selected by the encryption key setter 142 (step S2021 ). In one embodiment, an eight-bit encryption operand generator 1441, a sixteen-bit encryption operand generator 1442, a thirty-two-bit encryption operand generator 1443, and a sixty-four-bit encryption operand generator The generator 1444 is in the external key encryption mode, and the one-two-octet encryption operand generator 1445 is in the internal key encryption mode. In addition, the key in the encryption operator generator of the external key encryption mode will be provided by the external encryption key inputter 1446, and the key in the encryption operator generator of the internal key encryption mode will be provided by the internal encryption key storage. 1447 offers. Among them, the encrypted linear feedback shift register 1441L in the 8-bit encryption operation element generator 1441 extracts the second bit a[2] and the seventh bit a[7] and performs a logic operation through the generation encryption logic gate 1441G Then, the encryption operator 1441E is obtained; the encryption linear feedback shift register 1442L in the 16-bit encryption operator generator 1442 extracts the second bit b[2] and the fifteenth bit b[15], and generates The encryption logic gate 1442G performs logical operations to obtain the encryption operator 1442E; the encryption linear feedback shift register 1443L in the 32-bit encryption operator generator 1443 retrieves the first bit c[1] and the thirtieth One bit c[31] is obtained by generating the encryption logic gate 1443G for logical operation to obtain the encryption operator 1443E; the encryption linear feedback shift register 1444L in the 64-bit encryption operator generator 1444 extracts the first bit Element d[1] and the sixty-second bit d[62] are subjected to logic operation through the generation encryption logic gate 1444G to obtain the encryption operator 1444E; the encryption linear feedback shift in the encryption operator generator 1445 of one or two octets The register 1445L retrieves the second bit e[2] and the first 28-bit e[128], and then generates the encryption logic gate 1445G to perform a logic operation to obtain the encryption operator 1445E.

The encryption sequence ES is obtained by performing operations on the data packet and the encryption operator through the first logical operator G1 (step S2022 ). In one embodiment, the encryption operators 1441E, 1442E, 1443E, 1444E, and 1445E obtain the parallel encryption operators through the logic operation of the encryption logic operation module G12, and the parallel encryption operators and data packets are encrypted and obtained through the data encryption logic gate G14. Encrypted sequence ES.

Steps S2041-S2042 will be described below, please refer to "FIG. 9" and "FIG. 12" together. The five-layer parallel decryptor 144 generates a decryption operator according to the internal key decryption mode or the external key decryption mode selected by the decryption key setter 142 (step S2041 ). In one embodiment, the eight-bit decryption operand generator 2441, the sixteen-bit decryption operand generator 2442, the thirty-two-bit decryption operand generator 2443, and the sixty-four-bit decryption operand generate The generator 2444 is in the external key decryption mode, and the one-two-octet decryption operand generator 2445 is in the internal key decryption mode. The key in the decryption operator generator in the external key decryption mode will be provided by the external decryption key inputter 2446, and the key in the decryption operator generator in the internal key decryption mode will be provided by the internal decryption key storage 2447 supply. Among them, the decryption linear feedback shift register 2441L in the octet decryption operator generator 2441 extracts the second bit a[2] and the seventh bit a[7] through the generation and decryption logic gate 2441G for logical operation Then, the decryption operand 2441E is obtained; the decryption linear feedback shift register 2442L in the sixteen-bit decryption operand generator 2442 extracts the second bit b[2] and the fifteenth bit b[15] through the generation of The decryption logic gate 2442G obtains the decryption operator 2442E after performing logical operations; the decryption linear feedback shift register 2443L in the thirty-two-bit decryption operator generator 2443 retrieves the first bit c[1] and the thirtieth One bit c[31] is obtained by generating the decryption logic gate 2443G for logical operation to obtain the decryption operator 2443E; the decryption linear feedback shift register 2444L in the sixty-four-bit decryption operator generator 2444 extracts the first bit Element d[1] and the sixty-second bit d[62] are logically operated by generating and decrypting logic gate 2444G to obtain decryption operand 2444E; The register 2445L extracts the second bit e[2] and the first 28-bit e[128], and then generates the decryption logic gate 2445G and performs a logic operation to obtain the decryption operator 2445E.

The encrypted sequence ES and the decrypted operator are operated through the second logical operator G2 to obtain the restored data packet (step S2022 ). In one embodiment, the decryption operators 2441E, 2442E, 2443E, 2444E, and 2445E obtain parallel decryption operators through the logic operation of the decryption logic operation module G22, and the parallel decryption operators and the encrypted sequence ES are obtained by decrypting the data decryption logic gate G24. Restored data packets.

Compared with the prior art, the present invention can switch the used key to an internal key or an external key according to the required encryption method, and can implement different encryption methods through a set of hardware.

The present invention has been described in detail above, however, the above-mentioned is only a preferred embodiment of the present invention, and should not limit the scope of the present invention by this Equivalent changes and modifications should still fall within the scope of the patent of the present invention.

100: Parallel operation encryption and decryption system 10: Sender device 12: Data generation module 14: Data encryption module 142: Encryption key setter 144: Five-layer Parallel Encryptor 1441: Octet encryption operand generator 1441L: Encrypted Linear Feedback Shift Register 1441G: Generate encryption logic gate 1441E: Encryption Operand 1442: 16-bit encryption operand generator 1442L: Encrypted Linear Feedback Shift Register 1442G: Generate encryption logic gate 1442E: Encryption Operand 1443: Thirty-two-bit encryption operand generator 1443L: Encrypted Linear Feedback Shift Register 1443G: Generate encryption logic gate 1443E: Encryption Operand 1444: Sixty-four-bit encryption operand generator 1444L: Encrypted Linear Feedback Shift Register 1444G: Generate encryption logic gate 1444E: Encryption Operand 1445: One or two octet encryption operand generator 1445L: Encrypted Linear Feedback Shift Register 1445G: Generate encryption logic gate 1445E: Encryption Operand 1446: External encryption key input 14462: Encryption key generator 14464: Crypto Controller 1447: Internal encryption key store G1: The first logic operator G12: Encrypted logic operation module G14: Data encryption logic gate 20: Receiver device 22: Data Purpose Module 24: Data decryption module 242: Decryption key setter 244: Five-layer parallel decryptor 2441: Octet decryption operand generator 2441L: Decrypt Linear Feedback Shift Register 2441G: Generate decryption logic gate 2441E: Decryption operand 2442: 16-bit decryption operand generator 2442L: Decrypt Linear Feedback Shift Register 2442G: Generate decryption logic gate 2442E: Decryption operand 2443: Thirty-two-bit decryption operand generator 2443L: Decrypt Linear Feedback Shift Register 2443G: Generate decryption logic gate 2443E: Decryption operand 2444: Sixty-four-bit decryption operand generator 2444L: Decrypt Linear Feedback Shift Register 2444G: Generate decryption logic gate 2444E: Decryption operand 2445: One or two octet decryption operand generator 2445L: Decrypt Linear Feedback Shift Register 2445G: Generate decryption logic gate 2445E: decryption operand 2446: External decryption key input 24462: Decryption key generator 24464: Decrypt controller 2447: Internal decryption key store 30: Encrypted Input Controller 32: Encrypted Input 34: Encryption Controller 40: Decrypt the input controller 42: Decrypt the input device 44: Decrypt the controller G2: Second logic operator G22: Decryption logic operation module G24: Data Decryption Logic Gate ES: encrypted sequence S201-S205: Steps S2021-S2022: Steps S2041-S2042: Steps

FIG. 1 is a block diagram of a parallel computing encryption and decryption system of the present invention.

FIG. 2 is a block diagram of a data encryption module of the present invention.

FIG. 3 is a block diagram of the external encryption key input device of the present invention.

FIG. 4 is a block diagram of another embodiment of an external encryption key importer.

FIG. 5 is a schematic diagram of the logical operation of the five-layer encryptor of the present invention.

FIG. 6 is a block diagram of the data decryption module of the present invention.

FIG. 7 is a block diagram of the external decryption key input device of the present invention.

Figure 8 is a block diagram of another embodiment of an external decryption key input device.

FIG. 9 is a schematic diagram of the logical operation of the five-layer decryptor of the present invention.

FIG. 10 is a schematic flowchart of the parallel computing encryption and decryption system of the present invention.

FIG. 11 is a schematic diagram of the encryption flow of the five-layer parallel encryptor of the present invention.

FIG. 12 is a schematic diagram of the decryption flow of the five-layer parallel decryptor of the present invention.

100: Parallel operation encryption and decryption system

10: Sender device

12: Data generation module

14: Data encryption module

20: Receiver device

22: Data Purpose Module

24: Data decryption module

Claims (18)

A parallel computing encryption and decryption system, comprising: A sender device includes a data generation module and a data encryption module. The data encryption module includes an encryption key setter and a five-layer parallel encryptor. The encryption key setter includes an internal gold key encryption mode and an external key encryption mode, the encryption key setter is used to select the internal key encryption mode or the external key encryption mode, the data encryption module obtains at least one data packet from the data generation module, encrypting the data packet through the internal key encryption mode or the external key encryption mode selected by the five-layer parallel encryptor and outputting an encrypted sequence; and A receiver device includes a data destination module and a data decryption module. The data decryption module includes a decryption key setter and a five-layer parallel decryptor. The decryption key setter includes an internal gold key decryption mode and an external key decryption mode, the decryption key setter selects the internal key decryption mode or the external key decryption mode according to a preset or a mode selected by the encryption key setter, the data decrypts The module obtains the encrypted sequence from the sender device, decrypts the encrypted sequence through the internal key decryption mode or the external key decryption mode selected by the five-layer parallel decryptor, and outputs the restored data packet to The data purpose module. The parallel operation encryption and decryption system according to claim 1, wherein the five-layer parallel encryptor comprises an eight-bit encryption operation element generator, a sixteen-bit encryption operation element generator, a thirty-two-bit encryption operation element generator encryption operand generator, a sixty-four-bit encryption operand generator, a 1128-bit encryption operand generator, an external encryption key inputter, an internal encryption key storage, and a first A logic operator, wherein the 8-bit encryption operator generator, the 16-bit encryption operator generator, the 32-bit encryption operator generator, and the 64-bit encryption operator generate and the 128-bit encryption operator generator respectively generates encryption operators according to the external encryption key generated by the external encryption key input device or the internal encryption key stored in the internal encryption key storage , the encryption sequence is obtained after the encryption operation element and the data packet are operated by the first logic operator; the five-layer parallel decryptor includes an eight-bit decryption operation element generator, a sixteen-bit decryption operation element generator, a 32-bit decryption operator generator, a sixty-four-bit decryption operator generator, a 1128-bit decryption operator generator, an external decryption key input, an internal Decryption key storage, and a second logic operator, wherein the 8-bit decryption operator generator, the 16-bit decryption operator generator, the 32-bit decryption operator generator, The 64-bit decryption operator generator, and the 128-bit decryption operator generator according to the external decryption key generated by the external decryption key input device, or the internal decryption key storage key The stored internal decryption key generates decryption operators respectively, and the data packets are obtained after the decryption operators and the encryption sequence are operated by the second logic operator. The parallel computing encryption and decryption system according to claim 2, wherein the external encryption key input device comprises an encryption key generator and an encryption controller, the encryption key generator generates according to the external key encryption mode the external encryption key, the encryption controller outputs the external encryption key according to the external key encryption mode; the external decryption key input device includes a decryption key generator and a decryption controller, the decryption key generates The controller generates the external decryption key according to the external key decryption mode, and the decryption controller outputs the external decryption key according to the external key decryption mode. The parallel computing encryption and decryption system according to claim 2, wherein the external encryption key input device is an encryption input controller, and the encryption input controller comprises an encryption input device and an encryption controller, and the encryption input device uses When inputting the external encryption key, the encryption controller outputs the external encryption key according to the external key encryption mode; the external decryption key input device is a decryption input controller, and the decryption input controller includes a decryption input device , and a decryption controller, the decryption input device is used for inputting the external decryption key, and the decryption controller outputs the external decryption key according to the external key decryption mode. The parallel operation encryption and decryption system according to claim 3 or claim 4, wherein the 8-bit encryption operator generator, the 16-bit encryption operator generator, the 32-bit encryption operator The generator, the sixty-four-bit encryption operand generator, and the one-two-eight-bit encryption operand generator respectively comprise an encryption linear feedback shift register and one or more generating encryption logic gates, the encryption The linear feedback shift register has the inner encryption key or the outer encryption key, and the encryption linear feedback shift register passes through the inner encryption key or the plurality of encryption bit taps of the outer encryption key through the The encrypted operand is obtained after generating the encryption logic gate and performing logical operation; the eight-bit decryption operand generator, the sixteen-bit decryption operand generator, the thirty-two-bit decryption operand generator, the six-bit decryption operand generator The fourteen-bit decryption operand generator and the one-two-eight-bit decryption operand generator respectively comprise a decryption linear feedback shift register and one or more generating and decryption logic gates, the decryption linear feedback shift temporary The memory has the internal decryption key or the external decryption key, and the decryption linear feedback shift register performs a plurality of decryption bit taps of the internal decryption key or the external decryption key via the generated decryption logic gate. The decryption operand is obtained after the logical operation. The parallel operation encryption and decryption system according to claim 5, wherein the number of bits of the encryption bit tap and the decryption bit tap is two. A sender device, including: a data generation module; and A data encryption module, the data encryption module includes an encryption key setter and a five-layer parallel encryptor, the encryption key setter includes an internal key encryption mode and an external key encryption mode, the encryption key The key setter is used to select the internal key encryption mode or the external key encryption mode, the data encryption module obtains at least one data packet from the data generation module, and the internal key selected by the five-layer parallel encryptor The key encryption mode or the external key encryption mode encrypts the data packet and outputs an encryption sequence. The sender device according to claim 7, wherein the five-layer parallel encryptor comprises an 8-bit encryption operator generator, a 116-bit encryption operator generator, and a 32-bit encryption operator element generator, a sixty-four-bit encryption operand generator, a one-two-eight-bit encryption operand generator, an external encryption key inputter, an internal encryption key storage, and a first logic operation wherein, the 8-bit encryption operator generator, the 16-bit encryption operator generator, the 32-bit encryption operator generator, the 64-bit encryption operator generator, and the one-two-eight-bit encryption operator generator respectively generates encryption operators according to the external encryption key generated by the external encryption key input device or the internal encryption key stored in the internal encryption key storage, the The encrypted sequence is obtained by performing operations on the encrypted operator and the data packet through the first logical operator. The sender device according to claim 8, wherein the external encryption key input device comprises an encryption key generator and an encryption controller, the encryption key generator generates the external encryption key according to the external key encryption mode an encryption key, the encryption controller outputs the external encryption key according to the external key encryption mode. The sender device according to claim 8, wherein the external encryption key input device is an encryption input controller, the encryption input controller comprises an encryption input device, and an encryption controller, and the encryption input device is used for inputting For the external encryption key, the encryption controller outputs the external encryption key according to the external key encryption mode. The sender device according to claim 9 or claim 10, wherein the 8-bit encryption operator generator, the 16-bit encryption operator generator, and the 32-bit encryption operator generator , the sixty-four-bit encryption operation element generator, and the one-two-eight-bit encryption operation element generator respectively comprise an encryption linear feedback shift register and one or more generating encryption logic gates, the encryption linear feedback The shift register has the inner encryption key or the outer encryption key, and the encrypted linear feedback shift register encrypts a plurality of encrypted bit taps of the inner encryption key or the outer encryption key through the generated encryption The encrypted operand is obtained after the logic gate performs a logic operation. The sender device according to claim 11, wherein the number of bits of the encrypted bit tap is two. A receiver device, comprising: a data purpose module; and A data decryption module, the data decryption module includes a decryption key setter and a five-layer parallel decryptor, the decryption key setter includes an internal key decryption mode and an external key decryption mode, the decryption key The key setter selects an internal key decryption mode or an external key decryption mode according to a preset or a mode selected by an encryption key setter, the data decryption module obtains an encryption sequence from a sender device, The internal key decryption mode or the external key decryption mode selected by the five-layer parallel decryptor decrypts the encrypted sequence and outputs a restored data packet to the data destination module. The receiver device according to claim 13, wherein the five-layer parallel decryptor comprises an 8-bit decryption operator generator, a 116-bit decryption operator generator, and a 32-bit decryption operator element generator, a sixty-four-bit decryption operand generator, a one-two-eight-bit decryption operand generator, an external decryption key inputter, an internal decryption key storage, and a second logic operation wherein, the 8-bit decryption operator generator, the 16-bit decryption operator generator, the 32-bit decryption operator generator, the 64-bit decryption operator generator, and the 128-bit decryption operator generator generates decryption operators respectively according to the external decryption key generated by the external decryption key input device or the internal decryption key stored by the internal decryption key storage key. , the data packet is obtained after the decryption operator and the encryption sequence are operated by the second logic operator. The receiver device of claim 14, wherein the external decryption key input device comprises a decryption key generator and a decryption controller, the decryption key generator generates the external decryption key according to the external key decryption mode A decryption key, the decryption controller outputs the external decryption key according to the external key decryption mode. The receiver device of claim 14, wherein the external decryption key input device is a decryption input controller, the decryption input controller comprises a decryption input device, and a decryption controller, and the decryption input device is used for inputting For the external decryption key, the decryption controller outputs the external decryption key according to the external key decryption mode. The receiver device according to claim 15 or claim 16, wherein the 8-bit decryption operator generator, the 16-bit decryption operator generator, and the 32-bit decryption operator generator , the sixty-four-bit decryption operand generator, and the one-two-eight-bit decryption operand generator respectively comprise a decryption linear feedback shift register and one or more generating decryption logic gates, the decryption linear feedback The shift register has the inner decryption key or the outer decryption key, and the decryption linear feedback shift register decrypts the inner decryption key or a plurality of decryption bit taps of the outer decryption key via the generation The decryption operand is obtained after the logic gate performs a logic operation. The receiving end device according to claim 17, wherein the number of bits of the decrypted bit tap is two.

Images